ST TDA7491MV User Manual

25 W mono BTL class-D audio amplifier

Features

 20 W continuous output power:

R

= 8 Ω, THD = 10% at V

L

 25 W continuous output power:

R

= 6 Ω, THD = 10% at V

L

 Wide range single supply operation (5 V - 18 V)

 High efficiency (η = 90%)

 Four selectable, fixed gain settings of

nominally 20 dB, 26 dB, 30 dB and 32 dB

 Differential inputs minimize common-mode

noise

 Filterless operation

 No ‘pop’ at turn-on/off

 Standby and mute features

 Short-circuit protection

 Thermal overload protection

 Externally synchronizable

CC

CC

= 18 V

= 16 V

TDA7491MV

PowerSSO-36 with
exposed pad down

Description

The TDA7491MV is a mono BTL class-D audio
amplifier with single power supply designed for
LCD TVs and monitors.

Thanks to the high efficiency and an
exposed-pad-down (EPD) package no heatsink is
required.

Furthermore, the filterless operation allows a
reduction in the external component count.

The TDA7491MV is pin to pin compatible with the
TDA7491P, TDA7491LP and TDA7491HV for the
left channel as given in Section 6.1 on page 19.

Table 1. Device summary

Order code Operating temp. range Package Packaging

TDA7491MV 0 to 70 °C PowerSSO-36 EPD Tube

TDA7491MV13TR 0 to 70 °C PowerSSO-36 EPD Tape and reel

May 2009 Doc ID 14576 Rev 2 1/28

www.st.com

28

Contents TDA7491MV

Contents

1 Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 Pin out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.1 Test board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6 Applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.1 Compatibility with TDA7491 stereo BTL family . . . . . . . . . . . . . . . . . . . . 19

7 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.1 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.2 Gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.3 Input resistance and capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.4 Internal and external clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.4.1 Master mode (internal clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.4.2 Slave mode (external clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.5 Filterless modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.6 Output low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.7 Protection function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.8 Diagnostic output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.9 Heatsink requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2/28 Doc ID 14576 Rev 2

TDA7491MV List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 5. Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 6. PowerSSO-36 slug down dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 7. Mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 8. Gain settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 9. How to set up SYNCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Doc ID 14576 Rev 2 3/28

List of figures TDA7491MV

List of figures

Figure 1. Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Pin connection (top view, PCB view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Output power vs supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 4. THD vs output power (1 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5. THD vs output power (100 Hz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 6. THD vs Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 7. Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 8. FFT (0 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 9. FFT (-60 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 10. Closed-loop gain vs frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 11. Power dissipation and efficiency vs output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 12. Attenuation vs mute voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 13. Current consumption vs voltage on pin STBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 14. Attenuation vs voltage on pin STBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 15. Power supply rejection ratio vs frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 16. Test board (TDA7491HV) layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 17. PowerSSO-36 slug down outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 18. Applications circuit for class-D amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 19. Standby and mute circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 20. Turn-on/off sequence for minimizing speaker “pop” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 21. Device input circuit and frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 22. Master and slave connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 23. Unipolar PWM output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 24. Typical LC filter for a 8-Ω speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 25. Typical LC filter for a 4-Ω speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 26. Behavior of pin DIAG for various protection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 27. Power derating curves for PCB used as heatsink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4/28 Doc ID 14576 Rev 2

TDA7491MV Device block diagram

1 Device block diagram

Figure 1 shows the block diagram of the TDA7491MV.

Figure 1. Internal block diagram

Doc ID 14576 Rev 2 5/28

Pin description TDA7491MV

2 Pin description

2.1 Pin out

Figure 2. Pin connection (top view, PCB view)

SUB_GND

NC

NC

NC

NC

NC

NC

NC

NC

OUTN

OUTN

PVCC

PVCC

PGND

PGND

OUTP

OUTP

PGND

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

Exposed pad down

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

VSS

SVCC

VREF

SGND

VDDS

GAIN1

GAIN0

SVR

DIAG

SGND

VDDS

SYNCLK

ROSC

INN

INP

MUTE

STBY

VDDPW

6/28 Doc ID 14576 Rev 2

TDA7491MV Pin description

2.2 Pin list

Table 2. Pin description list

Number Name Type Description

1 SUB_GND POWER Connect to the frame

2,3 NC - No internal connection

4,5 NC - No internal connection

6,7 NC - No internal connection

8,9 NC - No internal connection

10,11 OUTN OUT Negative PWM output

12,13 PVCC POWER Power supply

14,15 PGND POWER Power stage ground

16,17 OUTP OUT Positive PWM output

18 PGND POWER Power stage ground

19 VDDPW OUT

3.3 V (nominal) regulator output referred to ground for power
stage

20 STBY INPUT Standby mode control

21 MUTE INPUT Mute mode control

22 INP INPUT Positive differential input

23 INN INPUT Negative differential input

24 ROSC OUT Master oscillator frequency-setting pin

25 SYNCLCK IN/OUT Clock in/out for external oscillator

26 VDDS OUT

3.3 V (nominal) regulator output referred to ground for signal
blocks

27 SGND POWER Signal ground

28 DIAG OUT Open-drain diagnostic output

29 SVR OUT Supply voltage rejection

30 GAIN0 INPUT Gain setting input 1

31 GAIN1 INPUT Gain setting input 2

32 VDDS POWER To be connected to VDDS (pin 26)

33 SGND POWER Signal ground

34 VREF OUT Half VDDS (nominal) referred to ground

35 SVCC POWER Signal power supply

36 VSS OUT 3.3 V (nominal) regulator output referred to power supply

Doc ID 14576 Rev 2 7/28

Electrical specifications TDA7491MV

3 Electrical specifications

3.1 Absolute maximum ratings

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

V

CC

T

op

T

j

T

stg

DC supply voltage for pins PVCCA, PVCCB, SVCC 24 V

Operating temperature 0 to 70 °C

Junction temperature -40 to 150 °C

Storage temperature -40 to 150 °C

3.2 Thermal data

Table 4. Thermal data

Symbol Parameter Min Typ Max Unit

R

th j-case

R

th j-amb

1. FR4 with vias to copper area of 9 cm2 (see also Section 7.9: Heatsink requirements on page 26).

Thermal resistance, junction to case - 2 3

Thermal resistance, junction to ambient
(mounted on recommended PCB)

3.3 Electrical specifications

Unless otherwise stated, the results in Ta bl e 5 below are given for the conditions:
V

=18V, RL (load) = 8 Ω, R

CC

Tamb = 25 °C.

Table 5. Electrical specifications

OSC

(1)

-24-

= R3 = 39 kΩ, C8 = 100 nF, f = 1 kHz, GV = 20 dB, and

°C/W

Symbol Parameter Condition Min Typ Max Unit

V

CC

I

q

I

qSTBY

V

OS

V

OS

I

OCP

T

R

V

j

i

OVP

Supply voltage for
pins PVCC, SVCC

Total quiescent Without LC filter - 26 35 mA

Quiescent current in standby - - 2.5 5.0 µA

Output offset voltage Play mode -150 - 150 mV

Output offset voltage Mute mode -60 - 60 mV

Overcurrent protection threshold RL = 0 Ω 35- A

Junction temperature at thermal
shut-down

Input resistance Differential input 55 60 - kΩ

Overvoltage protection threshold - 19 21 - V

8/28 Doc ID 14576 Rev 2

-5-18V

- - 150 - °C

TDA7491MV Electrical specifications

Table 5. Electrical specifications (continued)

Symbol Parameter Condition Min Typ Max Unit

V

R

P

P

P

P

UVP

dsON

o

o

o

D

Undervoltage protection
threshold

Power transistor on resistance

Output power

Output power

Output power

Dissipated power Po = 20 W THD = 10% - 2.0 - W

η Efficiency P

THD Total harmonic distortion P

G

V

Closed loop gain

- --4V

High side - 0.2 -

Ω

Low side - 0.2 -

THD = 10% - 20 -

W

THD = 1% - 16 -

R

= 8 Ω, THD = 10%

L

=12V

V

CC

= 8 Ω, THD = 1%

R

L

VCC=12V

R

= 6 Ω, THD = 10%

L

VCC=16V

-9.5-

W

-7.2-

-20-

W

= 6 Ω, THD = 1%

R

L

VCC=16V

= 20 W 80 90 - %

o

= 1 W - 0.1 0.2 %

o

-16-

GAIN0 = L, GAIN1 = L 18 20 22

GAIN0 = L, GAIN1 = H 24 26 28

dB

GAIN0 = H, GAIN1 = L 28 30 32

GAIN0 = H, GAIN1 = H 30 32 34

∆G

V

eN Total input noise

Gain matching - -1 - 1 dB

A Curve, G

= 20 dB - 20 -

V

µV

f = 22 Hz to 22 kHz - 25 35

SVRR Supply voltage rejection ratio

, T

T

r

f

SW

f

SWR

V

inH

V

inL

A

MUTE

Rise and fall times - - 50 - ns

f

Switching frequency Internal oscillator 290 310 330 kHz

Output switching frequency

Digital input high (H)

Digital input low (L) - - 0.8

Mute attenuation V

fr = 100 Hz, Vr = 0.5 V,
C

= 10 µF

SVR

With internal oscillator

With external oscillator

40 50 - dB

(1)

250 - -

(2)

250 - -

2.3 - -

-

= 1 V 60 80 - dB

MUTE

kHz

V

Doc ID 14576 Rev 2 9/28

Electrical specifications TDA7491MV

Table 5. Electrical specifications (continued)

Symbol Parameter Condition Min Typ Max Unit

V

Function
mode

Standby, mute and play modes

1. fSW = 106 / ((16 * R

2. f

SW

= f

/ 2 with the frequency of the external oscillator.

SYNCLK

+ 182) * 4) kHz, f

OSC

< 0.5 V, V

STBY

V

> 2.5 V,

STBY

V

< 0.8 V

MUTE

V

> 2.5 V,

STBY

> 2.5 V

V

MUTE

= 2 * fSW with R3 = 39 kΩ (see Figure 18.)

SYNCLK

MUTE

= X

Standby -

Mute -

Play -

10/28 Doc ID 14576 Rev 2

TDA7491MV Characterization curves

4 Characterization curves

The following characterization curves were made using the TDA7491MV demo board. The
LC filter for the 8-Ω load uses components of 33 µH and 220 nF.

All other test conditions are given along side the corresponding curves.

Figure 3. Output power vs supply voltage

Output Power vs. Supply Voltage(8 ohm)

Test Condition :

Vcc = 5~18V,

RL = 8 ohm,

Rosc =39kO, Cosc =100nF,

f =1kHz,

Gv =30dB,

Tamb =25℃

Specification Limit:

Typical:

Vs =18V,Rl = 8 ohm

Po =20W @THD =10%

Po =16W @THD =1%

Output Power vs. Supply Voltage(8 ohm)

22

22
20

20
18

18
16

16
14

14
12

12
10

10

Output Power (W)

Output Power (W)

Rl =8 ohm
f =1kHz

8

8
6

6
4

4
2

2
0

0

5 6 7 8 9 101112 131415161718

5 6 7 8 9 101112 131415161718

Supply Voltage (V)

Supply Voltage (V)

THD =10%

THD =1%

Figure 4. THD vs output power (1 kHz)

THD (%)

10

Test Condition:

Vcc =18V,

RL= 8 ohm,

Rosc =39kΩ, Cosc =100nF,

f =1kHz,

Gv =30dB,

Tamb =25℃

Specification Limit:

Typical:

Po =20W @ THD =10%

5

2

1

0.5

0.2

0.1

0.05

0.02

0.01

0.005
100m 30200m 500m 1 2 5 10 20

Output Power (W)

Doc ID 14576 Rev 2 11/28

Characterization curves TDA7491MV

Figure 5. THD vs output power (100 Hz)

THD (%)

10

Test Condition:

Vcc =18V,

RL= 8 ohm,

Rosc =39kΩ, Cosc =100nF,

f =100Hz,

Gv =30dB,

Tamb =25℃

Specification Limit:

Typical:

Po =20W @ THD =10%

5

2

1

0.5

0.2

0.1

0.05

0.02

0.01

0.005
100m 30200m 500m 1 2 5 10 20

Output Power (W)

Figure 6. THD vs Frequency

THD (%)

Test Condition:

Vcc =18V,

RL= 8 ohm,

Rosc =39kΩ, Cosc =100nF,

f =1kHz,

Gv =30dB,

Po =1W

Tamb =25℃

1

0.5

0.2

0.1

0.05

Specification Limit:

Typical: THD<0.5%

0.02

0.01
20 20k50 100 200 500 1k 2k 5k 10k

Frequency (Hz)

Figure 7. Frequency Response

Ampl (dB)

Test Condition:

Vcc =18V,

RL= 8 ohm,

Rosc =39kΩ, Cosc =100nF,

f =1kHz,

Gv =30dB,

Po =1W

Tamb =25℃

Specification Limit:

Max: +/-3dB

@20Hz to 20kHz

+2

+1

-0

-1

-2

-3

-4

-5
10 30k20 50 100 200 500 1k 2k 5k 10k

Frequency (Hz)

12/28 Doc ID 14576 Rev 2

TDA7491MV Characterization curves

Figure 8. FFT (0 dB)

FFT (dB)

+10

Test Condition:

Vcc =18V,

RL= 8 ohm,

Rosc =39kΩ, Cosc =100nF,

f = 1kHz,

Gv =30dB,

Po =1W

Tamb =25℃

Specification Limit:

Typical: >60dB

for the harmonic frequency

+0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

20 20k50 100 200 500 1k 2k 5k 10k

Frequency (Hz)

Figure 9. FFT (-60 dB)

FFT (dB)

+0

Test Condition:

Vcc =18V,

RL= 8 ohm,

Rosc =39kΩ, Cosc =100nF,

f =1kHz,

Gv =30dB,

Po = -60dB (@ 1W =0dB)

Tamb =25℃

Specification Limit:

Typical: > 90dB

for the harmonic frequency

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

20 20k50 100 200 500 1k 2k 5k 10k

Frequency (Hz)

Figure 10. Closed-loop gain vs frequency

5

Test Condition :

Vcc = 18V,

RL = 8 ohm,

Rosc =39kO, Cosc =100nF,

0dB@f=1kHz, Po=1w,
Gv=32dB,

Tamb =25℃

+0.

Gain=32dB

0

-

5

-0.

1

-

5

-1.

d

2

-

B
r

5

-2.

A

3

-

5

-3.

4

-

-4.5

-5
20 30k50 100 200 500 1k 2k 5k 10k 20k

Gain=26dB

Gain=30dB

Gain=22dB

Vcc=18V,

Rload=8ohm,

0dB@f=1kHz, Po=1w,
Gv=32dB

TDA7491MV 8ohm Closed-loop gain vs F req.at27

Hz

Doc ID 14576 Rev 2 13/28

Characterization curves TDA7491MV

Figure 11. Power dissipation and efficiency vs output power

Power dissipation & Efficiency vs Output power

Test Condition :

Vcc = 18V,

RL = 8 ohm,

Rosc =39kO, Cosc =100nF,

f =1kHz,

Gv =30dB,

Tamb =25℃

Efficiency (%)

Efficiency (%)

90

90

80

80

70

70

60

60

50

50

40

40

30

30

20

20

10

10

Power dissipation & Efficiency vs Output power

Vcc=18V

Rload=8ohm

Gain=30dB

f=1kHz

0

0

0 5 10 15 20

0 5 10 15 20

Output power per channel (W)

Output power per channel (W)

4

4

3.5

3.5

3

3

2.5

2.5

2

2

1.5

1.5

1

1

0.5

0.5

0

0

Dissipation Power (W)

Dissipation Power (W)

Figure 12. Attenuation vs mute voltage

Attenuation vs Mute voltage

Test Condition :

Vcc = 18V,

RL = 8 ohm,

Rosc =39kO, Cosc =100nF,

0dB@f =1kHz, Po=1w

Gv =30dB,

Tamb =25℃

10

10

0

0

-10

-10

-20

-20

-30

-30

-40

-40

-50

-50

-60

-60

Attenuation (dB)

Attenuation (dB)

-70

-70

-80

-80

-90

-90
0 0.5 1 1.5 2 2.5 3 3.5

0 0.5 1 1.5 2 2.5 3 3.5

Attenuation vs Mute voltage

Vcc=18V

Rload=8ohm

Gain=30dB

0dB@f=1kHz,Po=1w

Mute voltage (V)

Mute voltage (V)

Figure 13. Current consumption vs voltage on pin STBY

Test Condition :

Vcc = 18V,

RL = 8 ohm,

Rosc =39kO, Cosc =100nF,

Vin=0,

Gv =30dB,

Tamb =25℃

14/28 Doc ID 14576 Rev 2

30

30

25

25

20

20

15

15

10

10

Iquiescent (mA)

Iquiescent (mA)

5

5

0

0

0 0.5 1 1.5 2 2.5 3 3.5

0 0.5 1 1.5 2 2.5 3 3.5

Iquiescent vs Standby voltage

Iquiescent vs Standby voltage

Vcc=18V

Rload=8ohm

Gain=30dB

Vin=0

Standby voltage (V)

Standby voltage (V)

TDA7491MV Characterization curves

Figure 14. Attenuation vs voltage on pin STBY

Attenuation vs Standby voltage

Test Condition :

Vcc = 5~18V,

RL = 8 ohm,

Rosc =39k

O, Cosc =100nF,

0dB@f=1kHz, Po=1w,

Gv =30dB,

Tamb =25℃

10

10

0

0

-10

-10

-20

-20

-30

-30

-40

-40

-50

-50

-60

-60

-70

-70

-80

-80

Attenuation (dB)

Attenuation (dB)

-90

-90

-100

-100

-110

-110

-120

-120

-130

-130

00.5 11.5 22.5 33.5

00.5 11.5 22.5 33.5

Attenuation vs Standby voltage

Vcc=18V

Rload=8ohm

Gain=30dB

0dB@f=1kHz,Po=1W

Standby voltage (V)

Standby voltage (V)

Figure 15. Power supply rejection ratio vs frequency

+0

Test Condition :

Vcc = 18V,

RL = 8 ohm,

Rosc =39k

O, Cosc =100nF,

Vin=0,

Gv =30dB,

Tamb =25℃

d

B

r

A

T

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100
20 20k50 100 2 00 500 1k 2k 5k 10k

Ripple frequency=100Hz

Ripple voltage=500mV

Hz

Doc ID 14576 Rev 2 15/28

Characterization curves TDA7491MV

4.1 Test board

Figure 16. Test board (TDA7491HV) layout

16/28 Doc ID 14576 Rev 2

TDA7491MV Package mechanical data

5 Package mechanical data

The TDA7491MV comes in a 36-pin PowerSSO package with exposed pad down.

Figure 17 below shows the package outline and Tab le 6 gives the dimensions.

Figure 17. PowerSSO-36 EPD outline drawing

h x 45°

Doc ID 14576 Rev 2 17/28

Package mechanical data TDA7491MV

Table 6. PowerSSO-36 EPD dimensions

Dimensions in mm Dimensions in inches

Symbol

Min Typ Max Min Typ Max

A 2.15 - 2.47 0.085 - 0.097

A2 2.15 - 2.40 0.085 - 0.094

a1 0.00 - 0.10 0.000 - 0.004

b 0.18 - 0.36 0.007 - 0.014

c 0.23 - 0.32 0.009 - 0.013

D 10.10 - 10.50 0.398 - 0.413

E 7.40 - 7.60 0.291 - 0.299

e - 0.5 - - 0.020 -

e3 - 8.5 - - 0.335 -

F - 2.3 - - 0.091 -

G- - 0.10 - - 0.004

H 10.10 - 10.50 0.398 - 0.413

h- - 0.40 - - 0.016

k 0 - 8 degrees 0 - 8 degrees

L 0.60 - 1.00 0.024 - 0.039

M - 4.30 - - 0.169 -

N - - 10 degrees - - 10 degrees

O - 1.20 - - 0.047 -

Q - 0.80 - - 0.031 -

S - 2.90 - - 0.114 -

T - 3.65 - - 0.144 -

U - 1.00 - - 0.039 -

X 4.10 - 4.70 0.161 - 0.185

Y 6.50 - 7.10 0.256 - 0.280

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

18/28 Doc ID 14576 Rev 2

TDA7491MV Applications circuit

6 Applications circuit

Figure 18. Applications circuit for class-D amplifier

TDA7491MV

Input settings for gain:

GAIN0 : GAIN1 Nominal gain

0 V : 0 V 20 dB
0 V : 3.3 V 26 dB

3.3 V : 0 V 30 dB

3.3 V : 3.3 V 32 dB

Input settings for standby, mute and play:

STBY : MUTE Mode

0 V : 0 V Standby
0 V : 3.3 V Standby

3.3 V : 0 V Mute

3.3 V : 3.3 V Play

6.1 Compatibility with TDA7491 stereo BTL family

TDA7491MV mono BTL analog class-D amplifier is derived from the TDA7491 stereo
analog class-D BTL family. TDA7491MV has only the left channel of the stereo BTL family.

In order to guarantee the pin to pin compatibility when moving the application from stereo to
mono, it is necessary to connect the right channel inputs (pins 32 and 33 of TDA7491 BTL
family) to V

and GND, that is, pin 32 to VDDS and pin 33 to SGND.

CC

Doc ID 14576 Rev 2 19/28

Application information TDA7491MV

7 Application information

7.1 Mode selection

The three operating modes of the TDA7491MV are set by the two inputs STBY (pin 20) and
MUTE (pin 21).

z Standby mode: all circuits are turned off, very low current consumption.

z Mute mode: inputs are connected to ground and the positive and negative PWM

outputs are at 50% duty cycle.

z Play mode: the amplifiers are active.

The protection functions of the TDA7491MV are realized by pulling down the voltages of the
STBY and MUTE inputs shown in Figure 19. The input current of the corresponding pins
must be limited to 200 µA.

Table 7. Mode settings

Mode Selection STBY MUTE

Standby L

Mute H

Play H H

(1)

(1)

X (don’t care)

L

1. Drive levels defined in Table 5: Electrical specifications on page 8

Figure 19. Standby and mute circuits

0 V

0 V

Standby

3.3 V

Mute

3.3 V

R2
30 kΩ

R4
30 kΩ

C7

2.2 µF

C15

2.2 µF

STBY

TDA7491MV

MUTE

Figure 20. Turn-on/off sequence for minimizing speaker “pop”

20/28 Doc ID 14576 Rev 2

TDA7491MV Application information

7.2 Gain setting

The gain of the TDA7491MV is set by the two inputs, GAIN0 (pin 30) and GAIN1 (pin 31).
Internally, the gain is set by changing the feedback resistors of the amplifier.

Table 8. Gain settings

GAIN0 GAIN1 Nominal gain, Gv (dB)

0020

0126

1030

1132

7.3 Input resistance and capacitance

The input impedance is set by an internal resistor Ri = 60 kΩ (typical). An input capacitor
(Ci) is required to couple the AC input signal.

The equivalent circuit and frequency response of the input components are shown in

Figure 21. For Ci = 220 nF the high-pass filter cut-off frequency is below 20 Hz:

fc = 1 / (2 * π * Ri * Ci)

Figure 21. Device input circuit and frequency response

Rf

Input
signal

Input

Ci

pin

Ri

Doc ID 14576 Rev 2 21/28

Application information TDA7491MV

7.4 Internal and external clocks

The clock of the class-D amplifier can be generated internally or can be driven by an
external source.

If two or more class-D amplifiers are used in the same system, it is recommended that all
devices operate at the same clock frequency. This can be implemented by using one
TDA7491MV as master clock, while the other devices are in slave mode (that is, externally
clocked. The clock interconnect is via pin SYNCLK of each device. As explained below,
SYNCLK is an output in master mode and an input in slave mode.

7.4.1 Master mode (internal clock)

Using the internal oscillator, the output switching frequency, fSW, is controlled by the
resistor, R

fSW = 106 / ((16 * R

where R

In master mode, pin SYNCLK is used as a clock output pin, whose frequency is:

f

SYNCLK

For master mode to operate correctly then resistor R
below in Ta bl e 9 .

, connected to pin ROSC:

OSC

OSC

is in kΩ.

OSC

= 2 * fSW

+ 182) * 4) kHz

must be less than 60 kΩ as given

OSC

7.4.2 Slave mode (external clock)

In order to accept an external clock input the pin ROSC must be left open, that is, floating.
This forces pin SYNCLK to be internally configured as an input as given in Ta bl e 9 .

The output switching frequency of the slave devices is:

f

= f

SW

SYNCLK

Table 9. How to set up SYNCLK

Master R

Slave Floating (not connected) Input

Figure 22. Master and slave connection

/ 2

Mode ROSC SYNCLK

ROSC SYNCLK

Cosc
100 nF

< 60 kΩ Output

OSC

Master Slave

TDA7491MV

Output

Rosc
39 kΩ

TDA7491MV

SYNCLK ROSC

Input

22/28 Doc ID 14576 Rev 2

TDA7491MV Application information

7.5 Filterless modulation

The output modulation scheme of the BTL is called unipolar pulse width modulation (PWM).
The differential output voltages change between 0 V and +V
This is in contrast to the traditional bipolar PWM outputs which change between +V
and -VCC.

An advantage of this scheme is that it effectively doubles the switching frequency of the
differential output waveform. The OUTP and OUTN are in the same phase when the input is
zero, then the switching current is low and the loss in the load is small. In practice, a short
delay is introduced between these two outputs in order to avoid the BTL output switching at
the same time.

TDA7491MV can be used without a filter before the speaker, because the frequency of the
TDA7491MV output is beyond the audio frequency, the audio signal can be recovered by the
inherent inductance of the speaker and natural filter of the human ear.

Figure 23. Unipolar PWM output

INP

INN

and between 0 V and -VCC.

CC

CC

OUTP

OUTN

Differential
OUT

Doc ID 14576 Rev 2 23/28

Application information TDA7491MV

7.6 Output low-pass filter

To avoid EMI problems, it may be necessary to use a low-pass filter before the speaker. The
cutoff frequency should be larger than 22 kHz and much lower than the output switching
frequency. It is necessary to choose the L-C component values depending on the loud
speaker impedance. Some typical values, which give a cut-off frequency of 27 kHz, are
shown in Figure 24 and Figure 25 below.

Figure 24. Typical LC filter for a 8-Ω speaker

Figure 25. Typical LC filter for a 4-Ω speaker

24/28 Doc ID 14576 Rev 2

TDA7491MV Application information

7.7 Protection function

The TDA7491MV is fully protected against overvoltages, undervoltages, overcurrents and
thermal overloads as explained here.

Overvoltage protection (OVP)

If the supply voltage exceeds the value for V

given in Table 5: Electrical specifications on

OVP

page 8 the overvoltage protection is activated which forces the outputs to the

high-impedance state. When the supply voltage drops to below the threshold value the
device restarts.

Undervoltage protection (UVP)

If the supply voltage drops below the value for V

specifications on page 8 the undervoltage protection is activated which forces the outputs to

the high-impedance state. When the supply voltage recovers the device restarts.

given in Table 5: Electrical

UVP

Overcurrent protection (OCP)

If the output current exceeds the value for I

page 8 the overcurrent protection is activated which forces the outputs to the

high-impedance state. Periodically, the device attempts to restart. If the overcurrent
condition is still present then the OCP remains active. The restart time, T
by the R-C components connected to pin STBY.

given in Table 5: Electrical specifications on

OCP

, is determined

OC

Thermal protection (OTP)

If the junction temperature, Tj, reaches 145 °C (nominal), the device goes to mute mode and
the positive and negative PWM outputs are forced to 50% duty cycle. If the junction
temperature exceeds the value for Tj given in Table 5: Electrical specifications on page 8 the
device shuts down and the output is forced to the high impedance state. When the device
cools sufficiently the device restarts.

7.8 Diagnostic output

The output pin DIAG is an open drain transistor. When the protection is activated it is in the
high-impedance state. The pin can be connected to a power supply (< 18 V) by a pull-up
resistor whose value is limited by the maximum sinking current (200 µA) of the pin.

Figure 26. Behavior of pin DIAG for various protection conditions

VDD

Overcurrent
protection

VDD

TDA7491MV

Protection logic

Restart

DIAG

R1

OV, UV, OT
protection

Restart

Doc ID 14576 Rev 2 25/28

Application information TDA7491MV

g

7.9 Heatsink requirements

A thermal resistance of 24 °C/W can be obtained using the PCB copper ground layer with
16 vias connecting it to the contact area for the exposed pad. Ensure that the copper ground
area is a nominal 9 cm

Figure 27 shows the derating curves for copper areas of 4 cm

As with most amplifiers, the power dissipated within the device depends primarily on the
supply voltage, the load impedance and the output modulation level.

The maximum estimated power dissipation for the TDA7491MV is less than 4 W. When
properly mounted on the above PCB the junction temperature could increase by 96 °C.
However, with a musical program the dissipated power is about 40% less, leading to a
temperature increase of around 60 °C. Even at the maximum recommended ambient
temperature for consumer applications of 50 °C there is still a clear safety margin before the
maximum junction temperature (150 °C) is reached.

Figure 27. Power derating curves for PCB used as heatsink

2

for 24 °C/W.

2

and 9 cm2.

Pd (W)

8

7

6

5

Copper Area 3x3 cm
and via holes

TDA7491MV

TDA7491P

PowerSSO-36

PSSO36

4

3

2

Copper Area 2x2 cm
and via holes

1

0

0 20 40 60 80 100 120 140 160

Tamb ( °C)

26/28 Doc ID 14576 Rev 2

TDA7491MV Revision history

8 Revision history

Table 10. Document revision history

Date Revision Changes

21-Oct-2008 1 Initial release.

Updated text concerning oscillator R and C in Section 3.3:

Electrical specifications on page 8

, updated STBY and

UVP

29-May-2009 2

Updated test condition for Iq, added V
MUTE voltages and rectified several anomalies in Ta bl e 5 :

Electrical specifications on page 8

Updated equation for f

on page 10 and on page 22

SW

Updated Figure 16: Test board (TDA7491HV) layout on page 16
Updated Figure 17: PowerSSO-36 EPD outline drawing on

page 17 and Table 6: PowerSSO-36 EPD dimensions on
page 18

Updated Figure 18: Applications circuit for class-D amplifier on

page 19

Doc ID 14576 Rev 2 27/28

TDA7491MV

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28/28 Doc ID 14576 Rev 2