AVAILABLE
– MUSIC: 4 SELECTABLE RESPONSES
– MOVIE AND SIMULATED:
256 SELECTABLE RESPONSES
■ 2 SPEAKERS AND 2 RECORD
ATTENUATORS:
– 2 INDEPENDENT SPEAKERS AND 2 INDE-
PENDENT RECORD CONTROL
IN 1dB STEP FOR BALANCE FACILITY
– AVAILABIL ITY OF LO UDSPEA KER EQUAL -
IZATION FIXED BY EXTERNAL COMPONENTS
– INDEPENDENT MUTE FUNCTION
■ ALL FUNCTIONS PROGRAMMABLE VIA
SERIAL BUS
TDA7430
TDA7431
SDIP42TQFP44
able 1. Order Codes
Part NumberPackage
TDA7431SSDIP42
TDA7430TQFP44
TDA7430TRTape & Reel
2DESCRIPTION
The TDA7430/TDA7431 is volume tone (bass middle
and treble) balance (Left/Right) processors
canceller for quality audio applications in car radio
and Hi-Fi systems.
They reproduce surround sound by using programmable phase shifters and a signal matrix.
Control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor networks and switches combined with
operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology,
Low Distortion, Low Noise an d DC stepping are
obtained.
Operating Ambient Temperature0 to 70°C
Storage Temperature Range-55 to 150°C
Table 3. Quick Reference Data
SymbolParameterMin.Typ.Max.Unit
V
V
THDTotal Harmonic Distortion V = 0.1Vrms f = 1KHz0.010.1%
S/NSignal to Noise Ratio V
S
Supply Voltage7910.2V
S
Max Input Signal Handling2V
CL
= 1Vrms (mode = OFF)106dB
out
Channel Separation f = 1KHz90dB
C
Treble Control (2dB step)-1414dB
Middle Control (2dB step)-1414dB
Bass Control (2dB step)-1414dB
Balance Control 1dB step (LCH, RCH)-790dB
Mute Attenuation100dB
RMS
Table 4. Thermal Data
SymbolParameterValueUnit
R
2/23
th j-pin
Thermal Resistance Junction-pins85°C/W
Figure 4. TEST CIRCUIT (TDA7430)
680nF
D95AU224B
TDA7430 - TDA7431
2.7K
2.7K
22nF
22nF
4.7nF
100nF
1.2nF
5.6nF
5.6nF
5.6nF
100nF
22nF
18nF
18nF
MIDDLE-LO
22nF
MIDDLE-RO
PS4
PS3
PS2
PS1
LP1
TREBLE-R
TREBLE-L
LPVC
MIDDLE-LI
MIDDLE-RI
D95AU225B
2.2µF
9
40
41
42
43
LP
44
1
18
19
34
14
15
16
17
RECOUT-L RECOUT-R L-OUT R-OUT
BASSO-LVAR-RBASSO-R
876
27262524232221
2.2µF
VAR-L
2.2µF
REARIN
REAROUT
45
TDA7430
DIG-GND SCL SDA
0.47µF
0.47µF
R-IN4
R-IN3
373635
20
AGND
32
HP2
0.47µF
R-IN2
HP1
32
33
31
30
29
28
39
38
10
11
12
13
R-IN1
L-IN1
L-IN2
L-IN3
L-IN4
V
S
CREF
BASS-LO
BASS-LI
BASS-RO
BASS-RI
0.47µF
0.47µF
0.47µF
0.47µF
0.47µF
100nF10µF
22µF
220nF
100nF
100nF
5.6K
100nF
100nF
5.6K
1µF
MIX
Figure 5. TEST CIRCUIT (TDA7431)
2.2µF
22nF
22nF
4.7nF
100nF
1.2nF
5.6nF
5.6nF
5.6nF
100nF
22nF
18nF
2.7K
18nF
2.7K
MIDDLE-LO
22nF
MIDDLE-RO
MIDDLE-RI
PS4
PS3
PS2
PS1
LP1
TREBLE-R
TREBLE-L
LPVC
MIDDLE-LI
12111087373635
13
2
3
4
LP
5
6
22
23
38
18
19
20
21
323130292827262524
9
VOUTREF RECOUT-L RECOUT-R L-OUT R-OUT
2.2µF
VAR-L
TDA7431
680nF
0.47µF
HP1
HP2BASSO-LVAR-RBASSO-R
1µF
R-IN
DIG-GND SCL SDA ADDRAGND
MIX
0.47µF
L-IN
V
S
421
100nF10µF
41
40
39
34
33
NBRO
NBRIN
NBLIN
NBLO
15K
15K
220nF
220nF
7.5K
220nF
220nF
7.5K
22µF
CREF
100nF
14
BASS-LO
100nF
15
BASS-LI
BASS-RO
16
5.6K
100nF
100nF
17
BASS-RI
5.6K
3/23
TDA7430 - TDA7431
Figure 6. Block Diagram (TDA7430)
RECOUT-L
27
L-OUT
25
ATT
SPKR
79dB CONTROL
MUTE
SCL
SDA
222123
DIG GND
SPKR
R-OUT
RECOUT-R
24
26
ATT
MUTE
79dB CONTROL
D95AU221B
-
+
30K
2.2µF
BASSO-LVAR-L
79dB CONTROL
FIX
BASS-LO
100nF
5.6K
100nF
22nF
2.7K
18nF
5.6nF
107 6
RB
BASS-LI
MIDDLE-LO
RM
MIDDLE-LI
1514 11
19
TREBLE-L
PS4
22nF
22nF
4.7nF
100nF
5.6nF680nF
RPS4
4140
PS3
RPS3
PS2
RPS2
PS1
RPS1
HP2
34342
2
1
LP1HP1
31.5dB control
RHP1
RLP1
OFF
PS4
400Hz
PS3
400Hz
PS2
4KHz
PS1
90Hz
REC
SURR
R5
FIX
VAR
ATT
MUTE
3BAND
C BUS DECODER + LATCHES
2
BASS
MIDDLE
TREBLE
AMP
MIXING
MOVIE/SIM
MUSIC
MOVIE/
I
OFF
L-R
-
+
+
REAR
SURR
MUSIC
SIM
-
+
R6
-
+
+
FIX
FIX
MIDDLEBASS
TREBLE
AMP
MIXING
EFFECT
CONTROL
LPF
9KHz
-
+
30K
ATT
MUTE
SURR
RMRB
50K
Vref
SUPPLY
100K
31.5dB control
891218
2.2µF
BASSO-RVAR-R
79dB CONTROL
BASS-RO
BASS-RI
100nF 100nF
MIDDLE-RO
18nF 22nF
MIDDLE-RI
1716 13
5.6nF
TREBLE-R
REARIN
2.2µF
REAROUT
45
1.2nF
LP
22µF
CREF
AGND
S
V
3920 3844
MIX
LPVC
1µF100nF
MIX-IN
3234
5.6K
2.7K
VAR
REC
3BAND
REAR
SURR
OFF
ON
VOICE
+LPF
-
4/23
50K
50K
50K
L-IN3
50K
28
L-IN4
0.47µF
31
30
29
L-IN2
L-IN1
0.47µF
0.47µF
0.47µF
50K
33
35
R-IN2
R-IN1
0.47µF
0.47µF
37
36
R-IN4
R-IN3
0.47µF
0.47µF
50K
50K
50K
THE SWITCHES POSITION MATCHES THE RESET CONDITION
Figure 7. Block Diagram (TDA7431)
R
L
NBLO
NB2
NB1
NBLIN
NB-LA NB-LB
2.2µF
VAR-L
BASSO-L
30K
RECOUT-
32
79dB CONTROL
L-OUT
30
ATT
SPKR
79dB CONTROL
-
+
VAR
ATT
REC
MUTE
MUTE
FIX
SCL
SDA
272628
DIG GND
ADDR
25
TDA7430 - TDA7431
RECOUT-
R-OUT
29
31
30K
MUTE
D95AU222C
NBRO
40391213162293638
NB3
NBRIN
VAR-R
2.2µF
BASSO-R
79dB CONTROL
NB-RA NB-RB
NB4
ATT
SPKR
MUTE
79dB CONTROL
-
+
FIX
VAR
ATT
REC
5.6K
2.7K
100nF
100nF
22nF
18nF
5.6nF
22nF
22nF
4.7nF
100nF
5.6nF680nF
FIX
BASS-LO
1411 103433
RB
BASS-LI
MIDDLE-LO
RM
MIDDLE-LI
1918 15
23
TREBLE-L
PS4
RPS4
PS3
RPS3
PS2
RPS2
4321
PS1
RPS1
HP2
8
7
6
LP1HP1
31.5dB control
35
L-in
0.47µF
RHP1
RLP1
50K
SURR
OFF
PS4
400Hz
PS3
400Hz
PS2
4KHz
PS1
90Hz
R5
3BAND
REAR
BASS
MIDDLE
TREBLE
SURR
AMP
MIXING
MOVIE/SIM
MUSIC
OFF
MUSIC
MOVIE/
SIM
L-R
-
-
+
+
R6
-
+
+
FIX
C BUS DECODER + LATCHES
2
I
MIDDLEBASS
TREBLE
SURR
AMP
MIXING
EFFECT
CONTROL
LPF
9KHz
-
+
3BAND
OFF
VOICE
BASS-RO
REAR
SURR
RMRB
2120 17
Vref
SUPPLY
4224 415
ON
100K
+LPF
control
31.5dB
50K
37
R-in
0.47µF
TREBLE-R
VOUTREF
CREF
AGND
S
V
LP
MIX
LPVC
5.6K
BASS-RI
100nF 100nF
MIDDLE-RO
2.7K
18nF 22nF
MIDDLE-RI
5.6nF
22µF
1.2nF
MIX-IN
1µF100nF
THE SWITCHES POSITION MATCHES THE RESET CONDITION
5/23
TDA7430 - TDA7431
Table 5. Electrical Characteristcs (refer to the te st circu it T
= 600Ω, all controls flat (G = 0dB), Effect CTRL = -6dB, MODE = OFF; f = 1KHz unless otherwise
R
G
= 25°C, VS = 9V, RL = 10KΩ, Vin = 1Vrms;
amb
specified).
SymbolParameterTest ConditionMin.Typ.Ma x.Unit
SUPPLY
V
SVRRipple RejectionL
INPUT STAGE
R
V
C
RANGE
A
VMIN
A
VMAX
A
STEP
V
A
Supply Voltage7910.2V
S
I
Supply Current101826mA
S
/ R
CH
Input Resistance355065KΩ
IN
Clipping LevelTHD = 0.3%22.5V
CL
, Mode = OFF6080dB
CH out
Control Range31.5dB
Min. Attenuation-101dB
Max. Attenuation3131.532dB
Step Resolution0.51dB
DC Stepsadjacent att. step-303mV
Data transmission from microprocessor to the TDA7430/TDA7431 and viceversa takes place through the 2
2
wire s I
must be connected).
3.1 Data Validity
As shown in fig. 8, the data on the SDA line must be stable during the high period of the clock. The HIGH and
LOW state of the data line can only change when the clock signal on the SCL line is LOW.
C BUS interface, consisting of the tw o l ines SDA and SCL (pull- up res istors t o posi t ive suppl y voltage
3.2 Start and Stop Conditions
As shown in fig.9 a start condition is a HIGH to LOW transition of the SDA line while S CL is HIGH. The stop
condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
3.3 Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit.
The MSB is transferred first.
3.4 Acknowledge
The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 10).
The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during this clock
pulse.
The audioprocessor which has been addressed has to generate an acknowledge after the recept ion of each
byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master
transmitter can generate the STOP information in order to abort the transfer.
3.5 Tra nsmission wi th ou t Ack nowledge
Avoiding to detect the acknowledge of the audi oprocessor, the µP can use a simpler transmission: simply it
waits one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking.
9/23
TDA7430 - TDA7431
S
S
S
S
S
S
S
T
D95AU226A
Figure 8. Data va l id ity on the I2C bus
DA
CL
DATA LINE
STABLE, DATA
2
Figure 9. Timin g D i agra m of I
C bus
CL
DA
START
Figure 10. Ack n owledge on th e I
CL
DA
START
1
MSB
CHANGE
DATA
VALID
2
C bus
ALLOWED
D99AU1032
D99AU1031
STOP
23789
D99AU1033
ACKNOWLEDGMEN
FROM RECEIVER
I
2
CBU
4SOFTWARE SPECIFICATION
4.1 Interface Protocol
The interface protocol comprises:
■ A start condition (S)
■ A chip address byte, containing the TDA7430/TDA7431 address
■ A subaddress bytes
■ A sequence of data (N byte + achnowledge)
■ A stop condition (P)
Figure 11.
CHIP ADDRESS
MSB
S 1 0 0 0 0 0 A 0ACKACKDATAACKP
10/23
LSBMSBLSBMSBLSB
SUBADDRESSDATA 1 to DATA n
B
DATA
TDA7430 - TDA7431
D95AU306
D95AU307
5EXAMPLES
5.1 No Incremental Bus
The TDA7430/TDA7431 receives a start condition, the correct chip address, a subaddress with the MSB = 0 (no
incremental bus), N-datas (all these datas concern the subaddress selected), a stop condition.
Figure 12.
CHIP ADDRESS
MSB
S 1 0 0 0 0 0 A 0ACKACKDATAACK P
LSBMSBLSBMSBLSB
SUBADDRESSDATA
X
X
D3
X
0
D2 D1 D0
5.2 Incremental B us
The TDA7430/TDA7431 receives a start condition, the correct chip address, a subaddress with the MSB = 1
(incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDR ESS
from "1XXX1010" to "1XXX 1111" of DATA are ignored.The DA TA 1 concern thesubaddress sent, and the DATA
2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition.
Figure 13.
CHIP ADDRESS
MSB
S 1 0 0 0 0 0 A 0ACKACKDATAACKP
LSBMSBLSBMSBLSB
SUBADDRESSDATA 1 to DATA n
X
X
D3
X
1
D2 D1 D0
6DATA BYTES
Address = 80(HEX) ADDR open; 82 (HEX): need to connect supply
6.1 Function Selection
Table 6. The first byte (Subaddress)
MSBLSBSUBADDRESS
D7D6D5D4D3D2D1D0
BXXX0000INPUT ATTENUATION
BXXX0001SURROUND & OUT & EFFECT CONTROL
BXXX0010PHASE RESISTOR
BXXX0011BASS & NATURAL BASE
BXXX0100MIDDLE & TREBLE
BXXX0101SPEAKER ATTENUATION "L"
BXXX0110SPEAKER ATTENUATION "R"
BXXX0111AUX ATTENUATION "L"
BXXX1000AUX ATTENUATION"R"
BXXX1001INPUT MULTIPLEXER, & AUX OUT
B = 1 incremental bus; active
B = 0 no incremental bus;
X = indifferen t 0, 1
June 200410Changed the Style-sheet in compliance to the new “Corporate Technical
Pubblications Design Guide”
22/23
TDA7430 - TDA7431
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