(400Hz/800Hz/2400Hz)
– 15dB with 1dB steps
– soft-step control with programmable blend
times
– selectable low & high frequency boost
■ Volume
– +15dB to -79dB with 1dB step resolution
– soft-step control with programmable blend
times
– multi-step control
■ Bass
Table 1.Device summary
nd
–2
order frequency response
– center frequency programmable in 4 steps
(60Hz/80Hz/100Hz/200Hz)
– Q programmable 1.0/1.25/1.5/2.0
– DC gain programmable
– -15 to 15dB with 1dB resolution
– soft-step control with programmable blend
times
Order codesPackagePacking
TDA7417TQFP32Tray
TDA7417TRTQFP32Tape & reel
TDA7417
Car radio audio processor
TQFP32
■ Treble
– 2nd order frequency response
– center frequency programmable in 4 steps
(10KHz/12.5KHz/15KHz/17.5KHz)
– -15 to 15dB with 1dB resolution
■ High pass
– 2nd order frequency response
– center frequency programmable in 3 steps
(80Hz/120Hz/160Hz)
■ Speaker
– independent soft step speaker controls,
+15dB to -79dB with 1dB steps
– Independent programmable mix input with
50% mixing ratio for front speakers
–direct mute
– multi-step control
■ Mute Functions
– digitally controlled SoftMute with 3
programmable mute-times
(0.48ms/0.96ms/123ms)
Description
The TDA7417 is an high performance signal
processor specifically designed for car radio
applications with fully integrated audio filters.
The digital control allows a full programming of
the audioprocessor in a wide range of filter
characteristics.
By using BICMOS-process low distortion and low
noise are obtained.
1OUTINL-Left- full-differential stereo input or bass differential output I/O
2OUTINL+Left+ full-differential stereo input or bass differential output I/O
3LFINFront AC coupling left input I
4LRINRear AC coupling left input I
5SWINLSW AC coupling left inputI
6ACOUTLAC coupling left outputO
7SE1LSingle-ended input 1 left channelI
8SE2LSingle-ended input 2 left channelI
9CREFReference capacitorO
10VCCSupplyS
2
11SDAI
12SCLI
C bus dataI/O
2
C bus clockI
13GNDaGroundS
7/34
Pins descriptionTDA7417
Table 2.Pins description (continued)
NO.Pin NameDescriptionI/O
14QDLPseudo differential stereo input leftI
15QDGNDPseudo differential stereo input commonI
16QDRPseudo differential stereo input rightI
17SE2RSingle-ended input 2 right channelI
18SE1RSingle-ended input 1 right channelI
19ACOUTRAC coupling right output O
20SWINRSW AC coupling right inputI
21RRINRear AC coupling right inputI
22RFINFront AC coupling right inputI
23OUTINR+Right+ Full-differential stereo input or Bass differential output I/O
24OUTINR-Right- Full-differential stereo input or Bass differential output I/O
25OUTSWRSW right outputO
26OUTRRRear right outputO
27OUTRFFront right outputO
28DifinGMono differential input commonI
29MonoDifMono differential inputI
30OUTLFFront left outputO
31OUTLRRear left outputO
32OUTSWLSW left outputO
8/34
TDA7417Electrical specifications
3 Electrical specifications
3.1 Thermal data
Table 3.Thermal data
SymbolDescriptionValueUnit
R
Thj-case
Thermal resistance junction-case13°C/W
3.2 Absolute maximum ratings
Table 4.Absolute maximum ratings
SymbolParameterValueUnit
Operating supply voltage9.5V
Operating ambient temperature-40 to 85°C
Storage temperature range-55 to 150°C
ESD protection (Human Body Model) ±2000 V
ESD protection (Change Device Model)±750V
V
V
T
V
amb
T
S
stg
ESD
ESD
3.3 Electrical characteristics
Table 5.Electrical characteristics
SymbolParameterTest ConditionMin.Typ.Max.Unit
SUPPLY
V
= 8.5V; T
S
= 25 C; RL= 10kΩ; all gains = 0dB; f = 1kHz; unless otherwise specified
amb
V
s
I
s
Supply voltage88.59V
Supply current253445mA
INPUT SELECTOR
RinInput resistanceAll single ended inputs70100130kΩ
V
G
IN MIN
G
IN MAX
G
V
V
CL
S
IN
STEP
DC
offset
Clipping levelTHD = 1%22.3V
Input separation80100dB
Min. input gain-0.500.5dB
Max. input gain14.51515.5dB
Step resolution0.511.5dB
DC steps
Adjacent gain steps-515mV
G
MIN to GMAX
-15415mV
Remaining offset with AutoZero0.5mV
9/34
RMS
Electrical specificationsTDA7417
Table 5.Electrical characteristics (continued)
V
= 8.5V; T
S
SymbolParameterTest ConditionMin.Typ.Max.Unit
DIFFERENTIAL STEREO INPUTS
= 25 C; RL= 10kΩ; all gains = 0dB; f = 1kHz; unless otherwise specified
amb
R
in
Input resistanceDifferential70100130kΩ
CMRRCommon mode rejection ratio
DIFFERENTIAL MONO INPUTS
R
in
Input resistanceDifferential405672kΩ
CMRRCommon mode rejection ratio
MIXING CONTROL
M
G
A
A
LEVEL
MAX
MAX
STEP
Mixing ratioMain / Mix Source-6/-6dB
Max gain131517dB
Max attenuation-83-79-75dB
Step resolution0.511.5dB
LOUDNESS CONTROL
A
A
f
MAX
STEP
Peak
Max attenuation141516dB
Step resolution0.511.5dB
Peak frequency
(1)
VOLUME CONTROL
V
CM=1 VRMS@ 1kHz
V
CM=1 VRMS@ 10kHz
V
=1 VRMS@ 1kHz4060dB
CM
=1 VRMS@ 10kHz4060dB
V
CM
f
P1
f
P2
f
P3
4660dB
4660dB
360400440Hz
720800880Hz
220024002600Hz
G
A
A
V
MAX
MAX
STEP
E
A
E
T
DC
Max gain141516dB
Max attenuation-83-79-75dB
Step resolution0.511.5dB
Attenuation set error
G = -15to +15dB-101dB
G = -79 to -15dB-403dB
Tracking error2dB
DC steps
Adjacent attenuation steps-30.13mV
From 0dB to G
SOFT MUTE
A
MUTE
Mute attenuation80 100dB
T1 0.481ms
T
D
Delay time
T20.962ms
T370123170ms
10/34
MIN
-70.57mV
TDA7417Electrical specifications
Table 5.Electrical characteristics (continued)
V
= 8.5V; T
S
SymbolParameterTest ConditionMin.Typ.Max.Unit
BASS CONTROL
= 25 C; RL= 10kΩ; all gains = 0dB; f = 1kHz; unless otherwise specified
amb
FcCenter frequency
Q
BASS
C
RANGE
A
STEP
DC
GAIN
Quality factor
Control range±14±15±16dB
Step resolution0.511.5dB
Bass-DC-gain
TREBLE CONTROL
C
RANGE
A
STEP
f
c
Control range±14±15±16dB
Step resolution0.511.5dB
Center frequency
HPF
(1)
(1)
(1)
f
C1
f
C2
f
C3
f
C4
Q
1
1.11.251.4
Q
2
546066Hz
728088Hz
90100110Hz
180200220Hz
0.911.1
Q3 1.31.51.7
Q4 1.822.2
DC = off-10+1dB
DC = on3.54.45.5dB
f
C1
f
C2
f
C3
f
C4
81012kHz
1012.515kHz
121518kHz
1417.521kHz
f
HP
Highpass corner frequency
SPEAKER ATTENUATORS
G
A
A
STEP
A
MUTE
E
V
MAX
MAX
E
DC
Max gain141516dB
Max attenuation-83-79-75dB
Step resolution0.511.5dB
Mute attenuation8090dB
Attenuation set error2dB
DC stepsAdjacent attenuation steps-50.15mV
AUDIO OUTPUTS
Clipping levelTHD = 1%22.3V
Output impedance530100W
Output load resistance2kΩ
Output load capacitor10nF
R
V
OUT
R
C
CL
L
L
(1)
f
HP1
f
HP2
f
HP3
728088Hz
108120132Hz
144160176Hz
11/34
RMS
Electrical specificationsTDA7417
Table 5.Electrical characteristics (continued)
V
= 8.5V; T
S
SymbolParameterTest ConditionMin.Typ.Max.Unit
= 25 C; RL= 10kΩ; all gains = 0dB; f = 1kHz; unless otherwise specified
amb
V
DC
DC voltage level4.054.254.4V
AC COUPLING
R
ACIN
R
ACOUT
AC coupling input resistance355065kΩ
AC coupling output resistance550100Ω
IN/OUT CONTROL
R
in
CMRRCommon mode rejection ratio
V
CL(IN)
V
CL(OUT)
R
OUT
R
IMPED
V
DC
Input resistanceDifferential 70100130kΩ
VCM =1 VRMS@ 1kHz4060dB
=1 VRMS@ 10kHz4060dB
V
CM
In clipping level1.92V
Out clipping level1.92V
Output impedance50100Ω
High impedance200kΩ
DC voltage level3.13.33.5V
I2C TIMING
VIHHigh input voltage for SDA,SCL2.5V
VILLow input voltage for SDA,SCL0.7V
VOLLow output voltage for SDA0.4V
TrSDA and SCL rise time300ns
TfSDA and SCL fall time300ns
TsdahSCL falling to SDA input hold time00.9us
TsdasSDA input setup time to SCL rising100ns
RMS
RMS
GENERAL
BW=20Hz to 20 kHz all
e
NO
Output noise
gain = 0dB, HPF = off
BW=20Hz to 20 kHz
Output muted
S/NSignal to noise ratio
DDistortion
S
C
1. Min and max values are calculated according to simulation results; functionality is guaranteed by measuring a directly
correlated parameter
Channel separation left/right8090dB
all gain = 0dB flat;
V
=2V
o
RMS
V
IN
=1V
RMS;
all stages
HPF = off
0dB
95100dB
1225µV
615µV
0.010.1%
Note:It is not recommended that gain control and Softstep control be adjusted at the same time if
they are in the same byte.
It is not allowed to change multistep on/off or softstep on/off during the process of multistep
or softstep.
12/34
TDA7417Description of the audioprocessor
4 Description of the audioprocessor
4.1 Input stages
In the basic configuration, one stereo quasi-differential, one selectable full-differential and
two single ended stereo inputs are available. As Figure 3 shown.
Quasi-differential stereo Input (QD)
The QD input is implemented as a buffered quasi-differential stereo stage with 100kΩ inputimpedance at each input. The attenuation is fixed to -3.5dB in order to adapt the incoming
signal level.
Single-ended stereo input (SE1, SE2)
The input-impedance at each input is 100kΩ and the attenuation is fixed to -3.5dB for
incoming signals.
Full differential stereo Input (FD)
The FD input is implemented as a selectable full-differential stereo stage with 50k inputimpedance at each input or high impedance status. The attenuation is fixed to -3.5dB in
order to adapt the incoming signal level.The high impedance status is 100kΩ
Figure 3.Input stage
Quasi-differential
Full-differential
4.2 AutoZero
The AutoZero allows a reduction of the number of pins as well as external components by
canceling any offset generated by or before the In-Gain-stage (Please notice that externally
generated offsets, e.g. generated through the leakage current of the coupling capacitors,
are not canceled).
The auto-zeroing is started every time the input source is changed and needs max. 0.32ms
for the alignment. To avoid audible clicks the Audio processor is muted before the loudness
stage during this time.
SEL1/SER1
InGain
SEL2/SER2
Mute
13/34
Description of the audioprocessorTDA7417
AutoZero-Remain
In some cases, for example if the µP is executing a refresh cycle of the IIC-Busprogramming, it is not useful to start a new AutoZero-action because no new source is
selected and an undesired mute would appear at the outputs. For such applications, it can
be switched in the AutoZero-Remain-Mode (Bit 6 of the subaddress-byte). If this bit is set
to high, the AutoZero will not be invoked and the old adjustment-value remains.
4.3 Loudness
There are four parameters programmable in the loudness stage:
4.3.1 Attenuation
Figure 4 shows the attenuation as a function of frequency at fP = 400Hz.
Figure 4.Loudness Attenuation @ f
4.3.2 Peak Frequency
Figure 5 shows the four possible peak-frequencies at 400, 800 and 2400Hz.
Figure 5.Loudness Center frequencies @ Attn. = 15dB
= 400Hz
P
14/34
TDA7417Description of the audioprocessor
4.3.3 Low & high frequency boost
Figure 6 shows the different Loudness shapes in low & high frequency boost.
Figure 6.Loudness Attenuation, f
4.3.4 Flat Mode
In flat mode the loudness stage works as a 0dB to -15dB attenuator.
4.4 SoftMute
The digitally controlled Softmute stage allows muting/demuting the signal with a I2C-bus
programmable slope. The mute process can be activated by the I
realized in a special S-shaped curve to mute slow in the critical regions (see Figure 7).
=2.4kHz
c
2
C-bus. This slope is
Figure 7.Softmute-Timing
SOFT MUTE
+SIGNAL
REF
-SIGNAL
AC00061
Time
Note:Please notice that a started Mute-action is always terminated and could not be interrupted
by a change of the mute -signal
15/34
Description of the audioprocessorTDA7417
2
4.5 Multistep and Softstep Volume
When the volume-level is changed audible clicks could appear at the output. The root cause
of those clicks
could either be a DC-Offset before the volume-stage or the sudden change of the envelope
of the audio signal. With the Multistep and Softstep feature both kinds of clicks could be
reduced to a minimum and are no more audible. Multistep feature supports N dB change,
each step is 1dB;During 1dB transition, it will have 32 divisions if choosing softstep. The
blend-time from one step to the next is user selectable.
Figure 8.Soft Step and Multi Step timing
Soft Step (S.S.)
32 divisions1dB
Blend
Time
Multi Step (M.S.)
1dB
(2dB)
NdB
Blend
Time
Multi Soft Step (M.S.S.)
1dB32 divisions
Blend
Time
NdB
AC0006
16/34
TDA7417Description of the audioprocessor
4.6 Bass
There are four parameters programmable in the bass stage:
4.6.1 Attenuation
Figure 9 shows the attenuation as a function of frequency at a center frequency of 80Hz.
Figure 9.Bass Control @ f
4.6.2 Center Frequency
Figure 10 shows the eight possible center frequencies 60, 80, 100 and 200Hz.
Figure 10. Bass center Frequencies @ Gain = 14dB, Q = 1
= 80Hz, Q = 1
C
17/34
Description of the audioprocessorTDA7417
4.6.3 Quality Factors
Figure 11 shows the four possible quality factors 1, 1.25, 1.5 and 2.
Figure 11. Bass Quality factors @ Gain = 14dB, f
4.6.4 DC Mode
It is used for cut only for shelving filter. In this mode the DC-gain is increased by 4.4dB. In
addition the programmed center frequency and quality factor is decreased by 25% which
can be used to reach alternative center frequencies or quality factors. Figure 12 shows DC
mode.
Figure 12. Bass normal and DC Mode @ Gain = 14dB, f
= 80Hz
C
= 80Hz
c
Note: The center frequency, Q and DC-mode can be set fully independently.
18/34
TDA7417Description of the audioprocessor
4.7 Treble
There are two parameters programmable in the treble stage:
4.7.1 Attenuation
Figure 13 shows the attenuation as a function of frequency at a center frequency of
17.5kHz.
Figure 13. Treble Control @ f
4.7.2 Center Frequency
Figure 14 shows the four possible center frequencies 10k, 12.5k, 15k and 17.5kHz.
Figure 14. Treble Center Frequencies @ Gain = 14dB
= 17.5kHz
c
19/34
Description of the audioprocessorTDA7417
4.8 Highpass filter
The highpass filter has 2 order filter characteristics with programmable cut-off frequency
(80/120/160Hz)
Figure 15. Highpass Control
4.9 Output Selector and Mixing
The output-selector allows different sources to connect to the front output. The setup of the
output selector is shown in Figure 16. A Mixing-stage is placed after the front speakerattenuator and can be set to mixing-mode.
In normal mode, switch (sw1) turns to down and main signal is directly outputted through
front pin. In the mixing mode, switch (sw1) turns up, mono differential signal and main signal
are mixed with ratio -6/-6dB. Having a full volume-attenuator for the mix-signal, the stage
offers a wide flexibility to adapt the mixing levels.
Figure 16. Output Selector
Mono
Differential
Mix_out
Main
20/34
Attenuator
Attenuator
Attenuator
Attenuator
-6/-6
dB
sw
1
Rear
SW
TDA7417Description of the audioprocessor
4.10 IN/OUT control
IN/OUT control offers selectable full-differential stereo input or Bass output as figure15
shown. When used as full-differential input, bass buffer output is disabled, full-differential
input switch sw1(sw4) closes and sw2(sw3) closes. When used as bass output, fulldifferential input switch sw1(sw4) opens and sw2(sw3) still closes, single ended bass output
signal is converted to full differential output. IN/OUT control supports high impedance status
when bass buffer output is disabled, full-differential input switch sw1(sw4) opens and
sw2(sw3) closes.
Figure 17. IN/OUT control
Enable
BassOUTL
FDL
3.5dB
1
–1
-3.5dB
4.11 Audioprocessor Testing
In the test mode, which can be activated by setting bit D7 of the IIC subaddress byte and bit
D0 of the testing audioprocessor byte, several internal signals are available at the QDL pin.
In this mode, the input resistance of 100kOhm is disconnected from the pin. Internal signals
available for testing are listed in the data-byte specification. External clock can be available
at the SE1R pin.
+
D
1
-
+
D
1
-
sw1
+
-
sw2 50k
sw3
50k
sw4
50k
50k
OUT/INL+
OUT/INL-
AC00063
21/34
Description of the audioprocessorTDA7417
4.12 Test circuit
Figure 18. Test circuit
47μF47μF47μF47μF47μF47μF
100nF100nF
OUTSWLOUTSWLOUTSL OUTLFOUTRF OUTRRMonoDif DiffG
4.7μF
4.7μF
470nF
470nF
470nF
OUTINL-
OUTINL+
LFIN
LRIN
SWINL
2526272829303132
1
2
3
4
5
24
23
22
21
20
OUTINR-
OUTINR+
RFIN
RRIN
SWINR
4.7μF
4.7μF
470nF
470nF
470nF
100nF
100nF
ACOUTL
6
7
SE1L
8
910
SE2L
Cref
VccSDASCL GNDaQDLQDRQDGND
10μF
10μF100nF
121113141516
100nF
100nF10μF
19
18
17
ACOUTR
SE1R
SE2R
100nF
100nF
AC00064
22/34
TDA7417I2C Bus specification
5 I2C Bus specification
5.1 Interface Protocol
The interface protocol comprises:
●a start condition (S)
●a chip address byte (the LSB determines read/write transmission)
●a subaddress byte
●a sequence of data (N-bytes + acknowledge)
●a stop condition (P)
●the max. clock speed is 500kbits/s
●3.3V logic compatible
5.1.1 Receive Mode
S 100 0 1 00R/WACKTSAZAI A4A3 A2A1 A0ACK DATAACKP
S = Start
R/W = "0" -> Receive Mode (Chip can be programmed by P)
"1" -> Transmission Mode (Data could be received by P)
ACK = Acknowledge
P = Stop
TS = Testing mode
AZ = Auto zero remain
AI = Auto increment
5.1.2 Transmission Mode
S1000100R/WACKXXXXXXXSMACKP
SM = Soft mute activated for main channel
X = Not Used
The transmitted data is automatic updated after each ACK. Transmission can be repeated
without new chip address.
5.1.3 Reset Condition
A Power-On-Reset is invoked if the Supply-Voltage is below than 3.5V. After that the
following data is written automatically into the registers of all subaddresses:
Right Bass opmos2 out
Right Bass Vref
Left InGain
Right Bass opmos21 out
Left Volume
Left Loudness
Left Bass
Left Treble
REF5.5V
Left Highpass out
1.95V
VBG 1.26V
SSCLK
CLK200
SMCLK
Clock Source
external
internal
Clock Fast Mode
0
1
on
off
xNot used
31/34
Package informationTDA7417
7 Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 19. TQFP32 Mechanical Data & Package Dimensions
DIM.
A1.600.063
A10.050.15 0.0020.006
A21.351.40 1.45 0.053 0.055 0.057
B0.30 0.37 0.45 0.012 0.015 0.018
C0 .090.20 0.0040.008
D9.000.354
D17.0 00 .276
D35.6 00 .220
e0.800.031
E9.000.354
E17.000.276
E35.600.220
L0.45 0.60 0.75 0.018 0.024 0.030
L11.000.039
K0˚(min.), 3.5°(typ.), 7°(max.)
mminch
MIN. TYP. MAX. MIN. TYP. MAX.
D
D1
OUTLINE AND
MECHANICAL DATA
Weight: 0.20gr
TQFP32 (7 x 7 x 1.40mm)
A1
A
A2
1724
25
B
32
1
e
16
9
8
TQFP32
32/34
E3D3E1
0.10mm
.004
Seating Plane
E
L1
L
K
B
C
0060661 C
TDA7417Revision history
8 Revision history
Table 18.Document revision history
DateRevisionChanges
28-Feb-20071Initial release.
26-Jun-20072Corrected typo errors.
33/34
TDA7417
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