ST TDA7333N User Manual

Features

rd

■ 3

order high resolution sigma delta converter

for MPX sampling

■ Digital decimation and filtering stages

■ Demodulation of european radio data system

(RDS)

■ Demodulation of USA radio broadcast data

system (RBDS)

■ Automatic group and block synchronization

with flywheel mechanism

■ Error detection and correction

■ RAM buffer with a storage capacity of 24 RDS

blocks and related status information

■ Programmable interrupt source (RDS block A,

B, or D, TA, TA EON)

2

■ I

C/SPI bus interface

■ Input frequency range 4-21 MHz

■ Power down mode

■ 3.3 V power supply, 0.35 µm CMOS

technology

TDA7333N

RDS/RBDS processor

TSSOP16

Description

The TDA7333N circuit is a RDS/RDBS signal
processor, intended for recovering the inaudible
RDS/RBDS informations which are transmitted on
most FM radio broadcasting stations..

Table 1. Device summary

Order code Operating temp. range, °C Package Packing

TDA7333N -40 to +85 TSSOP16 Tube

TDA7333NTR -40 to +85 TSSOP16 Tape & reel

September 2009 Doc ID 12064 Rev 4 1/36

www.st.com

1

Contents TDA7333N

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.2 Fractional PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.3 Sigma delta converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.4 Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.5 Group and block synchronization module . . . . . . . . . . . . . . . . . . . . . . . . 14

3.6 Flywheel mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.7 RAM Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.8 Programming through serial bus interface . . . . . . . . . . . . . . . . . . . . . . . . 20

3.8.1 rds_int register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.8.2 rds_qu register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.8.3 rds_corrp register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.8.4 rds_bd_h register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.8.5 rds_bd_l register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.8.6 rds_bd_ctrl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.8.7 sinc4reg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.8.8 testreg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.8.9 pllreg4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.8.10 pllreg3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.8.11 pllreg2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.8.12 pllreg1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.8.13 pllreg0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.9 I2C transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.9.1 Write transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2/36 Doc ID 12064 Rev 4

TDA7333N Contents

3.9.2 Read transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.10 SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4 Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.1 Typical RDS data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Doc ID 12064 Rev 4 3/36

List of tables TDA7333N

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 4. General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 6. External pins alternate functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 7. Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4/36 Doc ID 12064 Rev 4

TDA7333N List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Fractional PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 4. Demodulator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 5. Group and block synchronization diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 6. Example for flywheel mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 7. RAM buffer usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 8. RAM buffer update depends on “syncw” bit rds_bd_ctrl[0] . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 9. RAM buffer states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 10. rds_int registe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 11. rds_qu register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 12. rds_corrp register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 13. rds_bd_h registe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 14. rds_bd_l register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 15. rds_bd_ctrl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 16. sinc4reg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 17. testreg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 18. pllreg4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 19. pllreg3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 20. pllreg2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 21. pllreg1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 22. pllreg0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 23. I
Figure 24. I
Figure 25. I
Figure 26. I
Figure 27. I
Figure 28. I

Figure 29. SPI data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 30.

Figure 31. Read out RDS data and related flags, no update of rds_int and rds_bd_ctrl registers. . . . 31

Figure 32. Write rds_int registers in SPI mode, reading 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 33. TSSOP16 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2

C data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2

C write transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2

C write operation example: write of rds_int and rds_bd_ctrl registers . . . . . . . . . . . . . . . 28

2

C read transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2

C read access example 1: read of 5 bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2

C read access example 2: read of 1 byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Write rds_int, rds_bd_ctrl and pll_reg4 registers in SPI mode, reading RDS data and related flags

. 31

Doc ID 12064 Rev 4 5/36

Block diagram and pin description TDA7333N

1 Block diagram and pin description

1.1 Block diagram

Figure 1. Block diagram

1.2 Pin description

Figure 2. Pin connection (top view)

VDDA

1

REF3

2

REF2

3

REF1

4

VSS

TM

RESETN

6/36 Doc ID 12064 Rev 4

TDA7333N

5

6

7

8

MPX

16

INTN

15

CSN

14

SA_DATAOUT

13

SDA_DATAIN

12

SCL_CLK

11

XTOVDDD

10

XTI

9

TDA7333N Block diagram and pin description

Table 2. Pin description

Pin # Pin name Function

1 VDDA Analog supply voltage

2 REF3 Reference voltage 3 of A/D converter (2.65 V)

3 REF2 Reference voltage 2 of A/D converter (1.65 V)

4 REF1 Reference voltage 1 of A/D converter (0.65 V)

5 VSS Common ground

6TM

7 VDDD Digital supply voltage

8 RESETN External reset input (active low)

9 XTI Oscillator input

10 XTO Oscillator output

11 SCL_CLK Clock signal for I

12 SDA_DATAIN Data line in I

13 SA_DATAOUT Slave address in I

14 CSN Chip select (1 = I

15 INTN

Testmode selection (scan test).
Normal mode must be connected to gnd.

2

C and SPI modes

2

C mode, data input in SPI mode

2

C mode, data output in SPI mode

2

C mode, 0=SPI mode)

Interrupt output (active low), prog. at buff.not empty,buff. full, block A,B,D
,TA, TA EON

16 MPX Multiplex input signal

Doc ID 12064 Rev 4 7/36

Electrical specifications TDA7333N

2 Electrical specifications

2.1 Absolute maximum ratings

Table 3. Absolute maximum ratings

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

V

V

T

3.3 V power supply voltages - -0.5 - 4 V

DD

Input voltage 5 V tolerant inputs -0.5 - 5.5 V

in

Output voltage 5 V tolerant output buffers in tri-state -0.5 - 5.5 V

out

Storage temperature - -55 - 150 °C

stg

Human body model ≥ ±2000 V

V

ESD withstand voltage

ESD

Machine model ≥ ±200 V

Charged device model, corner pins ≥ ±1000 V

2.2 General interface electrical characteristics

Table 4. General interface electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

il

I

ih

I

ozFT

Low level input current Vi = 0 V - - 1 µA

High level input current Vi = V

Five volt tolerant tri-state

Vo = 0 V or V

DD

DD

--1µA

--1µA

output leakage without pull

= 5.5 V - 1 3 µA

V

up/down device

o

2.3 Electrical characteristics

T

= -40 to +85 °C, V

amb

V

and V

DDD

Table 5. Electrical characteristics

must not differ more than 0.15 V

DDA

DDA/VDDD

Symbol Parameter Test conditions Min. Typ. Max. Unit

Supply (pin 1,5,7)

V

V

I

I

DDD

DDA

DDD

DDA

Digital supply voltage - 3.0 3.3 3.6 V

Analog supply voltage - 3.0 3.3 3.6 V

Digital supply current

Analog supply current

8/36 Doc ID 12064 Rev 4

= 3.0 to 3.6 V, f

= 8.55 MHz, unless otherwise specified

osc

Normal mode - 14 - mA

Power down mode - < 1 - µA

Normal mode - 11.7 - mA

Power down mode - < 1 - mA

TDA7333N Electrical specifications

Table 5. Electrical characteristics (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Digital inputs( pin 6,8,11,12,13,14)

Low level input voltage - - - 0.8 V

il

High level input voltage - 2.0 - - V

ih

Low level threshold input
falling

High level threshold input
rising

Schmitt trigger hysteresis - 0.4 - 0.7 V

hst

-1.0-1.15V

- 1.5 - 1.7 V

V

V

V

V

ilhyst

ihhyst

V

Digital outputs (pin 12,13,15) are open drains

V

V

High level output Voltage

oh

Low level output Voltage

ol

Open drain, depends on external
circuitry

I

=4 mA, takes into account

ol

200 mV drop in the supply voltage

-n/a-V

--0.4V

Analog inputs (pin 16)

V

MPX

Input Range of MPX Signal - - - 0.75 Vrms

- Input Impedance of MPX pin - - 55k - Ohm

C

Blocking Capac. of REF Pins

ref

Electrolyte capacitor parallel to
ceramic capacitor

-2.2-μF

-100-nF

Crystal/oscillator parameters

f

osc

f

oto

t

g

C

xti,Cxto

Quartz frequency - 4 10.25 21 MHz

Total quartz frequency
tolerance

Start up time - - - 10 ms

su

Oscillator transconductance - 0.0006 - - A/V

m

Load capacitance With crystal between XTI and XTO - 16 - pF

External XTI input frequency mode (pin 9)

f

exti

V

C

R

Externaly applied XTI
frequency

XTI input voltage

xti

Coupling capacitor for external

in

clock frequency

XTO pull up to VDDD - - 3.3 - kΩ

xto

T

= -40 to 85 °C - - 100 ppm

amb

- 4 10.25 21 MHz

With R
and f

= 3.3 kOhm,

xto

= 10.25 MHz

exti

220 - - mVpp

- - 100 - pF

Doc ID 12064 Rev 4 9/36

Electrical specifications TDA7333N

Table 5. Electrical characteristics (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

PLL parameters

f

t

O

vco

f

lock

I

M

VCO range - 150 - 250 MHz

VCO input range - 4 - 21 MHz

vin

PLL lock time - - - 500 µs

Input divide factor - 1 - 32 -

DF

Output divide factor - 2 - 32 -

DF

Integer multiplication factor - 10 - 128 -

F

FRA Fractional multiplication factor FRA/2

Bandpass filter

f

Pass-band frequencies - 55.6 - 58.4 kHz

p

R

f

stop

R

2

I

C (@ fsys = 8.55/8.664 MHz)

f

I2C

ts

Pass-band ripple - -0.5 - +0.5 dB

p

Stop-band corner frequencies - 53 - 61 kHz

Stop-band attenuation - - -43 - dB

s

Clock frequency in I2C mode - - - 400 kHz

Data setup time - 250 - - ns

udat

SPI (@ fsys = 8.55/8.664 MHz)

f

t

t

t

SPI

t

t

csu

csh

odv

t

t

Clock frequency in SPI mode - - - 1 MHz

Clock high time - 450 - - ns

ch

Clock low time - 450 - - ns

cl

Chip select setup time - 500 - - ns

Chip select hold - 500 - - ns

Output data valid - - - 250 ns

Output hold - 0 - - ns

oh

Deselect time - 1000 - - ns

t

d

Data setup time - 200 - - ns

su

Data hold time - 200 - - ns

t

h

14

0-214-

10/36 Doc ID 12064 Rev 4

TDA7333N Functional description

3 Functional description

3.1 Overview

The new RDS/RBDS processor contains all RDS/RBDS relevant functions on a single chip.
It recovers the inaudible RDS/RBDS information which are transmitted on most FM radio
broadcasting stations.

The oscillator frequency can be derived from the tuner with typical value of 10.25 MHz . The
device can operate with frequencies in the range of 4-21 MHz. Therefor the fractional PLL
must be initialized through I
reference clock with a freq. tolerance of ±0.7 kHz.

Due to an integrated 3
further processing is done in the digital. After filtering the highly over sampled output of the
A/D converter, the RDS/RBDS demodulator extracts the RDS data clock, RDS data signal
and the quality information. A next RDS/RBDS decoder will synchronize the bit wise RDS
stream to a group and block wise information. This processing includes an error detection
and error correction algorithm. In addition, an automatic flywheel control avoids overheads
in the data exchange between the RDS/RBDS processor and the host.

The device operates in accordance with the CENELEC Radio Data System (RDS)
specification EN50067.

2

C/SPI interface to generate the internal 8.55 MHz or 8.664 MHz

rd

order sigma delta converter, which samples the MPX signal, all

3.2 Fractional PLL

Figure 3. Fractional PLL

XTI)

f(

) = 8.55/

PLL

8.664 MHz

f(

Input

Divider

IDF

Phase

Comperator

& VCO

Fractional

Divider

14

FRAEN

MF + FRA/2

PLL ControllerMux

DITEN

f(vco)

LOCK

Output
Divider

ODF

fsys

pllreg4

pllreg3

pllreg2

pllreg1

pllreg0

Doc ID 12064 Rev 4 11/36