Digital controlled stereo audio processor with loudness
Features
■ Input multiplexer:
– 3 stereo inputs
– Selectable input gain for optimal adaptation
to different sources
■ Volume control in 1.25 dB steps
■ Loudness function
■ Treble and bass controL
■ Four speaker attenuators:
– 4 independent speakers control in 1.25d B
steps for balance and fader facilities
– Independent mute function
■ All functions programmable via serial I
2
C bus
TDA7303
SO-28
Selectable input gain and external loudness
function are provided. Control is accomplished by
2
serial I
C bus microprocessor interface.
Description
The TDA7303 is a volume, tone (bass and treble)
balance (left/right) and fader (front/rear)
processor for quality audio applications in car
radio, Hi-Fi and portable systems.
Table 1.Device summary
Order codePackagePacking
TDA7303SO-28Tray
TDA7303TRSO-28Tape and reel
The AC signal setting is obtained by resistor
networks and switches combined with operational
amplifiers.
Thanks to the used bipolar/CMOS technology, low
distortion, low noise and low DC stepping are
obtained.
THDTotal harmonic distortion V = 1 Vrms; f = 1 kHz0.01%
S/NSignal to noise ratio106dB
S
Supply voltage6910V
S
Max. input signal handling2Vrms
Channel separation f = 1 kHz103dB
C
Volume control 1.25d B step-78.750dB
Bass and treble control 2 dB step-14+14dB
Fader and balance control 1.25 dB step-38.750dB
Input gain 3.75 dB step1.25 dB step011.25dB
Mute attenuation100dB
2.3 Thermal data
Table 4.Thermal data
SymbolParameterValueUnit
R
th j-pins
Thermal resistance junction to pinsMax.85°C/W
7/20
Electrical specificationsTDA7303
2.4 Electrical characteristics
Table 5.Electrical characteristics
(T
= 25 °C, VS = 9 V, RL = 10 kΩ, RG = 600 Ω, all control flat (G = 0), f = 1 kHz unless
amb
otherwise specified)
SymbolParameterTest conditionMin. Typ.Max.Unit
Supply
V
Supply voltage6910V
S
Supply current811mA
I
S
SVRRipple rejection6080dB
Input selectors
R
Input resistanceInput 1, 2, 3, 450kΩ
II
V
S
G
G
INmax
G
Volu m e co n t rol
Clipping level22.5Vrms
CL
Input separation
IN
Output load resistancepin 7, 172kΩ
R
L
Min. input gain-101dB
INmin
(2)
80100dB
Max. input gain11.25dB
Step resolution3.75dB
STEP
e
Input noiseG = 11.25 dB2µV
IN
R
C
RANGE
A
A
VMAX
A
Input resistance33kΩ
IN
Control range707580dB
Min. attenuation-101dB
VMIN
Max. attenuation707580dB
Step resolution0.51.251.75dB
STEP
AV = 0 to -20 dB-1.2501.25dB
E
Attenuation set error
A
Tracking error2dB
E
T
= -20 to -60 dB-32dB
A
V
Speaker attenuators
C
S
A
MUTE
Bass control
Control range3537.540dB
range
Step resolution0.51.251.75dB
STEP
Attenuation set error1.5dB
E
A
Output mute attenuation80100dB
(1)
GbControl rangeMax. Boost/cut±12±14±16dB
B
STEP
Step resolution123dB
8/20
TDA7303Electrical specifications
Table 5.Electrical characteristics (continued)
(T
= 25 °C, VS = 9 V, RL = 10 kΩ, RG = 600 Ω, all control flat (G = 0), f = 1 kHz unless
amb
otherwise specified)
SymbolParameterTest conditionMin. Typ.Max.Unit
R
Treble control
Internal feedback resistance44kΩ
B
(1)
GtControl rangeMax. Boost/cut±13±14±15dB
T
STEP
Step Resolution123dB
Audio outputs
V
R
V
Clipping leveld = 0.3 %22.5Vrms
OCL
R
Output load resistance2kΩ
L
Output load capacitance10nF
C
L
Output resistance75Ω
OUT
DC voltage level4.24.54.8V
OUT
General
BW = 20-20 kHz, flat
e
NO
Output noise
(2)
output muted
all gains = 0 dB
2.5
5
A curve all gains = 0 dB3µV
S/NSignal to noise ratioall gains = 0 dB; V
A
= 0; VIN = 1 Vrms0.01%
V
dDistortion
= -20 dB, VIN = 1 Vrms0.090.3%
A
V
= -20 dB, VIN = 0.3 Vrms0.04%
A
V
= 1 Vrms106dB
O
ScChannel separation left/right80103dB
A
= 0 to -20 dB01dB
Total tracking error
V
-20 to -60 dB02dB
µV
µV
Bus inputs
V
V
V
1. Bass and treble response see attached diagram (Figure 19). The center frequency and quality of the resonance behavior
can be chosen by the external circuitry. A standard first order bass response can be realized by a standard feedback
network
2. The selected input is grounded through the 2.2 µF capacitor.
Input low voltage1V
IL
Input high voltage3V
IH
Input current-5+5µA
I
IN
Output voltage SDA acknowledge IO = 1.6 mA0.4V
O
9/20
Electrical specificationsTDA7303
2.5 Electrical characteristics curves
Figure 4.Loudness vs. volume attenuationFigure 5.Loudness vs. frequency (C
LOUD
100 nF) vs. volume attenuation
Figure 6.Loudness vs. external capacitorsFigure 7.Noise vs. volume/gain setting
=
Figure 8.Signal to noise ratio vs. volume
setting
10/20
Figure 9.Distortion and noise vs. frequency
(V
= 1 V)
IN
TDA7303Electrical specifications
Figure 10. Distortion and noise vs. frequency
(V
= 250 mV)
IN
Figure 12. Channel separation (L → R) vs.
frequency
Figure 11. Distortion vs. load resistance
Figure 13. Input separation (L1 → L2, L3) vs.
frequency
Figure 14. Supply voltage rejection vs.
frequency
Figure 15. Output clipping level vs. supply
voltage
11/20
Electrical specificationsTDA7303
Figure 16. Quiescent current vs. supply
Figure 17. Supply current vs. temperature
voltage
Figure 18. Bass resistance vs. temperatureFigure 19. Typical tone response (with the
external components indicated in
the test circuit)
12/20
TDA7303I2C bus interface
3 I2C bus interface
Data transmission from microprocessor to the TDA7303 and viceversa takes place through
the 2 wires I
positive supply voltage must be connected).
2
C bus interface, consisting of the two lines SDA and SCL (pull-up resistors to
3.1 Data validity
As shown in Figure 20, the data on the SDA line must be stable during the high period of the
clock. The high and low state of the data line can only change when the clock signal on the
SCL line is lOW.
3.2 Start and stop conditions
As shown in Figure 21 a start condition is a high to low transition of the SDA line while SCL
is high. The stop condition is a low to high transition of the SDA line while SCL is high.
3.3 Byte format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by
an acknowledge bit. The MSB is transferred first.
3.4 Acknowledge
The master (μP) puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse (see Figure 22). The peripheral (audioprocessor) that acknowledges has to pull-down
(low) the SDA line during the acknowledge clock pulse, so that the SDA line is stable low
during this clock pulse.
The audioprocessor which has been addressed has to generate an acknowledge after the
reception of each byte, otherwise the SDA line remains at the high level during the ninth
clock pulse time. In this case the master transmitter can generate the stop information in
order to abort the transfer.
3.5 Transmission without acknowledge
Avoiding to detect the acknowledge of the audioprocessor, the μP can use a simpler
transmission: simply it waits one clock without checking the slave acknowledging, and sends
the new data.
This approach of course is less protected from misreading and decreases the noise
immunity.
13/20
I2C bus interfaceTDA7303
Figure 20. Data validity on the I2C bus
SDA
SCL
DATA LINE
STABLE, DATA
VALID
Figure 21. Timing diagram of S-bus and I
SCL
SDA
CHANGE
DATA
ALLOWED
2
C bus
D99AU1031
2
I
CBUS
START
Figure 22. Acknowledge on the I
SCL
SDA
START
1
MSB
D99AU1032
2
C bus
23789
D99AU1033
STOP
ACKNOWLEDGMENT
FROM RECEIVER
Patent note:Purchase of I2C Components of STMicrolectronics,
conveys a license under the Philips I
use these components in an I
system conforms to the I
defined by Philips.
14/20
2
2
C system, provided that the
2
C Standard Specifications as
C Patent Rights to
TDA7303Software specification
4 Software specification
4.1 Interface protocol
The interface protocol comprises:
●A start condition (s)
●A chip address byte, containing the TDA7303 address (the 8th bit of the byte must be
0).
The TDA7303 must always acknowledge at the end of each transmitted byte.
For example attenuation of 25 dB on speaker RF is given by: 1 0 1 1 0 1 0 0
16/20
TDA7303Software specification
Table 10.Audio switch
MSBLSBFunction
0 1 0 G1G0S2S1S0 Audio Switch
00Stereo 1
01Stereo 2
10Stereo 3
11 Not allowed
0Loudness ON
1Loudness OFF
00+11.25 dB
01+7.5 dB
10+3.75d B
110 dB
For example to select the stereo 2 input with a gain of +7.5dB LOUDNESS ON the 8bit
string is: 0 1 0 0 1 0 0 1
Table 11.Bass and treble
MSBLSBFunction
0110C3C2C1C0Bass
0111C3C2C1C0Treble
0000-14
0001-12
0010-10
0011-8
0100-6
0101-4
0110-2
01110
11110
11102
11014
11006
10118
101010
100112
100014
C3 = Sign
For example Bass at -10dB is obtained by the following 8 bit string: 0 1 1 0 0 0 1 0
17/20
Package informationTDA7303
5 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
Figure 24. SO-28 mechanical data and package dimensions
DIM.
A2.650.104
a10.10.30.0040.012
b0.350.49 0.0140.019
b10.230.32 0.0090.013
C0.50.020
c145° (typ.)
D17.718.1 0.6970.713
E1010.65 0.3940.419
e1.270.050
e316.510.65
F7.47.6 0.2910.299
L0.41.27 0.0160.050
S8
mminch
MIN. TYP. MAX. MIN. TYP. MAX.
(max.)
°
OUTLINE AND
MECHANICAL DATA
SO-28
18/20
TDA7303Revision history
6 Revision history
Table 12.Document revision history
DateRevisionChanges
04-Aug-20061Initial release.
Updated “distortion” parameter in the Table 5: Electrical
characteristics on the page 9.
13-Mar-20092
18-Mar-20093
Modified the max. clock speed value in Section 4.1: Interface
protocol on page 15.
Updated Section 5: Package information on page 18.
Modified the test condition of the parameter “distortion” in the
Table 5: Electrical characteristics on the page 9.
19/20
TDA7303
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