ST STMPE1801 User Manual

18-bit enhanced port expander with keypad controller

Features

■ 18 GPIOs configurable as GPI, GPO, keypad

matrix, special key or dedicated key function

■ Operating voltage: 1.65 - 3.6 V

■ Hardware keypad controller (KPC)

(10 x 8 matrix with 4 optional dedicated keys maximum)

■ Keypad controller capable of detecting

keypress in hibernation mode

■ Interrupt output (open drain) pin

■ Advanced power management system

■ Ultra-low standby mode current

■ Programmable pull-up resistors for all GPIO

pins

■ ESD performance on GPIO pins:

– ± 8 kV human body model

(JESD22 A114-C)

■ ESD performance on V

SCL, SDA pins: – ± 3 kV human body model

(JESD22 A114-C)

, GND, INTB, R

STB

STMPE1801

Xpander Logic™

Flip-chip CSP 25

(2.03 x 2.03 mm)

Description

The STMPE1801 is a GPIO (general purpose input/output) port expander capable of interfacing a main digital ASIC via the two-line bidirectional

bus (I

C). A separate GPIO expander IC is often used in mobile multimedia platforms to resolve the problem of the limited number of GPIOs typically available on digital engines. The STMPE1801 offers high flexibility, as each I/O can be configured as input, output, special key, keypad matrix or dedicated key function. This device is designed to include very low quiescent current, and a wakeup feature for each I/O, to optimize the power consumption of the device. Potential applications for the STMPE1801 include portable media players, game consoles, mobile and smart phones.

Table 1. Device summary

Order code Package Packaging

STMPE1801BJR

March 2011 Doc ID 17884 Rev 3 1/60

Flip-chip CSP 25 (2.03 x 2.03 mm)

0.4 mm pitch

Tape and reel

www.st.com

Contents STMPE1801

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3 GPIO pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.2 Input/Output DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10

5 Register address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6 I2C specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1 I2C related pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.2 I2C addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.3 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.4 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.5 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.6 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.7 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.8 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.9 General call address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7 System controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.1 System level registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.2 States of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto-hibernate 20

7.2.2 . . . . . . . . . . . . . . . . . . . . . . . . Keypress detect in the Hibernate mode 21

2/60 Doc ID 17884 Rev 3

STMPE1801 Contents

8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocking system 22

8.0.1 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.0.2 Power mode programming sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9.1 Interrupt system register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

9.2 Interrupt latency for the GPIO hot keys . . . . . . . . . . . . . . . . . . . . . . . . . . 25

9.3 Programming sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

10 GPIO controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10.1 GPIO control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.1.1 Bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.2 Hotkey feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

10.2.1 Programming sequence for Hotkey . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

10.2.2 Minimum pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

11 Keypad controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

11.1 Keypad configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

11.2 Keypad controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

11.3 Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

11.4 Keypad combination key registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

11.5 Using the keypad controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

11.5.1 Ghost key handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

11.5.2 Key detection priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

11.5.3 Keypad wakeup from Hibernate mode . . . . . . . . . . . . . . . . . . . . . . . . . . 52

11.5.4 Keypad controller combination key interrupt . . . . . . . . . . . . . . . . . . . . . 52

12 Miscellaneous features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

12.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

13 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Doc ID 17884 Rev 3 3/60

Block diagram STMPE1801

1 Block diagram

Figure 1. STMPE1801 block diagram

'.$

234"

).4"

3#,

3$!

+EYPADCONTROLLER

-AIN&307-

'0)/CONTROL



)#

)NTERFACE

0/2

-58

+EYPADINPUT 2/72/7 '0)/

+EYPADOUTPUT #/,#/, '0)/ 

4/60 Doc ID 17884 Rev 3

STMPE1801 Pin settings

2 Pin settings

2.1 Pin connection

Figure 2. Pin connection (top-through view)

 

GPIO_14 GPIO9 GPIO2 GPIO7

RSTB

VCC

GPIO15 GPIO10 NC GPIO6

2.2 Pin description

Table 2. Pin description

Pin number Type Symbol Name and function

D4 I/O GPIO0 GPIO0/ROW0

C4 I/O GPIO1 GPIO1/ROW1

A4 I/O GPIO2 GPIO2/ROW2

E5 I/O GPIO3 GPIO3/ROW3

SDA GPIO16 GPIO1

GPIO17 GPIO0 GPIO4

SCL

INTB GND GPIO13 GPIO8 GPIO3

GPIO11

GPIO12

GPIO5

Flip-chip CSP 25

!-6

D5 I/O GPIO4 GPIO4/ROW4

C5 I/O GPIO5 GPIO5/ROW5

B5 I/O GPIO6 GPIO6/ROW6

A5 I/O GPIO7 GPIO7/ROW7

E4 I/O GPIO8 GPIO8/COL0

A3 I/O GPIO9 GPIO9/COL1

B3 I/O GPIO10 GPIO10/COL2

Doc ID 17884 Rev 3 5/60

Pin settings STMPE1801

Table 2. Pin description (continued)

Pin number Type Symbol Name and function

C3 I/O GPIO11 GPIO11/COL3

D3 I/O GPIO12 GPIO12/COL4

E3 I/O GPIO13 GPIO13/COL5

A2 I/O GPIO14 GPIO14/COL6

B2 I/O GPIO15 GPIO15/COL7

C2 I/O GPIO16 GPIO16/COL8

D2 I/O GPIO17 GPIO17/COL9

Open drain interrupt output pin. Programmable active low

E1 O INTB

A1 I RSTB

C1 A SDA I

D1 A SCL I2C clock. Fail safe

(a pull-up resistor is required) or active high (a pull-down resistor is required). Fail safe. Pull to V

if not in use.

External reset input. Active low. Fail safe. Reset pulse width must be more than 500 µs to be valid.

C data. Fail safe

B4 - NC No connect

B1 - V

E2 - GND Ground

2.3 GPIO pin functions

Table 3. GPIO pin function

Name Primary function Alternate function

GPIO0 GPIO Keypad row 0

GPIO1 GPIO Keypad row 1

GPIO2 GPIO Keypad row 2

GPIO3 GPIO Keypad row 3

GPIO4 GPIO Keypad row 4

GPIO5 GPIO Keypad row 5

GPIO6 GPIO Keypad row 6

GPIO7 GPIO Keypad row 7

GPIO8 GPIO Keypad column 0

GPIO9 GPIO Keypad column 1

Power supply

GPIO10 GPIO Keypad column 2

GPIO11 GPIO Keypad column 3

GPIO12 GPIO Keypad column 4

6/60 Doc ID 17884 Rev 3

STMPE1801 Pin settings

Table 3. GPIO pin function

Name Primary function Alternate function

GPIO13 GPIO Keypad column 5

GPIO14 GPIO Keypad column 6

GPIO15 GPIO Keypad column 7

GPIO16 GPIO Keypad column 8

GPIO17 GPIO Keypad column 9

The default function is always GPIO. As soon as the key scanning is enabled through the keypad registers, the function is then switched to the key function and then any configuration made in the GPIO registers is ignored.

Doc ID 17884 Rev 3 7/60

Maximum ratings STMPE1801

3 Maximum ratings

Stressing the device above the rating listed in the “absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

3.1 Absolute maximum ratings

Table 4. Absolute maximum ratings

Symbol Parameter Value Unit

Input voltage on GPIO pin 4.5 V

ESD

Supply voltage 4.5 V

Minimum ESD protection on each GPIO pin (HBM model - JESD22 A114-C)

ESD protection on other pins (HBM model -

JESD22 A114-C)

3.2 Thermal data

Table 5. Thermal data

Symbol Parameter Min Typ Max Unit

thJA

Thermal resistance junction-ambient – 100 – °C/W

Operating ambient temperature -40 25 85 °C

Operating junction temperature -40 25 125 °C

±8 kV

±3 kV

8/60 Doc ID 17884 Rev 3

STMPE1801 Electrical specification

4 Electrical specification

4.1 DC electrical characteristics

Table 6. DC electrical characteristics

Val ue

Symbol Parameter Test conditions

Min Typ Max

Unit

HIBERNATE

NTB

Supply voltage - 1.65

Active current (core and analog) - 1 key press

Hibernate current

Open drain output current

OL(max)

VCC=3.3 V

1.8 V − 28 55 µA

3.3 V

25 °C

1.8 V 85 °C

25 °C

3.3 V 85 °C

=0.45 V at

=1.8 V

=0.83 V at

− 90 140 µA

−−0.5

−−1

−−0.5

−−1

− 4 − mA

−

3.6 V

µA

Doc ID 17884 Rev 3 9/60

Electrical specification STMPE1801

4.2 Input/Output DC electrical characteristics

Table 7. I/O DC electrical characteristics

Val ue

Symbol Parameter Test conditions

= 1.8 V −−0.2 V

Low level input voltage

= 3.3 V −−0.2 V

VCC = 1.8 V 0.8 V

HYST

High level input voltage

Schmitt trigger hysteresis

Low level output voltage

High level output voltage

= 3.3 V 0.8 V

= 1.8 V − 0.10 −

= 3.3 V − 0.20 −

= 4 mA,

= 1.8 V

= 4 mA,

= 3.3 V

= -4 mA,

= 1.8 V

= -4 mA,

= 3.3 V

= 3.3 V.

Active implementation,

R value is determined by the

Equivalent pull-up

resistance

current measured at 0 V

= 1.8 V. Active

implementation, R value is

determined by the current measured at 0 V

Min Typ Max

−−

−−0.45

1.35

2.48

30 60 90

50 100 150

−−

Unit

kΩ

10/60 Doc ID 17884 Rev 3

STMPE1801 Register address

5 Register address

Table 8. STMPE1801 register summary table

Addres

00 CHIP_ID

01 VERSION_ID

02 SYS_CTRL System control No

04 INT_CTRL_LOW

05 INT_CTRL_HIGH RESERVED

06 INT_EN_MASK_LOW

07 INT_EN_MASK_HIGH RESERVED

08 INT_STA_LOW

09 INT_STA_HIGH RESERVED

0D INT_STA_GPIO_LOW

0E INT_STA_GPIO_MID

identification

Version

identification

Interrupt

control

Interrupt

enable mask

Interrupt status Yes

INT_EN_GPIO_MASK

_LOW

INT_EN_GPIO_MASK

_MID

INT_EN_GPIO_MASK

_HIGH

Interrupt

enable GPIO

Interrupt status

Chip

mask

GPIO

Auto-

increment

No 8-bit CHIP ID

No 8-bit VERSION ID

Ye s

76543210

SF_

RST

RESERVED IE4 IE3 IE2 IE1 IE0

IEG7IEG6IEG5IEG4IEG3IEG2IEG1IEG

IEG15IEG14IEG13IEG12IEG11IEG10IEG9IEG

ISG7ISG6ISG

ISG15ISG14ISG13ISG12ISG11ISG10ISG9ISG

RESERVED

RESERVED IC2 IC1 IC0

RESERVED

ISG4ISG3ISG2ISG1ISG

GPI

_DB

GPI

RSV

_DB

IEG17IEG

0F INT_STA_GPIO_HIGH RESERVED

10 GPIO_SET_LOW

11 GPIO_SET_MID IO15 IO14 IO13 IO12 IO11 IO10 IO9 IO8

12 GPIO_SET_HIGH RESERVED IO17 IO16

13 GPIO_CLR_LOW

14 GPIO_CLR_MID IO15 IO14 IO13 IO12 IO11 IO10 IO9 IO8

15 GPIO_CLR_HIGH RESERVED IO17 IO16

16 GPIO_MP_LOW

17 GPIO_MP_MID IO15 IO14 IO13 IO12 IO11 IO10 IO9 IO8

18 GPIO_MP_HIGH RESERVED IO17 IO16

GPIO set pin

state

GPIO clear pin

state

GPIO monitor

pin state

Doc ID 17884 Rev 3 11/60

Ye s

IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0

ISG17ISG

Table 8. STMPE1801 register summary table

Addres

19 GPIO_SET_DIR_LOW

1A GPIO_SET_DIR_MID IO15 IO14 IO13 IO12 IO11 IO10 IO9 IO8

1C GPIO_RE_LOW

1D GPIO_RE_MID IO15 IO14 IO13 IO12 IO11 IO10 IO9 IO8

1E GPIO_RE_HIGH RESERVED IO17 IO16

1F GPIO_FE_LOW

20 GPIO_FE_MID IO15 IO14 IO13 IO12 IO11 IO10 IO9 IO8

21 GPIO_FE_HIGH RESERVED IO17 IO16

23 GPIO_PULL_UP_MID IO15 IO14 IO13 IO12 IO11 IO10 IO9 IO8

30 KPC_ROW

GPIO set pin

direction

GPIO_SET_DIR_HIG

GPIO_PULL_UP_LO

GPIO_PULL_UP_HIG

GPIO rising

edge

GPIO falling

edge

GPIO pull up Yes

Keypad row

scanning

Auto-

increment

Ye s

76543210

IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0

RESERVED IO17 IO16

IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0

RESERVED IO17 IO16

ROW7ROW6ROW5ROW4ROW3ROW2ROW1RO

31 KPC_COL_LOW

32 KPC_COL_HIGH RESERVED

33 KPC_CTRL_LOW

34 KPC_CTRL_MID DB6 DB5 DB4 DB3 DB2 DB1 DB0

35 KPC_CTRL_HIGH

36 KPC_CMD

37 KPC_COMB_KEY_0

38 KPC_COMB_KEY_1 C4 C3 C2 C1 C0 R2 R1 R0

39 KPC_COMB_KEY_2 C4 C3 C2 C1 C0 R2 R1 R0

Keypad column

scanning

Key config:

Scan count and

dedicated key

Keypad

command

Keypad

combination

key mask

Ye s

Yes RESERVED

Ye s

COL7COL6COL5COL4COL3COL2COL1COL

COL9COL

SCAN_COUNT 0-3 DKEY 0-3

Rsv

B_K

C4 C3 C2 C1 C0 R2 R1 R0

RESERVED

SCAN_FR

KPC

SCA

_LC

12/60 Doc ID 17884 Rev 3

STMPE1801 Register address

Table 8. STMPE1801 register summary table

Addres

Auto-

increment

76543210

UP/

3A KPC_DATA_BYTE0

DWNC3 C2 C1 C0 R2 R1 R0

UP/

3B KPC_DATA_BYTE1

DWNC3 C2 C1 C0 R2 R1 R0

Keypad data Yes

UP/

3C KPC_DATA_BYTE2

DWNC3 C2 C1 C0 R2 R1 R0

3D KPC_DATA_BYTE3 SF7 SF6 SF5 SF4 SF3 SF2 SF1 SF0

3E KPC_DATA_BYTE4 RESERVED Dedicated Key 0 - 3

Doc ID 17884 Rev 3 13/60

I2C specification STMPE1801

6 I2C specification

The features supported by the I2C interface are listed below:

● I

C slave device

● Operates at V

● Compliant to Philips I

● Supports standard (up to 100 kbps) and fast (up to 400 kbps) modes

● 7-bit device addressing modes

● General call

● Start/Restart/Stop

6.1 I2C related pins

● SCL

● SDA

The device supports both 1.8 V I Vpullup at SCL and SDA externally is greater or equal to V

(1.8 - 3.6 V)

C specification version 2.1

C and 3.3 V I2C operations. It is recommended that

6.2 I2C addressing

The STMPE1801 7-bit addressing is set to 40h.

6.3 Start condition

A Start condition is identified by a falling edge of SDA while SCL is stable at high state. A Start condition must precede any data/command transfer. The device continuously monitors for a Start condition and does not respond to any transaction unless one is encountered.

The first byte is scanned after the START command is detected to check for device ID. Ensure that all state machines are flushed when START instruction is issued.

6.4 Stop condition

A Stop condition is identified by a rising edge of SDA while SCL is stable at high state. A Stop condition terminates the communication between the slave device and bus master. A read command that is followed by NoAck can be followed by a Stop condition to force the slave device into idle mode. When the slave device is in idle mode, it is ready to receive the

next I

C transaction. A Stop condition at the end of a write command stops the write

operation to the registers.

Once the Stop condition is detected, the device should release the bus and go to Hibernate mode if there is no more activity.

An I

C transaction with a START bit followed immediately by a STOP condition should not

cause any I

C lock-up.

14/60 Doc ID 17884 Rev 3

STMPE1801 I2C specification

6.5 Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter releases the SDA after sending eight bits of data. During the ninth bit, the receiver pulls the SDA low to acknowledge the receipt of the eight bits of data. The receiver may leave the SDA in high state if it does not acknowledge the receipt of the data.

6.6 Data input

The device samples the data input on SDA on the rising edge of the SCL. The SDA signal must be stable during the rising edge of SCL and the SDA signal must change only when SCL is driven low.

6.7 Memory addressing

For the bus master to communicate to the slave device, the bus master must initiate a Start condition and be followed by the slave device address. Accompanying the slave device address, there is a Read/Write bit (R/W operation.

If a match occurs on the slave device address, the corresponding device gives an acknowledgement on the SDA during the 9th bit time. If there is no match, it deselects itself from the bus by not responding to the transaction.

). The bit is set to 1 for Read and 0 for Write

6.8 Operation modes

Table 9. Operating modes

Mode Byte Programming sequence

Read ≥1

START, Device address, R/W =0, Register Address to be read

RESTART, Device Address, R/W =1, Data Read, STOP

If no STOP is issued, the Data Read can be continuously performed. If the register address falls within the range that allows address autoincrement, then register address auto-increments internally after every byte of data being read. For register address that fails within a nonincremental address range, the address is kept static throughout the entire read operation. Refer to Table 8.: STMPE1801 register summary

table for the address ranges that are auto-increment and non-increment.

An example of such a non-increment address is FIFO.

Doc ID 17884 Rev 3 15/60

I2C specification STMPE1801

Table 9. Operating modes

Mode Byte Programming sequence

START, Device Address, R/W =0, Register Address to be written, Data Write, STOP

If no STOP is issued, the Data Write can be continuously performed. If the register address falls within the range that allows address autoincrement, then register address auto-increment internally after every

Write ≥1

byte of data being written. For those register addresses that fall within a non-incremental address range, the address will be kept static throughout the entire write operation. Refer to Table 8.: STMPE1801

and non-increment. An example of a non-increment address is Data Port for initializing the PWM.

Figure 3. Operating modes

One B yte Read

6.9 General call address

A general call address is a transaction with the slave address of 0x00 and R/W =0. When a general call address is asserted, the STMPE1801 responds to this transaction with an acknowledgement and behaves as a slave-receiver mode. The meaning of a general call address is defined in the second byte sent by the master-transmitter.

Table 10. General call address

R/W

Second byte

value

0 0x06

0 0x00 Not allowed as second byte.

A 2-byte transaction in which the second byte tells the slave device to reset and write (or latch in) the 2-bit programmable part of the slave address.

Note: All other second byte values are ignored.

Definition

Doc ID 17884 Rev 3 17/60

System controller STMPE1801

7 System controller

7.1 System level registers

The system controller is the heart of the STMPE1801. It contains the registers for power control and chip identification.

The system registers are:

Address Register name

00 CHIP_ID

01 VERSION_ID

02 SYS_CTRL

CHIP_ID Chip identification register

76543 2 1 0

8-bit CHIP_ID

RRRRR R R R

11000 0 0 1

VERSION_ID Version identification register

76543 2 1 0

8-bit VERSION_ID

RRRRR R R R

00010 0 0 0

18/60 Doc ID 17884 Rev 3

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