ST STMPE1600 User Manual

STMPE1600

16-bit port expander with ultra-low power consumption Xpander Logic™

Preliminary data

Features

■16 GPIOs which default to 16 inputs on powerup

■Serial I2C interface (0 to 400 kHz) to the host with noise filter

■Operating voltage 1.65 V - 3.6 V

■I/O voltage 1.65 V - 3.6 V

■Interrupt output pin

■Internal power-on-reset

■Wakeup feature on each I/O

■Up to 8 devices sharing the same bus (3 address pins)

■8 mA current drive/sink on each GPIO at 3.3 V

■< 1µA suspend current

■ESD protection exceeds 2 KV HBM per JESD22-A114

■Latch-up testing exceeding 100 mA

■Package: QFN24 (4 x 4 mm with 0.5 mm pitch)

QFN24 (4 x 4 mm)

Description

The STMPE1600 is a GPIO (general purpose input/output) port expander able to interface a main digital ASIC via the two-line bidirectional bus (I2C). A separate GPIO expander IC is often used in mobile multimedia platforms to solve the problems of the limited amount of GPIOs typically available on the digital engine.

Applications

■Portable media players

■Game consoles

■Mobile phones

■Smart phones

Table 1. Device summary

I/O expanders provide a simple solution when additional I/O are needed for several interface functions such as sensors, pushbuttons, LEDs, fans, etc.

The STMPE1600 offers great flexibility as each I/O can be configured as input or output. The device has been designed with very low quiescent current and includes a wakeup feature for each I/O, to optimize the power consumption of the device.

Order code	Package	Packing
STMPE1600QTR	QFN24	Tape and reel
March 2010	Doc ID 16938 Rev 1		1/26
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to			www.st.com
change without notice.

STMPE1600 functional overview	STMPE1600

1 STMPE1600 functional overview

The STMPE1600 device consists of the following blocks:

–Main FSM GPIO controller

–I2C interface

–POR

–GPIOs

Figure 1. Block diagram

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	-AIN &3-
).4	'0)/
	CONTROLLER
		'0)/	'0)/
3#,+	) #
3$!4		0/2
!$$2
			6##
			!-6

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STMPE1600	STMPE1600 functional overview

1.1Pin assignment

Figure 2. QFN24 pin-mapping

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			1&.
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			MM PITCH
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	'0)/?	'0)/?	'.$	'0)/?	'0)/?	'0)/?

!-6

1.2Pin assignment (QFN24 package)

Table 2.	Pin assignment
Pin number		Name	Type	Function
1		GPIO_0	IO	GPIO 0
2		GPIO_1	IO	GPIO 1
3		GPIO_2	IO	GPIO 2
4		GPIO_3	IO	GPIO 3
5		GPIO_4	IO	GPIO 4
6		GPIO_5	IO	GPIO 5
7		GPIO_6	IO	GPIO 6
8		GPIO_7	IO	GPIO 7
9		GND	-	Ground connection
10		GPIO_8	IO	GPIO 8
11		GPIO_9	IO	GPIO 9

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STMPE1600 functional overview					STMPE1600
	Table 2.	Pin assignment
	Pin number		Name	Type	Function
	12		GPIO_10	IO	GPIO 10
	13		GPIO_11	IO	GPIO 11
	14		GPIO_12	IO	GPIO 12
	15		GPIO_13	IO	GPIO 13
	16		GPIO_14	IO	GPIO 14
	17		GPIO_15	IO	GPIO 15
	18		A0	I	I2C address 0. Up to 8 such devices can be addressed.
	19		SCL	I	I2C Clock. Fail-safe
	20		SDA	IO	I2C Data. Fail-safe
	21		VCC	-	Power supply for I2C and digital core and GPIOs
	22		INT	O	Interrupt output pin. Fail-safe
	23		A1	I	I2C address 1. Up to 8 such devices can be addressed.
	24		A2	I	I2C address 2. Up to 8 such devices can be addressed.

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STMPE1600

I2C block

2 I2C block

2.1I2C module

The STMPE1600 is interfaced to the main processor using an I2C bus.

2.1.1I2C address

The addressing scheme of STMPE1600 is designed to allow up to 8 devices to be connected to the same I2C bus. The slave device address is a 7-bit or 10-bit address where they are 42h, 43h, 44h, 45h, 46h, 47h, 48h and 49h (equivalent values in 7-bit and 10-bit addressing).

Figure 3. Addressing scheme

GND
VCC
SCL	SCL
SDA	SDA
	STMPE1600
	ADDR2,1,0

!-6

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I2C block						STMPE1600
	Table 3.	Eight programmable slave addresses
						Slave device address
	A2		A1		A0	(7-bit or 10-bit
						addressing)
	0		0		0	42h
	0		0		1	43h
	0		1		0	44h
	0		1		1	45h
	1		0		1	46h
	1		0		1	47h
	1		1		0	48h
	1		1		1	49h

For the bus master to communicate to the slave device, the bus master must initiate a Start condition and followed by the slave device address. Accompanying the slave device address, there is a Read/Write bit (R/W). The bit is set to 1 for Read and 0 for write operation.

If a match occurs on the slave device address, the corresponding device gives an acknowledge on the SDA during the 9th bit time. If there is no match, it deselects itself from the bus by not responding to the transaction.

Figure 4.	I2C timing
SDA
	tBUF		tHD:STA			tHD:STA
			tR	tF
SCL
				tHIGH	tSU:DAT	tSU:STA	tSU:STO
	P	S		tLOW	tHD:DAT	SR	P
							AI00589

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STMPE1600							I2C block
	Table 4.	I2C bus timing
	Symbol		Parameter	Min	Typ	Max		Uni
	fSCL		SCL clock frequency	0	–	400		kHz
	tLOW		Clock low period	1.3	–	–		µs
	tHIGH		Clock high period	600	–	–		ns
	tF		SDA and SCL fall time	–	–	300		ns
	tHD:STA		START condition hold time (after this	600	–	–		ns
			period the first clock is generated)
	tSU:STA		START condition setup time (only relevant	600	–	–		ns
			for a repeated start period)
	tSU:DAT		Data setup time	100	–	–		ns
	tHD:DAT		Data hold time	0	–	–		µs
	tSU:STO		STOP condition setup time	600	–	–		ns
	tBUF		Time the bus must be free before a new	1.3	–	–		µs
			transmission can start

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I2C features	STMPE1600

3 I2C features

The features that are supported by the I2C interface are as below:

–I2C slave device

–Operates from 1.65 V to 3.6 V

–Compliant to Philips I2C specification version 2.1

–Supports standard (up to 100Kbps) and fast (up to 400Kbps) modes

–7-bit and 10-bit device addressing modes with up to 8 slave device addresses

–General call

–Start/Restart/Stop

–Address up to 8 STMPE1600 devices via I2C

Start condition

A Start condition is identified by a falling edge of SDA while SCL is stable at high state. A Start condition must precede any data/command transfer. The device continuously monitors for a Start condition and will not respond to any transaction unless one is encountered.

Stop condition

A Stop condition is identified by a rising edge of SDA while SCL is stable at high state. A Stop condition terminates communication between the slave device and bus master. A read command that is followed by NoAck can be followed by a Stop condition to force the slave device into idle mode. When the slave device is in idle mode, it is ready to receive the next I2C transaction. A Stop condition at the end of a write command stops the write operation to registers.

Acknowledge bit

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter releases the SDA after sending eight bits of data. During the ninth bit, the receiver pulls the SDA low to acknowledge the receipt of the eight bits of data. The receiver may leave the SDA in high state if it would to not acknowledge the receipt of the data.

Data input

The device samples the data input on SDA on the rising edge of the SCL. The SDA signal must be stable during the rising edge of SCL and the SDA signal must change only when SCL is driven low.

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