ST STM8TL52G4, STM8TL52F4, STM8TL53C4, STM8TL53G4, STM8TL53F4 User Manual

STM8TL52G4 STM8TL52F4 STM8TL53C4 STM8TL53G4 STM8TL53F4

8-bit ultralow power touch sensing microcontroller with 16 Kbytes Flash, ProxSense™, timers, USART, SPI, I2C

Features

■Operating conditions

–Operating power supply: 1.65 V to 3.6 V

–Temperature range: –40 °C to 85 °C

■Low power features

–4 low power modes: Wait, Active-halt with AWU (1 µA), Active-halt with ProxSense™ (10 µA with scan every 200 ms),

Halt (0.4 µA)

–Dynamic power consumption: 150 µA/MHz

–Fast wakeup from Halt mode: 4.7 µs

–Ultralow leakage per I/O: 50 nA

■Advanced STM8 Core

–Harvard architecture with 3-stage pipeline

–Max freq.16 MHz,16 CISC MIPS peak

■Memories

–Up to 16 Kbytes of Flash program including up to 2 Kbytes of data EEPROM

–Error correction code (ECC)

–Flexible write and read protection modes

–In-application and in-circuit programming

–Data EEPROM capability

–4 Kbytes of static RAM

■Clock management

–Internal 16 MHz factory-trimmed RC

–Internal 38 kHz low consumption RC driving both the IWDG and the AWU

■Reset and supply management

–Ultralow power, ultrasafe power-on reset/ power-down reset

■Interrupt management

Datasheet production data

5&1&0.		5&1&0.			433/0
X MM		X XMM

■I/Os

–Up to 23 with 22 mappable on external interrupt vectors

–I/Os with programmable input pull-ups, high sink/source capability

■ProxSense™ patented acquisition technology with up to 300 touch sensing channels (20 receiver/transmitter channels and 15 transmitter channels) supporting projected capacitive acquisition method suitable for proximity detection.

■Timers

–Two 16-bit general purpose timers (TIM2 and TIM3) with up and down counter and 2 channels (used as IC, OC, PWM)

–One 8-bit timer (TIM4) with 7-bit prescaler

–Independent watchdog

–Window watchdog

–Auto-wakeup unit

–Beeper timer with 1, 2 or 4 kHz frequencies

■Communication interfaces

–SPI synchronous serial interface

–Fast I2C Multimaster/slave 400 kHz

–USART with fractional baud rate generator

–Nested interrupt controller with software priority control

–Up to 22 external interrupt sources

■Development support

–Hardware single wire interface module (SWIM) for fast on-chip programming and non intrusive debugging

–In-circuit emulation (ICE)

April 2012

Doc ID 022344 Rev 2

1/77

This is information on a product in full production.

www.st.com

STM8TL5xxx	Contents

Contents

1	Introduction		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 6
2	Description . .		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 7
3	Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. 9
	3.1	Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		10
	3.2	Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
	3.3	Single wire data interface (SWIM) and debug module . . . . . . . . . . . . . . .		11
	3.4	Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
	3.5	Memory	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
	3.6	Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		12
	3.7	Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		12
		3.7.1	Dual-mode voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
		3.7.2	ProxSense voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
	3.8	Clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		12
	3.9	Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
	3.10	Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
	3.11	Auto-wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
	3.12	General purpose and basic timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
	3.13	Beeper .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	3.14	USART .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
	3.15	SPI . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
	3.16	I2C . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
	3.17	ProxSense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		14
	3.18	TouchSensing dedicated library available upon request . . . . . . . . . . . . .		15
4	Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			16
5	Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			24
6	Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			34
7	Option bytes		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	36

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Contents STM8TL5xxx

8	Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	38
9	Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39
	9.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39

9.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.2	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		40
9.3	Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		41
	9.3.1	General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	41
	9.3.2	Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	42
	9.3.3	Power-up / power-down operating conditions . . . . . . . . . . . . . . . . . . . .	42
	9.3.4	Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	43
	9.3.5	Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	47
	9.3.6	Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	50
	9.3.7	I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	52
	9.3.8	Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	60
	9.3.9	EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	64

9.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

10	Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		67
	10.1	ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 67
	10.2	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	67
11	Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		73
12	STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		74

12.1 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

12.1.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 12.1.2 STM-STUDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.1.3 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

12.2 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

13

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

76

3/77	Doc ID 022344 Rev 2

STM8TL5xxx	List of tables

List of tables

Table 1. Device features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Legends/abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 3. STM8TL5xxx pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 4. I/O Port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 5. General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 6. CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 7. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 8. Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 9. Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 10. Unique ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 11. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 12. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 13. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 14. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 15. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 16. Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 17. Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 18. Total current consumption in Halt mode and Active-halt mode

VDD = 1.65 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 19. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 20. ProxSense peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 21. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 22. HSI_PXS oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 23. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 24. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 25. Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 26. Program memory endurance & retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 27. Data memory endurance & retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 28. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 29. Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 30. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 31. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 32. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 33. EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 34. EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 35. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 36. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 37. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 38. UFQFPN48 - 48-lead ultra thin fine pitch quad flat no-lead package (7x7),

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 39. UFQFPN28 - 28-lead ultra thin fine pitch quad flat no-lead package (4x4),

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 40. TSSOP20 - 20-pin thin shrink small outline package mechanical data . . . . . . . . . . . . . . . 71 Table 41. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

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List of figures	STM8TL5xxx

List of figures

Figure 1.	STM8TL5xxx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 9
Figure 2.	STM8TL53 48-pin UFQFPN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
Figure 3.	STM8TL53G4U6 28-pin UFQFPN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
Figure 4.	STM8TL52G4U6 28-pin UFQFPN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
Figure 5.	STM8TL53F4P6 TSSOP20 20-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
Figure 6.	STM8TL52F4P6 TSSOP20 20-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
Figure 7.	Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
Figure 8.	Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
Figure 9.	Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39
Figure 10.	Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40
Figure 11.	Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	42
Figure 12.	IDD(RUN) vs. VDD, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	43
Figure 13.	IDD(Wait) vs. VDD. fCPU = 16 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	44
Figure 14.	Typ. IDD(Halt) vs. VDD. fCPU = 2 MHz and 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	45
Figure 15.	Typical HSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 47
Figure 16.	Typical HSI accuracy vs. temperature, VDD = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	48
Figure 17.	Typical HSI_PXS frequency vs. VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
Figure 18.	Typical LSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	50
Figure 19.	Typical pull-up resistance RPU vs. VDD with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . .	52
Figure 20.	Typical VIL and VIH vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	53
Figure 21.	Typ. VOL at VDD = 1.8 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	55
Figure 22.	Typ. VOL at VDD = 3.0 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	55
Figure 23.	Typ. VDD - VOH at VDD = 1.8 V(standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	56
Figure 24.	Typ. VDD - VOH at VDD = 3.0 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	56
Figure 25.	Typ. VDD - VOH at VDD = 1.8 V (ProxSense_TX ports). . . . . . . . . . . . . . . . . . . . . . . . . . . .	57
Figure 26.	Typ. VDD - VOH at VDD = 1.8V (ProxSense RX ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . .	57
Figure 27.	Typical NRST pull-up resistance RPU vs. VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	58
Figure 28.	Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	59
Figure 29.	SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	61
Figure 30.	SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	61
Figure 31.	SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	62
Figure 32.	Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . .	64
Figure 33.	UFQFPN48 - 48-lead ultra thin fine pitch quad flat no-lead package
	outline (7x7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	67
Figure 34.	UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	68
Figure 35.	UFQFPN28 - 28-lead ultra thin fine pitch quad flat no-lead package
	outline (4x4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	69
Figure 36.	UFQFPN28 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	70
Figure 37.	TSSOP20 - 20-pin thin shrink small outline package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	71
Figure 38.	TSSOP20 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	72
Figure 39.	STM8TL5xxx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	73

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STM8TL5xxx		Introduction
1	Introduction
	This datasheet provides the STM8TL52G4, STM8TL52F4, STM8TL53C4, STM8TL53G4
	and STM8TL53F4 pinouts, ordering information, mechanical and electrical device
	characteristics.
	For complete information on the microcontroller memory, registers and peripherals, please
	refer to the STM8TL5xxx reference manual (RM0312) and to the STM8TL5xxx Flash
	programming manual (PM0212) for Flash memory related information. For information on
	the debug module and SWIM (single wire interface module), refer to the STM8 SWIM
	communication protocol and debug module user manual (UM0470). For information on the
	STM8 core, refer to the STM8 CPU programming manual (PM0044).
	All devices of the STM8TL5xxx product line provide the following benefits:
	●	Advanced capacitive sensing
		– Patented ProxSense ™ acquisition peripheral, providing high-end acquisition,
		filtering and environment adaptation
		– Outstanding signal-to-noise ratio for touch and proximity sensing
		– Up to 300 projected capacitive channels
	●	Reduced system cost
		– Up to 16 Kbytes of low-density embedded Flash program memory including up to
		2 Kbytes of data EEPROM
		– High system integration level with internal clock oscillators and watchdogs
		– Smaller battery and cheaper power supplies
	● Low power consumption and advanced features
		– Up to 16 MIPS at 16 MHz CPU clock frequency
		– Less than 150 µA/MHz, 0.8 µA in Active-halt mode with AWU, and 0.3 µA in Halt
		mode
		– Clock gated system and optimized power management
	●	Short development cycles
		– Application scalability across a common family product architecture with
		compatible pinout, memory map and modular peripherals
		– Full documentation and a wide choice of development tools
	●	Product longevity
		– Advanced core and peripherals made in a state-of-the-art technology
		– Product family operating from 1.65 V to 3.6 V supply
Note:	ProxSense ™ is a trademark of Azoteq (Pty) Ltd.

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Description	STM8TL5xxx

2 Description

The STM8TL5xxx devices feature the enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations. It uses a ProxSense charge transfer capacitive acquisition method that is capable of near range proximity detection.

The family includes an integrated debug module with a hardware interface (SWIM) which allows non-intrusive in-application debugging and ultrafast Flash programming. All STM8TL5xxx microcontrollers feature low power low-voltage single-supply program Flash memory.

The STM8TL5xxx are based on a generic set of state-of-the-art peripherals. The modular design of the peripheral set allows the same peripherals to be found in different ST microcontroller families including 32-bit families. This makes any transition to a different family very easy, and simplified even more by the use of a common set of development tools.

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STM8TL5xxx									Description
Table 1.		Device features
Features			STM8TL52F4		STM8TL53F4	STM8TL52G4		STM8TL53G4	STM8TL53C4
Flash (Kbytes)						16
Data EEPROM						2
(Kbytes)
RAM (Kbytes)						4
		Basic				1 (8-bit)
Timers
		General				2 (16-bit)
		purpose
Communi		SPI				1
cation		I2C				1
Interfaces
		USART				1
GPIOs				12			17		23
			Up to 12 touch		Up to 30 touch	Up to 25 touch		Up to 72 touch	Up to 300 touch
			sensing		sensing	sensing		sensing	sensing
			channels		channels	channels		channels	channels
ProxSense			(5 receiver/		(5 receiver/	(8 receiver/		(8 receiver/	(20 receiver/
			transmitter		transmitter	transmitter		transmitter	transmitter
			channels and 2		channels and 6	channels and 2		channels and 9	channels and 15
			transmitter		transmitter	transmitter		transmitter	transmitter
			channels)		channels)	channels)		channels)	channels)
Others			Window watchdog, independent watchdog, two 16-MHz and one 38-kHz internal RC, auto-
					wakeup counter, beeper
CPU frequency						16 MHz
Operating voltage						1.65 to 3.6 V
Operating						-40 to +85 °C
temperature
Packages			TSSOP20			UFQFPN28			UFQFPN48

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Product overview	STM8TL5xxx

3 Product overview

Figure 1. STM8TL5xxx block diagram

				@VDD
	16 MHz internal	Clock		Power	VDD = 1.65 V
	RC	Controller	VDD18	Voltage reg.	to 3.6 V
	38 kHz internal	and			VSS
		CSS
	RC
				Supply supervisor
			PDR	POR/PDR	NRST
	STM8 core		Clocks
			to core and
			peripherals
	Nested interrupt controller
	Up to 22 external interrupts			16 Kbytes
				program memory
	Debug module			+BYTES
	(SWIM)	bases		$ATA %02/-
PXS_VREG	Voltage reg.
PXS_RX(0a..9a, 0b..9b)				4 Kbytes RAM
		data
PXS_TX(0..14)	ProxSense			AWU
PXS_RFIN
PXS_TRIG		and		(38 kHz clock)
	16 MHz dedicated			IWDG
	internal RC	control
SCL, SDA	I2C			(38 kHz clock)
				WWDG
MOSI, MISO, SCK, NSS	SPI	Address,
RX, TX, CK	USART			Beeper	BEEP
	16-bit timer 2
				Port A	PA[7:0]
	16-bit timer 3			Port B	PB[6:0]
	8-bit timer 4			Port D	PD[7:0]

MS19122V3

Legend:

AWU: Auto-wakeup unit

Int. RC: internal RC oscillator

I²C: Inter-integrated circuit multimaster interface

POR/PDR: Power on reset / power down reset

SPI: Serial peripheral interface

SWIM: Single wire interface module

USART: Universal synchronous / asynchronous receiver / transmitter

IWDG: Independent watchdog

WWDG: Window watchdog

ProxSense™: capacitive sensing peripheral

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STM8TL5xxx	Product overview

3.1Central processing unit STM8

The 8-bit STM8 core is designed for code efficiency and performance with an Harvard architecture and a 3-stage pipeline.

It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing, and 80 instructions.

Architecture and registers

●Harvard architecture

●3-stage pipeline

●32-bit wide program memory bus - single cycle fetching most instructions

●X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify - write type data manipulations

●8-bit accumulator

●24-bit program counter - 16 Mbytes linear memory space

●16-bit stack pointer - access to a 64 Kbytes level stack

●8-bit condition code register - 7 condition flags for the result of the last instruction

Addressing

●20 addressing modes

●Indexed indirect addressing mode for lookup tables located anywhere in the address space

●Stack pointer relative addressing mode for local variables and parameter passing

Instruction set

●80 instructions with 2-byte average instruction size

●Standard data movement and logic/arithmetic functions

●8-bit by 8-bit multiplication

●16-bit by 8-bit and 16-bit by 16-bit division

●Bit manipulation

●Data transfer between stack and accumulator (push/pop) with direct stack access

●Data transfer using the X and Y registers or direct memory-to-memory transfers

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Product overview	STM8TL5xxx

3.2Development tools

Development tools for the STM8 microcontrollers include:

●The STICE advanced in-circuit emulation system offering tracing and code profiling

●The STVD high-level language debugger including C compiler, assembler and integrated development environment

●The STVP Flash programming software

●The STM-STUDIO real-time and non-intrusive graphical interface used to probe application variables and data

The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools.

3.3Single wire data interface (SWIM) and debug module

The debug module with its single wire data interface (SWIM) permits non-intrusive real-time in-circuit debugging and fast memory programming.

The Single wire interface is used for direct access to the debugging module and memory programming. The interface can be activated in all device operation modes.

The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers.

3.4Interrupt controller

The STM8TL5xxx features a nested vectored interrupt controller:

●Nested interrupts with 3 software priority levels

●22 interrupt vectors with hardware priority

●Up to 22 external interrupt sources on 10 vectors

●TRAP and RESET interrupts

3.5Memory

The STM8TL5xxx devices have the following main features:

●4 Kbytes of RAM

●The EEPROM is divided into two memory arrays (see the STM8TL5xxx reference manual (RM0312) for details on the memory mapping):

–16 Kbytes of low-density embedded Flash program including up to 2 Kbytes of data EEPROM. Data EEPROM and Flash program areas can be write protected independently by using the memory access security mechanism (MASS).

–64 option bytes (one block) of which 5 bytes are already used for the device.

–Error correction code is implemented on the EEPROM.

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STM8TL5xxx	Product overview

3.6Low power modes

To minimize power consumption, the product features three MCU low power modes:

●Wait mode: CPU clock stopped, selected peripherals at full clock speed.

●Active-halt mode:

–When wakeup time is programmed in the AWU unit, the CPU and peripheral clocks are stopped. The RAM content is preserved.

–When a ProxSense acquisition is ongoing, the wakeup is on ProxSense interrupts; the CPU and the other peripheral clocks are stopped.

●Halt mode: CPU and peripheral clocks are stopped, the device remains powered on. Wakeup is triggered by an external interrupt.

The ProxSense peripheral can return to low power mode between each conversion. The ProxSense acquisition can be operated in Run, Wait and Active-halt modes.

3.7Voltage regulators

The STM8TL5xxx devices embed an internal voltage regulator for generating the 1.8 V power supply for the core and peripherals and a second internal voltage regulator providing a stable power supply (around 1.45V) for the ProxSense peripheral.

3.7.1Dual-mode voltage regulator

This regulator has two different modes: main voltage regulator mode (MVR) and low power voltage regulator mode (LPVR). When in Active-halt mode, the regulator remains in MVR if ProxSense is active. When entering Halt or Active-halt modes, the system automatically switches from the MVR to the LPVR in order to reduce current consumption unless ProxSense is enabled.

3.7.2ProxSense voltage regulator

This regulator provides a very stable voltage to power the ProxSense peripheral including ProxSense pins in order to be independent of any power supply variations. This regulator is switched on while the ProxSense peripheral is enabled (bit PXSEN = 1) and bit LOW_POWER is set to ‘0’ in register PXS_CR1. Otherwise, when LOW_POWER is set to ‘1’, this regulator is only enabled during conversions (while CIPF = 1 and SYNCPF = 0).

3.8Clock control

The STM8TL5xxx embeds a robust clock controller. It is used to distribute the system clock (SYSCLK) to the core and the peripherals and to manage clock gating for low power modes. This system clock is a 16-MHz High Speed Internal RC oscillator (HSI RC), followed by a programmable prescaler.

In addition, a 38 kHz low speed internal RC oscillator is used by the Independent watchdog (IWDG) and Auto-wakeup unit (AWU).

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Product overview	STM8TL5xxx

3.9Independent watchdog

The independent watchdog (IWDG) peripheral can be used to resolve processor malfunctions due to hardware or software failures.

It is clocked by the 38 kHz LSI internal RC clock source, and thus stays active even in case of a CPU clock failure.

3.10Window watchdog

The window watchdog (WWDG) is based on a 7-bit downcounter that can be set as freerunning. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

3.11Auto-wakeup counter

The auto-wakeup (AWU) counter is used to wakeup the device from Active-halt mode.

3.12General purpose and basic timers

STM8TL5xxx devices contain two 16-bit general purpose timers (TIM2 and TIM3) and one 8-bit basic timer (TIM4).

16-bit general purpose timers

The 16-bit timers consist of 16-bit up/down auto-reload counters driven by a programmable prescaler. They perform a wide range of functions, including:

●Timebase generation

●Measuring the pulse lengths of input signals (input capture)

●Generating output waveforms (output compare, PWM and One pulse mode)

●Interrupt capability on various events (capture, compare, overflow, break, trigger)

●Synchronization with other timers or external signals (external clock, reset, trigger and enable)

8-bit basic timer

The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. It can be used for timebase generation with interrupt generation on timer overflow.

3.13Beeper

STM8TL5xxx devices include a beeper function used to generate a beep signal in the range of 1, 2 or 4 kHz when the LSI clock is operating at a frequency of 38 kHz.

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STM8TL5xxx	Product overview

3.14USART

The USART interface (USART) allows full duplex, asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format. It offers a very wide range of baud rates.

●1 Mbit/s full duplex SCI

●SPI emulation

●High precision baud rate generator

●Single wire half duplex mode

3.15SPI

The serial peripheral interface (SPI) provides half/ full duplex synchronous serial communication with external devices.

●Maximum speed: 8 Mbit/s (fSYSCLK/2) both for master and slave

●Full duplex synchronous transfers

●Simplex synchronous transfers on 2 lines with a possible bidirectional data line

●Master or slave operation - selectable by hardware or software

●Hardware CRC calculation

●Slave/master selection input pin

3.16I2C

The I2C bus interface (I2C) provides multi-master capability, and controls all I2C bus-specific sequencing, protocol, arbitration and timing.

●Master, slave and multi-master capability

●Dual addressing mode capability

●Standard mode up to 100 kHz and fast speed modes up to 400 kHz

●7-bit and 10-bit addressing modes

●Hardware CRC calculation

3.17ProxSense

The ProxSense peripheral uses a charge-transfer method to detect capacitance changes.

●Up to 300 capacitive sensing channels composed of 15 transmitters and 20 receivers with up to 10 Rx channels acquired in parallel

●Fast acquisition with a typical scan time of 250 µs for 10 Rx channels

●Configurable internal sampling capacitor (CS)

●Electrode Parasitic Capacitance Compensation (EPCC) to ensure the best sensitivity in all user environments

●RF noise detection, allowing to reject corrupted samples

●External trigger to de-synchronize the acquisition from known noise

●Can be configured to return to low power mode between each conversion

●Acquisition possible in Run, Wait and Active-halt modes

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Product overview	STM8TL5xxx

3.18TouchSensing dedicated library available upon request

●Complete C source code library with firmware examples (MISRA compliant)

●Multifunction capability to combine capacitive sensing functions with traditional MCU features

●Compatible with proximity, touchkey, linear and rotary touch sensor implementation

●Configuration of all ProxSense parameters

●Extra filtering and calibration functions

●TouchSensing user interface through firmware API for status reporting and application configuration

●Compliance with Cosmic, IAR and Raisonance C compilers

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STM8TL5xxx	Pin description

4 Pin description

Figure 2. STM8TL53 48-pin UFQFPN package pinout

083?48

083?48

083?48

083?48

083?484)-?42)'

083?484)-?42)'

083?484)-?#(

083?484)-?#(

083?484)-?#(

083?484)-?#(

0"(3

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;4)- ?#( = 53!24?#+ 30)?3#+ (3 0!

0$ (3 083?48

) #?3$! 53!24?48 30)?-)3/ (3 0!

083?28 B

) #?3#, 53!24?28 30)?-/3) (3 0!

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083?28A

083?28B

083?28A

083?28B

083?28A

083?28B

083?28A

083?28B

083?28A

083?28B

083?28A

083?28B

-3 6

1.HS corresponds to 20 mA high sink/source capability.

2.Power supply pins must be correctly decoupled with capacitors near the pins. Please refer to the power supply circuitry details in Section 9.3.2: Power supply on page 42 and the STM8TL5xxx reference manual (RM0312), Section 6: Power supply.

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Pin description

STM8TL5xxx

Figure 3. STM8TL53G4U6 28-pin UFQFPN package pinout

30)?.33;4)-?#( ]

37)- "%%0

083?484)-?42)'

083?48 4)-?#(

083?484)-?#(

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083?42)'(3 0!	083?2&). (3 0!	083?28A	083?28A	083?28A	083?28A	083?28A
#,+?##/

MS19100V1

1.HS corresponds to 20 mA high sink/source capability.

2.Power supply pins must be correctly decoupled with capacitors near the pins. Please refer to the power supply circuitry details in Section 9.3.2: Power supply on page 42 and the STM8TL5xxx reference manual (RM0312), Section 6: Power supply.

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STM8TL5xxx

Pin description

Figure 4. STM8TL52G4U6 28-pin UFQFPN package pinout

?#( ]

30)?.33;4)-

37)-"%%0

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MS30312V1

1.HS corresponds to 20 mA high sink/source capability.

2.Power supply pins must be correctly decoupled with capacitors near the pins. Please refer to the power supply circuitry details in Section 9.3.2: Power supply on page 42 and the STM8TL5xxx reference manual (RM0312) Section 6: Power supply.

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Pin description	STM8TL5xxx

Figure 5. STM8TL53F4P6 TSSOP20 20-pin package pinout

TIM3_TRIG/PXS_TX8/(HS)PB0			1	20			PD6(HS)/PXS_TX6/TIM3_CH1
BEEP/SWIM/(HS)PA0
			2	19			PD5(HS)/PXS_TX5/TIM2_CH2
[TIM3_CH1]/SPI_NSS/(HS)PA1
			3	18			PD4(HS)/PXS_TX4/TIM2_CH1
[TIM3_CH2]/USART_CK/SPI_SCK/(HS)PA2			4	17			PD1(HS)/PXS_TX1
I2C_SDA/USART_TX/SPI_MISO/(HS)PA3			5	16			PD0(HS)/PXS_TX0
I2C_SCL/USART_RX/SPI_MOSI/(HS)PA4			6	15			PXS_RX7a
VDD			7	14			PXS_RX6a
VSS			8	13			PXS_RX2a
PXS_VREG			9	12			PXS_RX1a
NRST/(HS)PA5			10	11			PXS_RX0a

1.HS corresponds to 20 mA high sink/source capability.

2.Power supply pins must be correctly decoupled with capacitors near the pins. Please refer to the power supply circuitry details in Section 9.3.2: Power supply on page 42 and the STM8TL5xxx reference manual (RM0312) Section 6: Power supply.

Figure 6. STM8TL52F4P6 TSSOP20 20-pin package pinout

TIM3_TRIG/(HS)PB0			1	20			PD6(HS)/TIM3_CH1
BEEP/SWIM/(HS)PA0
			2	19			PD5(HS)/TIM2_CH2
[TIM3_CH1]/SPI_NSS/(HS)PA1
			3	18			PD4(HS)/TIM2_CH1
[TIM3_CH2]/USART_CK/SPI_SCK/(HS)PA2			4	17			PD1(HS)/PXS_TX1
I2C_SDA/USART_TX/SPI_MISO/(HS)PA3			5	16			PD0(HS)/PXS_TX0
I2C_SCL/USART_RX/SPI_MOSI/(HS)PA4			6	15			PXS_RX7a
VDD			7	14			PXS_RX6a
VSS			8	13			PXS_RX2a
PXS_VREG			9	12			PXS_RX1a
NRST/(HS)PA5			10	11			PXS_RX0a

1.HS corresponds to 20 mA high sink/source capability.

2.Power supply pins must be correctly decoupled with capacitors near the pins. Please refer to the power supply circuitry details in Section 9.3.2: Power supply on page 42 and the STM8TL5xxx reference manual (RM0312) Section 6: Power supply.

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STM8TL5xxx

Pin description

Table 2.

Legends/abbreviations

Type

I = input, O = output, S = power supply

Level

Input

FT = 5 V tolerant, TC = 3 V capable

Output

HS = high sink/source (20 mA)

Port and control

Input

float = floating, wpu = weak pull-up

configuration

Output

T = true open drain, OD = open drain, PP = push-pull

Bold X (pin state after reset release).

Reset state

Unless otherwise specified, the pin state is the same during the reset phase

(i.e. “under reset”) and after internal reset release (i.e. at reset state).

Table 3.

STM8TL5xxx pin description

Pin no.

Input

Output

Alternate function

functionMain (afterreset)

UFQFPN48

UFQFPN28

TSSOP20

Pin name

Type

Level

floating

wpu

interruptExt.

sink/sourceHigh

OD

PP

Default

Remap

1

PB6/ PXS_TX14

I/O

TC

X

X

X

HS

X

X

Port B6

ProxSense

transmit 14

Port A0(1)

PA0(1)/SWIM/

2

27

2

I/O

TC

X

X

X

HS

X

X

SWIM

SWIM input and

BEEP

output

Beep output

PA1/SPI_NSS/

SPI master/

Timer 3 -

3

28

3

I/O

FT

X

X

X

HS

X

X

Port A1

channel

[TIM3_CH1]

slave select

1

PA2/SPI_SCK/

SPI clock

Timer 3 -

X

Port A2

USART

4

1

4

USART_CK/

I/O

FT

X

X

HS

X

X

channel

[TIM3_CH2](2)

synchronous

2

clock

SPI master in/

PA3/SPI_MISO/

slave out

5

2

5

USART_TX/

I/O

FT

X

X

X

HS

X

X

Port A3

USART transmit

I2C_SDA(2)

I2C data

SPI master out/

PA4/SPI_MOSI/

slave in

6

3

6

USART_RX/

I/O

FT

X

X

X

HS

X

X

Port A4

USART receive

I2C_SCL

I2C clock

Digital

7

4

7

VDD

S

power

supply

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Pin description

STM8TL5xxx

Table 3.

STM8TL5xxx pin description (continued)

Pin no.

Input

Output

Alternate function

functionMain (afterreset)

UFQFPN48

UFQFPN28

TSSOP20

Pin name

Type

Level

floating

wpu

interruptExt.

sink/sourceHigh

OD

PP

Default

Remap

8

5

8

VSS

S

Digital

ground

ProxSense

voltage

9

6

9

PXS_VREG

S

regulator

External

decoupling

capacitor

10

7

10

PA5/NRST(3)

I/O

TC

HS

X

X

Reset

Port A5 (output

only)

ProxSense

PA6/ PXS_TRIG/

external trigger

11

8

I/O

FT

X

X

X

HS

X

X

Port A6

input

CLK_CCO

CLK clock

output

12

9

PA7/PXS_RFIN

I/O

TC

X

X

X

HS

X

X

Port A7

ProxSense

antenna input

13

10

11

PXS_RX0a

PXS_RX0a

ProxSense

receiver 0a

14

PXS_RX0b

PXS_RX0b

ProxSense

receiver 0b

15

11

12

PXS_RX1a

PXS_RX1a

ProxSense

receiver 1a

16

PXS_RX1b

PXS_RX1b

ProxSense

receiver 1b

17

12

13

PXS_RX2a

PXS_RX2a

ProxSense

receiver 2a

18

PXS_RX2b

PXS_RX

ProxSense

receiver 2b

19

13

PXS_RX3a

PXS_RX3a

ProxSense

receiver 3a

20

PXS_RX3b

PXS_RX3b

ProxSense

receiver 3b

21

14

PXS_RX4a

PXS_RX4a

ProxSense

receiver 4a

22

PXS_RX4b

PXS_RX4b

ProxSense

receiver 4b

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Doc ID 022344 Rev 2

STM8TL5xxx

Pin description

Table 3.

STM8TL5xxx pin description (continued)

Pin no.

Input

Output

Alternate function

functionMain (afterreset)

UFQFPN48

UFQFPN28

TSSOP20

Pin name

Type

Level

floating

wpu

interruptExt.

sink/sourceHigh

OD

PP

Default

Remap

23

15

PXS_RX5a

PXS_RX5a

ProxSense

receiver 5a

24

PXS_RX5b

PXS_RX5b

ProxSense

receiver 5b

25

16

14

PXS_RX6a

PXS_RX6a

ProxSense

receiver 6a

26

PXS_RX6b

PXS_RX6b

ProxSense

receiver 6b

27

17

15

PXS_RX7a

PXS_RX7a

ProxSense

receiver 7a

28

PXS_RX7b

PXS_RX7b

ProxSense

receiver 7b

29

PXS_RX8a

PXS_RX8a

ProxSense

receiver 8a

30

PXS_RX8b

PXS_RX8b

ProxSense

receiver 8b

31

PXS_RX9a

PXS_RX9a

ProxSense

receiver 9a

32

PXS_RX9b

PXS_RX9b

ProxSense

receiver 9b

33

18

16

PD0/PXS_TX0

I/O

TC

X

X

X

HS

X

X

Port D0

ProxSense

transmitter 0

34

19

17

PD1/PXS_TX1

I/O

TC

X

X

X

HS

X

X

Port D1

ProxSense

transmitter 1

35

20

PD2/PXS_TX2(4)

I/O

TC

X

X

X

HS

X

X

Port D2

ProxSense

transmitter 2(4)

36

21

PD3/PXS_TX3(4)

I/O

TC

X

X

X

HS

X

X

Port D3

ProxSense

transmitter 3(4)

37

VSSIO

S

IOs ground

38

VDDIO

S

IOs power

supply

ProxSense

(4)

transmitter 4(4)

39

22

18

PD4/PXS_TX4

I/O

TC

X

X

X

HS

X

X

Port D4

/ TIM2_CH1

Timer 2 -

channel 1

Doc ID 022344 Rev 2

22/77

Pin description

STM8TL5xxx

Table 3.

STM8TL5xxx pin description (continued)

Pin no.

Input

Output

Alternate function

functionMain (afterreset)

UFQFPN48

UFQFPN28

TSSOP20

Pin name

Type

Level

floating

wpu

interruptExt.

sink/sourceHigh

OD

PP

Default

Remap

ProxSense

(4)

transmitter 5(4)

40

23

19

PD5/PXS_TX5

I/O

TC

X

X

X

HS

X

X

Port D5

/ TIM2_CH2

Timer 2 -

channel 2

ProxSense

(4)

transmitter 6(4)

41

24

20

PD6/PXS_TX6

I/O

TC

X

X

X

HS

X

X

Port D6

/ TIM3_CH1

Timer 3 -

channel1

ProxSense

(4)

transmitter 7(4)

42

25

PD7/PXS_TX7

I/O

TC

X

X

X

HS

X

X

Port D7

/ TIM3_CH2

Timer 3 -

channel 2

ProxSense

43

26

1

PB0/PXS_TX8

(4)

I/O

TC

X

X

X

HS

X

X

Port B0

transmitter 8(4)

/ TIM3_ETR

Timer 3 -

external trigger

ProxSense

44

PB1(2)/PXS_TX9

I/O

TC

X

X

X

HS

X

X

Port B1

transmitter 9

/ TIM2_ETR

Timer 2 -

external trigger

45

PB2/PXS_TX10

I/O

TC

X

X

X

HS

X

X

Port B2

ProxSense

transmitter 10

46

PB3/PXS_TX11

I/O

TC

X

X

X

HS

X

X

Port B3

ProxSense

transmitter 11

47

PB4/PXS_TX12

I/O

TC

X

X

X

HS

X

X

Port B4

ProxSense

transmitter 12

48

PB5/PXS_TX13

I/O

TC

X

X

X

HS

X

X

Port B5

ProxSense

transmitter 13

1.The PA0/SWIM pin is in input pull-up during the reset phase and after reset release.

2.A pull-up is applied to PA2, PA3 and PB1 during the reset phase. These three pins are input floating after reset release.

3.At power-up, the PA5/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA5), it can be configured only as output open-drain or push-pull, not as a general purpose input. Refer to Section Configuring NRST/PA5 pin as general purpose output in the STM8TL5xxx reference manual (RM0312).

4.Not available for STM8TL52xx.

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Doc ID 022344 Rev 2

STM8TL5xxx	Memory and register map

5 Memory and register map

Figure 7. Memory map

0x00 0000

0x00 0FFF

0x00 1000

0x00 47FF

0x00 4800

0x00 48FF

0x00 4900

0x00 4924

0x00 4925

0x00 4930

0x00 4931

0x00 49FF

0x00 5000

0x00 57FF

0x00 5800

0x00 7EFF

0x00 7F00

0x00 7FFF

0x00 8000

0x00 807F

0x00 8080

0x00 BFFF

RAM

(4 Kbytes)(1) including Stack

Reserved

Option Bytes

Reserved

Unique ID

Reserved

GPIO and

Peripheral registers(1)

Reserved

CPU/SWIM/Debug/ITC

registers

Interrupt vectors

Low-density

Flash program memory (up to 16 Kbytes)(1)

including Data EEPROM (up to 2 Kbytes)

MS19123V1

1.Refer to Table 5 for an overview of hardware register mapping, to Table 4 for details on I/O port hardware registers, and to Table 6 for information on CPU/SWIM/debug module controller registers.

Doc ID 022344 Rev 2

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