ST STM8S903K3, STM8S903F3 User Manual

STM8S903K3 STM8S903F3

UFQFPN32 5x5LQFP32 7x7 SDIP32 400 mils

TSSOP20 SO20W 300 milsUFQFPN20 3x3

16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, 1 Kbyte RAM, 640

bytes EEPROM,10-bit ADC, 2 timers, UART, SPI, I²C

Switch-off peripheral clocks individually

-

Permanently active, low consumption power-on

•

and power-down reset

Interrupt management

Nested interrupt controller with 32 interrupts

•

Up to 28 external interrupts on 7 vectors

•

Timers

Advanced control timer: 16-bit, 4 CAPCOM

•

channels, 3 complementary outputs, dead-time
insertion and flexible synchronization

16-bit general purpose timer, with 3 CAPCOM

•

channels (IC, OC or PWM)

8-bit basic timer with 8-bit prescaler

•

Auto wakeup timer

•

Window and independent watchdog timers

Features

•

Core

16 MHz advanced STM8 core with Harvard

•

architecture and 3-stage pipeline

Extended instruction set

•

Memories

Program memory: 8 Kbytes Flash; data retention

•

20 years at 55 °C after 10 kcycles

Data memory: 640 bytes true data EEPROM;

•

endurance 300 kcycles

RAM: 1 Kbytes

•

Clock, reset and supply management

2.95 to 5.5 V operating voltage

•

Flexible clock control, 4 master clock sources:

•

Low power crystal resonator oscillator

-

External clock input

-

Internal, user-trimmable 16 MHz RC

-

Internal low power 128 kHz RC

-

Clock security system with clock monitor

•

Power management:

•

Low power modes (wait, active-halt, halt)

-

Communications interfaces

UART with clock output for synchronous

•

operation, Smartcard, IrDA, LIN master mode

SPI interface up to 8 Mbit/s

•

I2C interface up to 400 Kbit/s

•

Analog to digital converter (ADC)

10-bit, ±1 LSB ADC with up to 7 muxed channels

•

+ 1 internal channel, scan mode and analog
watchdog

Internal reference voltage measurement

•

I/Os

Up to 28 I/Os on a 32-pin package including 21

•

high sink outputs

Highly robust I/O design, immune against current

•

injection

Development support

Embedded single wire interface module (SWIM)

•

for fast on-chip programming and non intrusive
debugging

Unique ID: 96-bit key including lot number

June 2012

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STM8S903K3 STM8S903F3Contents

Contents

1 Introduction ..............................................................................................................8

2 Description ...............................................................................................................9

3 Block diagram ........................................................................................................10

4 Product overview ...................................................................................................11

4.1 Central processing unit STM8 .....................................................................................11

4.2 Single wire interface module (SWIM) and debug module (DM) ..................................11

4.3 Interrupt controller .......................................................................................................12

4.4 Flash program and data EEPROM memory ................................................................12

4.5 Clock controller ............................................................................................................13

4.6 Power management ....................................................................................................14

4.7 Watchdog timers ..........................................................................................................14

4.8 Auto wakeup counter ...................................................................................................15

4.9 Beeper ........................................................................................................................15

4.10 TIM1 - 16-bit advanced control timer .........................................................................15

4.11 TIM5 - 16-bit general purpose timer ..........................................................................16

4.12 TIM6 - 8-bit basic timer ..............................................................................................16

4.13 Analog-to-digital converter (ADC1) ............................................................................16

4.14 Communication interfaces .........................................................................................17

4.14.1 UART1 ...............................................................................................17

4.14.2 SPI .....................................................................................................18

4.14.3 I²C ......................................................................................................18

5 Pinout and pin description ...................................................................................19

5.1 STM8S903F3 TSSOP20/SO20 pinout ........................................................................20

5.2 STM8S903F3 UFQFPN20 pinout ................................................................................21

5.3 TSSOP/SO/UFQFPN20 pin description ......................................................................22

5.4 STM8S903K3 UFQFPN32/LQFP32/SDIP32 pinout ....................................................23

5.5 UFQFPN/LQFP/SDIP32 pin description ......................................................................24

5.6 Alternate function remapping .......................................................................................26

6 Memory and register map .....................................................................................27

6.1 Memory map ................................................................................................................27

6.2 Register map ...............................................................................................................28

6.2.1 I/O port hardware register map ............................................................28

6.2.2 General hardware register map ...........................................................29

6.2.3 CPU/SWIM/debug module/interrupt controller registers .....................38

7 Interrupt vector mapping ......................................................................................41

8 Option bytes ...........................................................................................................43

8.1 STM8S903K3/F3 alternate function remapping bits ....................................................45

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ContentsSTM8S903K3 STM8S903F3

9 Unique ID ................................................................................................................49

10 Electrical characteristics ....................................................................................50

10.1 Parameter conditions .................................................................................................50

10.1.1 Minimum and maximum values .........................................................50

10.1.2 Typical values .....................................................................................50

10.1.3 Typical curves ....................................................................................50

10.1.4 Loading capacitor ...............................................................................50

10.1.5 Pin input voltage .................................................................................50

10.2 Absolute maximum ratings ........................................................................................51

10.3 Operating conditions ..................................................................................................53

10.3.1 VCAP external capacitor ....................................................................54

10.3.2 Supply current characteristics ............................................................55

10.3.3 External clock sources and timing characteristics .............................65

10.3.4 Internal clock sources and timing characteristics ...............................67

10.3.5 Memory characteristics ......................................................................69

10.3.6 I/O port pin characteristics .................................................................70

10.3.7 Reset pin characteristics ....................................................................78

10.3.8 SPI serial peripheral interface ............................................................81

10.3.9 I2C interface characteristics ...............................................................84

10.3.10 10-bit ADC characteristics ................................................................85

10.3.11 EMC characteristics .........................................................................89

11 Package information ............................................................................................92

11.1 32-pin LQFP package mechanical data .....................................................................92

11.2 32-lead UFQFPN package mechanical data .............................................................94

11.3 20-lead UFQFPN package mechanical data .............................................................95

11.4 UFQFPN recommended footprint ..............................................................................97

11.5 SDIP32 package mechanical data .............................................................................98

11.6 20-pin TSSOP package mechanical data ................................................................100

11.7 20-pin SO package mechanical data .......................................................................101

11.8 Thermal characteristics ............................................................................................102

11.8.1 Reference document ........................................................................103

11.8.2 Selecting the product temperature range .........................................103

12 Ordering information .........................................................................................104

12.1 STM8S903K3/F3 FASTROM microcontroller option list ..........................................104

13 STM8 development tools ..................................................................................110

13.1 Emulation and in-circuit debugging tools .................................................................110

13.2 Software tools ..........................................................................................................110

13.2.1 STM8 toolset ....................................................................................111

13.2.2 C and assembly toolchains ..............................................................111

13.3 Programming tools ..................................................................................................111

14 Revision history .................................................................................................112

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STM8S903K3 STM8S903F3List of tables

List of tables

Table 1. STM8S903K3/F3 access line features .......................................................................................9

Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ..................................14

Table 3. TIM timer features ....................................................................................................................16

Table 4. Legend/abbreviations for pinout tables ...................................................................................19

Table 5. TSSOP20/SO20/UFQFPN20 pin description ...........................................................................24

Table 6. UFQFPN32/LQFP32/SDIP32 pin description ...........................................................................24

Table 7. I/O port hardware register map ................................................................................................28

Table 8. General hardware register map ................................................................................................43

Table 9. CPU/SWIM/debug module/interrupt controller registers .........................................................54

Table 10. Interrupt mapping ...................................................................................................................41

Table 11. Option bytes .........................................................................................................................112

Table 12. Option byte description ...........................................................................................................43

Table 13. STM8S903K3 alternate function remapping bits [7:2] for 32-pin packages ...........................45

Table 14. STM8S903F3 alternate function remapping bits [7:2] for 20-pin packages ...........................46

Table 15. STM8S903K3 alternate function remapping bits [1:0] for 32-pin packages .........................102

Table 16. STM8S903F3 alternate function remapping bits [1:0] for 20-pin packages ...........................48

Table 17. Unique ID registers (96 bits) .................................................................................................112

Table 18. Voltage characteristics ...........................................................................................................51

Table 19. Current characteristics ...........................................................................................................51

Table 20. Thermal characteristics ..........................................................................................................52

Table 21. General operating conditions .................................................................................................53

Table 22. Operating conditions at power-up/power-down ......................................................................54

Table 23. Total current consumption with code execution in run mode at VDD= 5 V .............................55

Table 24. Total current consumption with code execution in run mode at VDD= 3.3 V ..........................56

Table 25. Total current consumption in wait mode at VDD= 5 V ............................................................57

Table 26. Total current consumption in wait mode at VDD= 3.3 V .........................................................57

Table 27. Total current consumption in active halt mode at VDD= 5 V ..................................................58

Table 28. Total current consumption in active halt mode at VDD= 3.3 V ...............................................59

Table 29. Total current consumption in halt mode at VDD= 5 V .............................................................60

Table 30. Total current consumption in halt mode at VDD= 3.3 V ..........................................................60

Table 31. Wakeup times .........................................................................................................................60

Table 32. Total current consumption and timing in forced reset state ....................................................61

Table 33. Peripheral current consumption .............................................................................................62

Table 34. HSE user external clock characteristics .................................................................................65

Table 35. HSE oscillator characteristics .................................................................................................65

Table 36. HSI oscillator characteristics ..................................................................................................67

Table 37. LSI oscillator characteristics ...................................................................................................68

Table 38. RAM and hardware registers ..................................................................................................69

Table 39. Flash program memory/data EEPROM memory ....................................................................69

Table 40. I/O static characteristics .........................................................................................................70

Table 41. Output driving current (standard ports) ..................................................................................72

Table 42. Output driving current (true open drain ports) ........................................................................73

Table 43. Output driving current (high sink ports) ..................................................................................73

Table 44. NRST pin characteristics ........................................................................................................78

Table 45. SPI characteristics ..................................................................................................................81

Table 46. I2C characteristics ..................................................................................................................84

Table 47. ADC characteristics ................................................................................................................85

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List of tablesSTM8S903K3 STM8S903F3

Table 48. ADC accuracy with R
Table 49. ADC accuracy with R

< 10 kΩ , VDD= 5 V .........................................................................86

AIN

< 10 kΩ R

AIN

, VDD= 3.3 V ..............................................................87

AIN

Table 50. EMS data ................................................................................................................................89

Table 51. EMI data .................................................................................................................................90

Table 52. ESD absolute maximum ratings .............................................................................................91

Table 53. Electrical sensitivities .............................................................................................................91

Table 54. 32-pin low profile quad flat package mechanical data .........................................................102

Table 55. 32-lead, ultra thin, fine pitch quad flat no-lead package mechanical data .............................94

Table 56. 20-lead, ultra thin, fine pitch quad flat no-lead package (3 x 3) package mechanical data ....96

Table 57. 32-lead shrink plastic DIP (400 ml) package mechanical data ..............................................99

Table 58. 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data .......................................................101

Table 59. 20-lead, plastic small outline (300 mils) mechanical data ....................................................101

Table 60. Thermal characteristics ........................................................................................................102

Table 61. Document revision history ....................................................................................................112

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STM8S903K3 STM8S903F3List of figures

List of figures

Figure 1. Block diagram .........................................................................................................................10

Figure 2. Flash memory organization ....................................................................................................13

Figure 3. STM8S903F3 TSSOP20/SO20 pinout ...................................................................................23

Figure 4. STM8S903F3 UFQFPN20 pinout ...........................................................................................23

Figure 5. STM8S903K3 UFQFPN32/LQFP32 pinout ............................................................................23

Figure 6. STM8S903K3 SDIP32 pinout .................................................................................................24

Figure 7. Memory map ...........................................................................................................................27

Figure 8. Pin loading conditions .............................................................................................................50

Figure 9. Pin input voltage .....................................................................................................................51

Figure 10. f

CPUmax

Figure 11. External capacitor C
Figure 12. Typ I
Figure 13. Typ I
Figure 14. Typ I
Figure 15. Typ I
Figure 16. Typ I
Figure 17. Typ I

Figure 18. HSE external clocksource .....................................................................................................65

Figure 19. HSE oscillator circuit diagram ...............................................................................................66

Figure 20. Typical HSI frequency variation vs VDD@ 4 temperatures ..................................................68

Figure 21. Typical LSI frequency variation vs VDD@ 4 temperatures ...................................................68

Figure 22. Typical VILand VIHvs VDD@ 4 temperatures ......................................................................71

Figure 23. Typical pull-up resistance vs VDD@ 4 temperatures ............................................................72

Figure 24. Typical pull-up current vs VDD@ 4 temperatures .................................................................72

Figure 25. Typ. VOL@ VDD= 5 V (standard ports) ................................................................................74

Figure 26. Typ. VOL@ VDD= 3.3 V (standard ports) .............................................................................74

Figure 27. Typ. VOL@ VDD= 5 V (true open drain ports) ......................................................................75

Figure 28. Typ. VOL@ VDD= 3.3 V (true open drain ports) ...................................................................75

Figure 29. Typ. VOL@ VDD= 5 V (high sink ports) ................................................................................76

Figure 30. Typ. VOL@ VDD= 3.3 V (high sink ports) .............................................................................76

Figure 31. Typ. VDD- VOH@ VDD= 5 V (standard ports) .......................................................................77

Figure 32. Typ. VDD- VOH@ VDD= 3.3 V (standard ports) ...................................................................77

Figure 33. Typ. VDD- VOH@ VDD= 5 V (high sink ports) .......................................................................78

Figure 34. Typ. VDD- VOH@ VDD= 3.3 V (high sink ports) ....................................................................78

Figure 35. Typical NRST VILand VIHvs VDD@ 4 temperatures ...........................................................79

Figure 36. Typical NRST pull-up resistance vs VDD@ 4 temperatures .................................................80

Figure 37. Typical NRST pull-up current vs VDD@ 4 temperatures ......................................................80

Figure 38. Recommended reset pin protection ......................................................................................81

Figure 39. SPI timing diagram - slave mode and CPHA = 0 ..................................................................83

Figure 40. SPI timing diagram - slave mode and CPHA = 1 ..................................................................83

Figure 41. SPI timing diagram - master mode

Figure 42. Typical application with I2C bus and timing diagram ............................................................85

Figure 43. ADC accuracy characteristics ...............................................................................................88

Figure 44. Typical application with ADC ................................................................................................88

Figure 45. 32-pin low profile quad flat package (7 x 7) ..........................................................................92

Figure 46. 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) ............................................94

Figure 47. 20-lead, ultra thin, fine pitch quad flat no-lead package outline (3 x 3) ................................95

versus V

DD(RUN)

DD(RUN)

DD(RUN)

DD(WFI)

DD(WFI)

DD(WFI)

..............................................................................................................54

DD

.......................................................................................................55

EXT

vs. VDDHSE user external clock, f
vs. f
vs. VDDHSI RC osc, f

HSE user external clock, VDD= 5 V ....................................................63

CPU

= 16 MHz .................................................................63

CPU

vs. VDDHSE user external clock, f
vs. f
vs. VDDHSI RC osc, f

HSE user external clock, VDD= 5 V .....................................................64

CPU

= 16 MHz .................................................................64

CPU

(1)

...................................................................................84

= 16 MHz .............................................62

CPU

= 16 MHz ..............................................64

CPU

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List of figuresSTM8S903K3 STM8S903F3

Figure 48. Recommended footprint for on-board emulation ..................................................................97

Figure 49. Recommended footprint without on-board emulation ...........................................................98

Figure 50. 32-lead shrink plastic DIP (400 ml) package ........................................................................98

Figure 51. 20-pin, 4.40 mm body, 0.65 mm pitch .................................................................................101

Figure 52. 20-lead, plastic small outline (300 mils) package ...............................................................101

Figure 53. STM8S903K3/F3 ordering information scheme ..................................................................104

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STM8S903K3 STM8S903F3Introduction

Introduction1

This datasheet contains the description of the device features, pinout, electrical characteristics,
mechanical data and ordering information.

For complete information on the STM8S microcontroller memory, registers and peripherals,

•

please refer to the STM8S microcontroller family reference manual (RM0016).

For information on programming, erasing and protection of the internal Flash memory

•

please refer to the STM8S Flash programming manual (PM0051).

For information on the debug and SWIM (single wire interface module) refer to the STM8

•

SWIM communication protocol and debug module user manual (UM0470).

For information on the STM8 core, please refer to the STM8 CPU programming manual

•

(PM0044).

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DescriptionSTM8S903K3 STM8S903F3

Description2

The STM8S903K3 and STM8S903F3 8-bit microcontrollers offer 8 Kbytes Flash program
memory, plus integrated true data EEPROM. The STM8S microcontroller family reference
manual (RM0016) refers to devices in this family as low-density. They provide the following
benefits: performance, robustness, and reduced system cost.

Device performance and robustness are ensured by advanced core and peripherals made
in a state-of-the art technology, a 16 MHz clock frequency, robust I/Os, independent watchdogs
with separate clock source, and a clock security system.

The system cost is reduced thanks to an integrated true data EEPROM for up to 300
kwrite/erase cycles and a high system integration level with internal clock oscillators, watchdog
and brown-out reset.

Full documentation is offered as well as a wide choice of development tools.

Table 1: STM8S903K3/F3 access line features

STM8S903F3STM8S903K3Device

2032Pin count

Max. number of GPIOs
(I/Os)

28

(1)

16

(2)

channels

outputs

program memory(bytes)

Data EEPROM (bytes)

Peripheral set

Multipurpose timer (TIM1), SPI, I2C, UART window WDG,
independent WDG, ADC, PWM timer (TIM5), 8-bit timer (TIM6)

(1)

Including 21 high sink outputs

(2)

Including 12 high sink outputs

(3)

No read-while-write (RWW) capability

8KLow density Flash

640

1KRAM (bytes)

1628Ext. interrupt pins

7Timer CAPCOM

23Timer complementary

57A/D converter channels

1221High sink I/Os

(3)

9/116DocID15590 Rev 8

XTAL 1-16 MHz

RC int. 16 MHz

RC int. 128 kHz

STM8 core

Debug/SWIM

I2C

SPI

UART1

16-bit general purpose

AWU timer

Reset block

Reset

POR

BOR

Clock controller

Detector

Clock to peripherals and core

8 Mbit/s

LIN master

Address and data bus

Window WDG

8 Kbytes

640 bytes

1 Kbytes

ADC1

4 CAPCOM

Reset

400 Kbit/s

Single wire
debug interf.

SPI emul.

channels

program

Flash

16-bit advanced control

timer (TIM1)

8-bit basic timer

data EEPROM

RAM

Up to

Beeper

1/2/4 kHz

beep

Independent WDG

(TIM6)

3 CAPCOM

channels

Up to

+ 3 complementary

outputs

Timer (TIM5)

Up to 7

channels

STM8S903K3 STM8S903F3Block diagram

Block diagram3

Figure 1: Block diagram

DocID15590 Rev 810/116

Product overviewSTM8S903K3 STM8S903F3

Product overview4

The following section intends to give an overview of the basic features of the device functional
modules and peripherals.

For more detailed information please refer to the corresponding family reference manual
(RM0016).

Central processing unit STM84.1

The 8-bit STM8 core is designed for code efficiency and performance.

It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.

Architecture and registers

Harvard architecture

•

3-stage pipeline

•

32-bit wide program memory bus - single cycle fetching for most instructions

•

X and Y 16-bit index registers - enabling indexed addressing modes with or without offset

•

and read-modify-write type data manipulations

8-bit accumulator

•

24-bit program counter - 16-Mbyte linear memory space

•

16-bit stack pointer - access to a 64 K-level stack

•

8-bit condition code register - 7 condition flags for the result of the last instruction

•

Addressing

20 addressing modes

•

Indexed indirect addressing mode for look-up tables located anywhere in the address

•

space

Stack pointer relative addressing mode for local variables and parameter passing

•

Instruction set

80 instructions with 2-byte average instruction size

•

Standard data movement and logic/arithmetic functions

•

8-bit by 8-bit multiplication

•

16-bit by 8-bit and 16-bit by 16-bit division

•

Bit manipulation

•

Data transfer between stack and accumulator (push/pop) with direct stack access

•

Data transfer using the X and Y registers or direct memory-to-memory transfers

•

Single wire interface module (SWIM) and debug module (DM)4.2

The single wire interface module and debug module permits non-intrusive, real-time in-circuit
debugging and fast memory programming.

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STM8S903K3 STM8S903F3Product overview

SWIM

Single wire interface module for direct access to the debug module and memory programming.
The interface can be activated in all device operation modes. The maximum data transmission
speed is 145 bytes/ms.

Debug module

The non-intrusive debugging module features a performance close to a full-featured emulator.
Beside memory and peripherals, also CPU operation can be monitored in real-time by means
of shadow registers.

R/W to RAM and peripheral registers in real-time

•

R/W access to all resources by stalling the CPU

•

Breakpoints on all program-memory instructions (software breakpoints)

•

Two advanced breakpoints, 23 predefined configurations

•

Interrupt controller4.3

Nested interrupts with three software priority levels

•

32 interrupt vectors with hardware priority

•

Up to 28 external interrupts on 7 vectors including TLI

•

Trap and reset interrupts

•

Flash program and data EEPROM memory4.4

8 Kbytes of Flash program single voltage Flash memory

•

640 bytes true data EEPROM

•

User option byte area

•

Write protection (WP)

Write protection of Flash program memory and data EEPROM is provided to avoid unintentional
overwriting of memory that could result from a user software malfunction.

There are two levels of write protection. The first level is known as MASS (memory access
security system). MASS is always enabled and protects the main Flash program memory,
data EEPROM and option bytes.

To perform in-application programming (IAP), this write protection can be removed by writing
a MASS key sequence in a control register. This allows the application to write to data
EEPROM, modify the contents of main program memory or the device option bytes.

A second level of write protection, can be enabled to further protect a specific area of memory
known as UBC (user boot code). Refer to the figure below.

The size of the UBC is programmable through the UBC option byte, in increments of 1 page
(64-byte block) by programming the UBC option byte in ICP mode.

This divides the program memory into two areas:

Main program memory: Up to 8 Kbytes minus UBC

•

User-specific boot code (UBC): Configurable up to 8 Kbytes

•

The UBC area remains write-protected during in-application programming. This means that
the MASS keys do not unlock the UBC area. It protects the memory used to store the boot

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UBC area

Program memory area

Data memory area ( 640 bytes)

Remains write protectedduring IAP

Data
EEPROM
memory

Write access possible forIAP

Option bytes

Programmable
bytes(1 page)

up to 8 Kbytes
(in 1 page steps)

area from 64

Low density
Flash program
memory
(8 Kbytes)

Product overviewSTM8S903K3 STM8S903F3

program, specific code libraries, reset and interrupt vectors, the reset routine and usually the
IAP and communication routines.

Figure 2: Flash memory organization

Read-out protection (ROP)

The read-out protection blocks reading and writing the Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated,
any attempt to toggle its status triggers a global erase of the program and data memory. Even
if no protection can be considered as totally unbreakable, the feature provides a very high
level of protection for a general purpose microcontroller.

Clock controller4.5

The clock controller distributes the system clock (f
to the core and the peripherals. It also manages clock gating for low power modes and ensures
clock robustness.

Features

Clock prescaler: To get the best compromise between speed and current consumption

•

the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.

Safe clock switching: Clock sources can be changed safely on the fly in run mode

•

through a configuration register. The clock signal is not switched until the new clock source
is ready. The design guarantees glitch-free switching.

Clock management: To reduce power consumption, the clock controller can stop the

•

clock to the core, individual peripherals or memory.

Master clock sources: Four different clock sources can be used to drive the master

•

clock:

-

1-16 MHz high-speed external crystal (HSE)

MASTER

) coming from different oscillators

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Bit

STM8S903K3 STM8S903F3Product overview

Up to 16 MHz high-speed user-external clock (HSE user-ext)

-

16 MHz high-speed internal RC oscillator (HSI)

-

128 kHz low-speed internal RC (LSI)

-

Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz

•

clock (HSI/8). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.

Clock security system (CSS): This feature can be enabled by software. If an HSE clock

•

failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an
interrupt can optionally be generated.

Configurable main clock output (CCO): This outputs an external clock for use by the

•

application.

Table 2: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers

Peripheral
clock

ADCCKEN23ReservedPCKEN27UART1PCKEN13TIM1PCKEN17

AWUPCKEN22ReservedPCKEN26ReservedPCKEN12IM5PCKEN16

ReservedPCKEN21ReservedPCKEN25SPIPCKEN11ReservedPCKEN15

clock

BitPeripheral

clock

BitPeripheral

clock

BitPeripheral

ReservedPCKEN20ReservedPCKEN24I2CPCKEN10TIM6PCKEN14

Power management4.6

For efficent power management, the application can be put in one of four different low-power
modes. You can configure each mode to obtain the best compromise between lowest power
consumption, fastest start-up time and available wakeup sources.

Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The

•

wakeup is performed by an internal or external interrupt or reset.

Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are

•

stopped. An internal wakeup is generated at programmable intervals by the auto wake up
unit (AWU). The main voltage regulator is kept powered on, so current consumption is
higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup
is triggered by the internal AWU interrupt, external interrupt or reset.

Active halt mode with regulator off: This mode is the same as active halt with regulator

•

on, except that the main voltage regulator is powered off, so the wake up time is slower.

Halt mode: In this mode the microcontroller uses the least power. The CPU and peripheral

•

clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by
external event or reset.

Watchdog timers4.7

The watchdog system is based on two independent timers providing maximum security to
the applications.

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Product overviewSTM8S903K3 STM8S903F3

Activation of the watchdog timers is controlled by option bytes or by software. Once activated,
the watchdogs cannot be disabled by the user program without performing a reset.

Window watchdog timer

The window watchdog is used to detect the occurrence of a software fault, usually generated
by external interferences or by unexpected logical conditions, which cause the application
program to abandon its normal sequence.

The window function can be used to trim the watchdog behavior to match the application
perfectly.

The application software must refresh the counter before time-out and during a limited time
window.

A reset is generated in two situations:

1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to
64 ms.

2. Refresh out of window: The downcounter is refreshed before its value is lower than the
one stored in the window register.

Independent watchdog timer

The independent watchdog peripheral can be used to resolve processor malfunctions due to
hardware or software failures.

It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure

The IWDG time base spans from 60 µs to 1 s.

Auto wakeup counter4.8

Used for auto wakeup from active halt mode

•

Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock

•

LSI clock can be internally connected to TIM1 input capture channel 1 for calibration

•

Beeper4.9

The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.

The beeper output port is only available through the alternate function remap option bit AFR7.

TIM1 - 16-bit advanced control timer4.10

This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver

16-bit up, down and up/down autoreload counter with 16-bit prescaler

•

Four independent capture/compare channels (CAPCOM) configurable as input capture,

•

output compare, PWM generation (edge and center aligned mode) and single pulse mode
output

15/116DocID15590 Rev 8

STM8S903K3 STM8S903F3Product overview

Synchronization module to control the timer with external signals or to synchronise with

•

TIM5 or TIM6

Break input to force the timer outputs into a defined state

•

Three complementary outputs with adjustable dead time

•

Encoder mode

•

Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break

•

TIM5 - 16-bit general purpose timer4.11

16-bit autoreload (AR) up-counter

•

15-bit prescaler adjustable to fixed power of 2 ratios 1…32768

•

3 individually configurable capture/compare channels

•

PWM mode

•

Interrupt sources: 3 x input capture/output compare, 1 x overflow/update

•

Synchronization module to control the timer with external signals or to synchronize with

•

TIM1 or TIM6

TIM6 - 8-bit basic timer4.12

Timer

size
(bits)

16TIM1

16TIM5

8TIM6

8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128

•

Clock source: CPU clock

•

Interrupt source: 1 x overflow/update

•

Synchronization module to control the timer with external signals or to synchronize with

•

TIM1 or TIM5.

Table 3: TIM timer features

PrescalerCounter

to 65536

from 1 to 32768

from 1 to 128

Counting
mode

CAPCOM
channels

Complementary
outputs

Ext.
trigger

No03UpAny power of 2

No00UpAny power of 2

Timer
synchronization/
chaining

YesYes34Up/downAny integer from 1

Analog-to-digital converter (ADC1)4.13

The STM8S903K3 family products contain a 10-bit successive approximation A/D converter
(ADC1) with up to 7 external and 1 internal multiplexed input channels and the following main
features:

Input voltage range: 0 to V

•

DD

DocID15590 Rev 816/116

Product overviewSTM8S903K3 STM8S903F3

Conversion time: 14 clock cycles

•

Single and continuous and buffered continuous conversion modes

•

Buffer size (n x 10 bits) where n = number of input channels

•

Scan mode for single and continuous conversion of a sequence of channels

•

Analog watchdog capability with programmable upper and lower thresholds

•

Internal reference voltage on channel AIN7

•

Analog watchdog interrupt

•

External trigger input

•

Trigger from TIM1 TRGO

•

End of conversion (EOC) interrupt

•

Internal bandgap reference voltage

Channel AIN7 is internally connected to the internal bandgap reference voltage. The internal
bandgap reference is constant and can be used, for example, to monitor VDD. It is independent
of variations in VDDand ambient temperature TA.

Communication interfaces4.14

The following communication interfaces are implemented:

UART1: Full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA

•

mode, single wire mode, LIN2.1 master capability

SPI : Full and half-duplex, 8 Mbit/s

•

I²C: Up to 400 Kbit/s

•

UART14.14.1

Main features

One Mbit/s full duplex SCI

•

SPI emulation

•

High precision baud rate generator

•

Smartcard emulation

•

IrDA SIR encoder decoder

•

LIN master mode

•

Single wire half duplex mode

•

Asynchronous communication (UART mode)

Full duplex communication - NRZ standard format (mark/space)

•

Programmable transmit and receive baud rates up to 1 Mbit/s (f

•

following any standard baud rate regardless of the input frequency

Separate enable bits for transmitter and receiver

•

Two receiver wakeup modes:

•

Address bit (MSB)

-

Idle line (interrupt)

-

/16) and capable of

CPU

17/116DocID15590 Rev 8

STM8S903K3 STM8S903F3Product overview

Transmission error detection with interrupt generation

•

Parity control

•

Synchronous communication

Full duplex synchronous transfers

•

SPI master operation

•

8-bit data communication

•

Maximum speed: 1 Mbit/s at 16 MHz (f

•

LIN master mode

Emission: Generates 13-bit synch break frame

•

Reception: Detects 11-bit break frame

•

SPI4.14.2

Maximum speed: 8 Mbit/s (f

•

Full duplex synchronous transfers

•

Simplex synchronous transfers on two lines with a possible bidirectional data line

•

Master or slave operation - selectable by hardware or software

•

CRC calculation

•

1 byte Tx and Rx buffer

•

Slave/master selection input pin

•

MASTER

/2) both for master and slave

CPU

/16)

I²C4.14.3

I²C master features:

•

Clock generation

-

Start and stop generation

-

I²C slave features:

•

Programmable I2C address detection

-

Stop bit detection

-

Generation and detection of 7-bit/10-bit addressing and general call

•

Supports different communication speeds:

•

Standard speed (up to 100 kHz)

-

Fast speed (up to 400 kHz)

-

DocID15590 Rev 818/116

Pinout and pin descriptionSTM8S903K3 STM8S903F3

Pinout and pin description5

Table 4: Legend/abbreviations for pinout tables

I= Input, O = Output, S = Power supplyType

Output speed

configuration

Reset state

InputLevel

O1 = Slow (up to 2 MHz)

O2 = Fast (up to 10 MHz)

O3 = Fast/slow programmability with slow as default state after reset

O4 = Fast/slow programmability with fast as default state after reset

Output

Bold X (pin state after internal reset release).

Unless otherwise specified, the pin state is the same during the reset
phase and after the internal reset release.

CM = CMOS

HS = High sinkOutput

float = floating, wpu = weak pull-upInputPort and control

T = True open drain, OD = Open drain, PP =
Push pull

19/116DocID15590 Rev 8

8

1
2
3
4
5
6
7

9
10

20
19
18
17
16
15
14
13
12
11

PD3(HS)/AIN4/TIM5_CH2/ADC_ETRTIM5_CH1[UART1_CK]BEEP/PD4(HS)

AIN5/UART1_TX/PD5(HS)

AIN6/UART1_RX/PD6(HS)

NRST

OSCIN/PA1

OSCOUT/PA2

V

SS

VCAP

V

DD

[SPI_NSS]/TIM5_CH3/PA3(HS)

PB4(T)/I2C_SCL[ADC_ETR]

PC3(HS)/TIM1_CH3[TLI][TIM1_CH1N]

PC4(HS)/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N]

PC5(HS)/SPI_SCK[TIM5_CH1]

PC6(HS)/SPI_MOSI[TIM1_CH1]

PC7(HS)/SPI_MISO[TIM1_CH2]

PD1(HS)/SWIM

PD2(HS)/AIN3[TIM5_CH3]

PB5(T)/[TIM1_BKIN]I2C_SDA

STM8S903K3 STM8S903F3Pinout and pin description

STM8S903F3 TSSOP20/SO20 pinout5.1

Figure 3: STM8S903F3 TSSOP20/SO20 pinout

1. (HS) high sink capability.

2. (T) true open drain (P-buffer and protection diode to VDDnot implemented).

3. [ ] alternate function remapping option (if the same alternate function is shown twice, it

indicates an exclusive choice not a duplication of the function).

DocID15590 Rev 820/116

2

1

3

4

5

6 7 8

9

11

12

13

14

15

16171819

VCAP

V

SS

OSCOUT/PA2

OSCIN/PA1

[UART1_TX]/[SPI_NSS]/TIM5_CH3/(HS) PA3

NRST

PD4 (HS)/BEEP / TIM5_CH1/UART1_CK

PD5(HS)/AIN5/UART1_TX

PD3 (HS)/AIN4/TIM5_CH2/ADC_ETR

PD2(HS)/AIN3/[TIM5_CH3]

PC4(HS)/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N]

PC5 (HS)/SPI_SCK/[TIM5_CH1]

PC6(HS)/SPI_MOSI/[TIM1_CH1]

PC7(HS)/SPI_MISO/[TIM1_CH2]

PD1(HS)/SWIM

[TIM1_BKIN]/I

2

C_SDA/(T)PB5

10

[TIM1_CH1N]/[TLI]/TIM1_CH3/(HS)PC3

PD6(HS)/AIN6/UART1_RX

20

V

DD

[ADC_ETR]/I

2

C_SCL/(T)PB4

Pinout and pin descriptionSTM8S903K3 STM8S903F3

STM8S903F3 UFQFPN20 pinout5.2

Figure 4: STM8S903F3 UFQFPN20 pinout

1. (HS) high sink capability.

2. (T) true open drain (P-buffer and protection diode to VDDnot implemented).

3. [ ] alternate function remapping option (if the same alternate function is shown twice, it

indicates an exclusive choice not a duplication of the function).

21/116DocID15590 Rev 8

TSSOP

SO20

20

25

PA1/ OSCIN

47

SS

69

DD

710

[UART1_TX]

1013

TIM1_CH3/TLI/[TIM1_CH1N ]

1114

CLK_CCO/AIN2/[TIM1_CH2N]

1518

PD1/ SWIM

1720

ADC_ETR

181

[UART1_CK]

STM8S903K3 STM8S903F3Pinout and pin description

Pin description TSSOP20_SO20_UFQFPN205.3

Table 5: TSSOP20/SO20/UFQFPN20 pin description

TypePin nameUFQFPN

(2)

(4)

Ext.

wpufloating

interrupt

OutputInput

sink

(1)

O1XXI/OPB5/ I2C_SDA [TIM1_BKIN]811

O1XXI/OPB4/ I2C_SCL [ADC_ETR]912

PPODSpeedHigh

XXO1XXXI/O

XXO1XXXI/OPA2/ OSCOUT36

XXO3HSXXXI/OPA3/ TIM5_CH3 [SPI_NSS]

(3)

T

(3)

T

XXO3HSXXXI/OPC3/

XXO3HSXXXI/OPC4/ TIM1_CH4/

XXO3HSXXXI/OPC5/SPI_SCK [TIM5_CH1]1215

XXO3HSXXXI/OPC6/ SPI_MOSI [TIM1_CH1]1316

XXO3HSXXXI/OPC7/ SPI_MISO [TIM1_CH2]1417

XXO4HSXXXI/O

XXO3HSXXXI/OPD2/AIN3/ [TIM5_CH3]1619

XXO3HSXXXI/OPD3/ AIN4/ TIM5_CH2/

XXO3HSXXXI/OPD4/ TIM5_CH1/ BEEP

XXO3HSXXXI/OPD5/ AIN5/ UART1_TX192

XXO3HSXXXI/OPD6/ AIN6/ UART1_RX203

Default alternate functionMain
function
(after
reset)

ResetXI/ONRST14

Resonator/ crystal inPort

A1

Resonator/ crystal outPort

A2

Digital groundSV

1.8 V regulator capacitorSVCAP58

Digital power supplySV

Timer 52 channel 3Port

A3

B5

B4

Timer 1 - channel 3Port

C3

Timer 1 - channel 4

Port

/configurable clock output

C4

C5

C6

C7

SWIM data interfacePort

D1

Port
D2

Analog input 4 Timer 52 -

Port

channel 2/ADC external

D3

trigger

Port

output

D4

Analog input 5/ UART1

Port

data transmit

D5

Analog input 6/ UART1

Port

data receive

D6

Alternate function after remap
[option bit]

SPI master/ slave select [AFR1]/
UART1 data transmit [AFR1:0]

Timer 1 - break input [AFR4]I2C dataPort

ADC external trigger [AFR4]I2C clockPort

Top level interrupt [AFR3] Timer
1 inverted channel 1 [AFR7]

Analog input 2 [AFR2]Timer 1
inverted channel 2 [AFR7]

Timer 5 channel 1 [AFR0]SPI clockPort

Timer 1 channel 1 [AFR0]PI master out/slave inPort

Timer 1 channel 2[AFR0]SPI master in/ slave outPort

Analog input 3 [AFR2] Timer 52

- channel 3 [AFR1]

UART clock [AFR2]Timer 5 - channel 1/BEEP

(1)

I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings ( see section
"Absolute maximum ratings").
(2)

When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is
recommended to use PA1 only in input mode if Halt/Active-halt is used in the application.
(3)

In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDDare not implemented)
(4)

The PD1 pin is in input pull-up during the reset phase and after internal reset release.

DocID15590 Rev 822/116

[ADC_ETR] I

2

C_SCL/(T) PB4

TIM1_ETR/AIN3/(HS) PB3

TIM1_CH3N/AIN2/(HS) PB2

TIM1_CH2N/AIN1/(HS) PB1

TIM1_CH1N/AIN0/(HS) PB0

PB7

PB6

[TIM1_BKIN] I

2

C_SDA/(T) PB5

32 31 30 29 28 27 26 25

24
23
22
21
20
19
18
17

9 10 11 12 13 14 15

16

1
2
3
4
5
6
7
8

VCAP

V

DD

[UART1_TX][SPI_NSS] TIM5_CH3/(HS) PA3

[UART1_RX]PF4

NRST

OSCIN/PA1

OSCOUT/PA2

V

SS

PC3 (HS)/TIM1_CH3 [TLI] [TIM1_CH1N]
PC2 (HS)/TIM1_CH2 [TIM1_CH3N]

PC1 (HS)/TIM1_CH1/UART1_CK [TIM1_CH2N]
PE5/SPI_NSS [TIM1_CH1N]

PC7 (HS)/SPI_MISO [TIM1_CH2]
PC6 (HS)/SPI_MOSI [TIM1_CH1]
PC5 (HS)/SPI_SCK [TIM5_CH1]
PC4 (HS)/TIM1_CH4/CLK_CCO [AIN2] [TIM1_CH2N]

PD3 (HS)/AIN4/TIM5_CH2/ADC_ETR

PD2 (HS)[AIN3] [TIM5_CH3]

PD1 (HS)/SWIM

PD0 (HS)/ TIM1_BKIN [CLK_CCO]

PD7 (HS)/TLI [TIM1_CH4]

PD6 (HS)/AIN6/UART1_RX

PD5 (HS)/AIN5/UART1_TX

PD4 (HS)/BEEP/TIM5_CH1 [UART1_CK]

Pinout and pin descriptionSTM8S903K3 STM8S903F3

STM8S903K3 UFQFPN32/LQFP32/SDIP32 pinout5.4

Figure 5: STM8S903K3 UFQFPN32/LQFP32 pinout

1. (HS) high sink capability.

2. (T) true open drain (P-buffer and protection diode to VDDnot implemented).

3. [ ] alternate function remapping option (if the same alternate function is shown twice, it

indicates an exclusive choice not a duplication of the function).

23/116DocID15590 Rev 8

8

1
2
3
4
5
6
7

9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

AIN4/TIM5_CH2/ADC_ETR/PD3(HS)

TIM5_CH1[UART1_CK]BEEP/PD4(HS)

AIN5/UART1_TX/PD5(HS)
AIN6/UART1_RX/PD6(HS)

[TIM1_CH4]TLI/PD7(HS)

NRST

OSCIN/PA1

OSCOUT/PA2

V

SS

VCAP

V

DD

[UART1_TX][SPI_NSS]/TIM5_CH3/PA3(HS)

[UART1_RX]/PF4

PB6

PB4(T)/I2C_SCL[ADC_ETR]

PB3(HS)[AIN3]TIM1_ETR

PB2(HS)/AIN2/TIM1_CH3N

PB1(HS)/AIN1/TIM1_CH2N

PB0(HS)/AIN0/TIM1_CH1N

PE5/SPI_NSS[TIM1_CH1N]

PC1(HS)/TIM1_CH1/UART1_CK[TIM1_CH2N]

PC2(HS)/TIM1_CH2[TIM1_CH3N]

PC3(HS)/TIM1_CH3[TLI][TIM1_CH1N]

PC4(HS)/TIM1_CH4/CLK_CCO[AIN2][TIM1_CH2N]

PC5(HS)/SPI_SCK[TIM5_CH1]

PC6(HS)/SPI_MOSI[TIM1_CH1]

PC7(HS)/SPI_MISO[TIM1_CH2]

PD0(HS)/TIM1_BKIN[CLK_CCO]

PD1(HS)/SWIM

PD2(HS)[AIN3][TIM5_CH3]

PB7

[TIM1_BKIN]I2C_SDA/PB5(T)

STM8S903K3 STM8S903F3Pinout and pin description

Figure 6: STM8S903K3 SDIP32 pinout

1. (HS) high sink capability.

2. (T) true open drain (P-buffer and protection diode to VDDnot implemented).

3. [ ] alternate function remapping option (if the same alternate function is shown twice, it

Pin description5.5

SDIP

LQFP32

32

27

PA1/ OSCIN

49

SS

611

DD

712

[UART1_TX]

indicates an exclusive choice not a duplication of the function).

Table 6: UFQFPN32/LQFP32/SDIP32 pin description

TypePin nameUFQFPN/

(2)

Ext.

wpufloating

interrupt

DocID15590 Rev 824/116

OutputInput

sink

(1)

PPODSpeedHigh

XXO1XXXI/O

XXO1XXXI/OPA2/ OSCOUT38

XXO3HSXXXI/OPA3/ TIM5_CH3 [SPI_NSS]

XXO1XXI/OPF4 [UART1_RX]813

XXO1XXXI/OPB7914

function
(after
reset)

ResetXI/ONRST16

A1

A2

Digital groundSV

1.8 V regulator capacitorSVCAP510

Digital power supplySV

A3

F4

Port
B7

Default alternate functionMain

Resonator/ crystal inPort

Resonator/ crystal outPort

Timer 52 channel 3Port

Alternate function after remap
[option bit]

SPI master/ slave select
[AFR1]/ UART1 data transmit
[AFR1:0]

UART1 data receive [AFR1:0]Port

Pinout and pin descriptionSTM8S903K3 STM8S903F3

SDIP

32

LQFP32

1823

[TIM1_CH2N]

2025

]

2126

CLK_CCO/AIN2/[TIM1_CH2N]

2631

PD1/ SWIM

292

[UART1_CK]

TypePin nameUFQFPN/

(4)

Ext.

wpufloating

interrupt

OutputInput

sink

(1)

O1XXI/OPB5/ I2C_SDA [TIM1_BKIN]1116

O1XXI/OPB4/ I2C_SCL [ADC_ETR]1217

PPODSpeedHigh

XXO1XXXI/OPB61015

(3)

T

(3)

T

XXO3HSXXXI/OPB3/ AIN3/TIM1_ETR1318

XXO3HSXXXI/OPB2/ AIN2/ TIM1_CH3N1419

XXO3HSXXXI/OPB1/ AIN1/ TIM1_CH2N1520

XXO3HSXXXI/OPB0/ AIN0/ TIM1_CH1N1621

XXO3HSXXXI/OPE5/ SPI_NSS [TIM1_CH1N]1722

XXO3HSXXXI/OPC1/ TIM1_CH1/ UART1_CK

XXO3HSXXXI/OPC2/ TIM1_CH2 [TIM1_CH3N]1924

XXO3HSXXXI/OPC3/ TIM1_CH3/TLI/[TIM1_CH1N

XXO3HSXXXI/OPC4/ TIM1_CH4/

XXO3HSXXXI/OPC5/SPI_SCK [TIM5_CH1]2227

XXO3HSXXXI/OPC6/ SPI_MOSI [TIM1_CH1]2328

XXO3HSXXXI/OPC7/ SPI_MISO [TIM1_CH2]2429

XXO3HSXXXI/OPD0/ TIM1_BKIN [CLK_CCO]2530

XXO4HSXXXI/O

XXO3HSXXXI/OPD2/AIN3/ [TIM5_CH3]2732

XXO3HSXXXI/OPD3/ AIN4/ TIM5_CH2/ ADC_ETR281

XXO3HSXXXI/OPD4/ TIM5_CH1/ BEEP

XXO3HSXXXI/OPD5/ AIN5/ UART1_TX303

XXO3HSXXXI/OPD6/ AIN6/ UART1_RX314

XXO3HSXXXI/OPD7/ TLI [TIM1_CH4]325

Default alternate functionMain
function
(after
reset)

Port
B6

B5

B4

Analog input 3/ Timer 1

Port

external trigger

B3

Analog input 2/ Timer 1 -

Port

inverted channel 3

B2

Analog input 1/ Timer 1 -

Port

inverted channel 2

B1

Analog input 0/ Timer 1 -

Port

inverted channel 1

B0

SPI master/ slave selectPort

E5

Timer 1 - channel 1

Port

UART1 clock

C1

Timer 1 - channel 2Port

C2

Timer 1 - channel 3Port

C3

Timer 1 - channel 4

Port

/configurable clock output

C4

C5

C6

C7

Timer 1 - break inputPort

D0

SWIM data interfacePort

D1

Port
D2

Analog input 4 Timer 52 -

Port

channel 2/ADC external

D3

trigger

Port

output

D4

Analog input 5/ UART1

Port

data transmit

D5

Analog input 6/ UART1

Port

data receive

D6

D7

Alternate function after remap
[option bit]

Timer 1 - break input [AFR4]I2C dataPort

ADC external trigger [AFR4]I2C clockPort

Timer 1 - inverted channel 1
[AFR1:0]

Timer 1 - inverted channel 2
[AFR1:0]

Timer 1 - inverted channel 3
[AFR1:0]

Toplevel interrupt [AFR3] Timer
1 inverted channel 1 [AFR7]

Analog input 2 [AFR2]Timer 1
inverted channel 2 [AFR7]

Timer 5 channel 1 [AFR0]SPI clockPort

Timer 1 channel 1 [AFR0]PI master out/slave inPort

Timer 1 channel 2[AFR0]SPI master in/ slave outPort

Configurable clock output
[AFR5]

Analog input 3 [AFR2] Timer 52

- channel 3 [AFR1]

UART clock [AFR2]Timer 5 - channel 1/BEEP

Timer 1 - channel 4 [AFR6]Top level interruptPort

(1)

I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings ( see section
"Absolute maximum ratings").
(2)

When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is
recommended to use PA1 only in input mode if Halt/Active-halt is used in the application.
(3)

In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDDare not implemented)
(4)

The PD1 pin is in input pull-up during the reset phase and after internal reset release.

25/116DocID15590 Rev 8

STM8S903K3 STM8S903F3Pinout and pin description

Alternate function remapping5.6

As shown in the rightmost column of the pin description table, some alternate functions can
be remapped at different I/O ports by programming one of eight AFR (alternate function
remap) option bits. When the remapping option is active, the default alternate function is no
longer available.

To use an alternate function, the corresponding peripheral must be enabled in the peripheral
registers.

Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO
section of the family reference manual, RM0016).

DocID15590 Rev 826/116

0x00 9FFF

Flash program memory

(8 Kbytes)

0x00 0000

RAM

0x00 03FF

(1 Kbyte)

513 bytes stack

0x00 4000

0x00 427F

640 bytes data EEPROM

Reserved

Reserved

Reserved

0x00 4280

0x00 A000

0x00 47FF

0x00 8000

32 interrupt vectors

0x00 807F

GPIO and periph. reg.

0x00 5000

0x00 57FF

0x00 5800

0x00 7FFF

0x00 480B

0x00 4FFF

0x00 7EFF

CPU/SWIM/debug/ITC

registers

0x00 7F00

Reserved

Reserved

Option bytes

0x00 480A

0x00 4800

0x00 0800

0x00 3FFF

0x00 8080

Reserved

Unique ID

0x00 4864
0x00 4865
0x00 4870
0x00 4871

Memory and register mapSTM8S903K3 STM8S903F3

Memory and register map6

Memory map6.1

Figure 7: Memory map

27/116DocID15590 Rev 8

STM8S903K3 STM8S903F3Memory and register map

Register map6.2

I/O port hardware register map6.2.1

Table 7: I/O port hardware register map

0x00 5000

0x00 5005

0x00 500A

Port A

Port B

Port C

Register nameRegister labelBlockAddress

Reset
status

0x00Port A data output latch registerPA_ODR

(1)

Port A input pin value registerPA_IDR0x00 5001

0xXX

0x00Port A data direction registerPA_DDR0x00 5002

0x00Port A control register 1PA_CR10x00 5003

0x00Port A control register 2PA_CR20x00 5004

0x00Port B data output latch registerPB_ODR

(1)

Port B input pin value registerPB_IDR0x00 5006

0xXX

0x00Port B data direction registerPB_DDR0x00 5007

0x00Port B control register 1PB_CR10x00 5008

0x00Port B control register 2PB_CR20x00 5009

0x00Port C data output latch registerPC_ODR

(1)

Port C input pin value registerPB_IDR0x00 500B

0xXX

0x00Port C data direction registerPC_DDR0x00 500C

0x00 500F

0x00 5014

Port D

Port E

0x00Port C control register 1PC_CR10x00 500D

0x00Port C control register 2PC_CR20x00 500E

0x00Port D data output latch registerPD_ODR

(1)

Port D input pin value registerPD_IDR0x00 5010

0xXX

0x00Port D data direction registerPD_DDR0x00 5011

0x02Port D control register 1PD_CR10x00 5012

0x00Port D control register 2PD_CR20x00 5013

0x00Port E data output latch registerPE_ODR

(1)

Port E input pin value registerPE_IDR0x00 5015

0xXX

0x00Port E data direction registerPE_DDR0x00 5016

0x00Port E control register 1PE_CR10x00 5017

DocID15590 Rev 828/116

Memory and register mapSTM8S903K3 STM8S903F3

0x00 5019

Port F

(1)

Depends on the external circuitry.

General hardware register map6.2.2

0x00 501E to

Reserved area (60 bytes)

Register nameRegister labelBlockAddress

Port F input pin value registerPF_IDR0x00 501A

Table 8: General hardware register map

Register nameRegister labelBlockAddress

Reset
status

0x00Port E control register 2PE_CR2Port E0x00 5018

0x00Port F data output latch registerPF_ODR

0xXX

0x00Port F data direction registerPF_DDR0x00 501B

0x00Port F control register 1PF_CR10x00 501C

0x00Port F control register 2PF_CR20x00 501D

Reset
status

(1)

0x00 5059

0x00 505A

0x00 505B

0x00 505C

0x00 505D

0x00 505E

0x00 505F

0x00 5060 to

0x00 5061

0x00 5062

0x00 5063

Flash

FLASH _IAPSR

Reserved area (2 bytes)

FLASH _PUKRFlash

Reserved area (1 byte)

0x00Flash control register 1FLASH_CR1

0x00Flash control register 2FLASH_CR2

0xFFFlash complementary control register 2FLASH_NCR2

0x00Flash protection registerFLASH _FPR

0xFFFlash complementary protection registerFLASH _NFPR

0x00Flash in-application programming status

register

0x00Flash program memory unprotection

register

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STM8S903K3 STM8S903F3Memory and register map

0x00 5064

0x00 5065 to

0x00 509F

0x00 50A0

0x00 50A1

0x00 50A2 to

0x00 50B2

0x00 50B3

0x00 50B4 to

0x00 50BF

Reserved area (59 bytes)

Reserved area (17 bytes)

Reserved area (12 bytes)

Register nameRegister labelBlockAddress

Reset
status

0x00Data EEPROM unprotection registerFLASH _DUKRFlash

0x00External interrupt control register 1EXTI_CR1ITC

0x00External interrupt control register 2EXTI_CR2

Reset status registerRST_SRRST

0xXX

(1)

0x00 50C0

0x00 50C1

0x00 50C2

0x00 50C3

0x00 50C4

0x00 50C5

0x00 50C6

0x00 50C7

0x00 50C8

0x00 50C9

0x01Internal clock control registerCLK_ICKRCLK

0x00External clock control registerCLK_ECKR

Reserved area (1 byte)

0xE1Clock master status registerCLK_CMSRCLK

0xE1Clock master switch registerCLK_SWR

0xXXClock switch control registerCLK_SWCR

0x18Clock divider registerCLK_CKDIVR

0xFFPeripheral clock gating register 1CLK_PCKENR1

0x00Clock security system registerCLK_CSSR

0x00Configurable clock control registerCLK_CCOR

0x00 50CA

0xFFPeripheral clock gating register 2CLK_PCKENR2

DocID15590 Rev 830/116

Memory and register mapSTM8S903K3 STM8S903F3

0x00 50CC

0x00 50CD

0x00 50CE to

0x00 50D0

0x00 50D1

0x00 50D2

0x00 50D3 to

00 50DF

0x00 50E0

0x00 50E1

Reserved area (3 bytes)

Reserved area (13 bytes)

Register nameRegister labelBlockAddress

Reset
status

0x00HSI clock calibration trimming registerCLK_HSITRIMR

SWIM clock control registerCLK_SWIMCCR

0bXXXX
XXX0

0x7FWWDG control registerWWDG_CRWWDG

0x7FWWDR window registerWWDG_WR

IWDG key registerIWDG_KRIWDG

0xXX

(2)

0x00IWDG prescaler registerIWDG_PR

0x00 50E2

0x00 50E3 to

0x00 50EF

0x00 50F0

0x00 50F1

0x00 50F2

0x00 50F3

0x00 50F4 to

0x00 50FF

0x00 5200

0x00 5201

Reserved area (13 bytes)

AWU_APR

Reserved area (12 bytes)

0xFFIWDG reload registerIWDG_RLR

0x00AWU control/status register 1AWU_CSR1AWU

0x3FAWU asynchronous prescaler buffer

register

0x00AWU timebase selection registerAWU_TBR

0x1FBEEP control/status registerBEEP_CSRBEEP

0x00SPI control register 1SPI_CR1SPI

0x00SPI control register 2SPI_CR2

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STM8S903K3 STM8S903F3Memory and register map

0x00 5202

0x00 5203

0x00 5204

0x00 5205

0x00 5206

0x00 5207

0x00 5208 to

0x00 520F

0x00 5210

0x00 5211

Reserved area (8 bytes)

Register nameRegister labelBlockAddress

Reset
status

0x00SPI interrupt control registerSPI_ICR

0x02SPI status registerSPI_SR

0x00SPI data registerSPI_DR

0x07SPI CRC polynomial registerSPI_CRCPR

0xFFSPI Rx CRC registerSPI_RXCRCR

0xFFSPI Tx CRC registerSPI_TXCRCR

0x00I2C control register 1I2C_CR1I2C

0x00I2C control register 2I2C_CR2

0x00 5212

0x00 5213

0x00 5214

0x00 5215

0x00 5216

0x00 5217

0x00 5218

0x00 5219

0x00 521A

0x00 521B

0x00I2C frequency registerI2C_FREQR

0x00I2C Own address register lowI2C_OARL

0x00I2C Own address register highI2C_OARH

Reserved

0x00I2C data registerI2C_DR

0x00I2C status register 1I2C_SR1

0x00I2C status register 2I2C_SR2

0x0xI2C status register 3I2C_SR3

0x00I2C interrupt control registerI2C_ITR

0x00I2C Clock control register lowI2C_CCRL

DocID15590 Rev 832/116

Memory and register mapSTM8S903K3 STM8S903F3

0x00 521C

0x00 521D

0x00 521E

0x00 521F to

0x00 522F

0x00 5230

0x00 5231

0x00 5232

0x00 5233

0x00 5234

Reserved area (17 bytes)

Register nameRegister labelBlockAddress

Reset
status

0x00I2C Clock control register highI2C_CCRH

0x02I2C TRISE registerI2C_TRISER

0x00I2C packet error checking registerI2C_PECR

0xC0UART1 status registerUART1_SRUART1

0xXXUART1 data registerUART1_DR

0x00UART1 baud rate register 1UART1_BRR1

0x00UART1 baud rate register 2UART1_BRR2

0x00UART1 control register 1UART1_CR1

0x00 5235

0x00 5236

0x00 5237

0x00 5238

0x00 5239

0x00 523A

0x00 523B to

0x00 523F

0x00 5250

0x00 5251

0x00UART1 control register 2UART1_CR2

0x00UART1 control register 3UART1_CR3

0x00UART1 control register 4UART1_CR4

0x00UART1 control register 5UART1_CR5

0x00UART1 guard time registerUART1_GTR

0x00UART1 precaler registerUART1_PSCR

Reserved area (21 bytes)

0x00TIM1 control register 1TIM1_CR1TIM1

0x00TIM1 control register 2TIM1_CR2

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STM8S903K3 STM8S903F3Memory and register map

0x00 5252

0x00 5253

0x00 5254

0x00 5255

0x00 5256

0x00 5257

0x00 5258

0x00 5259

0x00 525A

Register nameRegister labelBlockAddress

Reset
status

0x00TIM1 slave mode control registerTIM1_SMCR

0x00TIM1 external trigger registerTIM1_ETR

0x00TIM1 interrupt enable registerTIM1_IER

0x00TIM1 status register 1TIM1_SR1

0x00TIM1 status register 2TIM1_SR2

0x00TIM1 event generation registerTIM1_EGR

0x00TIM1 capture/compare mode register 1TIM1_CCMR1

0x00TIM1 capture/compare mode register 2TIM1_CCMR2

0x00TIM1 capture/compare mode register 3TIM1_CCMR3

0x00 525B

0x00 525C

0x00 525D

0x00 525E

0x00 525F

0x00 5260

0x00 5261

0x00 5262

0x00 5263

0x00 5264

TIM1_CCER1

TIM1_CCER2

TIM1 capture/compare enable register 1

TIM1 capture/compare enable register 2

0x00TIM1 capture/compare mode register 4TIM1_CCMR4

0x00

0x00

0x00TIM1 counter highTIM1_CNTRH

0x00TIM1 counter lowTIM1_CNTRL

0x00TIM1 prescaler register highTIM1_PSCRH

0x00TIM1 prescaler register lowTIM1_PSCRL

0xFFTIM1 auto-reload register highTIM1_ARRH

0xFFTIM1 auto-reload register lowTIM1_ARRL

0x00TIM1 repetition counter registerTIM1_RCR

0x00 5265

0x00TIM1 capture/compare register 1 highTIM1_CCR1H

DocID15590 Rev 834/116

Memory and register mapSTM8S903K3 STM8S903F3

0x00 5266

0x00 5267

0x00 5268

0x00 5269

0x00 526A

0x00 526B

0x00 526C

0x00 526D

0x00 526E

Register nameRegister labelBlockAddress

Reset
status

0x00TIM1 capture/compare register 1 lowTIM1_CCR1L

0x00TIM1 capture/compare register 2 highTIM1_CCR2H

0x00TIM1 capture/compare register 2 lowTIM1_CCR2L

0x00TIM1 capture/compare register 3 highTIM1_CCR3H

0x00TIM1 capture/compare register 3 lowTIM1_CCR3L

0x00TIM1 capture/compare register 4 highTIM1_CCR4H

0x00TIM1 capture/compare register 4 lowTIM1_CCR4L

0x00TIM1 break registerTIM1_BKR

0x00TIM1 dead-time registerTIM1_DTR

0x00 526F

0x00 5270 to

0x00 52FF

0x00 5300

0x00 5301

0x00 5302

0x00 5303

0x00 5304

0x00 5305

0x00 5306

0x00 5307

0x00TIM1 output idle state registerTIM1_OISR

Reserved area (147 bytes)

0x00TIM5 control register 1TIM5_CR1TIM5

0x00TIM5 control register 2TIM5_CR2

0x00TIM5 slave mode control registerTIM5_SMCR

0x00TIM5 interrupt enable registerTIM5_IER

0x00TIM5 status register 1TIM5_SR1

0x00TIM5 status register 2TIM5_SR2

0x00TIM5 event generation registerTIM5_EGR

0x00TIM5 capture/compare mode register 1TIM5_CCMR1

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STM8S903K3 STM8S903F3Memory and register map

0x00 5308

0x00 5309

0x00 530A

0x00 530B

00 530C0x

0x00 530D

0x00 530E

0x00 530F

0x00 5310

TIM5_CCER1

TIM5_CCER2

Register nameRegister labelBlockAddress

TIM5 capture/compare enable register 1

TIM5 capture/compare enable register 2

Reset
status

0x00TIM5 capture/compare mode register 2TIM5_CCMR2

0x00TIM5 capture/compare mode register 3TIM5_CCMR3

0x00

0x00

0x00TIM5 counter highTIM5_CNTRH

0x00TIM5 counter lowTIM5_CNTRL

0x00TIM5 prescaler registerTIM5_PSCR

0xFFTIM5 auto-reload register highTIM5_ARRH

0xFFTIM5 auto-reload register lowTIM5_ARRL

0x00 5311

0x00 5312

0x00 5313

0x00 5314

0x00 5315

0x00 5316

0x00 5317 to

0x00 533F

0x00 5340

0x00 5341

0x00 5342

0x00TIM5 capture/compare register 1 highTIM5_CCR1H

0x00TIM5 capture/compare register 1 lowTIM5_CCR1L

0x00TIM5 capture/compare register 2 highTIM5_CCR2H

0x00TIM5 capture/compare register 2 lowTIM5_CCR2L

0x00TIM5 capture/compare register 3 highTIM5_CCR3H

0x00TIM5 capture/compare register 3 lowTIM5_CCR3L

Reserved area (43 bytes)

0x00TIM6 control register 1TIM6_CR1TIM6

0x00TIM6 control register 2TIM6_CR2

0x00TIM6 slave mode control registerTIM6_SMCR

DocID15590 Rev 836/116

Memory and register mapSTM8S903K3 STM8S903F3

0x00 5343

0x00 5344

0x00 5345

0x00 5346

0x00 5347

0x00 5348

0x00 5349 to

0x00 53DF

0x00 53E0 to

0x00 53F3

Reserved area (153 bytes)

Register nameRegister labelBlockAddress

Reset
status

0x00TIM6 interrupt enable registerTIM6_IER

0x00TIM6 status registerTIM6_SR

0x00TIM6 event generation registerTIM6_EGR

0x00TIM6 counterTIM6_CNTR

0x00TIM6 prescaler registerTIM6_PSCR

0xFFTIM6 auto-reload registerTIM6_ARR

0x00ADC data buffer registersADC _DBxRADC1

0x00 53F4 to

0x00 53FF

0x00 5400

0x00 5401

0x00 5402

0x00 5403

0x00 5404

0x00 5405

0x00 5406

0x00 5407

0x00 5408

Reserved area (12 bytes)

0x00ADC control/status registerADC _CSRADC1

cont’d

0x00ADC configuration register 1ADC_CR1

0x00ADC configuration register 2ADC_CR2

0x00ADC configuration register 3ADC_CR3

0xXXADC data register highADC_DRH

0xXXADC data register lowADC_DRL

0x00ADC Schmitt trigger disable register highADC_TDRH

0x00ADC Schmitt trigger disable register lowADC_TDRL

0x03ADC high threshold register highADC_HTRH

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STM8S903K3 STM8S903F3Memory and register map

0x00 5409

0x00 540A

0x00 540B

0x00 540C

0x00 540D

0x00 540E

0x00 540F

0x00 5410 to

0x00 57FF

Reserved area (1008 bytes)

Register nameRegister labelBlockAddress

Reset
status

0xFFADC high threshold register lowADC_HTRL

0x00ADC low threshold register highADC_LTRH

0x00ADC low threshold register lowADC_LTRL

0x00ADC analog watchdog status register highADC_AWSRH

0x00ADC analog watchdog status register lowADC_AWSRL

0x00ADC analog watchdog control register highADC _AWCRH

0x00ADC analog watchdog control register lowADC_AWCRL

(1)

Depends on the previous reset source.

(2)

Write only register.

CPU/SWIM/debug module/interrupt controller registers6.2.3

Table 9: CPU/SWIM/debug module/interrupt controller registers

0x00 7F00

(1)

CPU

Reset statusRegister nameRegister labelBlockAddress

0x00AccumulatorA

0x00Program counter extendedPCE0x00 7F01

0x00Program counter highPCH0x00 7F02

0x00Program counter lowPCL0x00 7F03

0x00X index register highXH0x00 7F04

0x00X index register lowXL0x00 7F05

0x00Y index register highYH0x00 7F06

0x00Y index register lowYL0x00 7F07

0x03Stack pointer highSPH0x00 7F08

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Memory and register mapSTM8S903K3 STM8S903F3

Reset statusRegister nameRegister labelBlockAddress

0xFFStack pointer lowSPL0x00 7F09

0x28Condition code registerCCR0x00 7F0A

0x00 7F0B to
0x00 7F5F

0x00 7F70

0x00 7F78 to
0x00 7F79

0x00 7F81 to
0x00 7F8F

Reserved area (85 bytes)

0x00Global configuration registerCFG_GCRCPU0x00 7F60

0xFFInterrupt software priority register 1ITC_SPR1

0xFFInterrupt software priority register 2ITC_SPR20x00 7F71

0xFFInterrupt software priority register 3ITC_SPR30x00 7F72

0xFFInterrupt software priority register 4ITC_SPR40x00 7F73

ITC

0xFFInterrupt software priority register 5ITC_SPR50x00 7F74

0xFFInterrupt software priority register 6ITC_SPR60x00 7F75

0xFFInterrupt software priority register 7ITC_SPR70x00 7F76

0xFFInterrupt software priority register 8ITC_SPR80x00 7F77

Reserved area (2 bytes)

0x00SWIM control status registerSWIM_CSRSWIM0x00 7F80

Reserved area (15 bytes)

0x00 7F90

DM

DM_BK1RE

DM_BK2RE0x00 7F93

DM_CSR10x00 7F98

DM_CSR20x00 7F99

0xFFDM breakpoint 1 register extended

byte

0xFFDM breakpoint 1 register high byteDM_BK1RH0x00 7F91

0xFFDM breakpoint 1 register low byteDM_BK1RL0x00 7F92

0xFFDM breakpoint 2 register extended

byte

0xFFDM breakpoint 2 register high byteDM_BK2RH0x00 7F94

0xFFDM breakpoint 2 register low byteDM_BK2RL0x00 7F95

0x00DM debug module control register 1DM_CR10x00 7F96

0x00DM debug module control register 2DM_CR20x00 7F97

0x10DM debug module control/status

register 1

0x00DM debug module control/status

register 2

39/116DocID15590 Rev 8

0x00 7F9F

(1)

Accessible by debug module only

STM8S903K3 STM8S903F3Memory and register map

Reset statusRegister nameRegister labelBlockAddress

0xFFDM enable function registerDM_ENFCTR0x00 7F9A

Reserved area (5 bytes)0x00 7F9B to

DocID15590 Rev 840/116

Interrupt vector mappingSTM8S903K3 STM8S903F3

Interrupt vector mapping7

Table 10: Interrupt mapping

IRQ
no.

block

DescriptionSource

Port A external interruptsEXTI03

Wakeup from
halt mode

(1)

Yes

active-halt
mode

(1)

Vector addressWakeup from

0x00 8000YesYesResetRESET

0x00 8004--Software interruptTRAP

0x00 8008--External top level interruptTLI0

0x00 800CYes-Auto wake up from haltAWU1

0x00 8010--Clock controllerCLK2

0x00 8014Yes

0x00 8018YesYesPort B external interruptsEXTI14

0x00 801CYesYesPort C external interruptsEXTI25

0x00 8020YesYesPort D external interruptsEXTI36

0x00 8024YesYesPort E external interruptsEXTI47

0x00 8028Port FEXTI58

0x00 802C--Reserved9

0x00 8030YesYesEnd of transferSPI10

TIM111

trigger/ break

0x00 8034--TIM1 update/ overflow/ underflow/

0x00 8038--TIM1 capture/ compareTIM112

0x00 803C--TIM5 update/ overflow/ triggerTIM513

0x00 8040--TIM5 capture/ compareTIM514

0x00 8044--Reserved15

0x00 8048--Reserved16

0x00 804C--Tx completeUART117

0x00 8050--Receive register DATA FULLUART118

0x00 8054YesYesI2C interruptI2C19

0x00 8058--Reserved20

0x00 805C--Reserved21

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STM8S903K3 STM8S903F3Interrupt vector mapping

IRQ

block

no.

ADC122

Reserved

(1)

Except PA1

DescriptionSource

watchdog interrupt

Wakeup from
halt mode

Vector addressWakeup from
active-halt
mode

0x00 8060--ADC1 end of conversion/ analog

0x00 8064--TIM6 update/ overflow/ triggerTIM623

0x00 8068--EOP/ WR_PG_DISFlash24

0x00 806C to
0x00 807C

DocID15590 Rev 842/116

Option bytesSTM8S903K3 STM8S903F3

Option bytes8

Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.

Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in the table below.

Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP
option that can only be modified in ICP mode (via SWIM).

Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication
protocol and debug module user manual (UM0470) for information on SWIM programming
procedures.

Table 11: Option bytes

Addr.

0x4800

0x4801

0x4803

0x4805h

0x4807

0x4809

Option
name

protection
(ROP)

code(UBC)

function
remapping
(AFR)

option

option

startup

byte no.

Option bitsOption

01234567

AFR6AFR7OPT2Alternate

ReservedOPT3Miscell.

ReservedNOPT30x4806

ReservedNOPT40x4808

TRIM

NHSI
TRIM

LSI_ ENHSI

NLSI_
EN

EXT CLKReservedOPT4Clock

NEXT
CLK

IWDG
_HW

NIWDG
_HW

SEL

WUSEL

WWDG
_HW

NWWDG
_HW

NPRSC1NCKA

_HALT

G_HALT

SC0

Factory
default
setting

0x00ROP [7:0]OPT0Read-out

0x00UBC [7:0]OPT1User boot

0xFFNUBC [7:0]NOPT10x4802

0x00AFR0AFR1AFR2AFR3AFR4AFR5

0xFFNAFR0NAFR1NAFR2NAFR3NAFR4NAFR5NAFR6NAFR7NOPT20x4804

0x00WWDG

0xFFNWW

0x00PRS C0PRS C1CKAWU

0xFFNPR

0x00HSECNT [7:0]OPT5HSE clock

0xFFNHSECNT [7:0]NOPT50x480A

OPT0

Table 12: Option byte description

DescriptionOption byte no.

ROP[7:0] Memory readout protection (ROP)

0xAA: Enable readout protection (write access via SWIM protocol)

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STM8S903K3 STM8S903F3Option bytes

DescriptionOption byte no.

Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM memory readout protection for details.

OPT1

OPT2

OPT3

UBC[7:0] User boot code area

0x00: no UBC, no write-protection

0x01: Page 0 defined as UBC, memory write-protected

0x02: Pages 0 to 1 defined as UBC, memory write-protected.

Page 0 and 1 contain the interrupt vectors.

...

0x7F: Pages 0 to 126 defined as UBC, memory write-protected

Other values: Pages 0 to 127 defined as UBC, memory
write-protected

Note: Refer to the family reference manual (RM0016) section on
Flash write protection for more details.

AFR[7:0]

Refer to following section for alternate function remapping decriptions
of bits [7:2] and [1:0] respectively.

HSITRIM:High speed internal clock trimming register size

0: 3-bit trimming supported in CLK_HSITRIMR register

1: 4-bit trimming supported in CLK_HSITRIMR register

LSI_EN:Low speed internal clock enable

0: LSI clock is not available as CPU clock source

1: LSI clock is available as CPU clock source

IWDG_HW: Independent watchdog

0: IWDG Independent watchdog activated by software

1: IWDG Independent watchdog activated by hardware

WWDG_HW: Window watchdog activation

0: WWDG window watchdog activated by software

1: WWDG window watchdog activated by hardware

WWDG_HALT: Window watchdog reset on halt

DocID15590 Rev 844/116

DescriptionOption byte no.

0: No reset generated on halt if WWDG active

1: Reset generated on halt if WWDG active

Option bytesSTM8S903K3 STM8S903F3

OPT4

OPT5

EXTCLK: External clock selection

0: External crystal connected to OSCIN/OSCOUT

1: External clock signal on OSCIN

CKAWUSEL:Auto wake-up unit/clock

0: LSI clock source selected for AWU

1: HSE clock with prescaler selected as clock source for for AWU

PRSC[1:0] AWU clock prescaler

0x: 16 MHz to 128 kHz prescaler

10: 8 MHz to 128 kHz prescaler

11: 4 MHz to 128 kHz prescaler

HSECNT[7:0]:HSE crystal oscillator stabilization time

0x00: 2048 HSE cycles

0xB4: 128 HSE cycles

0xD2: 8 HSE cycles

0xE1: 0.5 HSE cycles

STM8S903K3/F3 alternate function remapping bits8.1

Table 13: STM8S903K3 alternate function remapping bits [7:2] for 32-pin packages

Option byte no.

OPT2

Description

AFR7 Alternate function remapping option 7

0: AFR7 remapping option inactive: Default alternate functions

1: Port C3 alternate function = TIM1_CH1N; port C4 alternate
function = TIM1_CH2N.

AFR6 Alternate function remapping option 6

0: AFR6 remapping option inactive: Default alternate function

1: Port D7 alternate function = TIM1_CH4.

(1)

(2)

.

(2)

.

45/116DocID15590 Rev 8

STM8S903K3 STM8S903F3Option bytes

Option byte no.

Description

(1)

AFR5 Alternate function remapping option 5

0: AFR5 remapping option inactive: Default alternate function

1: Port D0 alternate function = CLK_CCO.

AFR4 Alternate function remapping option 4

0: AFR4 remapping option inactive: Default alternate functions

1: Port B4 alternate function = ADC_ETR; port B5 alternate function
= TIM1_BKIN.

AFR3 Alternate function remapping option 3

0: AFR3 remapping option inactive: Default alternate function

1: Port C3 alternate function = TLI.

AFR2 Alternate function remapping option 2

0: AFR2 remapping option inactive: Default alternate functions

1: Port C4 alternate function = AIN2; port D2 alternate function =
AIN3; port D4 alternate function = UART1_CK.

(1)

Do not use more than one remapping option in the same port.

(2)

Refer to pinout description.

(2)

(2)

(2)

(2)

.

.

.

.

Table 14: STM8S903F3 alternate function remapping bits [7:2] for 20-pin packages

Option byte no.

OPT2

Description

AFR7 Alternate function remapping option 7

(1)

0: AFR7 remapping option inactive: Default alternate functions

1: Port C3 alternate function = TIM1_CH1N; port C4 alternate
function = TIM1_CH2N.

AFR6 Alternate function remapping option 6

Reserved.

AFR5 Alternate function remapping option 5

Reserved.

AFR4 Alternate function remapping option 4

0: AFR4 remapping option inactive: Default alternate functions

1: Port B4 alternate function = ADC_ETR; port B5 alternate function
= TIM1_BKIN.

AFR3 Alternate function remapping option 3

(2)

(2)

.

DocID15590 Rev 846/116

Option bytesSTM8S903K3 STM8S903F3

Option byte no.

Description

(1)

0: AFR3 remapping option inactive: Default alternate function

1: Port C3 alternate function = TLI.

AFR2 Alternate function remapping option 2

Reserved.

(1)

Do not use more than one remapping option in the same port.

(2)

Refer to pinout description.

Table 15: STM8S903K3 alternate function remapping bits [1:0] for 32-pin packages

AFR1 option bit
value

value

00

AFR1 and AFR0 remapping options inactive:
Default alternate functions

PC510

Alternate function mappingI/O portAFR0 option bit

(1)

TIM5_CH1

TIM1_CH1PC6

(2)

.

11

(1)

Refer to pinout description.

TIM1_CH2PC7

PA301

SPI_NSS

TIM5_CH3PD2

TIM5_CH3PD2

TIM5_CH1PC5

TIM1_CH1PC6

TIM1_CH2PC7

TIM1_CH3NPC2

TIM1_CH2NPC1

TIM1_CH1NPE5

UART1_TXPA3

UART1_RXPF4

47/116DocID15590 Rev 8

STM8S903K3 STM8S903F3Option bytes

Table 16: STM8S903F3 alternate function remapping bits [1:0] for 20-pin packages

AFR1 option bit
value

value

00

11

Alternate function mappingI/O portAFR0 option bit

AFR1 and AFR0 remapping options inactive:
Default alternate functions

PC510

TIM5_CH1

(1)

TIM1_CH1PC6

TIM1_CH2PC7

PA301

SPI_NSS

TIM5_CH3PD2

TIM5_CH3PD2

TIM5_CH1PC5

TIM1_CH1PC6

TIM1_CH2PC7

—PC2

—PC1

(1)

Refer to pinout description.

TIM1_CH1NPE5

UART1_TXPA3

UART1_RXPF4

DocID15590 Rev 848/116

Unique IDSTM8S903K3 STM8S903F3

Unique ID9

The devices feature a 96-bit unique device identifier which provides a reference number that
is unique for any device and in any context. The 96 bits of the identifier can never be altered
by the user.

The unique device identifier can be read in single bytes and may then be concatenated using
a custom algorithm.

The unique device identifier is ideally suited:

For use as serial numbers

•

For use as security keys to increase the code security in the program memory while using

•

and combining this unique ID with software cryptograhic primitives and protocols before
programming the internal memory.

To activate secure boot processes

•

Table 17: Unique ID registers (96 bits)

Address

0x4865

0x4867

0x486A

description

X co-ordinate

on the wafer

Y co-ordinate

on the wafer

Lot number

Unique ID bitsContent

01234567

U_ID[7:0]

U_ID[15:8]0x4866

U_ID[23:16]

U_ID[31:24]0x4868

U_ID[39:32]Wafer number0x4869

U_ID[47:40]

U_ID[55:48]0x486B

U_ID[63:56]0x486C

U_ID[71:64]0x486D

U_ID[79:72]0x486E

U_ID[87:80]0x486F

U_ID[95:88]0x4870

49/116DocID15590 Rev 8

50 pF

STM8 pin

STM8S903K3 STM8S903F3Electrical characteristics

Electrical characteristics10

Parameter conditions10.1

Unless otherwise specified, all voltages are referred to VSS.

Minimum and maximum values10.1.1

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100 % of the devices with an ambient temperature at TA= 25 °C and TA= T
the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on characterization,
the minimum and maximum values refer to sample tests and represent the mean value plus
or minus three times the standard deviation (mean ± 3 Σ).

Typical values10.1.2

Unless otherwise specified, typical data are based on TA= 25 °C, VDD= 5 V. They are given
only as design guidelines and are not tested.

Amax

(given by

Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ± 2 Σ).

Typical curves10.1.3

Unless otherwise specified, all typical curves are given only as design guidelines and are not
tested.

Loading capacitor10.1.4

The loading conditions used for pin parameter measurement are shown in the following figure.

Figure 8: Pin loading conditions

Pin input voltage10.1.5

The input voltage measurement on a pin of the device is described in the following figure.

DocID15590 Rev 850/116

STM8 pin

V

IN

Electrical characteristicsSTM8S903K3 STM8S903F3

Figure 9: Pin input voltage

Absolute maximum ratings10.2

Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.

Table 18: Voltage characteristics

UnitMaxMinRatingsSymbol

V

DDx

- V

SS

Supply voltage

(1)

6.5-0.3

V

|V

|V

V

IN

DDx

SSx

ESD

- VDD|

- VSS|

Input voltage on true open drain pins

Input voltage on any other pin

(2)

Variations between different power pins

Variations between all the different ground
pins

Electrostatic discharge voltage

(2)

6.5VSS- 0.3

VDD+ 0.3VSS- 0.3

50-

50-

See "Absolute

maximum ratings

V

mV

(electrical sensitivity)"

(1)

All power (VDD) and ground (VSS) pins must always be connected to the external power supply

(2)

I

INJ(PIN)

cannot be respected, the injection current must be limited externally to the I

must never be exceeded. This is implicitly insured if VINmaximum is respected. If VINmaximum

INJ(PIN)

value. A positive
injection is induced by VIN>VDDwhile a negative injection is induced by VIN<VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VINmaximum must always be respected

Table 19: Current characteristics

I

VDD

RatingsSymbol

Total current into VDDpower lines (source)

(2)

Max

(1)

Unit

mA100

51/116DocID15590 Rev 8

STM8S903K3 STM8S903F3Electrical characteristics

RatingsSymbol

I

VSS

I

IO

Total current out of VSSground lines (sink)

Output current sunk by any I/O and control pin

(2)

Output current source by any I/Os and control pin

I

INJ(PIN)

(3) (4)

Injected current on NRST pin

Injected current on OSCIN pin

Injected current on any other pin

INJ(PIN)

(3)

Total injected current (sum of all I/O and control pins)

must never be exceeded. This is implicitly insured if VINmaximum is respected. If VINmaximum

ΣI

INJ(PIN)

(1)

Data based on characterization results, not tested in production.

(2)

All power (VDD) and ground (VSS) pins must always be connected to the external supply.

(3)

I

cannot be respected, the injection current must be limited externally to the I

(5)

(5)

INJ(PIN)

value. A positive

Max

(1)

80

20

- 20

± 4

± 4

± 4

± 20

Unit

injection is induced by VIN>VDDwhile a negative injection is induced by VIN<VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VINmaximum must always be respected

(4)

ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins
should be avoided as this significantly reduces the accuracy of the conversion being performed on
another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins
which may potentially inject negative current. Any positive injection current within the limits specified for
I

INJ(PIN)

(5)

and ΣI

INJ(PIN)

in the I/O port pin characteristics section does not affect the ADC accuracy.

When several inputs are submitted to a current injection, the maximum ΣI

INJ(PIN)

is the absolute sum
of the positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣI

INJ(PIN)

maximum current injection on four I/O port pins of the device.

STG

J

Table 20: Thermal characteristics

UnitValueRatingsSymbol

-65 to +150Storage temperature rangeT
°C

150Maximum junction temperatureT

DocID15590 Rev 852/116

Electrical characteristicsSTM8S903K3 STM8S903F3

Operating conditions10.3

Table 21: General operating conditions

UnitMaxMinConditionsParameterSymbol

CPU

DD

VCAP

(3)

P

D

(1)

C

: capacitance of external

EXT

capacitor

ESR of external capacitor

for suffix 6

°C for suffix 3

(2)

MHz160Internal CPU clock frequencyf

V5.52.95Standard operating voltageV

nF3300470

Ω0.3-at 1 MHz

nH15-ESL of external capacitor

mW182-TSSOP20Power dissipation at TA= 85 °C

1000-SO20W

198-UFQFPN20

333-LQFP32

526-UFQFPN32

333-SDIP32

45-TSSOP20Power dissipation at TA= 125

250-SO20W

49-UFQFPN20

83-LQFP32

132-UFQFPN32

83-SDIP32

T

A

°C85-40Maximum power dissipationAmbient temperature for 6 suffix

version

125-40Maximum power dissipationAmbient temperature for 3 suffix

version

J

105-406 suffix versionJunction temperature rangeT

130-403 suffix version

(1)

Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter
dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum
value must be respected for the full application range.

(2)

This frequency of 1 MHz as a condition for VCAP parameters is given by design of internal regulator

53/116DocID15590 Rev 8

(3)

16

12

8
4

0

2.95

4.0

5.0

5.5

f

CPU

(MHz)

Functionality guaranteed

@TA-40 to 125 °C

Supply voltage

Functionality
not
guaranteed
in this area

To calculate P

Dmax(TA

), use the formula P

Dmax

= (T

STM8S903K3 STM8S903F3Electrical characteristics

- TA)/ΘJA(see Thermal characteristics).

Jmax

VDD

Figure 10: f

CPUmax

versus V

DD

Table 22: Operating conditions at power-up/power-down

(1)

UnitMaxTypMinConditionsParameterSymbol

µs/V∞2VDDrise time ratet

∞2VDDfall time rate

TEMP

V

IT+

threshold

V

IT-

2.82.652.5Brown-out reset

threshold

V

HYS(BOR)

hysteresis

(1)

Reset is always generated after a t

still above the minimum ooperating voltage (VDDmin) when the t

delay. The application must ensure that VDDis

TEMP

delay has elapsed.

TEMP

VCAP external capacitor10.3.1

Stabilization for the main regulator is achieved connecting an external capacitor C
V

pin. C

CAP

the series inductance to less than 15 nH.

is specified in the Operating conditions section. Care should be taken to limit

EXT

DocID15590 Rev 854/116

EXT

ms1.7VDDrisingReset release delayt

V2.852.72.6Power-on reset

mV70Brown-out reset

to the

C

Rleak

ESR ESL

Electrical characteristicsSTM8S903K3 STM8S903F3

Figure 11: External capacitor C

EXT

1. ESR is the equivalent series resistance and ESL is the equivalent inductance.

Supply current characteristics10.3.2

The current consumption is measured as described in Pin input voltage.

Total current consumption in run mode10.3.2.1

The MCU is placed under the following conditions:

All I/O pins in input mode with a static value at VDDor VSS(no load)

•

All peripherals are disabled (clock stopped by peripheral clock gating registers) except if

•

explicitly mentioned.

Subject to general operating conditions for VDDand TA.

Table 23: Total current consumption with code execution in run mode at VDD= 5 V

I

DD(RUN)

I

DD(RUN)

Supply current

in run mode,

code executed

from RAM

Supply current

in run mode,

code executed

from Flash

Supply current

in run mode,

code executed

from Flash

f

= f

CPU

MASTER

16 MHz

= f

CPU

MASTER

125 kHz

f

= f

CPU

MASTER

15.625 kHz

f

= f

CPU

MASTER

128 kHz

f

= f

CPU

MASTER

16 MHz

f

= f

CPU

MASTER

2 MHz

=

/128 =

/128 =

=

=

=

(2)

(1)

TypConditionsParameterSymbol

Max

Unit

-2.3HSE crystal osc. (16 MHz)

2.352HSE user ext. clock (16 MHz)

21.7HSI RC osc. (16 MHz)

-0.86HSE user ext. clock (16 MHz)f

0.870.7HSI RC osc. (16 MHz)

0.580.46HSI RC osc. (16 MHz/8)

mA

0.550.41LSI RC osc. (128 kHz)

-4.5HSE crystal osc. (16 MHz)

4.754.3HSE user ext. clock (16 MHz)

4.53.7HSI RC osc. (16 MHz)

1.050.84HSI RC osc. (16 MHz/8)
mA

55/116DocID15590 Rev 8

STM8S903K3 STM8S903F3Electrical characteristics

f

CPU

= f

MASTER

/128 =

125 kHz

f

CPU

= f

MASTER

/128 =

15.625 kHz

f

CPU

= f

MASTER

=

128 kHz

(1)

Data based on characterization results, not tested in production.

(2)

Default clock configuration measured with all peripherals off.

Table 24: Total current consumption with code execution in run mode at VDD= 3.3 V

(1)

TypConditionsParameterSymbol

Max

Unit

0.90.72HSI RC osc. (16 MHz)

0.580.46HSI RC osc. (16 MHz/8)

0.570.42LSI RC osc. (128 kHz)

I

DD(RUN)

Supply current

in run mode,

code executed

from RAM

Supply current

in run mode,

code executed

from Flash

f

CPU

= f

MASTER

=

16 MHz

CPU

= f

MASTER

/

128 = 125 kHz

f

CPU

= f

MASTER

/

128 = 15.625 kHz

f

CPU

= f

MASTER

=

128 kHz

f

CPU

= f

MASTER

=

16 MHz

f

CPU

= f

MASTER

=

2 MHz

f

CPU

= f

MASTER

/

128 = 125 kHz

(2)

TypConditionsParameterSymbol

Max

(1)

Unit

-1.8HSE crystal osc. (16 MHz)

2.32HSE user ext. clock (16 MHz)

21.5HSI RC osc. (16 MHz)

-0.81HSE user ext. clock (16 MHz)f

0.870.7HSI RC osc. (16 MHz)

0.580.46HSI RC osc. (16 MHz/8)

0.550.41LSI RC osc. (128 kHz)

mA

-4HSE crystal osc. (16 MHz)

4.73.9HSE user ext. clock (16 MHz)

4.53.7HSI RC osc. (16 MHz)

1.050.84HSI RC osc. (16 MHz/8)

0.90.72HSI RC osc. (16 MHz)

f

CPU

= f

MASTER

/

HSI RC osc. (16 MHz/8)

DocID15590 Rev 856/116

0.580.46

Electrical characteristicsSTM8S903K3 STM8S903F3

128 = 15.625 kHz

f

CPU

= f

MASTER

=

128 kHz

(1)

Data based on characterization results, not tested in production.

(2)

Default clock configuration measured with all peripherals off.

Total current consumption in wait mode10.3.2.2

Table 25: Total current consumption in wait mode at VDD= 5 V

f

= f

CPU

16 MHz

MASTER

=

TypConditionsParameterSymbol

Max

(1)

Unit

0.570.42LSI RC osc. (128 kHz)

TypConditionsParameterSymbol

Max

(1)

Unit

-1.6HSE crystal osc. (16 MHz)

1.31.1HSE user ext. clock (16 MHz)

1.10.89HSI RC osc. (16 MHz)

f

I

DD(WFI)

Supply

current in

= f

CPU

125 kHz

MASTER

/128 =

wait mode

f

CPU

= f

MASTER

/128 =

15.625 kHz

f

CPU

= f

MASTER

=

128 kHz

(1)

Data based on characterization results, not tested in production.

(2)

Default clock configuration measured with all peripherals off.

Table 26: Total current consumption in wait mode at VDD= 3.3 V

HSE crystal osc.

(16 MHz)

HSE user ext. clock

I

DD(WFI)

Supply current

in wait mode

f

= f

CPU

16 MHz

MASTER

=

(16 MHz)

(2)

0.880.7HSI RC osc. (16 MHz)
mA

0.570.45HSI RC osc. (16 MHz/8)

0.540.4LSI RC osc. (128 kHz)

TypConditionsParameterSymbol

Max

(1)

Unit

-1.1

mA

1.31.1

57/116DocID15590 Rev 8

STM8S903K3 STM8S903F3Electrical characteristics

HSI RC osc.

(16 MHz)

f

CPU

= f

MASTER

/ 128 =

125 kHz

f

CPU

= f

MASTER

/ 128 =

15.625 kHz

f

CPU

= f

MASTER

=

128 kHz

(1)

Data based on characterization results, not tested in production.

(2)

Default clock configuration measured with all peripherals off.

HSI RC osc.

(16 MHz)

HSI RC osc.

(16 MHz/8)

LSI RC osc.

(128 kHz)

Total current consumption in active halt mode10.3.2.3

(2)

TypConditionsParameterSymbol

Max

(1)

Unit

1.10.89

0.880.7

0.570.45

0.540.4

I

DD(AH)

I

DD(AH)

I

DD(AH)

I

DD(AH)

I

DD(AH)

Table 27: Total current consumption in active halt mode at VDD= 5 V

Conditions

Main

ParameterSymbol

Supply current
in active halt
mode

Supply current
in active halt
mode

Supply current
in active halt
mode

Supply current
in active halt
mode

Supply current
in active halt
mode

voltage
regulator

(2)

(MVR)

(3)

Clock sourceFlash mode

HSE crystal osc.

Operating modeOn

(16 MHz)

LSI RC osc.

Operating modeOn

(128 kHz)

HSE crystal osc.

Power-down modeOn

(16 MHz)

LSI RC osc.

Power-down modeOn

(128 kHz)

LSI RC osc.

Operating modeOff

(128 kHz)

Typ

Max

at 85

°C

(1)

Max

at 125

°C

(1)

--1030

300260200

--970

230200150

1108566

Unit

μA

DocID15590 Rev 858/116

Electrical characteristicsSTM8S903K3 STM8S903F3

Conditions

Main

ParameterSymbol

voltage
regulator

(2)

(MVR)

(3)

Supply current

I

DD(AH)

in active halt

Power-down mode

mode

(1)

Data based on characterization results, not tested in production

(2)

Configured by the REGAH bit in the CLK_ICKR register.

(3)

Configured by the AHALT bit in the FLASH_CR1 register.

Table 28: Total current consumption in active halt mode at VDD= 3.3 V

Conditions

Main

I

DD(AH)

ParameterSymbol

Supply current

in active halt

voltage
regulator

(2)

(MVR)

(3)

Clock sourceFlash mode

HSE crystal
osc. (16 MHz)Operating modeOn

mode

Clock sourceFlash mode

LSI RC osc.

(128 kHz)

Typ

Typ

Max at

85 °C

(1)

Max

at 85

°C

(1)

Max

at 125

°C

(1)

402010

Max at
125 °C

(1)

Unit

Unit

μA--550

LSI RC osc.

I

DD(AH)

Supply current

Operating mode

(128 kHz)

in active halt

I

DD(AH)

mode

On

HSE crystal
osc. (16 MHz)

Power-down

mode

I

DD(AH)

Supply current

I

DD(AH)

in active halt

mode

Off

I

DD(AH)

(1)

Data based on characterization results, not tested in production

(2)

Configured by the REGAH bit in the CLK_ICKR register.

(3)

Configured by the AHALT bit in the FLASH_CR1 register.

Operating mode

Power-down

mode

LSI RC osc.

(128 kHz)

(128 kHz)

290260200

--970

μA

230200150

1058066LSI RC osc.

351810

59/116DocID15590 Rev 8

Total current consumption in halt mode10.3.2.4

Table 29: Total current consumption in halt mode at VDD= 5 V

STM8S903K3 STM8S903F3Electrical characteristics

Flash in operating mode, HSI
clock after wakeup

I

DD(H)

Supply current in
halt mode

Flash in power-down mode, HSI
clock after wakeup

(1)

Data based on characterization results, not tested in production

Table 30: Total current consumption in halt mode at VDD= 3.3 V

Flash in operating mode, HSI
clock after wakeup

I

DD(H)

Supply current in
halt mode

Flash in power-down mode, HSI
clock after wakeup

(1)

Data based on characterization results, not tested in production

(1)

Max at

125 °C

(1)

Unit

TypConditionsParameterSymbol

Max at

85 °C

1057563

μA

55206.0

(1)

Max at

125 °C

(1)

Unit

TypConditionsParameterSymbol

Max at

85 °C

1007560

μA

30174.5

t

WU(WFI)

t

WU(AH)

Low power mode wakeup times10.3.2.5

Wakeup time from

wait mode to run

(3)

Wakeup time active

halt mode to run

(3)

mode

Wakeup time active

halt mode to run

(3)

mode

Table 31: Wakeup times

CPU

= f

MASTER

= 16 MHzmode

MVR voltage

Flash in operating

regulator

(4)

on

MVR voltage

regulator

(4)

on

mode

Flash in

power-down

DocID15590 Rev 860/116

(5)

(5)

HSI

(after

wakeup)

HSI

(after

wakeup)mode

(1)

TypConditionsParameterSymbol

Max

See

-0 to 16 MHz
note

Unit

(2)

-0.56f

(6)

1

(6)

(6)

2

μs

-3

Electrical characteristicsSTM8S903K3 STM8S903F3

(1)

TypConditionsParameterSymbol

Max

Unit

Wakeup time active

MVR voltage

Flash in operating

halt mode to run

(3)

mode

Wakeup time active

halt mode to run

(3)

mode

regulator

(4)

off

MVR voltage

regulator

(4)

off

mode

Flash in

power-down

Wakeup time from

t

WU(H)

(1)

Data guaranteed by design, not tested in production.

(2)

t

WU(WFI)

(3)

Measured from interrupt event to interrupt vector fetch.

(4)

Configured by the REGAH bit in the CLK_ICKR register.

(5)

Configured by the AHALT bit in the FLASH_CR1 register.

(6)

Plus 1 LSI clock depending on synchronization.

halt mode to run

(3)

mode

= 2 x 1/f

master

+ 6 x 1/f

CPU.

(5)

(5)

(5)

(5)

HSI

(after

wakeup)

HSI

(after

wakeup)mode

(6)

(6)

-48

-50

-52Flash in operating mode

-54Flash in power-down mode

Total current consumption and timing in forced reset state10.3.2.6

Table 32: Total current consumption and timing in forced reset state

I

DD(R)

(2)

state

t

RESETBL

Reset pin release to

vector fetch

(1)

Data guaranteed by design, not tested in production.

(2)

Characterized with all I/Os tied to VSS.

Current consumption of on-chip peripherals10.3.2.7

Subject to general operating conditions for VDDand TA.

TypConditionsParameterSymbol

Max

(1)

Unit

-400VDD= 5 VSupply current in reset
μA

-300VDD= 3.3 V

μs150-

61/116DocID15590 Rev 8

STM8S903K3 STM8S903F3Electrical characteristics

HSI internal RC/f

CPU

= f

MASTER

= 16 MHz, VDD= 5 V

Table 33: Peripheral current consumption

UnitTyp.ParameterSymbol

(2)

(2)

(1)

(1)

(2)

(1)

(3)

130TIM5 supply current

50TIM6 timer supply current

120UART1 supply current

45SPI supply current

65I2C supply current

1000ADC1 supply current when converting

I

DD(TIM1)

I

DD(TIM5)

I

DD(TIM6)

I

DD(UART1)

I

DD(SPI)

I

DD(I2C)

I

DD(ADC1)

(1)

Data based on a differential IDDmeasurement between reset configuration and timer

µA210TIM1 supply current

counter running at 16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in
production.

(2)

Data based on a differential IDDmeasurement between the on-chip peripheral when kept
under reset and not clocked and the on-chip peripheral when clocked and not kept under
reset. No I/O pads toggling. Not tested in production.

(3)

Data based on a differential IDDmeasurement between reset configuration and continuous

A/D conversions. Not tested in production.

Current consumption curves10.3.2.8

The following figures show typical current consumption measured with code executing in
RAM.

Figure 12: Typ I

DD(RUN)

vs. VDDHSE user external clock, f

CPU

= 16 MHz

DocID15590 Rev 862/116

Electrical characteristicsSTM8S903K3 STM8S903F3

Figure 13: Typ I

Figure 14: Typ I

DD(RUN)

DD(RUN)

vs. f

HSE user external clock, VDD= 5 V

CPU

vs. VDDHSI RC osc, f

CPU

= 16 MHz

63/116DocID15590 Rev 8

STM8S903K3 STM8S903F3Electrical characteristics

Figure 15: Typ I

Figure 16: Typ I

DD(WFI)

DD(WFI)

vs. VDDHSE user external clock, f

vs. f

HSE user external clock, VDD= 5 V

CPU

CPU

= 16 MHz

Figure 17: Typ I

DD(WFI)

DocID15590 Rev 864/116

vs. VDDHSI RC osc, f

CPU

= 16 MHz

External clock sources and timing characteristics10.3.3

V

HSEH

V

HSEL

External clock
source

OSCIN

f

HSE

STM8

HSE user external clock

Subject to general operating conditions for VDDand TA.

Table 34: HSE user external clock characteristics

Electrical characteristicsSTM8S903K3 STM8S903F3

UnitMaxMinConditionsParameterSymbol

f

HSE_ext

User external clock source
frequency

(1)

V

HSEH

OSCIN input pin high level
voltage

V

HSEL

(1)

OSCIN input pin low level
voltage

LEAK_HSE

(1)

Data based on characterization results, not tested in production.

OSCIN input leakage currentI

VSS< VIN< V

DD

Figure 18: HSE external clocksource

MHz160

DD

VDD+ 0.3 V0.7 x V

V

V

SS

0.3 x V

DD

μA+1-1

f

HSE

HSE crystal/ceramic resonator oscillator

The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and start-up stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).

Table 35: HSE oscillator characteristics

UnitMaxTypMinConditionsParameterSymbol

External high speed

oscillator frequency

MHz16-1

65/116DocID15590 Rev 8

OSCOUT

OSCIN

f

HSE

to core

C

L1

C

L2

R

F

STM8

Resonator

Consumption

control

g

m

R

m

C

m

L

m

C

O

Resonator

STM8S903K3 STM8S903F3Electrical characteristics

UnitMaxTypMinConditionsParameterSymbol

F

(1)

C

I

DD(HSE)

g

m

SU(HSE)

(1)

C is approximately equivalent to 2 x crystal Cload.

(2)

The oscillator selection can be optimized in terms of supply current using a high quality resonator with

Feedback resistorR

Recommended load

capacitance

HSE oscillator power

consumption

Oscillator

transconductance

(4)

(2)

C = 20 pF,

f

= 16 MHz

OSC

C = 10 pF,

f

=16 MHz

OSC

VDDis stabilizedStartup timet

--

--

6 (startup)

1.6 (stabilized)

6 (startup)

1.2 (stabilized)

(3)

(3)

mA/V--5

small Rmvalue. Refer to crystal manufacturer for more details

(3)

Data based on characterization results, not tested in production.

(4)

t

SU(HSE)

is the start-up time measured from the moment it is enabled (by software) to a stabilized 16
MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer.

kΩ-220-

pF20--

mA

ms-1-

Figure 19: HSE oscillator circuit diagram

HSE oscillator critical gmequation

g

= (2 × Π × f

mcrit

)2× Rm(2Co + C)

HSE

DocID15590 Rev 866/116

2

Rm: Notional resistance (see crystal specification)

Lm: Notional inductance (see crystal specification)

Cm: Notional capacitance (see crystal specification)

Co: Shunt capacitance (see crystal specification)

CL1= CL2= C: Grounded external capacitance

Electrical characteristicsSTM8S903K3 STM8S903F3

HSI

ACC

HSI

gm>> g

mcrit

Internal clock sources and timing characteristics10.3.4

Subject to general operating conditions for VDDand TA.

High speed internal RC oscillator (HSI)

Table 36: HSI oscillator characteristics

Frequencyf

Accuracy of HSI

oscillator

Accuracy of HSI

oscillator (factory

calibrated)

User-trimmed with

CLK_HSITRIMR register for

given VDDand T

conditions

VDD= 5 V, TA= 25°C

A

(1)

(2)

VDD= 5 V,

25 °C ≤ TA≤ 85 °C

UnitMaxTypMinConditionsParameterSymbol

MHz-16-

(3)

--

1.0

1--1

%

2.0--2.0

2.95 ≤ VDD≤ 5.5 V,

-40 °C ≤ TA≤ 125 °C

t

su(HSI)

HSI oscillator

wakeup time

including

calibration

I

DD(HSI)

HSI oscillator

power

consumption

(1)

Refer to application note.

(2)

Data based on characterization results, not tested in production.

(3)

Guaranteed by design, not tested in production.

-3.0

(2)

(2)

-

--

170-

3.0

1.0

250

(3)

(2)

μs

μA

67/116DocID15590 Rev 8

Figure 20: Typical HSI frequency variation vs VDD@ 4 temperatures

Low speed internal RC oscillator (LSI)

Subject to general operating conditions for VDDand TA.

STM8S903K3 STM8S903F3Electrical characteristics

LSI

su(LSI)

DD(LSI)

Table 37: LSI oscillator characteristics

Frequencyf

LSI oscillator wake-up timet

LSI oscillator power consumptionI

Figure 21: Typical LSI frequency variation vs VDD@ 4 temperatures

UnitMaxTypMinParameterSymbol

kHz150128110

μs7--

μA-5-

DocID15590 Rev 868/116

Memory characteristics10.3.5

RAM and hardware registers

Table 38: RAM and hardware registers

Electrical characteristicsSTM8S903K3 STM8S903F3

UnitMinConditionsParameterSymbol

V

RM

(1)

Minimum supply voltage without losing data stored in RAM (in halt mode or under reset)

Data retention mode

(1)

Halt mode (or reset)

V

IT-max

(2)

V

or in hardware registers (only in halt mode). Guaranteed by design, not tested in production.

(2)

Refer to the Operating conditions section for the value of V

IT-max

Flash program memory/data EEPROM memory

Table 39: Flash program memory/data EEPROM memory

ConditionsParameterSymbol

V

DD

Operating voltage

(all modes, execution/

f

CPU

≤ 16 MHz

Min

(1)

UnitMaxTyp

V5.5-2.95

write/erase)

t

prog

Standard programming time

(including erase) for

byte/word/block (1 byte/

6.66-

4 bytes/64 bytes)

Fast programming time for

1 block (64 bytes)

3.333-

ms

t

erase

N

RW

t

RET

Erase time for 1 block

(64 bytes)

Erase/write cycles

(2)

(program memory)

Erase/write cycles

(data memory)

(2)

Data retention (program

and data memory) after 10k

erase/write cycles at

TA= +55 °C

TA= +85 °C

TA= +125 °C

T

= 55°C

RET

3.333-

--10 k

cycles

-1 M300 k

years--20

69/116DocID15590 Rev 8

STM8S903K3 STM8S903F3Electrical characteristics

ConditionsParameterSymbol

Min

(1)

UnitMaxTyp

Data retention (data

memory) after 300k

erase/write cycles at

RET

= 85°C

--1

T

TA= +125 °C

I

DD

Supply current (Flash

programming or erasing

mA-2-

for 1 to 128 bytes)

(1)

Data based on characterization results, not tested in production.

(2)

The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes

even when a write/erase operation addresses a single byte.

I/O port pin characteristics10.3.6

General characteristics

Subject to general operating conditions for VDDand TAunless otherwise specified. All unused
pins must be kept at a fixed voltage: using the output mode of the I/O for example or an
external pull-up or pull-down resistor.

V

IL

V

IH

V

hys

R

pu

tR, t

Table 40: I/O static characteristics

UnitMaxTypMinConditionsParameterSymbol

Input low level voltage

VDD= 5 V

--0.3 V

0.3 x

V

DD

V

Input high level voltage

Hysteresis

Pull-up resistor

F

Rise and fall time

(10 % - 90 %)

(1)

VDD= 5 V, VIN= V

Fast I/Os

Load = 50 pF

SS

0.7 x
V

DD

Standard and high sink
I/Os

VDD+

-

0.3

mV-700-

kΩ805530

(3)

--

--

35

125

(3)

ns

Load = 50 pF

(3)

Fast I/Os

--

20

DocID15590 Rev 870/116

Load = 20 pF

Electrical characteristicsSTM8S903K3 STM8S903F3

UnitMaxTypMinConditionsParameterSymbol

Standard and high sink
I/Os

--

50

(3)

Load = 20 pF

I

lkg

I

lkg ana

I

lkg(inj)

Digital input leakage current

Analog input leakage current

Leakage current in adjacent
I/O

(1)

Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not

VSS≤ VIN≤V

VSS≤ VIN≤ V

DD

DD

Injection current ±4 mA

--

--

--

±1

±250

±1

(2)

(2)

(2)

tested in production.

(2)

Data based on characterisation results, not tested in production.

(3)

Data guaranteed by design.

Figure 22: Typical VILand VIHvs VDD@ 4 temperatures

μA

nA

μA

71/116DocID15590 Rev 8

STM8S903K3 STM8S903F3Electrical characteristics

Figure 23: Typical pull-up resistance vs VDD@ 4 temperatures

Figure 24: Typical pull-up current vs VDD@ 4 temperatures

Table 41: Output driving current (standard ports)

UnitMaxMinConditionsParameterSymbol

Output low level with 8 pins sunk

V

OL

Output low level with 4 pins sunk

Output high level with 8 pins sourced

V

OH

DocID15590 Rev 872/116

IIO= 10 mA,

VDD= 5 V

IIO= 4 mA,

VDD= 3.3 V

IIO= 10 mA,

VDD= 5 V

2.0-

(1)

1.0

-

V

-2.8

Electrical characteristicsSTM8S903K3 STM8S903F3

UnitMaxMinConditionsParameterSymbol

Output high level with 4 pins sourced

IIO= 4 mA,

VDD= 3.3 V

(1)

Data based on characterization results, not tested in production

Table 42: Output driving current (true open drain ports)

V

OL

V

OL

V

OL

(1)

Data based on characterization results, not tested in production

Output low level with 2 pins sunk

Output low level with 2 pins sunk

Output low level with 2 pins sunk

IIO= 10 mA, VDD= 5 V

IIO= 10 mA, VDD= 3.3
V

IIO= 20 mA, VDD= 5 V

Table 43: Output driving current (high sink ports)

V

OL

Output low level with 8 pins sunk

IIO= 10 mA,

VDD= 5 V

2.1

(1)

1 .0

1.5

2.0

(1)

(1)

-

UnitMaxConditionsParameterSymbol

V

UnitMaxMinConditionsParameterSymbol

V0.8-

Output low level with 4 pins sunk

IIO= 10 mA,

VDD= 3.3 V

V

OL

Output low level with 4 pins sunk

IIO= 20 mA,

VDD= 5 V

Output high level with 8 pins sourced

IIO= 10 mA,

VDD= 5 V

V

OH

Output high level with 4 pins sourced

Output high level with 4 pins sourced

IIO= 10 mA,

VDD= 3.3 V

IIO= 20 mA,

VDD= 5 V

(1)

Data based on characterization results, not tested in production

2.1

3.3

(1)

1.0

-

(1)

1.5

-

V

(1)

(1)

-4.0

-

-

73/116DocID15590 Rev 8

STM8S903K3 STM8S903F3Electrical characteristics

Figure 25: Typ. VOL@ VDD= 5 V (standard ports)

Figure 26: Typ. VOL@ VDD= 3.3 V (standard ports)

DocID15590 Rev 874/116

Electrical characteristicsSTM8S903K3 STM8S903F3

Figure 27: Typ. VOL@ VDD= 5 V (true open drain ports)

Figure 28: Typ. VOL@ VDD= 3.3 V (true open drain ports)

75/116DocID15590 Rev 8

STM8S903K3 STM8S903F3Electrical characteristics

Figure 29: Typ. VOL@ VDD= 5 V (high sink ports)

Figure 30: Typ. VOL@ VDD= 3.3 V (high sink ports)

DocID15590 Rev 876/116

Electrical characteristicsSTM8S903K3 STM8S903F3

Figure 31: Typ. VDD- VOH@ VDD= 5 V (standard ports)

Figure 32: Typ. VDD- VOH@ VDD= 3.3 V (standard ports)

77/116DocID15590 Rev 8

STM8S903K3 STM8S903F3Electrical characteristics

Figure 33: Typ. VDD- VOH@ VDD= 5 V (high sink ports)

Figure 34: Typ. VDD- VOH@ VDD= 3.3 V (high sink ports)

V

IL(NRST)

Reset pin characteristics10.3.7

Subject to general operating conditions for VDDand TAunless otherwise specified.

Table 44: NRST pin characteristics

NRST input low

level voltage

(1)

DocID15590 Rev 878/116

--0.3

DD

UnitMaxTypMinConditionsParameterSymbol

V0.3 x V

V

IH(NRST)

V

OL(NRST)

R

PU(NRST)

t

I FP(NRST)

t

IN FP(NRST)

NRST input high

level voltage

(1)

NRST output low

level voltage

(1)

NRST pull-up

resistor

(2)

NRST input filtered

(3)

pulse

NRST input not

filtered pulse

(3)

IOL=2 mA

DD

Electrical characteristicsSTM8S903K3 STM8S903F3

UnitMaxTypMinConditionsParameterSymbol

VDD+ 0.3-0.7 x V

0.5--

kΩ805530

75--

ns

--500

t

OP(NRST)

(1)

Data based on characterization results, not tested in production.

(2)

The RPUpull-up equivalent resistor is based on a resistive transistor

(3)

Data guaranteed by design, not tested in production.

NRST output

(3)

pulse

20

Figure 35: Typical NRST VILand VIHvs VDD@ 4 temperatures

μs--

79/116DocID15590 Rev 8

STM8S903K3 STM8S903F3Electrical characteristics

Figure 36: Typical NRST pull-up resistance vs VDD@ 4 temperatures

Figure 37: Typical NRST pull-up current vs VDD@ 4 temperatures

The reset network shown in the following figure protects the device against parasitic resets.
The user must ensure that the level on the NRST pin can go below V

IL(NRST)

max. (see Table

40: I/O static characteristics ), otherwise the reset is not taken into account internally.

For power consumption sensitive applications, the external reset capacitor value can be
reduced to limit the charge/discharge current. If NRST signal is used to reset external circuitry,
attention must be taken to the charge/discharge time of the external capacitor to fulfill the
external devices reset timing conditions. Minimum recommended capacity is 100 nF.

DocID15590 Rev 880/116

External

reset

circuit

(optional)

0.1 μF

NRST

VDD

RPU

Filter

Internal reset

STM8

Electrical characteristicsSTM8S903K3 STM8S903F3

Figure 38: Recommended reset pin protection

SPI serial peripheral interface10.3.8

Unless otherwise specified, the parameters given in the following table are derived from tests
performed under ambient temperature, f
t

MASTER

= 1/f

MASTER

.

MASTER

Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).

frequency and VDDsupply voltage conditions.

f

1/

SCK

t

c(SCK)

f

1/

SCK

t

c(SCK)

t

r(SCK)

t

f(SCK)

su(NSS)

h(NSS)

t

w(SCKH)

t

w(SCKL)

t

su(MI)

t

su(SI)

t

h(MI)

t

h(SI)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

ParameterSymbol

frequency

1/ t

SCK

c(SCK)

fall time

time

time

time

Table 45: SPI characteristics

Conditions

(1)

Master modeSPI clock

SPI clock frequencyf

Capacitive load: C = 30 pFSPI clock rise and

Slave modeNSS setup timet

Master modeSCK high and low

0

4 x

t

MASTER

70Slave modeNSS hold timet

t

/

SCK

2 - 15

5Master modeData input setup

5Slave mode

7Master modeData input hold

10Slave mode

(2)

25

t

SCK

2 +15

UnitMaxMin

MHz80

MHz7

ns

/

81/116DocID15590 Rev 8

STM8S903K3 STM8S903F3Electrical characteristics

UnitMaxMin

t

a(SO)

ParameterSymbol

(3) (4)

Conditions

Slave modeData output

access time

t

dis(SO)

(3) (5)

Slave modeData output

disable time

t

v(SO)

(3)

Data output valid

time

t

v(MO)

(3)

Data output valid

time

t

h(SO)

(3)

Data output hold

time

t

h(MO)

(3)

Data output hold

time

(1)

Parameters are given by selecting 10 MHz I/O output frequency.

(2)

Data characterization in progress.

(3)

Values based on design simulation and/or characterization results, and not tested in

Slave mode

(after enable edge)

Master mode

(after enable edge)

Slave mode

(after enable edge)

Master mode

(after enable edge)

(1)

25

27

11

(2)

(2)

3 x

t

MASTER

(2)

65

30

production.

(4)

Min time is for the minimum time to drive the output and the max time is for the maximum

time to validate the data.

(5)

Min time is for the minimum time to invalidate the output and the max time is for the

maximum time to put the data in Hi-Z.

DocID15590 Rev 882/116

ai14134

SCK Input

CPHA=0

MOSI

INPUT

MISO

OUT PUT

CPHA=0

MSB OUT

MSB IN

BIT6 OUT

LSB IN

LSB OUT

CPOL=0

CPOL=1

BIT1 IN

NSSinput

t

SU(NSS)

t

c(SCK)

t

h(NSS)

t

a(SO)

t

w(SCKH)

t

w(SCKL)

t

v(SO)

t

h(SO)

t

r(SCK)

t

f(SCK)

t

dis(SO)

t

su(SI)

t

h(SI)

ai14135

SCK Input

CPHA=1

MOSI

INPUT

MISO

OUT PUT

CPHA=1

MSB OUT

MSB IN

BIT6 OUT

LSB IN

LSB OUT

CPOL=0

CPOL=1

BIT1 IN

t

SU(NSS)

t

c(SCK)

t

h(NSS)

t

a(SO)

t

w(SCKH)

t

w(SCKL)

t

v(SO)

t

h(SO)

t

r(SCK)

t

f(SCK)

t

dis(SO)

t

su(SI)

t

h(SI)

NSS input

Electrical characteristicsSTM8S903K3 STM8S903F3

Figure 39: SPI timing diagram - slave mode and CPHA = 0

Figure 40: SPI timing diagram - slave mode and CPHA = 1

1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD.

83/116DocID15590 Rev 8

ai14136b

SCK output

CPHA=0

MOSI

OUTUT

MISO

INPUT

CPHA=0

MSBIN

MSB OUT

BIT6 IN

LSB OUT

LSB IN

CPOL=0

CPOL=1

BIT1 OUT

NSSinput

t

c(SCK)

t

w(SCKH)

t

w(SCKL)

t

r(SCK)

t

f(SCK)

t

h(MI)

High

SCK output

CPHA=1

CPHA=1

CPOL=0

CPOL=1

t

su(MI)

t

v(MO)

t

h(MO)

STM8S903K3 STM8S903F3Electrical characteristics

Figure 41: SPI timing diagram - master mode

(1)

1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD.

w(SCLL)

w(SCLH)

su(SDA)

h(SDA)

t

r(SDA)

t

r(SCL)

t

f(SDA)

t

f(SCL)

h(STA)

su(STA)

I2C interface characteristics10.3.9

ParameterSymbol

SDA data hold timet

Table 46: I2C characteristics

Standard mode I2C

(2)

Min

(3)

DocID15590 Rev 884/116

Max

Fast mode I2C

(2)

Min

-0

Unit

(1)

Max

(2)

(2)

-1.3-4.7SCL clock low timet
μs

-0.6-4.0SCL clock high timet

-100-250SDA setup timet

(4)

0

900

300-1000-SDA and SCL rise time

(3)

ns

300-300-SDA and SCL fall time

-0.6-4.0START condition hold timet
μs

-0.6-4.7Repeated START condition setup timet

t

f(SDA)

t

r(SDA)

t

su(SDA)th(SDA)

t

f(SCL)

t

r(SCL)

t

w(SCLL)

t

w(SCLH)

t

h(STA)

t

su(STO)

t

su(STA)tw(STO:STA)

SDA

SCL

4.7kΩ
SDA

SCL

100Ω

100Ω

4.7kΩ

I2C bus

START

START

STOP

REPEATED

START

STM8S

V

DD

V

DD

ai17490

Electrical characteristicsSTM8S903K3 STM8S903F3

su(STO)

t

w(STO:STA)

ParameterSymbol

STOP to START condition time

Standard mode I2C

Min

(2)

Max

Fast mode I2C

(2)

Min

(2)

Max

(1)

(2)

-0.6-4.0STOP condition setup timet

(bus free)

b

(1)

f

MASTER

(2)

Data based on standard I2C protocol requirement, not tested in production

(3)

The maximum hold time of the start condition has only to be met if the interface does not stretch the

, must be at least 8 MHz to achieve max fast I2C speed (400kHz)

low time

(4)

The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge

the undefined region of the falling edge of SCL

Figure 42: Typical application with I2C bus and timing diagram

Unit

μs-1.3-4.7

pF400-400-Capacitive load for each bus lineC

1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD.

10-bit ADC characteristics10.3.10

Subject to general operating conditions for VDD, f

MASTER

Table 47: ADC characteristics

ADC

, and TAunless otherwise specified.

UnitMaxTypMinConditionsParameterSymbol

MHz4-1VDD=2.95 to 5.5 VADC clock frequencyf

85/116DocID15590 Rev 8

STM8S903K3 STM8S903F3Electrical characteristics

UnitMaxTypMinConditionsParameterSymbol

6-1VDD=4.5 to 5.5 V

V

AIN

Conversion voltage range

(1)

SS

-V

DD

VV

V

BGREF

V1.251.221.19VDD=2.95 to 5.5 VInternal bandgap reference

voltage

C

ADC

pF-3-Internal sample and hold

capacitor

(1)

S

STAB

t

CONV

ADC

ADC

ADC

= 4 MHzMinimum sampling timet

= 6 MHz

= 4 MHzMinimum total conversion

-0.5-f

-Wake-up time from standbyt

7

µs-0.75-f

µs-

µs3.5f

time (including sampling time,

1/f

µs2.33f

ADC

10-bit resolution)

(1)

During the sample time the input capacitance C

ADC

= 6 MHz

14

(3 pF max) can be charged/discharged

AIN

by the external source. The internal resistance of the analog source must allow the
capacitance to reach its final voltage level within tS.After the end of the sample time tS,
changes of the analog input voltage have no effect on the conversion result. Values for the
sample clock tSdepend on programming.

|ET|

Table 48: ADC accuracy with R

(2)

ADC

= 2 MHzTotal unadjusted error

< 10 kΩ , VDD= 5 V

AIN

(1)

TypConditionsParameterSymbol

UnitMax

LSB3.51.6f

|EO|

|EG|

|ED|

(2)

(2)

= 4 MHz

ADC

= 6 MHz

ADC

= 2 MHzOffset error

ADC

= 4 MHz

ADC

= 6 MHz

ADC

= 2 MHzGain error

ADC

= 4 MHz

ADC

= 6 MHz

ADC

(2)

DocID15590 Rev 886/116

ADC

ADC

= 2 MHzDifferential linearity error

= 4 MHz

42.2f

4.52.4f

2.51.1f

31.5f

31.8f

31.5f

32.1f

42.2f

1.50.7f

1.50.7f

Electrical characteristicsSTM8S903K3 STM8S903F3

(1)

TypConditionsParameterSymbol

UnitMax

= 6 MHz

ADC

|EL|

(1)

Data based on characterisation results, not tested in production.

(2)

ADC accuracy vs. negative injection current: Injecting negative current on any of the

(2)

ADC

ADC

ADC

= 2 MHzIntegral linearity error

= 4 MHz

= 6 MHz

1.50.7f

1.50.6f

20.8f

20.8f

analog input pins should be avoided as this significantly reduces the accuracy of the
conversion being performed on another analog input. It is recommended to add a Schottky
diode (pin to ground) to standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for I

INJ(PIN)

and ΣI

INJ(PIN)

in the I/O

port pin characteristics section does not affect the ADC accuracy.

Table 49: ADC accuracy with R

ADC

ADC

< 10 kΩ R

AIN

= 2 MHzTotal unadjusted error|ET|

= 4 MHz

, VDD= 3.3 V

AIN

TypConditionsParameterSymbol

(1)

UnitMax

LSB3.51.6f

41.9f

= 2 MHzOffset error|EO|

ADC

= 4 MHz

ADC

= 2 MHzGain error|EG|

ADC

= 4 MHz

ADC

= 2 MHzDifferential linearity error|ED|

ADC

= 4 MHz

ADC

= 2 MHzIntegral linearity error|EL|

ADC

= 4 MHz

ADC

(1)

Data based on characterisation results, not tested in production.

2.51f

2.51.5f

31.3f

32f

10.7f

1.50.7f

1.50.6f

20.8f

87/116DocID15590 Rev 8

STM8

10-bit A/D

conversion

R

AIN

C

AIN

V

AIN

AINx

V

DD

V

T

0.6 V

V

T

0.6 V

I

L

± 1 µA

C

ADC

STM8S903K3 STM8S903F3Electrical characteristics

Figure 43: ADC accuracy characteristics

1. Example of an actual transfer curve.

2. The ideal transfer curve

3. End point correlation line

ET= Total unadjusted error: maximum deviation between the actual and the ideal transfer
curves.

EO= Offset error: deviation between the first actual transition and the first ideal one.

EG= Gain error: deviation between the last ideal transition and the last actual one.

ED= Differential linearity error: maximum deviation between actual steps and the ideal
one.

EL= Integral linearity error: maximum deviation between any actual transition and the end
point correlation line.

Figure 44: Typical application with ADC

DocID15590 Rev 888/116

Electrical characteristicsSTM8S903K3 STM8S903F3

EMC characteristics10.3.11

Susceptibility tests are performed on a sample basis during product characterization.

Functional EMS (electromagnetic susceptibility)10.3.11.1

While executing a simple application (toggling 2 LEDs through I/O ports), the product is
stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).

FESD: Functional electrostatic discharge (positive and negative) is applied on all pins of

•

the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2
standard.

FTB: A burst of fast transient voltage (positive and negative) is applied to VDDand V

•

through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with
the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed. The test results are given in the table
below based on the EMS levels and classes defined in application note AN1709 (EMC design
guide for STMicrocontrollers).

SS

Designing hardened software to avoid noise problems10.3.11.2

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be
recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring. See application note AN1015 (Software techniques
for improving microcontroller EMC performance).

Table 50: EMS data

Level/
class

2/B

4/A

(1)

(1)

V

V

FESD

EFTB

Voltage limits to be
applied on any I/O pin to
induce a functional
disturbance

Fast transient voltage
burst limits to be applied
through 100 pF on V
and VSSpins to induce a
functional disturbance

DD

ConditionsParameterSymbol

VDD= 3.3 V, TA= 25 °C, f
(HSI clock), conforming to IEC 61000-4-2

VDD= 3.3 V, TA= 25 °C ,f
(HSI clock),conforming to IEC 61000-4-4

MASTER

MASTER

= 16 MHz

= 16 MHz

89/116DocID15590 Rev 8

STM8S903K3 STM8S903F3Electrical characteristics

(1)

Data obtained with HSI clock configuration, after applying HW recommendations described

in AN2860 (EMC guidelines for STM8S microcontrollers).

Electromagnetic interference (EMI)10.3.11.3

Based on a simple application running on the product (toggling 2 LEDs through the I/O ports),
the product is monitored in terms of emission. This emission test is in line with the norm SAE
IEC 61967-2 which specifies the board and the loading of each pin.

Table 51: EMI data

Conditions

ParameterSymbol

General
conditions

Monitored
frequency band

Max f

16 MHz/

8 MHz

Peak level

VDD= 5 V

TA= 25 °C

0.1 MHz to

30 MHz
LQFP32
package

Conforming to

S

EMI

SAE IEC

30 MHz to

130 MHz

61967-2

130 MHz to

1 GHz

SAE EMI
level

(1)

Data based on characterisation results, not tested in production.

SAE EMI level

HSE/fCPU

16 MHz/

16 MHz

(1)

Unit

55

54

dBμV

55

2.52.5

Absolute maximum ratings (electrical sensitivity)10.3.11.4

Based on three different tests (ESD, DLU and LU) using specific measurement methods, the
product is stressed to determine its performance in terms of electrical sensitivity. For more
details, refer to the application note AN1181.

Electrostatic discharge (ESD)10.3.11.5

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied
to the pins of each sample according to each pin combination. The sample size depends on
the number of supply pins in the device (3 parts*(n+1) supply pin). One model can be simulated:

DocID15590 Rev 890/116

Electrical characteristicsSTM8S903K3 STM8S903F3

Human body model. This test conforms to the JESD22-A114A/A115A standard. For more
details, refer to the application note AN1181.

Table 52: ESD absolute maximum ratings

(1)

UnitMaximum

V

V

ESD(HBM)

(Human body model)

V

ESD(CDM)

(1)

Data based on characterization results, not tested in production

TA= 25°C, conforming toElectrostatic discharge

JESD22-A114voltage

TALQFP32 package =Electrostatic discharge

25°C, conforming tovoltage

SD22-C101(Charge device model)

ClassConditionsRatingsSymbol

value

4000A

1000IV

Static latch-up10.3.11.6

Two complementary static tests are required on six parts to assess the latch-up performance:

A supply overvoltage (applied to each power supply pin)

•

A current injection (applied to each input, output and configurable I/O pin) are performed

•

on each sample.

This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the
application note AN1181.

Table 53: Electrical sensitivities

(1)

ConditionsParameterSymbol

(1)

Class description: A Class is an STMicroelectronics internal specification. All its limits
are higher than the JEDEC specifications, that means when a device belongs to class A it
exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international
standard).

Class

ATA= 25 °CStatic latch-up classLU

ATA= 85 °C

ATA= 125 °C

91/116DocID15590 Rev 8

5V_ME

L

A1 K

L1

c

A

A2

ccc

C

D
D1
D3

E3

E1 E

16

17

24

25

b

32

1

Pin 1
identification

8

9

STM8S903K3 STM8S903F3Package information

Package information11

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK®packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.

32-pin LQFP package mechanical data11.1

Figure 45: 32-pin low profile quad flat package (7 x 7)

®

®

Table 54: 32-pin low profile quad flat package mechanical data

mmDim.

inches

(1)

MaxTypMinMaxTypMin

0.06301.600A

0.00590.00200.1500.050A1

0.05710.05510.05311.4501.4001.350A2

0.01770.01460.01180.4500.3700.300b

0.00790.00350.2000.090c

0.36220.35430.34659.2009.0008.800D

0.28350.27560.26777.2007.0006.800D1

DocID15590 Rev 892/116

Package informationSTM8S903K3 STM8S903F3

mmDim.

inches

(1)

0.22055.600D3

0.22055.600E3

0.03150.800e

0.03941.000L1

(1)

Values in inches are converted from mm and rounded to 4 decimal digits

MaxTypMinMaxTypMin

0.36220.35430.34659.2009.0008.800E

0.28350.27560.26777.2007.0006.800E1

0.02950.02360.01770.7500.6000.450L

7.0°3.5°0.0°7.0°3.5°0.0°k

0.00390.100ccc

93/116DocID15590 Rev 8

AOB8_ME

STM8S903K3 STM8S903F3Package information

32-lead UFQFPN package mechanical data11.2

Figure 46: 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5)

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint

life.

3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended
to connect and solder this backside pad to PCB ground.

4. Dimensions are in millimeters.

Table 55: 32-lead, ultra thin, fine pitch quad flat no-lead package mechanical data

mmDim.

inches

(1)

MaxTypMinMaxTypMin

0.02360.02170.01970.6000.5500.500A

0.00200.00080.0500.0200A1

0.00790.200A3

DocID15590 Rev 894/116

103_A0A5_ME

11

15

1620

1

5

D

e

b

e

E

A1

A

ddd

L2

10

L1

A3

L3

L4

D

E

TOP VIEW

SIDE VIEW

BOTTOMVIEW

Pin 1

Package informationSTM8S903K3 STM8S903F3

mmDim.

(1)

Values in inches are converted from mm and rounded to 4 decimal digits.

inches

(1)

20-lead UFQFPN package mechanical data11.3

MaxTypMinMaxTypMin

0.01180.00980.00710.3000.2500.180b

0.20280.19690.19095.1505.0004.850D

0.14570.12603.7003.4503.200D2

0.20280.19690.19095.1505.0004.850E

0.14570.13580.12603.7003.4503.200E2

0.01970.500e

0.01970.01570.01180.5000.4000.300L

0.00310.080ddd

Figure 47: 20-lead, ultra thin, fine pitch quad flat no-lead package outline (3 x 3)

95/116DocID15590 Rev 8

STM8S903K3 STM8S903F3Package information

1. Drawing is not to scale.

Table 56: 20-lead, ultra thin, fine pitch quad flat no-lead package (3 x 3) package

mechanical data

mmDim.

inches

(1)

MaxTypMinMaxTypMin

0.11813.000D

0.11813.000E

0.00600.152A3

0.01970.500e

0.02360.02170.01970.6000.5500.500A

0.00200.00080.00000.0500.0200.000A1

0.02360.02170.01970.6000.5500.500L1

0.01570.01380.01180.4000.3500.300L2

0.00590.150L3

0.00790.200L4

0.00200.050ddd

(1)

Values in inches are converted from mm and rounded to 4 decimal digits.

0.01180.00980.00710.3000.2500.180b

DocID15590 Rev 896/116

Bottom view

4mm

[0.157"]

4mm [0.157"]

0.5mm

0.5mm

0.3mm [0.012"]

0.9mm

[0.035"]

0.8mm

[0.032"]

1.65mm [0.065"]

ai15319

Package informationSTM8S903K3 STM8S903F3

UFQFPN recommended footprint11.4

Figure 48: Recommended footprint for on-board emulation

1. Drawing is not to scale

97/116DocID15590 Rev 8

76_ME

A2A1A

L

B1 B e

eA

DD

1

32

16

17

E1

E

C

eB

STM8S903K3 STM8S903F3Package information

Figure 49: Recommended footprint without on-board emulation

1. Drawing is not to scale

2. Dimensions are in millimeters

SDIP32 package mechanical data11.5

Figure 50: 32-lead shrink plastic DIP (400 ml) package

DocID15590 Rev 898/116

Package informationSTM8S903K3 STM8S903F3

Table 57: 32-lead shrink plastic DIP (400 ml) package mechanical data

mmDim.

inches

(1)

MaxTypMinMaxTypMin

0.20000.14800.14005.0803.7593.556A

0.02000.508A1

0.18000.14000.12004.5723.5563.048A2

0.02300.01800.01400.5840.4570.356B

0.05500.04000.03001.3971.0160.762B1

0.01400.01000.00790.3560.2540.203C

1.12011.10001.079928.45027.94027.430D

0.43500.40980.390011.05010.4109.906E

(1)

Values in inches are converted from mm and rounded to 4 decimal digits

0.37000.35000.30009.3988.8907.620E1

0.07001.778e

0.400010.160eA

0.500012.700eB

0.15000.12000.10003.8103.0482.540L

99/116DocID15590 Rev 8

YA_ME

1

20

CP

c

L

EE1

D

A2

A

k

eb

10

11

A1

L1

aaa

STM8S903K3 STM8S903F3Package information

20-pin TSSOP package mechanical data11.6

Figure 51: 20-pin, 4.40 mm body, 0.65 mm pitch

Table 58: 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data

mmDim.

inches

(1)

MaxTypMinMaxTypMin

0.04721.200A

0.00590.00200.1500.050A1

0.04130.03940.03151.0501.0000.800A2

0.01180.00750.3000.190b

0.00790.00350.2000.090c

0.25980.25590.25206.6006.5006.400D

0.25980.25200.24416.6006.4006.200E

0.17720.17320.16934.5004.4004.300E1

0.02560.650e

0.02950.02360.01770.7500.6000.450L

0.03941.000L1

DocID15590 Rev 8100/116