ST STM8S903K3, STM8S903F3 User Manual

STM8S903K3 STM8S903F3

UFQFPN32 5x5LQFP32 7x7 SDIP32 400 mils

TSSOP20 SO20W 300 milsUFQFPN20 3x3

16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, 1 Kbyte RAM, 640

bytes EEPROM,10-bit ADC, 2 timers, UART, SPI, I²C

Switch-off peripheral clocks individually

Permanently active, low consumption power-on

•

and power-down reset

Interrupt management

Nested interrupt controller with 32 interrupts

•

Up to 28 external interrupts on 7 vectors

•

Timers

Advanced control timer: 16-bit, 4 CAPCOM

•

channels, 3 complementary outputs, dead-time insertion and flexible synchronization

16-bit general purpose timer, with 3 CAPCOM

•

channels (IC, OC or PWM)

8-bit basic timer with 8-bit prescaler

•

Auto wakeup timer

•

Window and independent watchdog timers

Features

•

Core

16 MHz advanced STM8 core with Harvard

•

architecture and 3-stage pipeline

Extended instruction set

•

Memories

Program memory: 8 Kbytes Flash; data retention

•

20 years at 55 °C after 10 kcycles

Data memory: 640 bytes true data EEPROM;

•

endurance 300 kcycles

RAM: 1 Kbytes

•

Clock, reset and supply management

2.95 to 5.5 V operating voltage

•

Flexible clock control, 4 master clock sources:

•

Low power crystal resonator oscillator

External clock input

Internal, user-trimmable 16 MHz RC

Internal low power 128 kHz RC

Clock security system with clock monitor

•

Power management:

•

Low power modes (wait, active-halt, halt)

Communications interfaces

UART with clock output for synchronous

•

operation, Smartcard, IrDA, LIN master mode

SPI interface up to 8 Mbit/s

•

I2C interface up to 400 Kbit/s

•

Analog to digital converter (ADC)

10-bit, ±1 LSB ADC with up to 7 muxed channels

•

+ 1 internal channel, scan mode and analog watchdog

Internal reference voltage measurement

•

I/Os

Up to 28 I/Os on a 32-pin package including 21

•

high sink outputs

Highly robust I/O design, immune against current

•

injection

Development support

Embedded single wire interface module (SWIM)

•

for fast on-chip programming and non intrusive debugging

Unique ID: 96-bit key including lot number

June 2012

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STM8S903K3 STM8S903F3Contents

1 Introduction ..............................................................................................................8

2 Description ...............................................................................................................9

3 Block diagram ........................................................................................................10

4 Product overview ...................................................................................................11

4.1 Central processing unit STM8 .....................................................................................11

4.2 Single wire interface module (SWIM) and debug module (DM) ..................................11

4.3 Interrupt controller .......................................................................................................12

4.4 Flash program and data EEPROM memory ................................................................12

4.5 Clock controller ............................................................................................................13

4.6 Power management ....................................................................................................14

4.7 Watchdog timers ..........................................................................................................14

4.8 Auto wakeup counter ...................................................................................................15

4.9 Beeper ........................................................................................................................15

4.10 TIM1 - 16-bit advanced control timer .........................................................................15

4.11 TIM5 - 16-bit general purpose timer ..........................................................................16

4.12 TIM6 - 8-bit basic timer ..............................................................................................16

4.13 Analog-to-digital converter (ADC1) ............................................................................16

4.14 Communication interfaces .........................................................................................17

4.14.1 UART1 ...............................................................................................17

4.14.2 SPI .....................................................................................................18

4.14.3 I²C ......................................................................................................18

5 Pinout and pin description ...................................................................................19

5.1 STM8S903F3 TSSOP20/SO20 pinout ........................................................................20

5.2 STM8S903F3 UFQFPN20 pinout ................................................................................21

5.3 TSSOP/SO/UFQFPN20 pin description ......................................................................22

5.4 STM8S903K3 UFQFPN32/LQFP32/SDIP32 pinout ....................................................23

5.5 UFQFPN/LQFP/SDIP32 pin description ......................................................................24

5.6 Alternate function remapping .......................................................................................26

6 Memory and register map .....................................................................................27

6.1 Memory map ................................................................................................................27

6.2 Register map ...............................................................................................................28

6.2.1 I/O port hardware register map ............................................................28

6.2.2 General hardware register map ...........................................................29

6.2.3 CPU/SWIM/debug module/interrupt controller registers .....................38

7 Interrupt vector mapping ......................................................................................41

8 Option bytes ...........................................................................................................43

8.1 STM8S903K3/F3 alternate function remapping bits ....................................................45

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ContentsSTM8S903K3 STM8S903F3

9 Unique ID ................................................................................................................49

10 Electrical characteristics ....................................................................................50

10.1 Parameter conditions .................................................................................................50

10.1.1 Minimum and maximum values .........................................................50

10.1.2 Typical values .....................................................................................50

10.1.3 Typical curves ....................................................................................50

10.1.4 Loading capacitor ...............................................................................50

10.1.5 Pin input voltage .................................................................................50

10.2 Absolute maximum ratings ........................................................................................51

10.3 Operating conditions ..................................................................................................53

10.3.1 VCAP external capacitor ....................................................................54

10.3.2 Supply current characteristics ............................................................55

10.3.3 External clock sources and timing characteristics .............................65

10.3.4 Internal clock sources and timing characteristics ...............................67

10.3.5 Memory characteristics ......................................................................69

10.3.6 I/O port pin characteristics .................................................................70

10.3.7 Reset pin characteristics ....................................................................78

10.3.8 SPI serial peripheral interface ............................................................81

10.3.9 I2C interface characteristics ...............................................................84

10.3.10 10-bit ADC characteristics ................................................................85

10.3.11 EMC characteristics .........................................................................89

11 Package information ............................................................................................92

11.1 32-pin LQFP package mechanical data .....................................................................92

11.2 32-lead UFQFPN package mechanical data .............................................................94

11.3 20-lead UFQFPN package mechanical data .............................................................95

11.4 UFQFPN recommended footprint ..............................................................................97

11.5 SDIP32 package mechanical data .............................................................................98

11.6 20-pin TSSOP package mechanical data ................................................................100

11.7 20-pin SO package mechanical data .......................................................................101

11.8 Thermal characteristics ............................................................................................102

11.8.1 Reference document ........................................................................103

11.8.2 Selecting the product temperature range .........................................103

12 Ordering information .........................................................................................104

12.1 STM8S903K3/F3 FASTROM microcontroller option list ..........................................104

13 STM8 development tools ..................................................................................110

13.1 Emulation and in-circuit debugging tools .................................................................110

13.2 Software tools ..........................................................................................................110

13.2.1 STM8 toolset ....................................................................................111

13.2.2 C and assembly toolchains ..............................................................111

13.3 Programming tools ..................................................................................................111

14 Revision history .................................................................................................112

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STM8S903K3 STM8S903F3List of tables

List of tables

Table 1. STM8S903K3/F3 access line features .......................................................................................9

Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ..................................14

Table 3. TIM timer features ....................................................................................................................16

Table 4. Legend/abbreviations for pinout tables ...................................................................................19

Table 5. TSSOP20/SO20/UFQFPN20 pin description ...........................................................................24

Table 6. UFQFPN32/LQFP32/SDIP32 pin description ...........................................................................24

Table 7. I/O port hardware register map ................................................................................................28

Table 8. General hardware register map ................................................................................................43

Table 9. CPU/SWIM/debug module/interrupt controller registers .........................................................54

Table 10. Interrupt mapping ...................................................................................................................41

Table 11. Option bytes .........................................................................................................................112

Table 12. Option byte description ...........................................................................................................43

Table 13. STM8S903K3 alternate function remapping bits [7:2] for 32-pin packages ...........................45

Table 14. STM8S903F3 alternate function remapping bits [7:2] for 20-pin packages ...........................46

Table 15. STM8S903K3 alternate function remapping bits [1:0] for 32-pin packages .........................102

Table 16. STM8S903F3 alternate function remapping bits [1:0] for 20-pin packages ...........................48

Table 17. Unique ID registers (96 bits) .................................................................................................112

Table 18. Voltage characteristics ...........................................................................................................51

Table 19. Current characteristics ...........................................................................................................51

Table 20. Thermal characteristics ..........................................................................................................52

Table 21. General operating conditions .................................................................................................53

Table 22. Operating conditions at power-up/power-down ......................................................................54

Table 23. Total current consumption with code execution in run mode at VDD= 5 V .............................55

Table 24. Total current consumption with code execution in run mode at VDD= 3.3 V ..........................56

Table 25. Total current consumption in wait mode at VDD= 5 V ............................................................57

Table 26. Total current consumption in wait mode at VDD= 3.3 V .........................................................57

Table 27. Total current consumption in active halt mode at VDD= 5 V ..................................................58

Table 28. Total current consumption in active halt mode at VDD= 3.3 V ...............................................59

Table 29. Total current consumption in halt mode at VDD= 5 V .............................................................60

Table 30. Total current consumption in halt mode at VDD= 3.3 V ..........................................................60

Table 31. Wakeup times .........................................................................................................................60

Table 32. Total current consumption and timing in forced reset state ....................................................61

Table 33. Peripheral current consumption .............................................................................................62

Table 34. HSE user external clock characteristics .................................................................................65

Table 35. HSE oscillator characteristics .................................................................................................65

Table 36. HSI oscillator characteristics ..................................................................................................67

Table 37. LSI oscillator characteristics ...................................................................................................68

Table 38. RAM and hardware registers ..................................................................................................69

Table 39. Flash program memory/data EEPROM memory ....................................................................69

Table 40. I/O static characteristics .........................................................................................................70

Table 41. Output driving current (standard ports) ..................................................................................72

Table 42. Output driving current (true open drain ports) ........................................................................73

Table 43. Output driving current (high sink ports) ..................................................................................73

Table 44. NRST pin characteristics ........................................................................................................78

Table 45. SPI characteristics ..................................................................................................................81

Table 46. I2C characteristics ..................................................................................................................84

Table 47. ADC characteristics ................................................................................................................85

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List of tablesSTM8S903K3 STM8S903F3

Table 48. ADC accuracy with R Table 49. ADC accuracy with R

< 10 kΩ , VDD= 5 V .........................................................................86

AIN

< 10 kΩ R

AIN

, VDD= 3.3 V ..............................................................87

AIN

Table 50. EMS data ................................................................................................................................89

Table 51. EMI data .................................................................................................................................90

Table 52. ESD absolute maximum ratings .............................................................................................91

Table 53. Electrical sensitivities .............................................................................................................91

Table 54. 32-pin low profile quad flat package mechanical data .........................................................102

Table 55. 32-lead, ultra thin, fine pitch quad flat no-lead package mechanical data .............................94

Table 56. 20-lead, ultra thin, fine pitch quad flat no-lead package (3 x 3) package mechanical data ....96

Table 57. 32-lead shrink plastic DIP (400 ml) package mechanical data ..............................................99

Table 58. 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data .......................................................101

Table 59. 20-lead, plastic small outline (300 mils) mechanical data ....................................................101

Table 60. Thermal characteristics ........................................................................................................102

Table 61. Document revision history ....................................................................................................112

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STM8S903K3 STM8S903F3List of figures

List of figures

Figure 1. Block diagram .........................................................................................................................10

Figure 2. Flash memory organization ....................................................................................................13

Figure 3. STM8S903F3 TSSOP20/SO20 pinout ...................................................................................23

Figure 4. STM8S903F3 UFQFPN20 pinout ...........................................................................................23

Figure 5. STM8S903K3 UFQFPN32/LQFP32 pinout ............................................................................23

Figure 6. STM8S903K3 SDIP32 pinout .................................................................................................24

Figure 7. Memory map ...........................................................................................................................27

Figure 8. Pin loading conditions .............................................................................................................50

Figure 9. Pin input voltage .....................................................................................................................51

Figure 10. f

CPUmax

Figure 11. External capacitor C Figure 12. Typ I Figure 13. Typ I Figure 14. Typ I Figure 15. Typ I Figure 16. Typ I Figure 17. Typ I

Figure 18. HSE external clocksource .....................................................................................................65

Figure 19. HSE oscillator circuit diagram ...............................................................................................66

Figure 20. Typical HSI frequency variation vs VDD@ 4 temperatures ..................................................68

Figure 21. Typical LSI frequency variation vs VDD@ 4 temperatures ...................................................68

Figure 22. Typical VILand VIHvs VDD@ 4 temperatures ......................................................................71

Figure 23. Typical pull-up resistance vs VDD@ 4 temperatures ............................................................72

Figure 24. Typical pull-up current vs VDD@ 4 temperatures .................................................................72

Figure 25. Typ. VOL@ VDD= 5 V (standard ports) ................................................................................74

Figure 26. Typ. VOL@ VDD= 3.3 V (standard ports) .............................................................................74

Figure 27. Typ. VOL@ VDD= 5 V (true open drain ports) ......................................................................75

Figure 28. Typ. VOL@ VDD= 3.3 V (true open drain ports) ...................................................................75

Figure 29. Typ. VOL@ VDD= 5 V (high sink ports) ................................................................................76

Figure 30. Typ. VOL@ VDD= 3.3 V (high sink ports) .............................................................................76

Figure 31. Typ. VDD- VOH@ VDD= 5 V (standard ports) .......................................................................77

Figure 32. Typ. VDD- VOH@ VDD= 3.3 V (standard ports) ...................................................................77

Figure 33. Typ. VDD- VOH@ VDD= 5 V (high sink ports) .......................................................................78

Figure 34. Typ. VDD- VOH@ VDD= 3.3 V (high sink ports) ....................................................................78

Figure 35. Typical NRST VILand VIHvs VDD@ 4 temperatures ...........................................................79

Figure 36. Typical NRST pull-up resistance vs VDD@ 4 temperatures .................................................80

Figure 37. Typical NRST pull-up current vs VDD@ 4 temperatures ......................................................80

Figure 38. Recommended reset pin protection ......................................................................................81

Figure 39. SPI timing diagram - slave mode and CPHA = 0 ..................................................................83

Figure 40. SPI timing diagram - slave mode and CPHA = 1 ..................................................................83

Figure 41. SPI timing diagram - master mode

Figure 42. Typical application with I2C bus and timing diagram ............................................................85

Figure 43. ADC accuracy characteristics ...............................................................................................88

Figure 44. Typical application with ADC ................................................................................................88

Figure 45. 32-pin low profile quad flat package (7 x 7) ..........................................................................92

Figure 46. 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) ............................................94

Figure 47. 20-lead, ultra thin, fine pitch quad flat no-lead package outline (3 x 3) ................................95

versus V

DD(RUN)

DD(WFI)

..............................................................................................................54

.......................................................................................................55

EXT

vs. VDDHSE user external clock, f vs. f vs. VDDHSI RC osc, f

HSE user external clock, VDD= 5 V ....................................................63

CPU

= 16 MHz .................................................................63

CPU

vs. VDDHSE user external clock, f vs. f vs. VDDHSI RC osc, f

HSE user external clock, VDD= 5 V .....................................................64

CPU

= 16 MHz .................................................................64

CPU

(1)

...................................................................................84

= 16 MHz .............................................62

CPU

= 16 MHz ..............................................64

CPU

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List of figuresSTM8S903K3 STM8S903F3

Figure 48. Recommended footprint for on-board emulation ..................................................................97

Figure 49. Recommended footprint without on-board emulation ...........................................................98

Figure 50. 32-lead shrink plastic DIP (400 ml) package ........................................................................98

Figure 51. 20-pin, 4.40 mm body, 0.65 mm pitch .................................................................................101

Figure 52. 20-lead, plastic small outline (300 mils) package ...............................................................101

Figure 53. STM8S903K3/F3 ordering information scheme ..................................................................104

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STM8S903K3 STM8S903F3Introduction

Introduction1

This datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information.

For complete information on the STM8S microcontroller memory, registers and peripherals,

•

please refer to the STM8S microcontroller family reference manual (RM0016).

For information on programming, erasing and protection of the internal Flash memory

•

please refer to the STM8S Flash programming manual (PM0051).

For information on the debug and SWIM (single wire interface module) refer to the STM8

•

SWIM communication protocol and debug module user manual (UM0470).

For information on the STM8 core, please refer to the STM8 CPU programming manual

•

(PM0044).

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DescriptionSTM8S903K3 STM8S903F3

Description2

The STM8S903K3 and STM8S903F3 8-bit microcontrollers offer 8 Kbytes Flash program memory, plus integrated true data EEPROM. The STM8S microcontroller family reference manual (RM0016) refers to devices in this family as low-density. They provide the following benefits: performance, robustness, and reduced system cost.

Device performance and robustness are ensured by advanced core and peripherals made in a state-of-the art technology, a 16 MHz clock frequency, robust I/Os, independent watchdogs with separate clock source, and a clock security system.

The system cost is reduced thanks to an integrated true data EEPROM for up to 300 kwrite/erase cycles and a high system integration level with internal clock oscillators, watchdog and brown-out reset.

Full documentation is offered as well as a wide choice of development tools.

Table 1: STM8S903K3/F3 access line features

STM8S903F3STM8S903K3Device

2032Pin count

Max. number of GPIOs (I/Os)

(1)

(2)

channels

outputs

program memory(bytes)

Data EEPROM (bytes)

Peripheral set

Multipurpose timer (TIM1), SPI, I2C, UART window WDG, independent WDG, ADC, PWM timer (TIM5), 8-bit timer (TIM6)

(1)

Including 21 high sink outputs

(2)

Including 12 high sink outputs

(3)

No read-while-write (RWW) capability

8KLow density Flash

640

1KRAM (bytes)

1628Ext. interrupt pins

7Timer CAPCOM

23Timer complementary

57A/D converter channels

1221High sink I/Os

(3)

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XTAL 1-16 MHz

RC int. 16 MHz

RC int. 128 kHz

STM8 core

Debug/SWIM

I2C

SPI

UART1

16-bit general purpose

AWU timer

Reset block

Reset

POR

BOR

Clock controller

Detector

Clock to peripherals and core

8 Mbit/s

LIN master

Address and data bus

Window WDG

8 Kbytes

640 bytes

1 Kbytes

ADC1

4 CAPCOM

Reset

400 Kbit/s

Single wire debug interf.

SPI emul.

channels

program

Flash

16-bit advanced control

timer (TIM1)

8-bit basic timer

data EEPROM

RAM

Up to

Beeper

1/2/4 kHz

beep

Independent WDG

(TIM6)

3 CAPCOM

channels

Up to

+ 3 complementary

outputs

Timer (TIM5)

Up to 7

channels

STM8S903K3 STM8S903F3Block diagram

Block diagram3

Figure 1: Block diagram

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Product overviewSTM8S903K3 STM8S903F3

Product overview4

The following section intends to give an overview of the basic features of the device functional modules and peripherals.

For more detailed information please refer to the corresponding family reference manual (RM0016).

Central processing unit STM84.1

The 8-bit STM8 core is designed for code efficiency and performance.

It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions.

Architecture and registers

Harvard architecture

•

3-stage pipeline

•

32-bit wide program memory bus - single cycle fetching for most instructions

•

X and Y 16-bit index registers - enabling indexed addressing modes with or without offset

•

and read-modify-write type data manipulations

8-bit accumulator

•

24-bit program counter - 16-Mbyte linear memory space

•

16-bit stack pointer - access to a 64 K-level stack

•

8-bit condition code register - 7 condition flags for the result of the last instruction

•

Addressing

20 addressing modes

•

Indexed indirect addressing mode for look-up tables located anywhere in the address

•

space

Stack pointer relative addressing mode for local variables and parameter passing

•

Instruction set

80 instructions with 2-byte average instruction size

•

Standard data movement and logic/arithmetic functions

•

8-bit by 8-bit multiplication

•

16-bit by 8-bit and 16-bit by 16-bit division

•

Bit manipulation

•

Data transfer between stack and accumulator (push/pop) with direct stack access

•

Data transfer using the X and Y registers or direct memory-to-memory transfers

•

Single wire interface module (SWIM) and debug module (DM)4.2

The single wire interface module and debug module permits non-intrusive, real-time in-circuit debugging and fast memory programming.

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STM8S903K3 STM8S903F3Product overview

SWIM

Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms.

Debug module

The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in real-time by means of shadow registers.

R/W to RAM and peripheral registers in real-time

•

R/W access to all resources by stalling the CPU

•

Breakpoints on all program-memory instructions (software breakpoints)

•

Two advanced breakpoints, 23 predefined configurations

•

Interrupt controller4.3

Nested interrupts with three software priority levels

•

32 interrupt vectors with hardware priority

•

Up to 28 external interrupts on 7 vectors including TLI

•

Trap and reset interrupts

•

Flash program and data EEPROM memory4.4

8 Kbytes of Flash program single voltage Flash memory

•

640 bytes true data EEPROM

•

User option byte area

•

Write protection (WP)

Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction.

There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, data EEPROM and option bytes.

To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to write to data EEPROM, modify the contents of main program memory or the device option bytes.

A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code). Refer to the figure below.

The size of the UBC is programmable through the UBC option byte, in increments of 1 page (64-byte block) by programming the UBC option byte in ICP mode.

This divides the program memory into two areas:

Main program memory: Up to 8 Kbytes minus UBC

•

User-specific boot code (UBC): Configurable up to 8 Kbytes

•

The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot

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UBC area

Program memory area

Data memory area ( 640 bytes)

Remains write protectedduring IAP

Data EEPROM memory

Write access possible forIAP

Option bytes

Programmable bytes(1 page)

up to 8 Kbytes (in 1 page steps)

area from 64

Low density Flash program memory (8 Kbytes)

Product overviewSTM8S903K3 STM8S903F3

program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines.

Figure 2: Flash memory organization

Read-out protection (ROP)

The read-out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program and data memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.

Clock controller4.5

The clock controller distributes the system clock (f to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness.

Features

Clock prescaler: To get the best compromise between speed and current consumption

•

the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.

Safe clock switching: Clock sources can be changed safely on the fly in run mode

•

through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching.

Clock management: To reduce power consumption, the clock controller can stop the

•

clock to the core, individual peripherals or memory.

Master clock sources: Four different clock sources can be used to drive the master

•

clock:

1-16 MHz high-speed external crystal (HSE)

MASTER

) coming from different oscillators

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Bit

STM8S903K3 STM8S903F3Product overview

Up to 16 MHz high-speed user-external clock (HSE user-ext)

16 MHz high-speed internal RC oscillator (HSI)

128 kHz low-speed internal RC (LSI)

Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz

•

clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.

Clock security system (CSS): This feature can be enabled by software. If an HSE clock

•

failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated.

Configurable main clock output (CCO): This outputs an external clock for use by the

•

application.

Table 2: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers

Peripheral clock

ADCCKEN23ReservedPCKEN27UART1PCKEN13TIM1PCKEN17

AWUPCKEN22ReservedPCKEN26ReservedPCKEN12IM5PCKEN16

ReservedPCKEN21ReservedPCKEN25SPIPCKEN11ReservedPCKEN15

clock

BitPeripheral

clock

BitPeripheral

clock

BitPeripheral

ReservedPCKEN20ReservedPCKEN24I2CPCKEN10TIM6PCKEN14

Power management4.6

For efficent power management, the application can be put in one of four different low-power modes. You can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources.

Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The

•

wakeup is performed by an internal or external interrupt or reset.

Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are

•

stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.

Active halt mode with regulator off: This mode is the same as active halt with regulator

•

on, except that the main voltage regulator is powered off, so the wake up time is slower.

Halt mode: In this mode the microcontroller uses the least power. The CPU and peripheral

•

clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset.

Watchdog timers4.7

The watchdog system is based on two independent timers providing maximum security to the applications.

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Product overviewSTM8S903K3 STM8S903F3

Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset.

Window watchdog timer

The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence.

The window function can be used to trim the watchdog behavior to match the application perfectly.

The application software must refresh the counter before time-out and during a limited time window.

A reset is generated in two situations:

1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to 64 ms.

2. Refresh out of window: The downcounter is refreshed before its value is lower than the one stored in the window register.

Independent watchdog timer

The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures.

It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case of a CPU clock failure

The IWDG time base spans from 60 µs to 1 s.

Auto wakeup counter4.8

Used for auto wakeup from active halt mode

•

Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock

•

LSI clock can be internally connected to TIM1 input capture channel 1 for calibration

•

Beeper4.9

The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz.

The beeper output port is only available through the alternate function remap option bit AFR7.

TIM1 - 16-bit advanced control timer4.10

This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver

16-bit up, down and up/down autoreload counter with 16-bit prescaler

•

Four independent capture/compare channels (CAPCOM) configurable as input capture,

•

output compare, PWM generation (edge and center aligned mode) and single pulse mode output

15/116DocID15590 Rev 8

STM8S903K3 STM8S903F3Product overview

Synchronization module to control the timer with external signals or to synchronise with

•

TIM5 or TIM6

Break input to force the timer outputs into a defined state

•

Three complementary outputs with adjustable dead time

•

Encoder mode

•

Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break

•

TIM5 - 16-bit general purpose timer4.11

16-bit autoreload (AR) up-counter

•

15-bit prescaler adjustable to fixed power of 2 ratios 1…32768

•

3 individually configurable capture/compare channels

•

PWM mode

•

Interrupt sources: 3 x input capture/output compare, 1 x overflow/update

•

Synchronization module to control the timer with external signals or to synchronize with

•

TIM1 or TIM6

TIM6 - 8-bit basic timer4.12

Timer

size (bits)

16TIM1

16TIM5

8TIM6

8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128

•

Clock source: CPU clock

•

Interrupt source: 1 x overflow/update

•

Synchronization module to control the timer with external signals or to synchronize with

•

TIM1 or TIM5.

Table 3: TIM timer features

PrescalerCounter

to 65536

from 1 to 32768

from 1 to 128

Counting mode

CAPCOM channels

Complementary outputs

Ext. trigger

No03UpAny power of 2

No00UpAny power of 2

Timer synchronization/ chaining

YesYes34Up/downAny integer from 1

Analog-to-digital converter (ADC1)4.13

The STM8S903K3 family products contain a 10-bit successive approximation A/D converter (ADC1) with up to 7 external and 1 internal multiplexed input channels and the following main features:

Input voltage range: 0 to V

•

DocID15590 Rev 816/116

Product overviewSTM8S903K3 STM8S903F3

Conversion time: 14 clock cycles

•

Single and continuous and buffered continuous conversion modes

•

Buffer size (n x 10 bits) where n = number of input channels

•

Scan mode for single and continuous conversion of a sequence of channels

•

Analog watchdog capability with programmable upper and lower thresholds

•

Internal reference voltage on channel AIN7

•

Analog watchdog interrupt

•

External trigger input

•

Trigger from TIM1 TRGO

•

End of conversion (EOC) interrupt

•

Internal bandgap reference voltage

Channel AIN7 is internally connected to the internal bandgap reference voltage. The internal bandgap reference is constant and can be used, for example, to monitor VDD. It is independent of variations in VDDand ambient temperature TA.

Communication interfaces4.14

The following communication interfaces are implemented:

UART1: Full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA

•

mode, single wire mode, LIN2.1 master capability

SPI : Full and half-duplex, 8 Mbit/s

•

I²C: Up to 400 Kbit/s

•

UART14.14.1

Main features

One Mbit/s full duplex SCI

•

SPI emulation

•

High precision baud rate generator

•

Smartcard emulation

•

IrDA SIR encoder decoder

•

LIN master mode

•

Single wire half duplex mode

•

Asynchronous communication (UART mode)

Full duplex communication - NRZ standard format (mark/space)

•

Programmable transmit and receive baud rates up to 1 Mbit/s (f

•

following any standard baud rate regardless of the input frequency

Separate enable bits for transmitter and receiver

•

Two receiver wakeup modes:

•

Address bit (MSB)

Idle line (interrupt)

/16) and capable of

CPU

17/116DocID15590 Rev 8

STM8S903K3 STM8S903F3Product overview

Transmission error detection with interrupt generation

•

Parity control

•

Synchronous communication

Full duplex synchronous transfers

•

SPI master operation

•

8-bit data communication

•

Maximum speed: 1 Mbit/s at 16 MHz (f

•

LIN master mode

Emission: Generates 13-bit synch break frame

•

Reception: Detects 11-bit break frame

•

SPI4.14.2

Maximum speed: 8 Mbit/s (f

•

Full duplex synchronous transfers

•

Simplex synchronous transfers on two lines with a possible bidirectional data line

•

Master or slave operation - selectable by hardware or software

•

CRC calculation

•

1 byte Tx and Rx buffer

•

Slave/master selection input pin

•

MASTER

/2) both for master and slave

CPU

/16)

I²C4.14.3

I²C master features:

•

Clock generation

Start and stop generation

I²C slave features:

•

Programmable I2C address detection

Stop bit detection

Generation and detection of 7-bit/10-bit addressing and general call

•

Supports different communication speeds:

•

Standard speed (up to 100 kHz)

Fast speed (up to 400 kHz)

DocID15590 Rev 818/116

Pinout and pin descriptionSTM8S903K3 STM8S903F3

Pinout and pin description5

Table 4: Legend/abbreviations for pinout tables

I= Input, O = Output, S = Power supplyType

Output speed

configuration

Reset state

InputLevel

O1 = Slow (up to 2 MHz)

O2 = Fast (up to 10 MHz)

O3 = Fast/slow programmability with slow as default state after reset

O4 = Fast/slow programmability with fast as default state after reset

Output

Bold X (pin state after internal reset release).

Unless otherwise specified, the pin state is the same during the reset phase and after the internal reset release.

CM = CMOS

HS = High sinkOutput

float = floating, wpu = weak pull-upInputPort and control

T = True open drain, OD = Open drain, PP = Push pull

19/116DocID15590 Rev 8

1 2 3 4 5 6 7

9 10

20 19 18 17 16 15 14 13 12 11

PD3(HS)/AIN4/TIM5_CH2/ADC_ETRTIM5_CH1[UART1_CK]BEEP/PD4(HS)

AIN5/UART1_TX/PD5(HS)

AIN6/UART1_RX/PD6(HS)

NRST

OSCIN/PA1

OSCOUT/PA2

VCAP

[SPI_NSS]/TIM5_CH3/PA3(HS)

PB4(T)/I2C_SCL[ADC_ETR]

PC3(HS)/TIM1_CH3[TLI][TIM1_CH1N]

PC4(HS)/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N]

PC5(HS)/SPI_SCK[TIM5_CH1]

PC6(HS)/SPI_MOSI[TIM1_CH1]

PC7(HS)/SPI_MISO[TIM1_CH2]

PD1(HS)/SWIM

PD2(HS)/AIN3[TIM5_CH3]

PB5(T)/[TIM1_BKIN]I2C_SDA

STM8S903K3 STM8S903F3Pinout and pin description

STM8S903F3 TSSOP20/SO20 pinout5.1

Figure 3: STM8S903F3 TSSOP20/SO20 pinout

1. (HS) high sink capability.

2. (T) true open drain (P-buffer and protection diode to VDDnot implemented).

3. [ ] alternate function remapping option (if the same alternate function is shown twice, it

indicates an exclusive choice not a duplication of the function).

DocID15590 Rev 820/116

6 7 8

16171819

VCAP

OSCOUT/PA2

OSCIN/PA1

[UART1_TX]/[SPI_NSS]/TIM5_CH3/(HS) PA3

NRST

PD4 (HS)/BEEP / TIM5_CH1/UART1_CK

PD5(HS)/AIN5/UART1_TX

PD3 (HS)/AIN4/TIM5_CH2/ADC_ETR

PD2(HS)/AIN3/[TIM5_CH3]

PC4(HS)/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N]

PC5 (HS)/SPI_SCK/[TIM5_CH1]

PC6(HS)/SPI_MOSI/[TIM1_CH1]

PC7(HS)/SPI_MISO/[TIM1_CH2]

PD1(HS)/SWIM

[TIM1_BKIN]/I

C_SDA/(T)PB5

[TIM1_CH1N]/[TLI]/TIM1_CH3/(HS)PC3

PD6(HS)/AIN6/UART1_RX

[ADC_ETR]/I

C_SCL/(T)PB4

Pinout and pin descriptionSTM8S903K3 STM8S903F3

STM8S903F3 UFQFPN20 pinout5.2

Figure 4: STM8S903F3 UFQFPN20 pinout

1. (HS) high sink capability.

2. (T) true open drain (P-buffer and protection diode to VDDnot implemented).

3. [ ] alternate function remapping option (if the same alternate function is shown twice, it

indicates an exclusive choice not a duplication of the function).

21/116DocID15590 Rev 8

TSSOP

SO20

PA1/ OSCIN

710

[UART1_TX]

1013

TIM1_CH3/TLI/[TIM1_CH1N ]

1114

CLK_CCO/AIN2/[TIM1_CH2N]

1518

PD1/ SWIM

1720

ADC_ETR

181

[UART1_CK]

STM8S903K3 STM8S903F3Pinout and pin description

Pin description TSSOP20_SO20_UFQFPN205.3

Table 5: TSSOP20/SO20/UFQFPN20 pin description

TypePin nameUFQFPN

(2)

(4)

Ext.

wpufloating

interrupt

OutputInput

sink

(1)

O1XXI/OPB5/ I2C_SDA [TIM1_BKIN]811

O1XXI/OPB4/ I2C_SCL [ADC_ETR]912

PPODSpeedHigh

XXO1XXXI/O

XXO1XXXI/OPA2/ OSCOUT36

XXO3HSXXXI/OPA3/ TIM5_CH3 [SPI_NSS]

(3)

XXO3HSXXXI/OPC3/

XXO3HSXXXI/OPC4/ TIM1_CH4/

XXO3HSXXXI/OPC5/SPI_SCK [TIM5_CH1]1215

XXO3HSXXXI/OPC6/ SPI_MOSI [TIM1_CH1]1316

XXO3HSXXXI/OPC7/ SPI_MISO [TIM1_CH2]1417

XXO4HSXXXI/O

XXO3HSXXXI/OPD2/AIN3/ [TIM5_CH3]1619

XXO3HSXXXI/OPD3/ AIN4/ TIM5_CH2/

XXO3HSXXXI/OPD4/ TIM5_CH1/ BEEP

XXO3HSXXXI/OPD5/ AIN5/ UART1_TX192

XXO3HSXXXI/OPD6/ AIN6/ UART1_RX203

Default alternate functionMain function (after reset)

ResetXI/ONRST14

Resonator/ crystal inPort

Resonator/ crystal outPort

Digital groundSV

1.8 V regulator capacitorSVCAP58

Digital power supplySV

Timer 52 channel 3Port

Timer 1 - channel 3Port

Timer 1 - channel 4

Port

/configurable clock output

SWIM data interfacePort

Port D2

Analog input 4 Timer 52 -

Port

channel 2/ADC external

trigger

Port

output

Analog input 5/ UART1

Port

data transmit

Analog input 6/ UART1

Port

data receive

Alternate function after remap [option bit]

SPI master/ slave select [AFR1]/ UART1 data transmit [AFR1:0]

Timer 1 - break input [AFR4]I2C dataPort

ADC external trigger [AFR4]I2C clockPort

Top level interrupt [AFR3] Timer 1 inverted channel 1 [AFR7]

Analog input 2 [AFR2]Timer 1 inverted channel 2 [AFR7]

Timer 5 channel 1 [AFR0]SPI clockPort

Timer 1 channel 1 [AFR0]PI master out/slave inPort

Timer 1 channel 2[AFR0]SPI master in/ slave outPort

Analog input 3 [AFR2] Timer 52

- channel 3 [AFR1]

UART clock [AFR2]Timer 5 - channel 1/BEEP

(1)

I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings ( see section "Absolute maximum ratings"). (2)

When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode if Halt/Active-halt is used in the application. (3)

In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDDare not implemented) (4)

The PD1 pin is in input pull-up during the reset phase and after internal reset release.

DocID15590 Rev 822/116

[ADC_ETR] I

C_SCL/(T) PB4

TIM1_ETR/AIN3/(HS) PB3

TIM1_CH3N/AIN2/(HS) PB2

TIM1_CH2N/AIN1/(HS) PB1

TIM1_CH1N/AIN0/(HS) PB0

PB7

PB6

[TIM1_BKIN] I

C_SDA/(T) PB5

32 31 30 29 28 27 26 25

24 23 22 21 20 19 18 17

9 10 11 12 13 14 15

1 2 3 4 5 6 7 8

VCAP

[UART1_TX][SPI_NSS] TIM5_CH3/(HS) PA3

[UART1_RX]PF4

NRST

OSCIN/PA1

OSCOUT/PA2

PC3 (HS)/TIM1_CH3 [TLI] [TIM1_CH1N] PC2 (HS)/TIM1_CH2 [TIM1_CH3N]

PC1 (HS)/TIM1_CH1/UART1_CK [TIM1_CH2N] PE5/SPI_NSS [TIM1_CH1N]

PC7 (HS)/SPI_MISO [TIM1_CH2] PC6 (HS)/SPI_MOSI [TIM1_CH1] PC5 (HS)/SPI_SCK [TIM5_CH1] PC4 (HS)/TIM1_CH4/CLK_CCO [AIN2] [TIM1_CH2N]

PD3 (HS)/AIN4/TIM5_CH2/ADC_ETR

PD2 (HS)[AIN3] [TIM5_CH3]

PD1 (HS)/SWIM

PD0 (HS)/ TIM1_BKIN [CLK_CCO]

PD7 (HS)/TLI [TIM1_CH4]

PD6 (HS)/AIN6/UART1_RX

PD5 (HS)/AIN5/UART1_TX

PD4 (HS)/BEEP/TIM5_CH1 [UART1_CK]

Pinout and pin descriptionSTM8S903K3 STM8S903F3

STM8S903K3 UFQFPN32/LQFP32/SDIP32 pinout5.4

Figure 5: STM8S903K3 UFQFPN32/LQFP32 pinout

1. (HS) high sink capability.

2. (T) true open drain (P-buffer and protection diode to VDDnot implemented).

3. [ ] alternate function remapping option (if the same alternate function is shown twice, it

indicates an exclusive choice not a duplication of the function).

23/116DocID15590 Rev 8

1 2 3 4 5 6 7

9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

AIN4/TIM5_CH2/ADC_ETR/PD3(HS)

TIM5_CH1[UART1_CK]BEEP/PD4(HS)

AIN5/UART1_TX/PD5(HS) AIN6/UART1_RX/PD6(HS)

[TIM1_CH4]TLI/PD7(HS)

NRST

OSCIN/PA1

OSCOUT/PA2

VCAP

[UART1_TX][SPI_NSS]/TIM5_CH3/PA3(HS)

[UART1_RX]/PF4

PB6

PB4(T)/I2C_SCL[ADC_ETR]

PB3(HS)[AIN3]TIM1_ETR

PB2(HS)/AIN2/TIM1_CH3N

PB1(HS)/AIN1/TIM1_CH2N

PB0(HS)/AIN0/TIM1_CH1N

PE5/SPI_NSS[TIM1_CH1N]

PC1(HS)/TIM1_CH1/UART1_CK[TIM1_CH2N]

PC2(HS)/TIM1_CH2[TIM1_CH3N]

PC3(HS)/TIM1_CH3[TLI][TIM1_CH1N]

PC4(HS)/TIM1_CH4/CLK_CCO[AIN2][TIM1_CH2N]

PC5(HS)/SPI_SCK[TIM5_CH1]

PC6(HS)/SPI_MOSI[TIM1_CH1]

PC7(HS)/SPI_MISO[TIM1_CH2]

PD0(HS)/TIM1_BKIN[CLK_CCO]

PD1(HS)/SWIM

PD2(HS)[AIN3][TIM5_CH3]

PB7

[TIM1_BKIN]I2C_SDA/PB5(T)

STM8S903K3 STM8S903F3Pinout and pin description

Figure 6: STM8S903K3 SDIP32 pinout

1. (HS) high sink capability.

2. (T) true open drain (P-buffer and protection diode to VDDnot implemented).

3. [ ] alternate function remapping option (if the same alternate function is shown twice, it

Pin description5.5

SDIP

LQFP32

PA1/ OSCIN

611

712

[UART1_TX]

indicates an exclusive choice not a duplication of the function).

Table 6: UFQFPN32/LQFP32/SDIP32 pin description

TypePin nameUFQFPN/

(2)

Ext.

wpufloating

interrupt

DocID15590 Rev 824/116

OutputInput

sink

(1)

PPODSpeedHigh

XXO1XXXI/O

XXO1XXXI/OPA2/ OSCOUT38

XXO3HSXXXI/OPA3/ TIM5_CH3 [SPI_NSS]

XXO1XXI/OPF4 [UART1_RX]813

XXO1XXXI/OPB7914

function (after reset)

ResetXI/ONRST16

Digital groundSV

1.8 V regulator capacitorSVCAP510

Digital power supplySV

Port B7

Default alternate functionMain

Resonator/ crystal inPort

Resonator/ crystal outPort

Timer 52 channel 3Port

Alternate function after remap [option bit]

SPI master/ slave select [AFR1]/ UART1 data transmit [AFR1:0]

UART1 data receive [AFR1:0]Port

Pinout and pin descriptionSTM8S903K3 STM8S903F3

SDIP

LQFP32

1823

[TIM1_CH2N]

2025

]

2126

CLK_CCO/AIN2/[TIM1_CH2N]

2631

PD1/ SWIM

292

[UART1_CK]

TypePin nameUFQFPN/

(4)

Ext.

wpufloating

interrupt

OutputInput

sink

(1)

O1XXI/OPB5/ I2C_SDA [TIM1_BKIN]1116

O1XXI/OPB4/ I2C_SCL [ADC_ETR]1217

PPODSpeedHigh

XXO1XXXI/OPB61015

(3)

XXO3HSXXXI/OPB3/ AIN3/TIM1_ETR1318

XXO3HSXXXI/OPB2/ AIN2/ TIM1_CH3N1419

XXO3HSXXXI/OPB1/ AIN1/ TIM1_CH2N1520

XXO3HSXXXI/OPB0/ AIN0/ TIM1_CH1N1621

XXO3HSXXXI/OPE5/ SPI_NSS [TIM1_CH1N]1722

XXO3HSXXXI/OPC1/ TIM1_CH1/ UART1_CK

XXO3HSXXXI/OPC2/ TIM1_CH2 [TIM1_CH3N]1924

XXO3HSXXXI/OPC3/ TIM1_CH3/TLI/[TIM1_CH1N

XXO3HSXXXI/OPC4/ TIM1_CH4/

XXO3HSXXXI/OPC5/SPI_SCK [TIM5_CH1]2227

XXO3HSXXXI/OPC6/ SPI_MOSI [TIM1_CH1]2328

XXO3HSXXXI/OPC7/ SPI_MISO [TIM1_CH2]2429

XXO3HSXXXI/OPD0/ TIM1_BKIN [CLK_CCO]2530

XXO4HSXXXI/O

XXO3HSXXXI/OPD2/AIN3/ [TIM5_CH3]2732

XXO3HSXXXI/OPD3/ AIN4/ TIM5_CH2/ ADC_ETR281

XXO3HSXXXI/OPD4/ TIM5_CH1/ BEEP

XXO3HSXXXI/OPD5/ AIN5/ UART1_TX303

XXO3HSXXXI/OPD6/ AIN6/ UART1_RX314

XXO3HSXXXI/OPD7/ TLI [TIM1_CH4]325

Default alternate functionMain function (after reset)

Port B6

Analog input 3/ Timer 1

Port

external trigger

Analog input 2/ Timer 1 -

Port

inverted channel 3

Analog input 1/ Timer 1 -

Port

inverted channel 2

Analog input 0/ Timer 1 -

Port

inverted channel 1

SPI master/ slave selectPort

Timer 1 - channel 1

Port

UART1 clock

Timer 1 - channel 2Port

Timer 1 - channel 3Port

Timer 1 - channel 4

Port

/configurable clock output

Timer 1 - break inputPort

SWIM data interfacePort

Port D2

Analog input 4 Timer 52 -

Port

channel 2/ADC external

trigger

Port

output

Analog input 5/ UART1

Port

data transmit

Analog input 6/ UART1

Port

data receive

Alternate function after remap [option bit]

Timer 1 - break input [AFR4]I2C dataPort

ADC external trigger [AFR4]I2C clockPort

Timer 1 - inverted channel 1 [AFR1:0]

Timer 1 - inverted channel 2 [AFR1:0]

Timer 1 - inverted channel 3 [AFR1:0]

Toplevel interrupt [AFR3] Timer 1 inverted channel 1 [AFR7]

Analog input 2 [AFR2]Timer 1 inverted channel 2 [AFR7]

Timer 5 channel 1 [AFR0]SPI clockPort

Timer 1 channel 1 [AFR0]PI master out/slave inPort

Timer 1 channel 2[AFR0]SPI master in/ slave outPort

Configurable clock output [AFR5]

Analog input 3 [AFR2] Timer 52

- channel 3 [AFR1]

UART clock [AFR2]Timer 5 - channel 1/BEEP

Timer 1 - channel 4 [AFR6]Top level interruptPort

(1)

In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDDare not implemented) (4)

The PD1 pin is in input pull-up during the reset phase and after internal reset release.

25/116DocID15590 Rev 8

STM8S903K3 STM8S903F3Pinout and pin description

Alternate function remapping5.6

As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. When the remapping option is active, the default alternate function is no longer available.

To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers.

Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO section of the family reference manual, RM0016).

DocID15590 Rev 826/116

0x00 9FFF

Flash program memory

(8 Kbytes)

0x00 0000

RAM

0x00 03FF

(1 Kbyte)

513 bytes stack

0x00 4000

0x00 427F

640 bytes data EEPROM

Reserved

0x00 4280

0x00 A000

0x00 47FF

0x00 8000

32 interrupt vectors

0x00 807F

GPIO and periph. reg.

0x00 5000

0x00 57FF

0x00 5800

0x00 7FFF

0x00 480B

0x00 4FFF

0x00 7EFF

CPU/SWIM/debug/ITC

registers

0x00 7F00

Reserved

Option bytes

0x00 480A

0x00 4800

0x00 0800

0x00 3FFF

0x00 8080

Reserved

Unique ID

0x00 4864 0x00 4865 0x00 4870 0x00 4871

Memory and register mapSTM8S903K3 STM8S903F3

Memory and register map6

Memory map6.1

Figure 7: Memory map

27/116DocID15590 Rev 8

STM8S903K3 STM8S903F3Memory and register map

Register map6.2

I/O port hardware register map6.2.1

Table 7: I/O port hardware register map

0x00 5000

0x00 5005

0x00 500A

Port A

Port B

Port C

Reset status

0x00Port A data output latch registerPA_ODR

(1)

Port A input pin value registerPA_IDR0x00 5001

0xXX

0x00Port A data direction registerPA_DDR0x00 5002

0x00Port A control register 1PA_CR10x00 5003

0x00Port A control register 2PA_CR20x00 5004

0x00Port B data output latch registerPB_ODR

(1)

Port B input pin value registerPB_IDR0x00 5006

0xXX

0x00Port B data direction registerPB_DDR0x00 5007

0x00Port B control register 1PB_CR10x00 5008

0x00Port B control register 2PB_CR20x00 5009

0x00Port C data output latch registerPC_ODR

(1)

Port C input pin value registerPB_IDR0x00 500B

0xXX

0x00Port C data direction registerPC_DDR0x00 500C

0x00 500F

0x00 5014

Port D

Port E

0x00Port C control register 1PC_CR10x00 500D

0x00Port C control register 2PC_CR20x00 500E

0x00Port D data output latch registerPD_ODR

(1)

Port D input pin value registerPD_IDR0x00 5010

0xXX

0x00Port D data direction registerPD_DDR0x00 5011

0x02Port D control register 1PD_CR10x00 5012

0x00Port D control register 2PD_CR20x00 5013

0x00Port E data output latch registerPE_ODR

(1)

Port E input pin value registerPE_IDR0x00 5015

0xXX

0x00Port E data direction registerPE_DDR0x00 5016

0x00Port E control register 1PE_CR10x00 5017

DocID15590 Rev 828/116

Memory and register mapSTM8S903K3 STM8S903F3

0x00 5019

Port F

(1)

Depends on the external circuitry.

General hardware register map6.2.2

0x00 501E to

Reserved area (60 bytes)

Port F input pin value registerPF_IDR0x00 501A

Table 8: General hardware register map

Reset status

0x00Port E control register 2PE_CR2Port E0x00 5018

0x00Port F data output latch registerPF_ODR

0xXX

0x00Port F data direction registerPF_DDR0x00 501B

0x00Port F control register 1PF_CR10x00 501C

0x00Port F control register 2PF_CR20x00 501D

Reset status

(1)

0x00 5059

0x00 505A

0x00 505B

0x00 505C

0x00 505D

0x00 505E

0x00 505F

0x00 5060 to

0x00 5061

0x00 5062

0x00 5063

Flash

FLASH _IAPSR

Reserved area (2 bytes)

FLASH _PUKRFlash

Reserved area (1 byte)

0x00Flash control register 1FLASH_CR1

0x00Flash control register 2FLASH_CR2

0xFFFlash complementary control register 2FLASH_NCR2

0x00Flash protection registerFLASH _FPR

0xFFFlash complementary protection registerFLASH _NFPR

0x00Flash in-application programming status

0x00Flash program memory unprotection

29/116DocID15590 Rev 8

STM8S903K3 STM8S903F3Memory and register map

0x00 5064

0x00 5065 to

0x00 509F

0x00 50A0

0x00 50A1

0x00 50A2 to

0x00 50B2

0x00 50B3

0x00 50B4 to

0x00 50BF

Reserved area (59 bytes)

Reserved area (17 bytes)

Reserved area (12 bytes)

Reset status

0x00Data EEPROM unprotection registerFLASH _DUKRFlash

0x00External interrupt control register 1EXTI_CR1ITC

0x00External interrupt control register 2EXTI_CR2

Reset status registerRST_SRRST

0xXX

(1)

0x00 50C0

0x00 50C1

0x00 50C2

0x00 50C3

0x00 50C4

0x00 50C5

0x00 50C6

0x00 50C7

0x00 50C8

0x00 50C9

0x01Internal clock control registerCLK_ICKRCLK

0x00External clock control registerCLK_ECKR

Reserved area (1 byte)

0xE1Clock master status registerCLK_CMSRCLK

0xE1Clock master switch registerCLK_SWR

0xXXClock switch control registerCLK_SWCR

0x18Clock divider registerCLK_CKDIVR

0xFFPeripheral clock gating register 1CLK_PCKENR1

0x00Clock security system registerCLK_CSSR

0x00Configurable clock control registerCLK_CCOR

0x00 50CA

0xFFPeripheral clock gating register 2CLK_PCKENR2

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