ST STM8S105K4, STM8S105K6, STM8S105S4, STM8S105S6, STM8S105C4 User Manual

...

Download

Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbytes Flash,

LQFP48 7x7

LQFP44 10x10

LQFP32 7x7

SDIP32 400 ml

UFQFPN32 5x5

integrated EEPROM,10-bit ADC, timers, UART, SPI, I²C

Features

Core

16 MHz advanced STM8 core with Harvard

•

architecture and 3-stage pipeline

Extended instruction set

•

Memories

Medium-density Flash/EEPROM:

•

Program memory up to 32 Kbytes; data

retention 20 years at 55°C after 10 kcycles

Data memory up to 1 Kbytes true data

EEPROM; endurance 300 kcycles

RAM: Up to 2 Kbytes

•

Clock, reset and supply management

2.95 V to 5.5 V operating voltage

•

Flexible clock control, 4 master clock sources:

•

Low power crystal resonator oscillator

External clock input

Internal, user-trimmable 16 MHz RC

Internal low power 128 kHz RC

Clock security system with clock monitor

•

Power management:

•

Low power modes (wait, active-halt, halt)

Switch-off peripheral clocks individually

Permanently active, low consumption power-on

•

and power-down reset

STM8S105xx

Interrupt management

Nested interrupt controller with 32 interrupts

•

Up to 37 external interrupts on 6 vectors

•

Timers

2x 16-bit general purpose timers, with 2+3

•

CAPCOM channels (IC, OC or PWM)

Advanced control timer: 16-bit, 4 CAPCOM

•

channels, 3 complementary outputs, dead-time insertion and flexible synchronization

8-bit basic timer with 8-bit prescaler

•

Auto wake-up timer

•

Window and independent watchdog timers

•

Communications interfaces

UART with clock output for synchronous

•

operation, Smartcard, IrDA, LIN

SPI interface up to 8 Mbit/s

•

I2C interface up to 400 Kbit/s

•

Analog-to-digital converter (ADC)

10-bit, ±1 LSB ADC with up to 10 multiplexed

•

channels, scan mode and analog watchdog

I/Os

Up to 38 I/Os on a 48-pin package including 16

•

high sink outputs

Highly robust I/O design, immune against current

•

injection

Development support

Embedded single wire interface module (SWIM)

•

for fast on-chip programming and non intrusive debugging

Unique ID

96-bit unique key for each device

•

Table 1: Device summary

Part numberReference

STM8S105xx

STM8S105K4, STM8S105K6, STM8S105S4,

STM8S105S6, STM8S105C4, STM8S105C6

June 2012

DocID14771 Rev 12

1/124

www.st.com

STM8S105xxContents

1 Introduction ..............................................................................................................8

2 Description ...............................................................................................................9

3 Block diagram ........................................................................................................10

4 Product overview ...................................................................................................11

4.1 Central processing unit STM8 .....................................................................................11

4.2 Single wire interface module (SWIM) and debug module (DM) ..................................11

4.3 Interrupt controller .......................................................................................................12

4.4 Flash program and data EEPROM memory ................................................................12

4.5 Clock controller ............................................................................................................13

4.6 Power management ....................................................................................................14

4.7 Watchdog timers ..........................................................................................................15

4.8 Auto wakeup counter ...................................................................................................15

4.9 Beeper ........................................................................................................................15

4.10 TIM1 - 16-bit advanced control timer .........................................................................16

4.11 TIM2, TIM3 - 16-bit general purpose timers ..............................................................16

4.12 TIM4 - 8-bit basic timer ..............................................................................................16

4.13 Analog-to-digital converter (ADC1) ............................................................................17

4.14 Communication interfaces .........................................................................................17

4.14.1 UART2 ...............................................................................................17

4.14.2 SPI .....................................................................................................18

4.14.3 I²C ......................................................................................................19

5 Pinout and pin description ...................................................................................20

5.1 STM8S105 pinouts and pin description .......................................................................21

5.1.1 Alternate function remapping ...............................................................27

6 Memory and register map .....................................................................................29

6.1 Memory map ................................................................................................................29

6.2 Register map ...............................................................................................................30

6.2.1 I/O port hardware register map ............................................................30

6.2.2 General hardware register map ...........................................................33

6.2.3 CPU/SWIM/debug module/interrupt controller registers ......................44

7 Interrupt vector mapping ......................................................................................47

8 Option bytes ...........................................................................................................49

9 Unique ID ................................................................................................................54

10 Electrical characteristics ....................................................................................55

10.1 Parameter conditions .................................................................................................55

10.1.1 Minimum and maximum values .........................................................55

10.1.2 Typical values .....................................................................................55

DocID14771 Rev 122/124

ContentsSTM8S105xx

10.1.3 Typical curves ....................................................................................55

10.1.4 Typical current consumption ..............................................................55

10.1.5 Loading capacitor ...............................................................................56

10.1.6 Pin input voltage .................................................................................56

10.2 Absolute maximum ratings ........................................................................................56

10.3 Operating conditions ..................................................................................................58

10.3.1 VCAP external capacitor ....................................................................61

10.3.2 Supply current characteristics ............................................................61

10.3.3 External clock sources and timing characteristics .............................73

10.3.4 Internal clock sources and timing characteristics ...............................75

10.3.5 Memory characteristics ......................................................................78

10.3.6 I/O port pin characteristics .................................................................79

10.3.7 Typical output level curves .................................................................83

10.3.8 Reset pin characteristics ....................................................................88

10.3.9 SPI serial peripheral interface ............................................................91

10.3.10 I2C interface characteristics .............................................................94

10.3.11 10-bit ADC characteristics ................................................................96

10.3.12 EMC characteristics .........................................................................99

11 Package information ..........................................................................................103

11.1 48-pin LQFP package mechanical data ...................................................................103

11.2 44-pin LQFP package mechanical data ...................................................................105

11.3 32-pin LQFP package mechanical data ...................................................................106

11.4 32-lead UFQFPN package mechanical data ...........................................................108

11.5 SDIP32 package mechanical data ...........................................................................109

12 Thermal characteristics ....................................................................................111

12.1 Reference document ...............................................................................................112

12.2 Selecting the product temperature range ................................................................112

13 Ordering information .........................................................................................113

13.1 STM8S105 FASTROM microcontroller option list ...................................................113

14 STM8 development tools ..................................................................................118

14.1 Emulation and in-circuit debugging tools .................................................................118

14.2 Software tools ..........................................................................................................118

14.2.1 STM8 toolset ....................................................................................119

14.2.2 C and assembly toolchains ..............................................................119

14.3 Programming tools ..................................................................................................119

15 Revision history .................................................................................................120

3/124DocID14771 Rev 12

STM8S105xxList of tables

List of tables

Table 1. Device summary .........................................................................................................................1

Table 2. STM8S105xx access line features .............................................................................................9

Table 3. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ..................................14

Table 4. TIM timer features ...................................................................................................................16

Table 5. Legend/abbreviations for pinout tables ...................................................................................20

Table 6. Pin description for STM8S105 microcontrollers .......................................................................24

Table 7. Flash, Data EEPROM and RAM boundary addresses ..........................................................105

Table 8. I/O port hardware register map ..............................................................................................108

Table 9. General hardware register map ................................................................................................33

Table 10. CPU/SWIM/debug module/interrupt controller registers ......................................................109

Table 11. Interrupt mapping ....................................................................................................................47

Table 12. Option bytes ..........................................................................................................................54

Table 13. Option byte description ...........................................................................................................50

Table 14. Description of alternate function remapping bits [7:0] of OPT2 ..............................................52

Table 15. Unique ID registers (96 bits) ...................................................................................................54

Table 16. Voltage characteristics ...........................................................................................................56

Table 17. Current characteristics ...........................................................................................................57

Table 18. Thermal characteristics ..........................................................................................................58

Table 19. General operating conditions .................................................................................................59

Table 20. Operating conditions at power-up/power-down ......................................................................60

Table 21. Total current consumption with code execution in run mode at VDD= 5 V .............................61

Table 22. Total current consumption with code execution in run mode at VDD= 3.3 V ..........................73

Table 23. Total current consumption in wait mode at VDD= 5 V ............................................................64

Table 24. Total current consumption in wait mode at VDD= 3.3 V .........................................................65

Table 25. Total current consumption in active halt mode at VDD= 5 V ..................................................65

Table 26. Total current consumption in active halt mode at VDD= 3.3 V ...............................................66

Table 27. Total current consumption in halt mode at VDD= 5 V .............................................................67

Table 28. Total current consumption in halt mode at VDD= 3.3 V ..........................................................68

Table 29. Wakeup times .........................................................................................................................68

Table 30. Total current consumption and timing in forced reset state ..................................................102

Table 31. Peripheral current consumption .............................................................................................69

Table 32. HSE user external clock characteristics .................................................................................73

Table 33. HSE oscillator characteristics .................................................................................................74

Table 34. HSI oscillator characteristics ..................................................................................................75

Table 35. LSI oscillator characteristics ...................................................................................................77

Table 36. RAM and hardware registers ..................................................................................................78

Table 37. Flash program memory/data EEPROM memory ....................................................................78

Table 38. I/O static characteristics .........................................................................................................79

Table 39. Output driving current (standard ports) ..................................................................................82

Table 40. Output driving current (true open drain ports) ........................................................................82

Table 41. Output driving current (high sink ports) ..................................................................................83

Table 42. NRST pin characteristics ........................................................................................................88

Table 43. SPI characteristics ..................................................................................................................91

Table 44. I2C characteristics ..................................................................................................................94

Table 45. ADC characteristics ................................................................................................................96

Table 46. ADC accuracy with R Table 47. ADC accuracy with R

< 10 kΩ , V

AIN

< 10 kΩ R

AIN

= 5 V .......................................................................97

DDA

AIN

, V

= 3.3 V ............................................................98

DDA

DocID14771 Rev 124/124

List of tablesSTM8S105xx

Table 48. EMS data ..............................................................................................................................100

Table 49. EMI data ...............................................................................................................................101

Table 50. ESD absolute maximum ratings ...........................................................................................102

Table 51. Electrical sensitivities ...........................................................................................................102

Table 52. 48-pin low profile quad flat package mechanical data .........................................................103

Table 53. 44-pin low profile quad flat package mechanical data .........................................................105

Table 54. 32-pin low profile quad flat package mechanical data .........................................................120

Table 55. 32-lead, ultra thin, fine pitch quad flat no-lead package mechanical data ...........................108

Table 56. 32-lead shrink plastic DIP (400 ml) package mechanical data ............................................109

Table 57. Thermal characteristics

(1)

....................................................................................................111

Table 58. Document revision history ...................................................................................................120

5/124DocID14771 Rev 12

STM8S105xxList of figures

List of figures

Figure 1. STM8S105xx access line block diagram ................................................................................10

Figure 2. Flash memory organisation ....................................................................................................13

Figure 3. LQFP 48-pin pinout .................................................................................................................21

Figure 4. LQFP 44-pin pinout .................................................................................................................22

Figure 5. LQFP/UFQFPN 32-pin pinout ................................................................................................23

Figure 6. SDIP 32-pin pinout ..................................................................................................................24

Figure 7. Memory map ...........................................................................................................................29

Figure 8. Supply current measurement conditions ................................................................................55

Figure 9. Pin loading conditions .............................................................................................................56

Figure 10. Pin input voltage ...................................................................................................................56

Figure 11. f

CPUmax

Figure 12. External capacitor C Figure 13. Typ. I Figure 14. Typ. I Figure 15. Typ. I Figure 16. Typ. I Figure 17. Typ. I Figure 18. Typ. I

Figure 19. HSE external clocksource .....................................................................................................74

Figure 20. HSE oscillator circuit diagram ...............................................................................................75

Figure 21. Typical HSI accuracy at VDD= 5 V vs 5 temperatures ..........................................................76

Figure 22. Typical HSI accuracy vs VDD@ 4 temperatures ..................................................................77

Figure 23. Typical LSI accuracy vs VDD@ 4 temperatures ...................................................................78

Figure 24. Typical VILand VIHvs VDD@ 4 temperatures ......................................................................81

Figure 25. Typical pull-up resistance vs VDD@ 4 temperatures ............................................................81

Figure 26. Typical pull-up current vs VDD@ 4 temperatures .................................................................82

Figure 27. Typ. VOL@ VDD= 5 V (standard ports) ................................................................................84

Figure 28. Typ. VOL@ VDD= 3.3 V (standard ports) .............................................................................84

Figure 29. Typ. VOL@ VDD= 5 V (true open drain ports) ......................................................................85

Figure 30. Typ. VOL@ VDD= 3.3 V (true open drain ports) ...................................................................85

Figure 31. Typ. VOL@ VDD= 5 V (high sink ports) ................................................................................86

Figure 32. Typ. VOL@ VDD= 3.3 V (high sink ports) .............................................................................86

Figure 33. Typ. VDD- VOH@ VDD= 5 V (standard ports) .......................................................................87

Figure 34. Typ. VDD- VOH@ VDD= 3.3 V (standard ports) ....................................................................87

Figure 35. Typ. VDD- VOH@ VDD= 5 V (high sink ports) ......................................................................88

Figure 36. Typ. VDD- VOH@ VDD= 3.3 V (high sink ports) ...................................................................88

Figure 37. Typical NRST VILand VIHvs VDD@ 4 temperatures ...........................................................89

Figure 38. Typical NRST pull-up resistance vs VDD@ 4 temperatures .................................................90

Figure 39. Typical NRST pull-up current vs VDD@ 4 temperatures ......................................................90

Figure 40. Recommended reset pin protection ......................................................................................91

Figure 41. SPI timing diagram - slave mode and CPHA = 0 ..................................................................93

Figure 42. SPI timing diagram - slave mode and CPHA = 1 Figure 43. SPI timing diagram - master mode Figure 44. Typical application with I2C bus and timing diagram

Figure 45. ADC accuracy characteristics ...............................................................................................99

Figure 46. Typical application with ADC ................................................................................................99

Figure 47. 48-pin low profile quad flat package (7 x 7) ........................................................................103

versus V

DD(RUN)

DD(WFI)

..............................................................................................................60

vs. V vs. f

vs. V vs. V vs. f

DD ,

CPU ,

DD ,

CPU

.......................................................................................................61

EXT

HSE user external clock, f

HSE user external clock, VDD= 5 V ..................................................71

HSI RC osc, f

HSE user external clock, f

, HSE user external clock VDD= 5 V ....................................................72

vs. VDD, HSI RC osc, f

= 16 MHz ...........................................70

CPU

= 16 MHz ..............................................................71

CPU

= 16 MHz ................................................................73

CPU

(1)

...................................................................................94

= 16 MHz ............................................72

CPU

(1)

.............................................................93

(1)

.......................................................95

DocID14771 Rev 126/124

List of figuresSTM8S105xx

Figure 48. 44-pin low profile quad flat package ...................................................................................105

Figure 49. 32-pin low profile quad flat package (7 x 7) ........................................................................106

Figure 50. 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) ..........................................108

Figure 51. 32-lead shrink plastic DIP (400 ml) package ......................................................................109

Figure 52. STM8S105xx access line ordering information scheme .....................................................113

7/124DocID14771 Rev 12

STM8S105xxIntroduction

Introduction1

This datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information.

For complete information on the STM8S microcontroller memory, registers and peripherals,

•

please refer to the STM8S microcontroller family reference manual (RM0016).

For information on programming, erasing and protection of the internal Flash memory

•

please refer to the STM8S Flash programming manual (PM0051).

For information on the debug and SWIM (single wire interface module) refer to the STM8

•

SWIM communication protocol and debug module user manual (UM0470).

For information on the STM8 core, please refer to the STM8 CPU programming manual

•

(PM0044).

DocID14771 Rev 128/124

DescriptionSTM8S105xx

Description2

The STM8S105xx access line 8-bit microcontrollers offer from 16 to 32 Kbytes Flash program memory, plus integrated true data EEPROM. They are referred to as medium-density devices in the STM8S microcontroller family reference manual (RM0016).

All devices of the STM8S105xx access line provide the following benefits: reduced system cost, performance and robustness, short development cycles, and product longevity.

The system cost is reduced thanks to an integrated true data EEPROM for up to 300 kwrite/erase cycles and a high system integration level with internal clock oscillators, watchdog, and brown-out reset.

Device performance is ensured by a 16 MHz CPU clock frequency and enhanced characteristics which include robust I/O, independent watchdogs (with a separate clock source), and a clock security system.

Short development cycles are guaranteed due to application scalability across a common family product architecture with compatible pinout, memory map and and modular peripherals. Full documentation is offered with a wide choice of development tools.

Product longevity is ensured in the STM8S family thanks to their advanced core which is made in a state-of-the art technology for applications with 2.95 V to 5.5 V operating supply.

Table 2: STM8S105xx access line features

STM8S105K4STM8S105K6STM8S105S4STM8S105S6STM8S105C4STM8S105C6Device

323244444848Pin count

of GPIOs

channels

complementary outputs

channels

Flash Program memory (bytes)

(bytes)

Peripheral set

252534343838Maximum number

232331313535Ext. Interrupt pins

888899Timer CAPCOM

333333Timer

77991010A/D Converter

121215151616High sink I/Os

16K32K16K32K16K32KMedium density

102410241024102410241024Data EEPROM

2K2K2K2K2K2KRAM (bytes)

Advanced control timer (TIM1), General-purpose timers (TIM2 and TIM3), Basic timer (TIM4) SPI, I2C, UART, Window WDG, Independent WDG, ADC

9/124DocID14771 Rev 12

XTAL 1-16 MHz

RC int. 16 MHz

RC int. 128 kHz

STM8 core

Debug/SWIM

I2C

SPI

UART2

16-bit general purpose

AWU timer

Reset block

Reset

POR

BOR

Clock controller

Detector

Clock to peripherals and core

8 Mbit/s

Address and data bus

Window WDG

Independent WDG

Up to 32 Kbytes

1 Kbytes

Up to 2 Kbytes

Boot ROM

ADC1

Reset

400 Kbit/s

Single wire debug interf.

program Flash

16-bit advanced control

timer (TIM1)

timers (TIM2, TIM3)

8-bit basic timer

(TIM4)

data EEPROM

RAM

Master/slave autosynchro LIN master SPI emul.

Beeper

1/2/4 kHz beep

5 CAPCOM channels

Up to

4 CAPCOM channels +3

Up to

complementary outputs

STM8S105xxBlock diagram

Block diagram3

Figure 1: STM8S105xx access line block diagram

DocID14771 Rev 1210/124

Product overviewSTM8S105xx

Product overview4

The following section intends to give an overview of the basic features of the device functional modules and peripherals.

For more detailed information please refer to the corresponding family reference manual (RM0016).

Central processing unit STM84.1

The 8-bit STM8 core is designed for code efficiency and performance.

It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions.

Architecture and registers

Harvard architecture

•

3-stage pipeline

•

32-bit wide program memory bus - single cycle fetching for most instructions

•

X and Y 16-bit index registers - enabling indexed addressing modes with or without offset

•

and read-modify-write type data manipulations

8-bit accumulator

•

24-bit program counter - 16-Mbyte linear memory space

•

16-bit stack pointer - access to a 64 K-level stack

•

8-bit condition code register - 7 condition flags for the result of the last instruction

•

Addressing

20 addressing modes

•

Indexed indirect addressing mode for look-up tables located anywhere in the address

•

space

Stack pointer relative addressing mode for local variables and parameter passing

•

Instruction set

80 instructions with 2-byte average instruction size

•

Standard data movement and logic/arithmetic functions

•

8-bit by 8-bit multiplication

•

16-bit by 8-bit and 16-bit by 16-bit division

•

Bit manipulation

•

Data transfer between stack and accumulator (push/pop) with direct stack access

•

Data transfer using the X and Y registers or direct memory-to-memory transfers

•

Single wire interface module (SWIM) and debug module (DM)4.2

The single wire interface module and debug module permits non-intrusive, real-time in-circuit debugging and fast memory programming.

11/124DocID14771 Rev 12

STM8S105xxProduct overview

SWIM

Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms.

Debug module

The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in real-time by means of shadow registers.

R/W to RAM and peripheral registers in real-time

•

R/W access to all resources by stalling the CPU

•

Breakpoints on all program-memory instructions (software breakpoints)

•

Two advanced breakpoints, 23 predefined configurations

•

Interrupt controller4.3

Nested interrupts with three software priority levels

•

32 interrupt vectors with hardware priority

•

Up to 37 external interrupts on 6 vectors including TLI

•

Trap and reset interrupts

•

Flash program and data EEPROM memory4.4

Up to 32 Kbytes of Flash program single voltage Flash memory

•

Up to 1 Kbytes true data EEPROM

•

Read while write: Writing in data memory possible while executing code in program memory

•

User option byte area

•

Write protection (WP)

Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction.

There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, data EEPROM and option bytes.

To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to write to data EEPROM, modify the contents of main program memory or the device option bytes.

A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code). Refer to the figure below.

The size of the UBC is programmable through the UBC option byte, in increments of 1 page (512 bytes) by programming the UBC option byte in ICP mode.

This divides the program memory into two areas:

Main program memory: Up to 32 Kbytes minus UBC

•

User-specific boot code (UBC): Configurable up to 32 Kbytes

•

DocID14771 Rev 1212/124

Programmable area

Data

Program memory area

Data memory area ( 1 Kbyte)

EEPROM

UBC area

Remains write protected during IAP

memory

Write access possible for IAP

(1 page steps)

Option bytes

(2 first pages) up to

Medium density Flash program memory (up to 32 Kbytes)

from 1 Kbyte 32 Kbytes

Product overviewSTM8S105xx

The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines.

Figure 2: Flash memory organisation

Read-out protection (ROP)

The read-out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program and data memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.

Clock controller4.5

The clock controller distributes the system clock (f to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness.

Features

Clock prescaler: To get the best compromise between speed and current consumption

•

the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.

Safe clock switching: Clock sources can be changed safely on the fly in run mode

•

through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching.

Clock management: To reduce power consumption, the clock controller can stop the

•

clock to the core, individual peripherals or memory.

Master clock sources: Four different clock sources can be used to drive the master

•

clock:

1-16 MHz high-speed external crystal (HSE)

Up to 16 MHz high-speed user-external clock (HSE user-ext)

MASTER

) coming from different oscillators

13/124DocID14771 Rev 12

STM8S105xxProduct overview

16 MHz high-speed internal RC oscillator (HSI)

128 kHz low-speed internal RC (LSI)

Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz

•

clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.

Clock security system (CSS): This feature can be enabled by software. If an HSE clock

•

failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated.

Configurable main clock output (CCO): This outputs an external clock for use by the

•

application.

Table 3: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers

Bit

Peripheral clock

ADCPCKEN2 3ReservedPCKEN2 7UART2PCKEN1 3TIM1PCKEN1 7

AWUPCKEN2 2ReservedPCKEN2 6ReservedPCKEN1 2TIM3PCKEN1 6

ReservedPCKEN2 1ReservedPCKEN2 5SPIPCKEN1 1TIM2PCKEN1 5

ReservedPCKEN2 0ReservedPCKEN2 4I2CPCKEN1 0TIM4PCKEN1 4

clock

BitPeripheral

clock

BitPeripheral

clock

BitPeripheral

Power management4.6

For efficent power management, the application can be put in one of four different low-power modes. You can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources.

Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The

•

wakeup is performed by an internal or external interrupt or reset.

Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are

•

stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.

Active halt mode with regulator off: This mode is the same as active halt with regulator

•

on, except that the main voltage regulator is powered off, so the wake up time is slower.

Halt mode: In this mode the microcontroller uses the least power. The CPU and peripheral

•

clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset.

DocID14771 Rev 1214/124

Product overviewSTM8S105xx

Watchdog timers4.7

The watchdog system is based on two independent timers providing maximum security to the applications.

Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset.

Window watchdog timer

The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence.

The window function can be used to trim the watchdog behavior to match the application perfectly.

The application software must refresh the counter before time-out and during a limited time window.

A reset is generated in two situations:

1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to 64 ms.

2. Refresh out of window: The downcounter is refreshed before its value is lower than the one stored in the window register.

Independent watchdog timer

The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures.

It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case of a CPU clock failure

The IWDG time base spans from 60 µs to 1 s.

Auto wakeup counter4.8

Used for auto wakeup from active halt mode

•

Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock

•

LSI clock can be internally connected to TIM3 input capture channel 1 for calibration

•

Beeper4.9

The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz.

The beeper output port is only available through the alternate function remap option bit AFR7.

15/124DocID14771 Rev 12

STM8S105xxProduct overview

TIM1 - 16-bit advanced control timer4.10

This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver

16-bit up, down and up/down autoreload counter with 16-bit prescaler

•

Four independent capture/compare channels (CAPCOM) configurable as input capture,

•

output compare, PWM generation (edge and center aligned mode) and single pulse mode output

Synchronization module to control the timer with external signals

•

Break input to force the timer outputs into a defined state

•

Three complementary outputs with adjustable dead time

•

Encoder mode

•

Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break

•

TIM2, TIM3 - 16-bit general purpose timers4.11

16-bit autoreload (AR) up-counter

•

15-bit prescaler adjustable to fixed power of 2 ratios 1…32768

•

Timers with 3 or 2 individually configurable capture/compare channels

•

PWM mode

•

Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update

•

Timer

size (bits)

16TIM1

16TIM2

16TIM3

TIM4 - 8-bit basic timer4.12

8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128

•

Clock source: CPU clock

•

Interrupt source: 1 x overflow/update

•

Table 4: TIM timer features

PrescalerCounter

Any integer from 1 to 65536

1 to 32768

Counting mode

down

CAPCOM channels

Complem. outputs

Ext. trigger

No03UpAny power of 2 from

No02UpAny power of 2 from

Timer synchronization/ chaining

NoYes34Up/

DocID14771 Rev 1216/124

Product overviewSTM8S105xx

Timer

Timer synchronization/ chaining

size (bits)

8TIM4

PrescalerCounter

1 to 128

Counting mode

CAPCOM channels

Complem. outputs

Ext. trigger

No00UpAny power of 2 from

Analog-to-digital converter (ADC1)4.13

The STM8S105xx products contain a 10-bit successive approximation A/D converter (ADC1) with up to 10 multiplexed input channels and the following main features:

Input voltage range: 0 to V

•

Conversion time: 14 clock cycles

•

Single and continuous and buffered continuous conversion modes

•

Buffer size (n x 10 bits) where n = number of input channels

•

Scan mode for single and continuous conversion of a sequence of channels

•

Analog watchdog capability with programmable upper and lower thresholds

•

Analog watchdog interrupt

•

External trigger input

•

Trigger from TIM1 TRGO

•

End of conversion (EOC) interrupt

•

DDA

Note: Additional AIN12 analog input is not selectable in ADC scan mode or with analog watchdog. Values converted from AIN12 are stored only into the ADC_DRH/ADC_DRL registers.

Communication interfaces4.14

The following communication interfaces are implemented:

UART2: Full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA

•

mode, LIN2.1 master/slave capability

SPI : Full and half-duplex, 8 Mbit/s

•

I²C: Up to 400 Kbit/s

•

UART24.14.1

Main features

One Mbit/s full duplex SCI

•

SPI emulation

•

High precision baud rate generator

•

Smartcard emulation

•

IrDA SIR encoder decoder

•

17/124DocID14771 Rev 12

LIN master mode

•

LIN slave mode

•

Asynchronous communication (UART mode)

Full duplex communication - NRZ standard format (mark/space)

•

Programmable transmit and receive baud rates up to 1 Mbit/s (f

•

following any standard baud rate regardless of the input frequency

Separate enable bits for transmitter and receiver

•

Two receiver wakeup modes:

•

Address bit (MSB)

Idle line (interrupt)

Transmission error detection with interrupt generation

•

Parity control

•

Synchronous communication

Full duplex synchronous transfers

•

SPI master operation

•

8-bit data communication

•

Maximum speed: 1 Mbit/s at 16 MHz (f

•

CPU

/16)

STM8S105xxProduct overview

/16) and capable of

CPU

LIN master mode

Emission: Generates 13-bit synch break frame

•

Reception: Detects 11-bit break frame

•

LIN slave mode

Autonomous header handling - one single interrupt per valid message header

•

Automatic baud rate synchronization - maximum tolerated initial clock deviation ±15 %

•

Synch delimiter checking

•

11-bit LIN synch break detection - break detection always active

•

Parity check on the LIN identifier field

•

LIN error management

•

Hot plugging support

•

SPI4.14.2

Maximum speed: 8 Mbit/s (f

•

Full duplex synchronous transfers

•

Simplex synchronous transfers on two lines with a possible bidirectional data line

•

Master or slave operation - selectable by hardware or software

•

CRC calculation

•

1 byte Tx and Rx buffer

•

Slave/master selection input pin

•

MASTER

/2) both for master and slave

DocID14771 Rev 1218/124

I²C4.14.3

I²C master features:

•

Clock generation

Start and stop generation

I²C slave features:

•

Programmable I2C address detection

Stop bit detection

Generation and detection of 7-bit/10-bit addressing and general call

•

Supports different communication speeds:

•

Standard speed (up to 100 kHz)

Fast speed (up to 400 kHz)

Product overviewSTM8S105xx

19/124DocID14771 Rev 12

STM8S105xxPinout and pin description

Pinout and pin description5

Table 5: Legend/abbreviations for pinout tables

I= Input, O = Output, S = Power supplyType

Output speed

configuration

Reset state

InputLevel

O1 = Slow (up to 2 MHz)

O2 = Fast (up to 10 MHz)

O3 = Fast/slow programmability with slow as default state after reset

O4 = Fast/slow programmability with fast as default state after reset

Output

Bold X (pin state after internal reset release).

Unless otherwise specified, the pin state is the same during the reset phase and after the internal reset release.

CM = CMOS

HS = High sinkOutput

float = floating, wpu = weak pull-upInputPort and control

T = True open drain, OD = Open drain, PP = Push pull

DocID14771 Rev 1220/124

44 43 42 41 40 39 38 37

36 35 34 33 32 31 30 29 28 27 26 25

13 14 15 16 17 18

19 20 21 22

1 2 3 4 5 6 7 8 9 10 11

48 47 46 45

(HS) PA6

AIN8/PE7

PC1 (HS)/TIM1_CH1/UART2_CK PE5/SPI_NSS

PG1

AIN9/PE6

PD3 (HS)/TIM2_CH2 [ADC_ETR]

PD2 (HS)/TIM3_CH1 [TIM2_CH3]

PE0 (HS)/CLK_CCO

PE1 (T)/I2C_SCL

PE2 (T)/I2C_SDAA

PE3/TIM1_BKIN

PD7/TLI [TIM1_CH4]

PD6/UART2_RX

PD5/UART2_TX

PD4 (HS)/TIM2_CH1 [BEEP]

PD1 (HS)/SWIM

PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO]

VSSIO_2 PC5 (HS)/SPI_SCK PC4 (HS)/TIM1_CH4 PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2

PG0 PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI VDDIO_2

AIN7/PB7

AIN6/PB6

[I2C_SDA] AIN5/PB5

[TIM1_ETR] AIN3/PB3

[TIM1_CH3N] AIN2/PB2

[TIM1_CH2N] AIN1/PB1

[TIM1_CH1N] AIN0/PB0

VDDA

VSSA

VSS

VCAP

VDD

VDDIO_1

[TIM3_CH1] TIM2_CH3/PA3

(HS) PA4

(HS) PA5

NRST

OSCIN/PA1

OSCOUT/PA2

VSSIO_1

[I2C_SCL] AIN4/PB4

Pinout and pin descriptionSTM8S105xx

STM8S105 pinouts and pin description5.1

Figure 3: LQFP 48-pin pinout

1. (HS) high sink capability.

2. (T) True open drain (P-buffer and protection diode to VDDnot implemented).

3. [ ] alternate function remapping option (If the same alternate function is shown twice, it

indicates an exclusive choice not a duplication of the function).

21/124DocID14771 Rev 12

Figure 4: LQFP 44-pin pinout

AIN6/PB6

[I2C_SDA] AIN5/PB5

[TIM1_ETR] AIN3/PB3

[TIM1_CH3N] AIN2/PB2

[TIM1_CH2N] AIN1/PB1

[TIM1_CH1N] AIN0/PB0

AIN9/PE6

VDDA

VSSA

AIN7/PB7

44 43 42 41 40 39 38 37 36 35 34

33 32 31 30 29 28 27 26 25 24 23

12 13 14 15 16 17 18

19 20 21 22

1 2 3 4 5 6 7 8 9 10 11

VSS

VCAP

VDD VDDIO_1 (HS) PA4 (HS) PA5 (HS) PA6

NRST

OSCIN/PA1

OSCOUT/PA2

VSSIO_1

VDDIO_2 VSSIO_2 PC5 (HS)/SPI_SCK PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2 PC1 (HS)/TIM1_CH1 PE5/SPI_NSS/UART2_CK

PG1 PG0 PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI

PD3 (HS)/TIM2_CH2 [ADC_ETR]

PD2 (HS)/TIM3_CH1 [TIM2_CH3]

PD1 (HS)/SWIM

PE1 (T)/I2C_SCL

PE2 (T)/I2C_SDA

PD7/TLI [TIM1_CH4]

PD6/UART2_RX

PD5/UART2_TX

PD4 (HS)/TIM2_CH1 [BEEP]

PE0 (HS)/CLK_CCO

PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO]

[I2C_SCL] AIN4/PB4

STM8S105xxPinout and pin description

1. (HS) high sink capability.

2. (T) True open drain (P-buffer and protection diode to VDDnot implemented).

3. [ ] alternate function remapping option (If the same alternate function is shown twice, it

indicates an exclusive choice not a duplication of the function).

DocID14771 Rev 1222/124

[TIM1_ETR] AIN3/PB3

[TIM1_CH3N] AIN2/PB2

[TIM1_CH2N] AIN1/PB1

[TIM1_CH1N] AIN0/PB0

VDDA

VSSA

32 31 30 29 28 27 26 25

24 23 22 21 20 19 18 17

9 10 11 12 13 14 15

1 2 3 4 5 6 7 8

VCAP

VDD

VDDIO

AIN12/PF4

NRST

OSCIN/PA1

OSCOUT/PA2

VSS

PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2 PC1 (HS)/TIM1_CH1/UART2_CK PE5/SPI_NSS

PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI PC5 (HS)/SPI_SCK PC4 (HS)/TIM1_CH4

PD3 (HS)/TIM2_CH2 [ADC_ETR]

PD2 (HS)/TIM3_CH1 [TIM2_CH3]

PD1 (HS)/SWIM

PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO]

PD7/TLI [TIM1_CH4]

PD6/UART2_RX

PD5/UART2_TX

PD4 (HS)/TIM2_CH1 [BEEP]

[I2C_SDA] AIN5/PB5

[I2C_SCL] AIN4/PB4

Pinout and pin descriptionSTM8S105xx

Figure 5: LQFP/UFQFPN 32-pin pinout

1. (HS) high sink capability.

2. [ ] alternate function remapping option (If the same alternate function is shown twice, it

indicates an exclusive choice not a duplication of the function).

23/124DocID14771 Rev 12

1 2 3 4 5 6 7

9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

ADC_ETR/TIM2_CH2/(HS) PD3

[BEEP] TIM2_CH1/(HS) PD4

UART2_TX/PD5

UART2_RX/PD6

[TIM1_CH4] TLI/PD7

NRST

OSCIN/PA1

OSCOUT/PA2

VSS

VCAP

VDD

AIN12/PF4

[I2C_SDA] AIN5/PB5 PB4/AIN4[ I2C_SCL]

PB3/AIN3 [TIM1_ETR]

PB2/AIN2 [TIM1_CH3N]

PB1/AIN1 [TIM1_CH2N]

PB0/AIN0 [TIM1_CH1N]

PE5/SPI_NSS

PC1 (HS)/TIM1_CH1/UART2_CK

PC2 (HS)/TIM1_CH2

PC3 (HS)/TIM1_CH3

PC4 (HS)/TIM1_CH4

PC5 (HS)/SPI_SCK

PC6 (HS)/SPI_MOSI

PC7 (HS)/SPI_MISO

PD0 (HS)/TIM3_CH2 [TIM1_BKIN][CLK_CCO]

PD1 (HS)/SWIM

PD2 (HS)/TIM3_CH1 [TIM2_CH3]

105_ai15057

VDDIO

VDDA

VSSA

STM8S105xxPinout and pin description

Figure 6: SDIP 32-pin pinout

1. (HS) high sink capability.

2. (T) True open drain (P-buffer and protection diode to VDDnot implemented).

3. [ ] alternate function remapping option (If the same alternate function is shown twice, it

indicates an exclusive choice not a duplication of the function).

LQFP44LQFP48

UFQFPN32

Table 6: Pin description for STM8S105 microcontrollers

PPODSpeedHigh

Main function (after reset)

ResetXI/ONRST6111

I/O groundSV

Digital groundSV

1.8 V regulator capacitorSVCAP10566

Digital power supplySV

I/O power supplySV

7222

OSC IN

8333

OSC OUT

--44

SSIO_1

9455

11677

12788

DDIO_1

OutputInputTypePin namePin number

Ext.

wpufloatingSDIP32LQFP32/

interrupt

sink

DocID14771 Rev 1224/124

Default alternate function

Resonator/Port A1XXO1XXI/OPA1/

crystal in

Resonator/Port A2XXO1XXXI/OPA2/

crystal out

Alternate function after remap [option bit]

Pinout and pin descriptionSTM8S105xx

Default alternate function

Timer 2 -

channel 3

Analog input 12

(2)

Analog input 7Port B7XXO1XXXI/OPB7/

Analog input 6Port B6XXO1XXXI/OPB6/

PPODSpeedHigh

Main function (after reset)

Port A3XXO1XXXI/OPA3/

Port A4XXO3HSXXXI/OPA4--910

Port A5XXO3HSXXXI/OPA5--1011

Port A6XXO3HSXXXI/OPA6--1112

Port F4XXO1XXI/OPF4/

Analog power supplySV

Analog groundSV

OutputInputTypePin namePin number

Ext.

LQFP44LQFP48

UFQFPN32

---9 TIM2 _CH3 [TIM3 _CH1]

138--

AIN12

(1)

1491213

DDA

15101314

SSA

--1415 AIN7

--1516 AIN6

wpufloatingSDIP32LQFP32/

interrupt

sink

Alternate function after remap [option bit]

TIM3_ CH1 [AFR1]

16111617

AIN5 [I2C_ SDA]

17121718

AIN4 [I2C_ SCL]

18131819

AIN3 [TIM1_ ETR]

19141920

AIN2 [TIM1_ CH3N]

20152021

AIN1 [TIM1_ CH2N]

21162122

AIN0 [TIM1_ CH1N]

---23 AIN8

Analog input 5Port B5XXO1XXXI/OPB5/

Analog input 4Port B4XXO1XXXI/OPB4/

Analog input 3Port B3XXO1XXXI/OPB3/

Analog input 2Port B2XXO1XXXI/OPB2/

Analog input 1Port B1XXO1XXXI/OPB1/

Analog input 0Port B0XXO1XXXI/OPB0/

Analog input 8Port E7XXO1XXXI/OPE7/

I2C_SDA [AFR6]

I2C_SCL [AFR6]

TIM1_ ETR [AFR5]

TIM1_ CH3N [AFR5]

TIM1_ CH2N [AFR5]

TIM1_ CH1N [AFR5]

25/124DocID14771 Rev 12

STM8S105xxPinout and pin description

(3)

Alternate function after remap [option bit]

Default alternate function

Analog input 9

SPI master/slave select

Timer 1 -Port C1XXO3HSXXXI/OPC1/

channel 1/ UART2 synchronous clock

Timer 1-Port C2XXO3HSXXXI/OPC2/

channel 2

Timer 1 -Port C3XXO3HSXXXI/OPC3/

channel 3

Timer 1 -Port C4XXO3HSXXXI/OPC4/

channel 4

SPI clockPort C5XXO3HSXXXI/OPC5/

PPODSpeedHigh

Main function (after reset)

Port E6XXO1XXXI/OPE6/

Port E5XXO1XXXI/OPE5/SPI_

OutputInputTypePin namePin number

Ext.

LQFP44LQFP48

UFQFPN32

--2224 AIN9

22172325

NSS

23182426

TIM1_ CH1/ UART2_CK

24192527

TIM1_ CH2

25202628

TIM1_ CH3

2621-29

TIM1_ CH4

27222730

SPI_ SCK

wpufloatingSDIP32LQFP32/

interrupt

sink

--2831

SSIO_2

--2932

DDIO_2

28233033

SPI_ MOSI

29243134

SPI_ MISO

---37 TIM1_ BKIN

(4)

--3438 I2C_ SDA

--3539 I2C_ SCL

--3640 CLK_ CCO

O1XXI/OPE2/

(4)

O1XXI/OPE1/

I/O groundSV

I/O power supplySV

Port C6XXO3HSXXXI/OPC6/

Port C7XXO3HSXXXI/OPC7/

Port G0XXO1XXI/OPG0--3235

Port G1XXO1XXI/OPG1--3336

Port E3XXO1XXXI/OPE3/

Port E0XXO3HSXXXI/OPE0/

SPI master out/slave in

SPI master in/ slave out

Timer 1 - break input

I2C dataPort E2

I2C clockPort E1

Configurable clock output

DocID14771 Rev 1226/124

Pinout and pin descriptionSTM8S105xx

Default alternate function

Timer 3 -

channel 2

SWIM data interface

Timer 3 -

channel 1

Timer 2 -

channel 2

Timer 2 -

channel 1

PPODSpeedHigh

Main function (after reset)

Port D0XXO3HSXXXI/OPD0/

Port D1XXO4HSXXXI/OPD1/

Port D2XXO3HSXXXI/OPD2/

Port D3XXO3HSXXXI/OPD3/

Port D4XXO3HSXXXI/OPD4/

OutputInputTypePin namePin number

Ext.

LQFP44LQFP48

UFQFPN32

30253741

TIM3_ CH2 [TIM1_ BKIN] [CLK_ CCO]

31263842

32273943

1284044

2294145

SWIM

TIM3_ CH1 [TIM2_ CH3]

TIM2_ CH2 [ADC_ ETR]

TIM2_ CH1 [BEEP]

(5)

wpufloatingSDIP32LQFP32/

interrupt

sink

Alternate function after remap [option bit]

TIM1_ BKIN [AFR3]/ CLK_ CCO [AFR2]

TIM2_CH3 [AFR1]

ADC_ ETR [AFR0]

BEEP output [AFR7]

3304246

UART2_ TX

4314347

UART2_ RX

5324448

[TIM1_ CH4]

(1)

A pull-up is applied to PF4 during the reset phase. This pin is input floating after reset release.

(2)

AIN12 is not selectable in ADC scan mode or with analog watchdog.

(3)

In 44-pin package, AIN9 cannot be used by ADC scan mode.

(4)

In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to VDDare not implemented).

(5)

The PD1 pin is in input pull-up during the reset phase and after internal reset release.

Port D5XXO1XXXI/OPD5/

Port D6XXO1XXXI/OPD6/

Alternate function remapping5.1.1

As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. When the remapping option is active, the default alternate function is no longer available.

To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers.

UART2 data transmit

UART2 data receive

Top level interruptPort D7XXO1XXXI/OPD7/TLI

TIM1_ CH4 [AFR4]

27/124DocID14771 Rev 12

STM8S105xxPinout and pin description

Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO section of the family reference manual, RM0016).

DocID14771 Rev 1228/124

0x00 FFFF

Flash program memory

(16to 32 Kbytes)

0x00 8000

Reserved

0x01 0000

0x02 7FFF

0x00 0000

RAM

0x00 07FF

(2 Kbytes)

0x00 4000

0x00 43FF

1 Kbyte data EEPROM

Reserved

0x00 4400

0x00 47FF

32 interrupt vectors

0x00 807F

GPIO and periph. reg.

0x00 5000

0x00 57FF

0x00 5800

0x00 7FFF

0x00 4900

0x00 4FFF

2 Kbytes boot ROM

0x00 6000

0x00 67FF

0x00 6800

0x00 7EFF

CPU/SWIM/debug/ITC

registers

0x00 7F00

0x00 5FFF

Reserved

Option bytes

0x00 4800

0x00 487F

512 bytes stack

Memory and register mapSTM8S105xx

Memory and register map6

Memory map6.1

Figure 7: Memory map

The following table lists the boundary addresses for each memory size. The top of the stack is at the RAM end address in each case.

29/124DocID14771 Rev 12

STM8S105xxMemory and register map

Table 7: Flash, Data EEPROM and RAM boundary addresses

End addressStart addressSize (bytes)Memory area

0x00 FFFF0x00 800032KFlash program memory

0x00 BFFF0x00 800016K

0x00 07FF0x00 00002KRAM

0x00 43FF0x00 40001024Data EEPROM

Register map6.2

I/O port hardware register map6.2.1

Table 8: I/O port hardware register map

Reset status

0x00Port A data output latch registerPA_ODRPort A0x00 5000

0xXXPort A input pin value registerPA_IDR0x00 5001

0x00Port A data direction registerPA_DDR0x00 5002

0x00Port A control register 1PA_CR10x00 5003

0x00Port A control register 2PA_CR20x00 5004

0x00Port B data output latch registerPB_ODRPort B0x00 5005

0xXXPort B input pin value registerPB_IDR0x00 5006

0x00Port B data direction registerPB_DDR0x00 5007

0x00Port B control register 1PB_CR10x00 5008

0x00Port B control register 2PB_CR20x00 5009

DocID14771 Rev 1230/124

Memory and register mapSTM8S105xx

Reset status

0x00Port C data output latch registerPC_ODRPort C0x00 500A

0xXXPort C input pin value registerPC_IDR0x00 500B

0x00Port C data direction registerPC_DDR0x00 500C

0x00Port C control register 1PC_CR10x00 500D

0x00Port C control register 2PC_CR20x00 500E

0x00Port D data output latch registerPD_ODRPort D0x00 500F

0xXXPort D input pin value registerPD_IDR0x00 5010

0x00Port D data direction registerPD_DDR0x00 5011

0x02Port D control register 1PD_CR10x00 5012

0x00Port D control register 2PD_CR20x00 5013

0x00Port E data output latch registerPE_ODRPort E0x00 5014

0xXXPort E input pin value registerPE_IDR0x00 5015

0x00Port E data direction registerPE_DDR0x00 5016

0x00Port E control register 1PE_CR10x00 5017

0x00Port E control register 2PE_CR20x00 5018

0x00Port F data output latch registerPF_ODRPort F0x00 5019

0xXXPort F input pin value registerPF_IDR0x00 501A

0x00Port F data direction registerPF_DDR0x00 501B

0x00Port F control register 1PF_CR10x00 501C

31/124DocID14771 Rev 12

STM8S105xxMemory and register map

Reset status

0x00Port F control register 2PF_CR20x00 501D

0x00Port G data output latch registerPG_ODRPort G0x00 501E

0xXXPort G input pin value registerPG_IDR0x00 501F

0x00Port G data direction registerPG_DDR0x00 5020

0x00Port G control register 1PG_CR10x00 5021

0x00Port G control register 2PG_CR20x00 5022

0x00Port H data output latch registerPH_ODRPort H0x00 5023

0xXXPort H input pin value registerPH_IDR0x00 5024

0x00Port H data direction registerPH_DDR0x00 5025

0x00Port H control register 1PH_CR10x00 5026

0x00Port H control register 2PH_CR20x00 5027

0x00Port I data output latch registerPI_ODRPort I0x00 5028

0xXXPort I input pin value registerPI_IDR0x00 5029

0x00Port I data direction registerPI_DDR0x00 502A

0x00Port I control register 1PI_CR10x00 502B

0x00Port I control register 2PI_CR20x00 502C

DocID14771 Rev 1232/124

General hardware register map6.2.2

0x00 5059

Memory and register mapSTM8S105xx

Table 9: General hardware register map

Reset statusRegister nameRegister labelBlockAddress

Reserved area (10 bytes)0x00 5050 to

0x00 5061

Flash0x00 505A

FLASH_NCR20x00 505C

FLASH _NFPR0x00 505E

protection register

FLASH _IAPSR0x00 505F

programming status register

Reserved area (2 bytes)0x00 5060 to

FLASH _PUKRFlash0x00 5062

unprotection register

0x00Flash control register 1FLASH_CR1

0x00Flash control register 2FLASH_CR20x00 505B

0xFFFlash complementary control

0x00Flash protection registerFLASH _FPR0x00 505D

0xFFFlash complementary

0x00Flash in-application

0x00Flash program memory

0x00 509F

Reserved area (1 byte)0x00 5063

FLASH _DUKRFlash0x00 5064

Reserved area (59 bytes)0x00 5065 to

EXTI_CR1ITC0x00 50A0

EXTI_CR20x00 50A1

0x00Data EEPROM unprotection

0x00External interrupt control

33/124DocID14771 Rev 12

0x00 50B2

0x00 50BF

STM8S105xxMemory and register map

Reset statusRegister nameRegister labelBlockAddress

Reserved area (17 bytes)0x00 50A2 to

(1)

Reset status registerRST_SRRST0x00 50B3

0xXX

Reserved area (12 bytes)0x00 50B4 to

0x01Internal clock control registerCLK_ICKRCLK0x00 50C0

0x00External clock control registerCLK_ECKR0x00 50C1

Reserved area (1 byte)0x00 50C2

0xE1Clock master status registerCLK_CMSRCLK0x00 50C3

0xE1Clock master switch registerCLK_SWR0x00 50C4

0xXXClock switch control registerCLK_SWCR0x00 50C5

0x18Clock divider registerCLK_CKDIVR0x00 50C6

CLK_PCKENR10x00 50C7

0xFFPeripheral clock gating register

0x00Clock security system registerCLK_CSSR0x00 50C8

CLK_CCOR0x00 50C9

0x00Configurable clock control

CLK_PCKENR20x00 50CA

0xFFPeripheral clock gating register

0x00CAN clock control registerCLK_CANCCR0x00 50CB

CLK_HSITRIMR0x00 50CC

0x00HSI clock calibration trimming

SWIM clock control registerCLK_SWIMCCR0x00 50CD

0bXXXX XXX0

DocID14771 Rev 1234/124

0x00 50D0

0x00 50DF

Memory and register mapSTM8S105xx

Reset statusRegister nameRegister labelBlockAddress

Reserved area (3 bytes)0x00 50CE to

0x7FWWDG control registerWWDG_CRWWDG0x00 50D1

0x7FWWDR window registerWWDG_WR0x00 50D2

Reserved area (13 bytes)0x00 50D3 to

(2)

IWDG key registerIWDG_KRIWDG0x00 50E0

0xXX

0x00IWDG prescaler registerIWDG_PR0x00 50E1

0xFFIWDG reload registerIWDG_RLR0x00 50E2

0x00 50EF

0x00 50FF

Reserved area (13 bytes)0x00 50E3 to

0x00AWU control/ status register 1AWU_CSR1AWU0x00 50F0

AWU_APR0x00 50F1

0x3FAWU asynchronous prescaler

buffer register

AWU_TBR0x00 50F2

0x00AWU timebase selection

0x1FBEEP control/ status registerBEEP_CSRBEEP0x00 50F3

Reserved area (12 bytes)0x00 50F4 to

0x00SPI control register 1SPI_CR1SPI0x00 5200

0x00SPI control register 2SPI_CR20x00 5201

0x00SPI interrupt control registerSPI_ICR0x00 5202

0x02SPI status registerSPI_SR0x00 5203

35/124DocID14771 Rev 12

0x00 520F

STM8S105xxMemory and register map

Reset statusRegister nameRegister labelBlockAddress

0x00SPI data registerSPI_DR0x00 5204

0x07SPI CRC polynomial registerSPI_CRCPR0x00 5205

0xFFSPI Rx CRC registerSPI_RXCRCR0x00 5206

0xFFSPI Tx CRC registerSPI_TXCRCR0x00 5207

Reserved area (8 bytes)0x00 5208 to

0x00I2C control register 1I2C_CR1I2C0x00 5210

0x00I2C control register 2I2C_CR20x00 5211

0x00I2C frequency registerI2C_FREQR0x00 5212

0x00I2C Own address register lowI2C_OARL0x00 5213

0x00I2C own address register highI2C_OARH0x00 5214

Reserved0x00 5215

0x00I2C data registerI2C_DR0x00 5216

0x00I2C status register 1I2C_SR10x00 5217

0x00I2C status register 2I2C_SR20x00 5218

0x00I2C status register 3I2C_SR30x00 5219

0x00I2C interrupt control registerI2C_ITR0x00 521A

0x00I2C clock control register lowI2C_CCRL0x00 521B

0x00I2C clock control register highI2C_CCRH0x00 521C

0x02I2C TRISE registerI2C_TRISER0x00 521D

DocID14771 Rev 1236/124

Memory and register mapSTM8S105xx

Reset statusRegister nameRegister labelBlockAddress

0x00 522F

0x00 523F

I2C_PECR0x00 521E

0x00I2C packet error checking

Reserved area (17 bytes)0x00 521F to

Reserved area (6 bytes)0x00 5230 to

0xC0UART2 status registerUART2_SRUART20x00 5240

0xXXUART2 data registerUART2_DR0x00 5241

0x00UART2 baud rate register 1UART2_BRR10x00 5242

0x00UART2 baud rate register 2UART2_BRR20x00 5243

0x00UART2 control register 1UART2_CR10x00 5244

0x00UART2 control register 2UART2_CR20x00 5245

0x00 524F

0x00UART2 control register 3UART2_CR30x00 5246

0x00UART2 control register 4UART2_CR40x00 5247

0x00UART2 control register 5UART2_CR50x00 5248

0x00UART2 control register 6UART2_CR60x00 5249

0x00UART2 guard time registerUART2_GTR0x00 524A

0x00UART2 prescaler registerUART2_PSCR0x00 524B

Reserved area (4 bytes)0x00 524C to

0x00TIM1 control register 1TIM1_CR1TIM10x00 5250

0x00TIM1 control register 2TIM1_CR20x00 5251

37/124DocID14771 Rev 12

STM8S105xxMemory and register map

Reset statusRegister nameRegister labelBlockAddress

TIM1_SMCR0x00 5252

0x00TIM1 slave mode control

0x00TIM1 external trigger registerTIM1_ETR0x00 5253

0x00TIM1 interrupt enable registerTIM1_IER0x00 5254

0x00TIM1 status register 1TIM1_SR10x00 5255

0x00TIM1 status register 2TIM1_SR20x00 5256

0x00TIM1 event generation registerTIM1_EGR0x00 5257

TIM1_CCMR10x00 5258

0x00TIM1 capture/ compare mode

TIM1_CCMR20x00 5259

0x00TIM1 capture/compare mode

TIM1_CCMR30x00 525A

0x00TIM1 capture/ compare mode

TIM1_CCMR40x00 525B

0x00TIM1 capture/compare mode

TIM1_CCER10x00 525C

0x00TIM1 capture/ compare enable

TIM1_CCER20x00 525D

0x00TIM1 capture/compare enable

0x00TIM1 counter highTIM1_CNTRH0x00 525E

0x00TIM1 counter lowTIM1_CNTRL0x00 525F

0x00TIM1 prescaler register highTIM1_PSCRH0x00 5260

0x00TIM1 prescaler register lowTIM1_PSCRL0x00 5261

DocID14771 Rev 1238/124

Memory and register mapSTM8S105xx

Reset statusRegister nameRegister labelBlockAddress

0xFFTIM1 auto-reload register highTIM1_ARRH0x00 5262

0xFFTIM1 auto-reload register lowTIM1_ARRL0x00 5263

TIM1_RCR0x00 5264

0x00TIM1 repetition counter

TIM1_CCR1H0x00 5265

0x00TIM1 capture/ compare

TIM1_CCR1L0x00 5266

0x00TIM1 capture/ compare

TIM1_CCR2H0x00 5267

0x00TIM1 capture/ compare

TIM1_CCR2L0x00 5268

0x00TIM1 capture/ compare

TIM1_CCR3H0x00 5269

0x00TIM1 capture/ compare

TIM1_CCR3L0x00 526A

0x00TIM1 capture/ compare

0x00 52FF

TIM1_CCR4H0x00 526B

0x00TIM1 capture/ compare

TIM1_CCR4L0x00 526C

0x00TIM1 capture/ compare

0x00TIM1 break registerTIM1_BKR0x00 526D

0x00TIM1 dead-time registerTIM1_DTR0x00 526E

0x00TIM1 output idle state registerTIM1_OISR0x00 526F

Reserved area (147 bytes)0x00 5270 to

0x00TIM2 control register 1TIM2_CR1TIM20x00 5300

39/124DocID14771 Rev 12

STM8S105xxMemory and register map

Reset statusRegister nameRegister labelBlockAddress

0x00TIM2 interrupt enable registerTIM2_IER0x00 5301

0x00TIM2 status register 1TIM2_SR10x00 5302

0x00TIM2 status register 2TIM2_SR20x00 5303

0x00TIM2 event generation registerTIM2_EGR0x00 5304

TIM2_CCMR10x00 5305

0x00TIM2 capture/ compare mode

TIM2_CCMR20x00 5306

0x00TIM2 capture/ compare mode

TIM2_CCMR30x00 5307

0x00TIM2 capture/ compare mode

TIM2_CCER10x00 5308

0x00TIM2 capture/ compare enable

TIM2_CCER20x00 5309

0x00TIM2 capture/ compare enable

0x00TIM2 counter highTIM2_CNTRH0x00 530A

0x00TIM2 counter lowTIM2_CNTRL0x00 530B

0x00TIM2 prescaler registerTIM2_PSCR0x00 530C

0xFFTIM2 auto-reload register highTIM2_ARRH0x00 530D

0xFFTIM2 auto-reload register lowTIM2_ARRL0x00 530E

TIM2_CCR1H0x00 530F

0x00TIM2 capture/ compare

TIM2_CCR1L0x00 5310

0x00TIM2 capture/ compare

DocID14771 Rev 1240/124

Memory and register mapSTM8S105xx

Reset statusRegister nameRegister labelBlockAddress

0x00 531F

TIM2_CCR2H0x00 5311

0x00TIM2 capture/ compare reg. 2

high

TIM2_CCR2L0x00 5312

0x00TIM2 capture/ compare

TIM2_CCR3H0x00 5313

0x00TIM2 capture/ compare

TIM2_CCR3L0x00 5314

0x00TIM2 capture/ compare

Reserved area (11 bytes)0x00 5315 to

0x00TIM3 control register 1TIM3_CR1TIM30x00 5320

0x00TIM3 interrupt enable registerTIM3_IER0x00 5321

0x00TIM3 status register 1TIM3_SR10x00 5322

0x00TIM3 status register 2TIM3_SR20x00 5323

0x00TIM3 event generation registerTIM3_EGR0x00 5324

TIM3_CCMR10x00 5325

0x00TIM3 capture/ compare mode

TIM3_CCMR20x00 5326

0x00TIM3 capture/ compare mode

TIM3_CCER10x00 5327

0x00TIM3 capture/ compare enable

0x00TIM3 counter highTIM3_CNTRH0x00 5328

0x00TIM3 counter lowTIM3_CNTRL0x00 5329

0x00TIM3 prescaler registerTIM3_PSCR0x00 532A

41/124DocID14771 Rev 12

STM8S105xxMemory and register map

Reset statusRegister nameRegister labelBlockAddress

0xFFTIM3 auto-reload register highTIM3_ARRH0x00 532B

0xFFTIM3 auto-reload register lowTIM3_ARRL0x00 532C

0x00 533F

TIM3_CCR1H0x00 532D

0x00TIM3 capture/ compare

TIM3_CCR1L0x00 532E

0x00TIM3 capture/ compare

TIM3_CCR2H0x00 532F

0x00TIM3 capture/ compare

TIM3_CCR2L0x00 5330

0x00TIM3 capture/ compare

Reserved area (15 bytes)0x00 5331 to

0x00TIM4 control register 1TIM4_CR1TIM40x00 5340

0x00TIM4 interrupt enable registerTIM4_IER0x00 5341

0x00TIM4 status registerTIM4_SR0x00 5342

0x00 53DF

0x00 53F3

0x00TIM4 event generation registerTIM4_EGR0x00 5343

0x00TIM4 counterTIM4_CNTR0x00 5344

0x00TIM4 prescaler registerTIM4_PSCR0x00 5345

0xFFTIM4 auto-reload registerTIM4_ARR0x00 5346

Reserved area (153 bytes)0x00 5347 to

0x00ADC data buffer registersADC _DBxRADC10x00 53E0 to

DocID14771 Rev 1242/124

0x00 53FF

Memory and register mapSTM8S105xx

Reset statusRegister nameRegister labelBlockAddress

Reserved area (12 bytes)0x00 53F4 to

0x00ADC control/ status registerADC _CSRADC10x00 5400

0x00ADC configuration register 1ADC_CR10x00 5401

0x00ADC configuration register 2ADC_CR20x00 5402

0x00ADC configuration register 3ADC_CR30x00 5403

0xXXADC data register highADC_DRH0x00 5404

0xXXADC data register lowADC_DRL0x00 5405

ADC_TDRH0x00 5406

0x00ADC Schmitt trigger disable

ADC_TDRL0x00 5407

0x00ADC Schmitt trigger disable

ADC_HTRH0x00 5408

0x03ADC high threshold register

high

ADC_HTRL0x00 5409

0xFFADC high threshold register

low

ADC_LTRH0x00 540A

0x00ADC low threshold register

high

0x00ADC low threshold register lowADC_LTRL0x00 540B

ADC_AWSRH0x00 540C

0x00ADC analog watchdog status

ADC_AWSRL0x00 540D

0x00ADC analog watchdog status

43/124DocID14771 Rev 12

STM8S105xxMemory and register map

Reset statusRegister nameRegister labelBlockAddress

ADC _AWCRH0x00 540E

ADC_AWCRL0x00 540F

Reserved area (1008 bytes)0x00 5410 to

0x00 57FF

(1)

Depends on the previous reset source.

(2)

Write only register.

CPU/SWIM/debug module/interrupt controller registers6.2.3

Table 10: CPU/SWIM/debug module/interrupt controller registers

0x00ADC analog watchdog control

Reset status

0x00 7F00

(1)

0x00AccumulatorACPU

0x00Program counter extendedPCE0x00 7F01

0x00Program counter highPCH0x00 7F02

0x00Program counter lowPCL0x00 7F03

0x00X index register highXH0x00 7F04

0x00X index register lowXL0x00 7F05

0x00Y index register highYH0x00 7F06

0x00Y index register lowYL0x00 7F07

0x07Stack pointer highSPH0x00 7F08

0xFFStack pointer lowSPL0x00 7F09

DocID14771 Rev 1244/124

Memory and register mapSTM8S105xx

0x00 7F5F

Reset status

0x28Condition code registerCCR0x00 7F0A

Reserved area (85 bytes)0x00 7F0B to

0x00Global configuration registerCFG_GCRCPU0x00 7F60

0xFFInterrupt software priority register 1ITC_SPR1ITC0x00 7F70

0xFFInterrupt software priority register 2ITC_SPR20x00 7F71

0xFFInterrupt software priority register 3ITC_SPR30x00 7F72

0xFFInterrupt software priority register 4ITC_SPR40x00 7F73

0xFFInterrupt software priority register 5ITC_SPR50x00 7F74

0x00 7F79

0x00 7F8F

0xFFInterrupt software priority register 6ITC_SPR60x00 7F75

0xFFInterrupt software priority register 7ITC_SPR70x00 7F76

0xFFInterrupt software priority register 8ITC_SPR80x00 7F77

Reserved area (2 bytes)0x00 7F78 to

0x00SWIM control status registerSWIM_CSRSWIM0x00 7F80

Reserved area (15 bytes)0x00 7F81 to

DM_BK1REDM0x00 7F90

0xFFDM breakpoint 1 register extended

byte

0xFFDM breakpoint 1 register high byteDM_BK1RH0x00 7F91

0xFFDM breakpoint 1 register low byteDM_BK1RL0x00 7F92

45/124DocID14771 Rev 12

STM8S105xxMemory and register map

Reset status

DM_BK2RE0x00 7F93

0xFFDM breakpoint 2 register extended

byte

0xFFDM breakpoint 2 register high byteDM_BK2RH0x00 7F94

0xFFDM breakpoint 2 register low byteDM_BK2RL0x00 7F95

0x00DM debug module control register 1DM_CR10x00 7F96

0x00DM debug module control register 2DM_CR20x00 7F97

DM_CSR10x00 7F98

0x10DM debug module control/status

DM_CSR20x00 7F99

0x00DM debug module control/status

Reserved area (5 bytes)0x00 7F9B to

0x00 7F9F

(1)

Accessible by debug module only

0xFFDM enable function registerDM_ENFCTR0x00 7F9A

DocID14771 Rev 1246/124

Interrupt vector mappingSTM8S105xx

Interrupt vector mapping7

Table 11: Interrupt mapping

IRQ no.

block

DescriptionSource

Port A external interruptsEXTI03

Wakeup from halt mode

(1)

Yes

Wakeup from active-halt mode

(1)

Vector address

0x00 8000YesYesResetRESET

0x00 8004--Software interruptTRAP

0x00 8008--External top level interruptTLI0

0x00 800CYes-Auto wake up from haltAWU1

0x00 8010--Clock controllerCLK2

0x00 8014Yes

0x00 8018YesYesPort B external interruptsEXTI14

0x00 801CYesYesPort C external interruptsEXTI25

0x00 8020YesYesPort D external interruptsEXTI36

0x00 8024YesYesPort E external interruptsEXTI47

0x00 80288

0x00 802C--Reserved9

0x00 8030YesYesEnd of transferSPI10

TIM111

underflow/ trigger/ break

0x00 8034--TIM1 update/ overflow/

0x00 8038--TIM1 capture/ compareTIM112

0x00 803C--TIM update/ overflowTIM213

0x00 8040--TIM capture/ compareTIM214

47/124DocID14771 Rev 12

STM8S105xxInterrupt vector mapping

IRQ no.

block

UART221

ADC122

DescriptionSource

FULL

analog watchdog interrupt

Wakeup from halt mode

Wakeup from active-halt mode

Vector address

0x00 8044--Update/ overflowTIM315

0x00 8048--Capture/ compareTIM316

0x00 804C--Reserved17

0x00 8050--Reserved18

0x00 8054YesYesI2C interruptI2C19

0x00 8058--Tx completeUART220

0x00 805C--Receive register DATA

0x00 8060--ADC1 end of conversion/

Reserved

(1)

Except PA1

0x00 8064--TIM update/ overflowTIM423

0x00 8068--EOP/ WR_PG_DISFlash24

0x00 806C to 0x00 807C

DocID14771 Rev 1248/124

Option bytesSTM8S105xx

Option bytes8

Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for redundancy.

Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in the table below.

Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP option that can only be modified in ICP mode (via SWIM).

Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures.

Table 12: Option bytes

Addr.

0x4800

0x4801

0x4803

0x4805h

0x4807

Option name

protection (ROP)

code(UBC)

function remapping (AFR)

option

byte no.

Option bitsOption

01234567

AFR6AFR7OPT2Alternate

ReservedOPT3Miscell.

ReservedNOPT30x4806

TRIM

NHSI TRIM

LSI_ ENHSI

NLSI_ EN

EXT CLKReservedOPT4Clock

IWDG _HW

NIWDG _HW

SEL

WWDG _HW

NWWDG _HW

_HALT

G_HALT

Factory default setting

00hROP [7:0]OPT0Read-out

00hUBC [7:0]OPT1User boot

FFhNUBC [7:0]NOPT10x4802

00hAFR0AFR1AFR2AFR3AFR4AFR5

FFhNAFR0NAFR1NAFR2NAFR3NAFR4NAFR5NAFR6NAFR7NOPT20x4804

00hWWDG

FFhNWW

00hPRS C0PRS C1CKAWU

0x4809

startup

Reserved0x480B

OPT6

ReservedNOPT40x4808

NEXT CLK

WUSEL

NPRSC1NCKA

SC0

FFhNPR

00hHSECNT [7:0]OPT5HSE clock

FFhNHSECNT [7:0]NOPT50x480A

00hReserved

49/124DocID14771 Rev 12

STM8S105xxOption bytes

Addr.

0x480C

0x480E

0x487F

Option name

Reserved0x480D

Bootloader0x487E

byte no.

NOPT6

OPT7

NOPT7

OPTBL

NOPTBL

Option bitsOption

01234567

Factory default setting

FFhReserved

00hReserved

FFhReserved

00hBL[7:0]

FFhNBL[7:0]

Table 13: Option byte description

DescriptionOption byte no.

ROP[7:0] Memory readout protection (ROP)OPT0

AAh: Enable readout protection (write access via SWIM protocol)

Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM memory readout protection for details.

UBC[7:0] User boot code areaOPT1

0x00: no UBC, no write-protection

0x01: Page 0 to 1 defined as UBC, memory write-protected

0x02: Page 0 to 3 defined as UBC, memory write-protected

0x03: Page 0 to 4 defined as UBC, memory write-protected

...

0x3E: Pages 0 to 63 defined as UBC, memory write-protected

Other values: Reserved

Note: Refer to the family reference manual (RM0016) section on Flash write protection for more details.

AFR[7:0]OPT2

Refer to following table for the alternate function remapping decriptions of bits [7:2].

HSITRIM:High speed internal clock trimming register sizeOPT3

0: 3-bit trimming supported in CLK_HSITRIMR register

1: 4-bit trimming supported in CLK_HSITRIMR register

DocID14771 Rev 1250/124

DescriptionOption byte no.

LSI_EN:Low speed internal clock enable

0: LSI clock is not available as CPU clock source

1: LSI clock is available as CPU clock source

IWDG_HW: Independent watchdog

0: IWDG Independent watchdog activated by software

1: IWDG Independent watchdog activated by hardware

WWDG_HW: Window watchdog activation

0: WWDG window watchdog activated by software

1: WWDG window watchdog activated by hardware

WWDG_HALT: Window watchdog reset on halt

0: No reset generated on halt if WWDG active

Option bytesSTM8S105xx

1: Reset generated on halt if WWDG active

EXTCLK: External clock selectionOPT4

0: External crystal connected to OSCIN/OSCOUT

1: External clock signal on OSCIN

CKAWUSEL:Auto wake-up unit/clock

0: LSI clock source selected for AWU

1: HSE clock with prescaler selected as clock source for for AWU

PRSC[1:0] AWU clock prescaler

0x: 16 MHz to 128 kHz prescaler

10: 8 MHz to 128 kHz prescaler

11: 4 MHz to 128 kHz prescaler

HSECNT[7:0]:HSE crystal oscillator stabilization timeOPT5

0x00: 2048 HSE cycles

0xB4: 128 HSE cycles

0xD2: 8 HSE cycles

0xE1: 0.5 HSE cycles

51/124DocID14771 Rev 12

STM8S105xxOption bytes

DescriptionOption byte no.

ReservedOPT6

ReservedOPT7

BL[7:0] Bootloader option byteOPTBL

For STM8S products, this option is checked by the boot ROM code after reset. Depending on the content of addresses 0x487E, 0x487F, and 0x8000 (reset vector), the CPU jumps to the bootloader or to the reset vector. Refer to the UM0560 (STM8L/S bootloader manual) for more details.

For STM8L products, the bootloader option bytes are on addresses 0xXXXX and 0xXXXX+1 (2 bytes). These option bytes control whether the bootloader is active or not. For more details, refer to the UM0560 (STM8L/S bootloader manual) for more details.

Table 14: Description of alternate function remapping bits [7:0] of OPT2

Option byte no.

Description

(1)

AFR7 Alternate function remapping option 7OPT2

0: AFR7 remapping option inactive: Default alternate function

(2)

1: Port D4 alternate function = BEEP.

AFR6 Alternate function remapping option 6

0: AFR6 remapping option inactive: Default alternate functions

(2)

1: Port B5 alternate function = I2C_SDA; port B4 alternate function = I2C_SCL.

AFR5 Alternate function remapping option 5

0: AFR5 remapping option inactive: Default alternate functions

(2)

1: Port B3 alternate function = TIM1_ETR; port B2 alternate function = TIM1_NCC3; port B1 alternate function = TIM1_CH2N; port B0 alternate function = TIM1_CH1N.

AFR4 Alternate function remapping option 4

0: AFR4 remapping option inactive: Default alternate function

(2)

1: Port D7 alternate function = TIM1_CH4.

AFR3 Alternate function remapping option 3

0: AFR3 remapping option inactive: Default alternate function

(2)

1: Port D0 alternate function = TIM1_BKIN.

AFR2 Alternate function remapping option 2

DocID14771 Rev 1252/124

Option bytesSTM8S105xx

Option byte no.

Description

(1)

0: AFR2 remapping option inactive: Default alternate function

1: Port D0 alternate function = CLK_CCO.Note: AFR2 option has priority over AFR3 if both are activated.

AFR1 Alternate function remapping option 1

0: AFR1 remapping option inactive: Default alternate functions

1: Port A3 alternate function = TIM3_CH1; port D2 alternate function TIM2_CH3.

AFR0 Alternate function remapping option 0

0: AFR0 remapping option inactive: Default alternate function

1: Port D3 alternate function = ADC_ETR.

(1)

Do not use more than one remapping option in the same port.

(2)

Refer to pinout description.

(2)

53/124DocID14771 Rev 12

STM8S105xxUnique ID

Unique ID9

The devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user.

The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm.

The unique device identifier is ideally suited:

For use as serial numbers

•

For use as security keys to increase the code security in the program memory while using

•

and combining this unique ID with software cryptograhic primitives and protocols before programming the internal memory.

To activate secure boot processes

•

Table 15: Unique ID registers (96 bits)

Address

0x48CD

0x48CF

0x48D2

description

X co-ordinate

on the wafer

Y co-ordinate

on the wafer

Lot number

Unique ID bitsContent

01234567

U_ID[7:0]

U_ID[15:8]0x48CE

U_ID[23:16]

U_ID[31:24]0x48D0

U_ID[39:32]Wafer number0x48D1

U_ID[47:40]

U_ID[55:48]0x48D3

U_ID[63:56]0x48D4

U_ID[71:64]0x48D5

U_ID[79:72]0x48D6

U_ID[87:80]0x48D7

U_ID[95:88]0x48D8

DocID14771 Rev 1254/124

5 V or 3.3 V

V V

V V V V

DD DDA

DDIO SS

SSA

SSIO

Electrical characteristicsSTM8S105xx

Electrical characteristics10

Parameter conditions10.1

Unless otherwise specified, all voltages are referred to VSS.

Minimum and maximum values10.1.1

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an ambient temperature at TA= 25 °C and TA= T the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ± 3 Σ).

Typical values10.1.2

Unless otherwise specified, typical data are based on TA= 25 °C, VDD= 5 V. They are given only as design guidelines and are not tested.

Amax

(given by

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ± 2 Σ).

Typical curves10.1.3

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

Typical current consumption10.1.4

For typical current consumption measurements, VDD, V in the configuration shown in the following figure.

Figure 8: Supply current measurement conditions

DDIO

and V

are connected together

DDA

55/124DocID14771 Rev 12

STM8 PIN

50 pF

STM8 PIN

STM8S105xxElectrical characteristics

Loading capacitor10.1.5

The loading conditions used for pin parameter measurement are shown in the following figure.

Figure 9: Pin loading conditions

Pin input voltage10.1.6

The input voltage measurement on a pin of the device is described in the following figure.

Figure 10: Pin input voltage

Absolute maximum ratings10.2

Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 16: Voltage characteristics

UnitMaxMinRatingsSymbol

(1)

- V

DDx

PE2)

(2)

DocID14771 Rev 1256/124

DDA andVDDIO

)

6.5VSS- 0.3Input voltage on true open drain pins (PE1,

V6.5-0.3Supply voltage (including V

Electrical characteristicsSTM8S105xx

UnitMaxMinRatingsSymbol

DDx

(2)

VDD+ 0.3VSS- 0.3Input voltage on any other pin

mV50Variations between different power pins|V

VDD|

SSx

ESD

- VSS|

Electrostatic discharge voltageV

see Absolute maximum

50Variations between all the different ground pins|V

ratings (electrical sensitivity)

(1)

All power (VDD, V

DDIO

, V

) and ground (VSS, V

DDA

SSIO

, V

) pins must always be

SSA

connected to the external power supply

(2)

INJ(PIN)

must never be exceeded. This is implicitly insured if VINmaximum is respected. If VINmaximum cannot be respected, the injection current must be limited externally to the I

INJ(PIN)

value. A positive injection is induced by VIN>VDDwhile a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the corresponding VINmaximum must always be respected

Table 17: Current characteristics

(1)

RatingsSymbol

UnitMax.

VDD

VSS

ΣI

(2)

60Total current out of VSSground lines (sink)

mA60Total current into VDDpower lines (source)

20Output current sunk by any I/O and control pinI

20Output current source by any I/Os and control pin

pins) for devices with two V

pins) for devices with one V

pins) for devices with two V

pins) for devices with one V

DDIO

SSIO

pins

(3)

200Total output current sourced (sum of all I/O and control

100Total output current sourced (sum of all I/O and control

160Total output current sunk (sum of all I/O and control

80Total output current sunk (sum of all I/O and control

57/124DocID14771 Rev 12

STM8S105xxElectrical characteristics

(1)

RatingsSymbol

UnitMax.

INJ(PIN)

(4) (5)

±4Injected current on NRST pinI

±4Injected current on OSCIN pin

(6)

ΣI

INJ(PIN)

(1)

(2)

(4)

Data based on characterization results, not tested in production.

All power (VDD, V

DDIO

, V

) and ground (VSS, V

DDA

SSIO

, V

SSA

) pins must always be

(6)

±4Injected current on any other pin

±20Total injected current (sum of all I/O and control pins)

connected to the external supply.

(3)

I/O pins used simultaneously for high current source/sink must be uniformly spaced

around the package between the V

(4)

INJ(PIN)

must never be exceeded. This is implicitly insured if VINmaximum is respected.

DDIO/VSSIO

pins.

If VINmaximum cannot be respected, the injection current must be limited externally to the I

INJ(PIN)

(5)

Negative injection disturbs the analog performance of the device. See note in I2C interface

characteristics.

(6)

When several inputs are submitted to a current injection, the maximum ΣI

INJ(PIN)

is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with ΣI

INJ(PIN)

maximum current injection on four I/O

port pins of the device.

Table 18: Thermal characteristics

UnitValueRatingsSymbol

STG

150Maximum junction temperatureT

°C-65 to 150Storage temperature rangeT

Operating conditions10.3

The device must be used in operating conditions that respect the parameters in the table below. In addition, full account must be taken of all physical capacitor characteristics and tolerances.

DocID14771 Rev 1258/124

Table 19: General operating conditions

Electrical characteristicsSTM8S105xx

UnitMaxMinConditionsParameterSymbol

CPU

VDD/ V

VCAP

(3)

DD_IO

(1)

frequency

voltage

: capacitance of

EXT

external capacitor

ESR of external capacitor

at 1 MHz

(2)

ESL of external capacitor

Power dissipation at TA = 85 °C for suffix

44 and 48-pin devices, with output on eight standard ports, two high6or TA= 125° C for

suffix 3 sink ports and two open

drain ports simultaneously

(4)

MHz160Internal CPU clock

V5.52.95Standard operating

nF3300470C

Ohm0.3

nH15

mW443

32-pin package, with

360

output on eight standard ports and two high sink ports simultaneously

Ambient temperature for 6 suffix version

dissipation

Ambient temperature for 3 suffix version

dissipation

(4)

°C85-40Maximum power

125-40Maximum power

105-406 suffix versionJunction temperature

range

130-403 suffix version

(1)

Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum value must be respected for the full application range.

59/124DocID14771 Rev 12

8 4

2.95

4.0

5.0

5.5

CPU

(MHz)

Functionality guaranteed

@TA-40 to 125 °C

Supply voltage

Functionality not guaranteed in this area

STM8S105xxElectrical characteristics

(2)

This frequency of 1 MHz as a condition for VCAP parameters is given by design of internal regulator.

(3)

To calculate P

Dmax(TA

characteristics ) with the value for T

), use the formula P

given in the current table and the value for Θ

Jmax

Dmax

= (T

- TA)/ΘJA(see Thermal

Jmax

given in Thermal characteristics.

(4)

Refer to Thermal characteristics

VDD

Figure 11: f

CPUmax

versus V

Table 20: Operating conditions at power-up/power-down

VDDrise time ratet

VDDfall time rate

(1)

UnitMaxTypMinConditionsParameterSymbol

µs/V∞2.0

∞2.0

TEMP

IT+

VDDrisingReset releasedelayt

threshold

IT-

threshold

HYS(BOR)

hysteresis

(1)

Guaranteed by design, not tested in production.

DocID14771 Rev 1260/124

(1)

ms1.7

V2.952.82.65Power-on reset

2.882.72.58Brown-out reset

mV70Brown-out reset

ESR

Leak

ESL

Electrical characteristicsSTM8S105xx

VCAP external capacitor10.3.1

Stabilization for the main regulator is achieved connecting an external capacitor C V

CAP

pin. C

is specified in the Operating conditions section. Care should be taken to limit

EXT

the series inductance to less than 15 nH.

Figure 12: External capacitor C

EXT

1. ESR is the equivalent series resistance and ESL is the equivalent inductance.

Supply current characteristics10.3.2

The current consumption is measured as described in Pin input voltage.

Total current consumption in run mode10.3.2.1

Table 21: Total current consumption with code execution in run mode at VDD= 5 V

to the

DD(RUN)

Supply current in run mode, code

= f

CPU

MASTER

= 16 MHz

(16 MHz)

executed from RAM 3.22.6HSE user ext. clock

(16 MHz)

= f

CPU

125 kHz

MASTER

/128 =

(16 MHz)

(1)

TypConditionsParameterSymbol

UnitMax

mA3.2HSE crystal osc.

3.22.5HSI RC osc.

2.21.6HSE user ext. clock

2.01.3HSI RC osc.

61/124DocID14771 Rev 12

STM8S105xxElectrical characteristics

(1)

TypConditionsParameterSymbol

UnitMax

DD(RUN)

Supply current in run mode, code

= f

CPU

MASTER

15.625 kHz

= f

CPU

= 128 kHz

= f

CPU

= 16 MHz

/128 =

(16 MH3z/8)

MASTER

(128 kHz)

MASTER

(16 MHz)

executed fromFlash 8.07.0HSE user ext. clock

(16 MHz)

= f

CPU

= 2 MHz

CPU

125 kHz

MASTER

= f

MASTER

/128 =

(16 MHz/8)

(16 MHz)

(2)

0.75HSI RC osc.

0.55LSI RC osc.

7.7HSE crystal osc.

8.07.0HSI RC osc.

1.5HSI RC osc.

2.01.35HSI RC osc.

= f

CPU

MASTER

15.625 kHz

= f

CPU

= 128 kHz

(1)

Data based on characterization results, not tested in production.

(2)

Default clock configuration measured with all peripherals off.

/128 =

(16 MHz/8)

MASTER

(128 kHz)

0.75HSI RC osc.

0.6LSI RC osc.

Table 22: Total current consumption with code execution in run mode at VDD= 3.3 V

(1)

UnitMax

mA2.8HSE crystal osc.

DD(RUN)

current in run

CPU

= f

MASTER

DocID14771 Rev 1262/124

TypConditionsParameterSymbol

= 16 MHzSupply

(16 MHz)

Electrical characteristicsSTM8S105xx

(1)

TypConditionsParameterSymbol

UnitMax

mode, code executed from RAM

current in run mode, code executed from Flash

= f

CPU

MASTER

= 125 kHz

= f

CPU

MASTER

15.625 kHz

= f

CPU

= f

MASTER

/128

/128 =

= 128 kHz

= 16 MHzSupply

3.22.6HSE user ext. clock

(16 MHz)

3.22.5HSI RC osc.

(16 MHz)

2.21.6HSE user ext. clock

(16 MHz)

2.01.3HSI RC osc.

(16 MHz)

0.75HSI RC osc. (16 MHz/8)f

0.55LSI RC osc.

(128 kHz)

7.3HSE crystal osc.

(16 MHz)

8.07.0HSE user ext. clock

(16 MHz)

8.07.0HSI RC osc.

= f

CPU

= f

MASTER

= 125 kHz

= f

CPU

MASTER

15.625 kHz

= 2 MHz

/128

/128 =

(16 MHz)

(16 MHz/8)

(16 MHz)

(16 MHz/8)

1.5HSI RC osc.

(2)

2.01.35HSI RC osc.

0.75HSI RC osc.

63/124DocID14771 Rev 12

STM8S105xxElectrical characteristics

(1)

TypConditionsParameterSymbol

UnitMax

CPU

= f

MASTER

= 128 kHz

(128 kHz)

(1)

Data based on characterization results, not tested in production.

(2)

Default clock configuration measured with all peripherals off.

Total current consumption in wait mode10.3.2.2

Table 23: Total current consumption in wait mode at VDD= 5 V

DD(WFI)

Supply current in wait mode

CPU

MHz

= f

MASTER

= 16

(16 MHz)

0.6LSI RC osc.

(1)

TypConditionsParameterSymbol

UnitMax

mA2.15HSE crystal osc.

2.01.55HSE user ext. clock

1.91.5HSI RC osc.

(16 MHz)

= f

CPU

MASTER

= 125 kHz

= f

CPU

MASTER

= 15.625 kHz

= f

CPU

MASTER

kHz

(1)

Data based on characterization results, not tested in production.

(2)

Default clock configuration measured with all peripherals off.

/128

= 128

(16 MHz)

(16 MHz/8)

(128 kHz)

(2)

1.3HSI RC osc.

0.7HSI RC osc.

0.5LSI RC osc.

DocID14771 Rev 1264/124

Electrical characteristicsSTM8S105xx

Table 24: Total current consumption in wait mode at VDD= 3.3 V

TypConditionsParameterSymbol

(1)

UnitMax

DD(WFI)

Supply current in wait mode

CPU

MHz

= f

MASTER

= 16

(16 MHz)

= f

CPU

MASTER

= 125 kHz

= f

CPU

MASTER

= 15.625 kHz

= f

CPU

MASTER

128 kHz

(1)

Data based on characterization results, not tested in production.

(2)

Default clock configuration measured with all peripherals off.

/128

(16 MHz)

(16 MHz/8)

(128 kHz)

(2)

mA1.75HSE crystal osc.

2.01.55HSE user ext. clock

1.91.5HSI RC osc.

1.3HSI RC osc.

0.7HSI RC osc.

0.5LSI RC osc.

Total current consumption in active halt mode10.3.2.3

DD(AH)

Table 25: Total current consumption in active halt mode at VDD= 5 V

Max at 85

(1)

°C

125 °C

Main

(3)

TypConditionsParameterSymbol

Clock sourceFlash mode voltage regulator

(2)

(MVR)

OnSupply current in active halt mode

Operating mode

osc.

(16 MHz)

400320200LSI RC osc.

UnitMax at

(1)

µA1080HSE crystal

65/124DocID14771 Rev 12

STM8S105xxElectrical characteristics

Main voltage regulator

(2)

(MVR)

Off

Power-down mode

Operating mode

mode

(3)

Clock sourceFlash mode

(128 kHz)

osc.

(16 MHz)

(128 kHz)

TypConditionsParameterSymbol

Max at 85

(1)

°C

125 °C

UnitMax at

(1)

1030HSE crystal

350270140LSI RC osc.

22012068LSI RC osc.

1506012Power-down

(1)

Data based on characterization results, not tested in production

(2)

Configured by the REGAH bit in the CLK_ICKR register.

(3)

Configured by the AHALT bit in the FLASH_CR1 register.

Table 26: Total current consumption in active halt mode at VDD= 3.3 V

Clock sourceFlash

osc.

(16 MHz)

DD(AH)

current in active halt mode

Main voltage regulator

(2)

(MVR)

OnSupply

(3)

mode

Operating mode

(128 kHz)

Max

TypConditionsParameterSymbol

(1)

125 °C

at 85 °C

UnitMax at

(1)

µA680HSE crystal

400320200LSI RC osc.

DocID14771 Rev 1266/124

Electrical characteristicsSTM8S105xx

Main voltage regulator

(2)

(MVR)

mode

(3)

Clock sourceFlash

Power-down mode

osc.

(16 MHz)

(128 kHz)

Off

Operating mode

(128 kHz)

mode

(1)

Data based on characterization results, not tested in production.

(2)

Configured by the REGAH bit in the CLK_ICKR register.

(3)

Configured by the AHALT bit in the FLASH_CR1 register.

Max

TypConditionsParameterSymbol

(1)

125 °C

at 85 °C

UnitMax at

(1)

630HSE crystal

350270140LSI RC osc.

22012066LSI RC osc.

1506010Power-down

Total current consumption in halt mode10.3.2.4

Table 27: Total current consumption in halt mode at VDD= 5 V

DD(H)

(1)

Data based on characterization results, not tested in production.

Supply current in halt mode

clock after wakeup

HSI clock after wakeup

TypConditionsParameterSymbol

Max at 85 °C

(1)

125 °C

UnitMax at

(1)

µA1509062Flash in operating mode, HSI

80256.5Flash in powerdown mode,

67/124DocID14771 Rev 12

STM8S105xxElectrical characteristics

Table 28: Total current consumption in halt mode at VDD= 3.3 V

WU(WFI)

DD(H)

Supply current in halt mode

clock after wakeup

HSI clock after wakeup

(1)

Data based on characterization results, not tested in production.

Low power mode wakeup times10.3.2.5

Table 29: Wakeup times

Wakeup time from

wait mode to run

(3)

0 to 16 MHz

= f

CPU

MASTER

= 16 MHzmode

TypConditionsParameterSymbol

Max at 85 °C

(1)

125 °C

UnitMax at

(1)

µA1509060Flash in operating mode, HSI

80204.5Flash in powerdown mode,

(1)

TypConditionsParameterSymbol

Max

See note

Unit

(2)

0.56f

WU(AH)

WU(H)

Wakeup time active

halt mode to run

(3)

mode

Wakeup time active

halt mode to run

(3)

mode

Wakeup time active

halt mode to run

(3)

mode

Wakeup time active

halt mode to run

(3)

mode

Wakeup time from

halt mode to run

MVR voltage

regulator

(4)

MVR voltage

regulator

(4)

MVR voltage

regulator

(4)

off

MVR voltage

regulator

(4)

off

Flash in operating

(5)

mode

Flash in

power-down

(5)

Flash in operating

(5)

mode

Flash in

power-down

(5)

HSI

(after

wakeup)

HSI

(after

wakeup)mode

HSI

(after

wakeup)

HSI

(after

wakeup)mode

52Flash in operating mode

54Flash in power-down mode

(6)

μs

DocID14771 Rev 1268/124

(3)

mode

(1)

Data guaranteed by design, not tested in production.

(2)

WU(WFI)

(3)

Measured from interrupt event to interrupt vector fetch.

(4)

Configured by the REGAH bit in the CLK_ICKR register.

(5)

Configured by the AHALT bit in the FLASH_CR1 register.

(6)

Plus 1 LSI clock depending on synchronization.

= 2 x 1/f

master

+ 7 x 1/f

CPU.

Total current consumption and timing in forced reset state10.3.2.6

Table 30: Total current consumption and timing in forced reset state

Electrical characteristicsSTM8S105xx

(1)

Unit

UnitMax

TypConditionsParameterSymbol

Max

TypConditionsParameterSymbol

DD(R)

RESETBL

(2)

state

Reset pin release to vector fetch

(1)

Data guaranteed by design, not tested in production.

(2)

Characterized with all I/Os tied to VSS.

Current consumption of on-chip peripherals10.3.2.7

Subject to general operating conditions for VDDand TA.

HSI internal RC/f

DD(TIM1)

DD(TIM2)

CPU

= f

MASTER

= 16 MHz.

Table 31: Peripheral current consumption

(1)

500VDD= 5 VSupply current in reset

μA

400VDD= 3.3 V

μs150

UnitTyp.ParameterSymbol

230TIM1 supply current

µA

115TIM2 supply current

69/124DocID14771 Rev 12

STM8S105xxElectrical characteristics

UnitTyp.ParameterSymbol

DD(TIM3)

DD(TIM4)

DD(UART2)

DD(SPI)

DD(I2C)

DD(ADC1)

(1)

Data based on a differential IDDmeasurement between reset configuration and timer

(2)

(1)

(2)

(3)

90TIM3 timer supply current

30TIM4 timer supply current

110UART2 supply current

45SPI supply current

65I2C supply current

955ADC1 supply current when converting

counter running at 16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production.

(2)

Data based on a differential IDDmeasurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling. Not tested in production.

(3)

Data based on a differential IDDmeasurement between reset configuration and continuous A/D conversions. Not tested in production.

Current consumption curves10.3.2.8

The following figures show typical current consumption measured with code executing in RAM.

Figure 13: Typ. I

DD(RUN)

DocID14771 Rev 1270/124

vs. V

HSE user external clock, f

DD ,

CPU

= 16 MHz

Electrical characteristicsSTM8S105xx

Figure 14: Typ. I

Figure 15: Typ. I

DD(RUN)

vs. f

HSE user external clock, VDD= 5 V

CPU ,

vs. V

HSI RC osc, f

DD ,

CPU

= 16 MHz

71/124DocID14771 Rev 12

STM8S105xxElectrical characteristics

Figure 16: Typ. I

Figure 17: Typ. I

DD(WFI)

vs. V

vs. f

HSE user external clock, f

DD ,

, HSE user external clock VDD= 5 V

CPU

= 16 MHz

DocID14771 Rev 1272/124

Electrical characteristicsSTM8S105xx

Figure 18: Typ. I

DD(WFI)

vs. VDD, HSI RC osc, f

External clock sources and timing characteristics10.3.3

HSE user external clock

Subject to general operating conditions for VDDand TA.

CPU

= 16 MHz

Table 32: HSE user external clock characteristics

HSE_ext

User external clock source frequency

HSEH

(1)

OSCIN input pin high level voltage

HSEL

(1)

OSCIN input pin low level voltage

LEAK_HSE

(1)

Data based on characterization results, not tested in production.

OSCIN input leakage currentI

VSS< VIN< V

UnitMaxMinConditionsParameterSymbol

MHz160

VDD+ 0.3 V0.7 x V

0.3 x V

μA+1-1

73/124DocID14771 Rev 12

HSEH

HSEL

External clock source

OSCIN

HSE

STM8

STM8S105xxElectrical characteristics

Figure 19: HSE external clocksource

HSE crystal/ceramic resonator oscillator

The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...).

HSE

(1)

DD(HSE)

SU(HSE)

External high speed

oscillator frequency

Feedback resistorR

Recommended load

capacitance

HSE oscillator power

consumption

Oscillator

transconductance

(4)

Table 33: HSE oscillator characteristics

(2)

C = 20 pF,

= 16 MHz

OSC

C = 10 pF,

=16 MHz

OSC

VDDis stabilizedStartup timet

6 (startup)

1.6 (stabilized)

6 (startup)

1.2 (stabilized)

UnitMaxTypMinConditionsParameterSymbol

MHz161

kΩ220

pF20

(3)

mA/V5

ms1

(1)

C is approximately equivalent to 2 x crystal Cload.

DocID14771 Rev 1274/124

OSCOUT

OSCIN

HSE

to core

STM8

Resonator

Consumption

control

Resonator

Electrical characteristicsSTM8S105xx

(2)

The oscillator selection can be optimized in terms of supply current using a high quality resonator with

small Rmvalue. Refer to crystal manufacturer for more details

(3)

Data based on characterization results, not tested in production.

(4)

SU(HSE)

is the start-up time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

Figure 20: HSE oscillator circuit diagram

HSE oscillator critical gmequation

mcrit

= (2 × Π × f

)2× Rm(2Co + C)

HSE

Rm: Notional resistance (see crystal specification)

Lm: Notional inductance (see crystal specification)

Cm: Notional capacitance (see crystal specification)

Co: Shunt capacitance (see crystal specification)

CL1= CL2= C: Grounded external capacitance

gm>> g

mcrit

Internal clock sources and timing characteristics10.3.4

Subject to general operating conditions for VDDand TA.

High speed internal RC oscillator (HSI)

Table 34: HSI oscillator characteristics

UnitMaxTypMinConditionsParameterSymbol

HSI

MHz16Frequencyf

75/124DocID14771 Rev 12

ACC

Accuracy of HSI

HSI

oscillator

User-trimmed with CLK_HSITRIMR register for given VDDand T conditions

(1)

STM8S105xxElectrical characteristics

UnitMaxTypMinConditionsParameterSymbol

(2)

%1.0

Accuracy of HSI

(3)

oscillator (factory calibrated)

85 °C

2.95 ≤ VDD≤ 5.5 V,-40 °C

-3.0

≤ TA≤ 125 °C

su(HSI)

HSI oscillator wakeup time including calibration

DD(HSI)

consumption

(1)

Refer to application note.

(2)

Guaranteed by design, not tested in production.

(3)

Data based on characterization results, not tested in production.

Figure 21: Typical HSI accuracy at VDD= 5 V vs 5 temperatures

(3)

1.0-1.0VDD= 5 V, TA= 25°C

2.0-2.0VDD= 5 V, 25 °C ≤ TA≤

(3)

3.0

(2)

µs1.0

(3)

170HSI oscillator power

µA250

DocID14771 Rev 1276/124

Figure 22: Typical HSI accuracy vs VDD@ 4 temperatures

Low speed internal RC oscillator (LSI)

Subject to general operating conditions for VDDand TA.

Electrical characteristicsSTM8S105xx

Table 35: LSI oscillator characteristics

LSI

su(LSI)

DD(LSI)

(1)

Guaranteeed by design, not tested in production.

LSI oscillator wakeup timet

(1)

UnitMaxTypMinParameterSymbol

kHz146128110Frequencyf

µs7

µA5LSI oscillator power consumptionI

77/124DocID14771 Rev 12

Figure 23: Typical LSI accuracy vs VDD@ 4 temperatures

Memory characteristics10.3.5

RAM and hardware registers

STM8S105xxElectrical characteristics

Table 36: RAM and hardware registers

UnitMinConditionsParameterSymbol

(1)

Minimum supply voltage without losing data stored in RAM (in halt mode or under reset)

(1)

Halt mode (or reset)Data retention mode

IT-max

(2)

or in hardware registers (only in halt mode). Guaranteed by design, not tested in production. refer to Operating conditions for the value of V

(2)

Refer to the Operating conditions section for the value of V

IT-max

Flash program memory/data EEPROM memory

General conditions: TA= -40 to 125°C.

Table 37: Flash program memory/data EEPROM memory

ConditionsParameterSymbol

CPU

≤ 16 MHzOperating voltage (all modes,

(1)

UnitMaxTypMin

V5.52.95f

execution/write/erase)

prog

ms6.66.0Standard programming time (including erase) for byte/word/block (1 byte/4 bytes/128 bytes)

DocID14771 Rev 1278/124

Electrical characteristicsSTM8S105xx

erase

RET

(128 bytes)

(2)

(program

memory)

(2)

after 10k erase/write cycles at T

= +85 °C

10k erase/write cycles at TA= +85 °C

300 k erase/write cyclesat TA= +125 °C

ConditionsParameterSymbol

(1)

UnitMaxTypMin

ms3.33.0Fast programming time for 1 block

ms3.33.0Erase time for 1 block (128 bytes)t

cycles10 kTA= +85 °CErase/write cycles

1.0M300 kTA= +125 ° CErase/write cycles(data memory)

RET

= 55° CData retention (program memory)

= 55° CData retention (data memory) after

= 85° CData retention (data memory) after

20T

1.0T

years20T

mA2.0Supply current (Flash programming or erasing for 1 to 128 bytes)

(1)

Data based on characterization results, not tested in production.

(2)

The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes

even when a write/erase operation addresses a single byte.

I/O port pin characteristics10.3.6

General characteristics

Subject to general operating conditions for VDDand TAunless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor.

Table 38: I/O static characteristics

UnitMaxTypMinConditionsParameterSymbol

voltage

VDD= 5 VInput low level

-0.3

0.3 x V

79/124DocID14771 Rev 12

STM8S105xxElectrical characteristics

UnitMaxTypMinConditionsParameterSymbol

hys

tR, t

lkg

lkg ana

Input high level voltage

Hysteresis

Pull-up resistorR

time(10 % - 90 %)

Input leakage current, analog and digital

Analog input leakage current

(1)

VDD= 5 V, VIN= V

Fast I/Os load = 50 pFRise and fall

Standard and high sink I/OsLoad = 50 pF

Fast I/Os load = 20 pF

Standard and high sink I/OsLoad = 20 pF

VSS≤ VIN≤ V

0.7 x V

VDD+ 0.3

(3)

125

(3)

(2)

±1.0

(2)

±250

mV700

kΩ805530

µA

lkg(inj)

adjacent I/O

(1)

Hysteresis voltage between Schmitt trigger switching levels. Based on characterization

(2)

Injection current ±4 mALeakage current in

±1.0

(2)

results, not tested in production.

(2)

Data based on characterization results, not tested in production.

(3)

Data guaranteed by design.

DocID14771 Rev 1280/124

µA

Electrical characteristicsSTM8S105xx

Figure 24: Typical VILand VIHvs VDD@ 4 temperatures

Figure 25: Typical pull-up resistance vs VDD@ 4 temperatures

81/124DocID14771 Rev 12

Figure 26: Typical pull-up current vs VDD@ 4 temperatures

1. The pull-up is a pure resistor (slope goes through 0).

STM8S105xxElectrical characteristics

Table 39: Output driving current (standard ports)

Output low level with four pins

sunk

IIO= 4 mA,

VDD= 3.3 V

Output low level with eight pins sunk

Output high level with four

pins sourced

VDD= 5 V

IIO= 4 mA,

VDD= 3.3 V

Output high level with eight pins sourced

(1)

Data based on characterization results, not tested in production

VDD= 5 V

Table 40: Output driving current (true open drain ports)

UnitMaxMinConditionsParameterSymbol

(1)

V1.0

2.0IIO= 10 mA,

(1)

V2.0

2.4IIO= 10 mA,

UnitMaxConditionsParameterSymbol

IIO= 10 mA, VDD= 3.3 VOutput low level with two pins

(1)

V1.5

sunk

DocID14771 Rev 1282/124

IIO= 20 mA, VDD= 5 V

(1)

Data based on characterization results, not tested in production

Table 41: Output driving current (high sink ports)

Output low level with four pins

sunk

IIO= 10 mA,

VDD= 3.3 V

Electrical characteristicsSTM8S105xx

UnitMaxConditionsParameterSymbol

1.0IIO= 10 mA, VDD= 5 V

(1)

2.0

UnitMaxMinConditionsParameterSymbol

(1)

V1.1

Output low level with eight pins sunk

Output low level with four pins sunk

Output high level with four pins

sourced

VDD= 5 V

IIO= 20 mA,

VDD= 5 V

IIO= 10 mA,

VDD= 3.3 V

Output high level with eight pins sourced

Output high level with four pins sourced

(1)

Data based on characterization results, not tested in production

VDD= 5 V

IIO= 20 mA,

VDD= 5 V

Typical output level curves10.3.7

1.9

3.8IIO= 10 mA,

2.9

(1)

0.9IIO= 10 mA,

1.6

(1)

The following figures show typical output level curves measured with output on a single pin.

83/124DocID14771 Rev 12

Figure 27: Typ. VOL@ VDD= 5 V (standard ports)

Figure 28: Typ. VOL@ VDD= 3.3 V (standard ports)

STM8S105xxElectrical characteristics

DocID14771 Rev 1284/124

Electrical characteristicsSTM8S105xx

Figure 29: Typ. VOL@ VDD= 5 V (true open drain ports)

Figure 30: Typ. VOL@ VDD= 3.3 V (true open drain ports)

85/124DocID14771 Rev 12

Figure 31: Typ. VOL@ VDD= 5 V (high sink ports)

Figure 32: Typ. VOL@ VDD= 3.3 V (high sink ports)

STM8S105xxElectrical characteristics

DocID14771 Rev 1286/124

Electrical characteristicsSTM8S105xx

Figure 33: Typ. VDD- VOH@ VDD= 5 V (standard ports)

Figure 34: Typ. VDD- VOH@ VDD= 3.3 V (standard ports)

87/124DocID14771 Rev 12

Figure 35: Typ. VDD- VOH@ VDD= 5 V (high sink ports)

Figure 36: Typ. VDD- VOH@ VDD= 3.3 V (high sink ports)

STM8S105xxElectrical characteristics

IL(NRST)

IH(NRST)

Reset pin characteristics10.3.8

Subject to general operating conditions for VDDand TAunless otherwise specified.

Table 42: NRST pin characteristics

NRST input low

level voltage

(1)

NRST input high

IOL=2 mA

DocID14771 Rev 1288/124

--0.3

0.3 x V

VDD+ 0.3-0.7 x V

UnitMaxTypMinConditionsParameterSymbol

OL(NRST)

PU(NRST)

I FP(NRST)

IN FP(NRST)

OP(NRST)

level voltage

(1)

NRST output low

level voltage

(1)

NRST pull-up

resistor

(2)

NRST input filtered

(3)

pulse

NRST input not

filtered pulse

(3)

NRST output

(3)

pulse

Electrical characteristicsSTM8S105xx

UnitMaxTypMinConditionsParameterSymbol

0.5--

kΩ805530

75--

--500

μs--

(1)

Data based on characterization results, not tested in production.

(2)

The RPUpull-up equivalent resistor is based on a resistive transistor

(3)

Data guaranteed by design, not tested in production.

Figure 37: Typical NRST VILand VIHvs VDD@ 4 temperatures

89/124DocID14771 Rev 12

STM8S105xxElectrical characteristics

Figure 38: Typical NRST pull-up resistance vs VDD@ 4 temperatures

Figure 39: Typical NRST pull-up current vs VDD@ 4 temperatures

The reset network shown in the following figure protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below V

IL(NRST)

max. (see Table

38: I/O static characteristics ), otherwise the reset is not taken into account internally.

For power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current. If NRST signal is used to reset external circuitry, attention must be taken to the charge/discharge time of the external capacitor to fulfill the external devices reset timing conditions. Minimum recommended capacity is 100 nF.

DocID14771 Rev 1290/124

External

reset

circuit

(optional)

0.1 μF

NRST

VDD

RPU

Filter

Internal reset

STM8

Electrical characteristicsSTM8S105xx

Figure 40: Recommended reset pin protection

SPI serial peripheral interface10.3.9

Unless otherwise specified, the parameters given in the following table are derived from tests performed under ambient temperature, f t

MASTER

= 1/f

MASTER

Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

frequency and VDDsupply voltage conditions.

SCK

c(SCK)

r(SCK)

f(SCK)

su(NSS)

h(NSS)

w(SCKH)

w(SCKL)

su(MI)

su(SI)

(1)

frequency

and fall time

low time

setup time

Table 43: SPI characteristics

Slave modeNSS setup timet

Master modeSCK high and

4 x t

MASTER

/2 -

SCK

5Master modeData input

60Slave mode

25Capacitive load: C = 30 pFSPI clock rise

SCK

UnitMaxMinConditionsParameterSymbol

MHz80Master modeSPI clock

ns70Slave modeNSS hold timet

/2 +

setup time

5Slave modeData input

91/124DocID14771 Rev 12

STM8S105xxElectrical characteristics

UnitMaxMinConditionsParameterSymbol

h(MI)

h(SI)

a(SO)

dis(SO)

v(SO)

v(MO)

h(SO)

(1)

(1) (2)

(1) (3)

(1)

time

access time

disable time

Data output valid time

Data output hold time

Slave modeData output

(after enable edge)

7Master modeData input hold

10Slave modeData input hold

3 x t

MASTER

25Slave modeData output

73Slave mode

36Master mode

28Slave mode

h(MO)

(1)

12Master mode

(after enable edge)

(1)

Values based on design simulation and/or characterization results, and not tested in

production.

(2)

Min time is for the minimum time to drive the output and the max time is for the maximum

time to validate the data.

(3)

Min time is for the minimum time to invalidate the output and the max time is for the

maximum time to put the data in Hi-Z.

DocID14771 Rev 1292/124

ai14134

SCK Input

CPHA=0

MOSI

INPUT

MISO

OUT PUT

CPHA=0

MSB OUT

MSB IN

BIT6 OUT

LSB IN

LSB OUT

CPOL=0

CPOL=1

BIT1 IN

NSSinput

SU(NSS)

c(SCK)

h(NSS)

a(SO)

w(SCKH)

w(SCKL)

v(SO)

h(SO)

r(SCK)

f(SCK)

dis(SO)

su(SI)

h(SI)

ai14135

SCK Input

CPHA=1

MOSI

INPUT

MISO

OUT PUT

CPHA=1

MSB OUT

MSB IN

BIT6 OUT

LSB IN

LSB OUT

CPOL=0

CPOL=1

BIT1 IN

SU(NSS)

c(SCK)

h(NSS)

a(SO)

w(SCKH)

w(SCKL)

v(SO)

h(SO)

r(SCK)

f(SCK)

dis(SO)

su(SI)

h(SI)

NSS input

Electrical characteristicsSTM8S105xx

Figure 41: SPI timing diagram - slave mode and CPHA = 0

Figure 42: SPI timing diagram - slave mode and CPHA = 1

1. Measurement points are made at CMOS levels: 0.3 VDDand 0.7 VDD.

(1)

93/124DocID14771 Rev 12

ai14136b

SCK intput

CPHA=0

MOSI

OUTUT

MISO

INPUT

CPHA=0

MSBIN

MSB OUT

BIT6 IN

LSB OUT

LSB IN

CPOL=0

CPOL=1

BIT1 OUT

NSSinput

c(SCK)

w(SCKH)

w(SCKL)

r(SCK)

f(SCK)

h(MI)

High

SCK output

CPHA=1

CPOL=0

CPOL=1

su(MI)

v(MO)

h(MO)

STM8S105xxElectrical characteristics

Figure 43: SPI timing diagram - master mode

(1)

1. Measurement points are made at CMOS levels: 0.3 VDDand 0.7 VDD.

w(SCLL)

w(SCLH)

su(SDA)

h(SDA)

r(SDA)

r(SCL)

f(SDA)

f(SCL)

I2C interface characteristics10.3.10

SDA data hold timet

Table 44: I2C characteristics

Standard mode I2CParameterSymbol

Min

(3)

(2)

Max

(2)

Min

(4)

(2)

Max

(1)

(2)

(3)

UnitFast mode I2C

μs1.34.7SCL clock low timet

μs0.64.0SCL clock high timet

ns100250SDA setup timet

ns900

ns3001000SDA and SCL rise time

ns300300SDA and SCL fall time

DocID14771 Rev 1294/124

ai15385b

START

SDA

I²C bus

STM8S105xx

SDA

SCL

f(SDA)

r(SDA)

SCL

h(STA)

w(SCLH)

w(SCLL)

su(SDA)

r(SCL)

f(SCL)

h(SDA)

START REPEATED

START

su(STA)

su(STO)

STOP

su(STA:STO)

Electrical characteristicsSTM8S105xx

(1)

Standard mode I2CParameterSymbol

UnitFast mode I2C

Max

(2)

μs0.64.0START condition hold timet

μs0.64.7

h(STA)

su(STA)

Repeated START condition

Min

(2)

Max

(2)

Min

(2)

setup time

su(STO)

w(STO:STA)

STOP to START condition time

μs0.64.0STOP condition setup timet

μs1.34.7

(bus free)

(1)

MASTER

(2)

Data based on standard I2C protocol requirement, not tested in production.

(3)

The maximum hold time of the start condition has only to be met if the interface does not stretch the

, must be at least 8 MHz to achieve max fast I2C speed (400kHz).

pF400400Capacitive load for each bus lineC

low time.

(4)

The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge

the undefined region of the falling edge of SCL.

Figure 44: Typical application with I2C bus and timing diagram

1. Measurement points are made at CMOS levels: 0.3 x VDDand 0.7 x V

(1)

95/124DocID14771 Rev 12

STM8S105xxElectrical characteristics

10-bit ADC characteristics10.3.11

Subject to general operating conditions for V

Table 45: ADC characteristics

ADC

DDA

Positive reference voltageV

Negative reference voltageV

Conversion voltage range

(2)

REF+

REF-

AIN

Devices with external V

, f

DDA

MASTER

=2.95 to 5.5 VADC clock frequencyf

DDA

=4.5 to 5.5 V

DDA

REF+/VREF-

, and TAunless otherwise specified.

UnitMaxTypMinConditionsParameterSymbol

MHz4.01.0V

6.01.0V

V5.53.0Analog supplyV

2.75

V SSA

REF-

(1)

V DDAV SSA

DDA

(1)

REF+

V0.5

pins

ADC

pF3.0Internal sample and hold

capacitor

(2)

STAB

CONV

ADC

= 4 MHzSampling timet

= 6 MHz

= 4 MHzTotal conversion time

0.5f

µs0.75f

µs7.0Wakeup time from standbyt

µs3.5f (including sampling time, 10-bit resolution)

(1)

Data guaranteed by design, not tested in production..

(2)

During the sample time the input capacitance C

ADC

= 6 MHz

AIN

(3 pF max) can be charged/discharged

µs2.33f

1/f

by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS.After the end of the sample time tS,

ADC

DocID14771 Rev 1296/124

Electrical characteristicsSTM8S105xx

changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tSdepend on programming.

|ET|

|EO|

|EG|

Table 46: ADC accuracy with R

(2)

ADC

= 2 MHzTotal unadjusted error

= 4 MHz

= 6 MHz

= 2 MHzOffset error

= 4 MHz

= 6 MHz

= 2 MHzGain error

= 4 MHz

< 10 kΩ , V

AIN

DDA

TypConditionsParameterSymbol

= 5 V

(1)

UnitMax

LSB2.51.0f

3.01.4f

3.51.6f

2.00.6f

2.51.1f

2.51.2f

2.00.2f

2.50.6f

= 6 MHz

ADC

|ED|

|EL|

(1)

Data based on characterisation results, not tested in production.

(2)

ADC accuracy vs. negative injection current: Injecting negative current on any of the

(2)

ADC

= 2 MHzDifferential linearity error

= 4 MHz

= 6 MHz

= 2 MHzIntegral linearity error

= 4 MHz

= 6 MHz

2.50.8f

1.50.7f

1.50.8f

1.50.6f

analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current.

97/124DocID14771 Rev 12

STM8S105xxElectrical characteristics

Any positive injection current within the limits specified for I

INJ(PIN)

port pin characteristics section does not affect the ADC accuracy.

|ET|

|EO|

|EG|

|ED|

Table 47: ADC accuracy with R

(2)

ADC

< 10 kΩ R

AIN

= 2 MHzTotal unadjusted error

= 4 MHz

= 2 MHzOffset error

= 4 MHz

= 2 MHzGain error

= 4 MHz

= 2 MHzDifferential linearity error

AIN

, V

and ΣI

DDA

TypConditionsParameterSymbol

INJ(PIN)

= 3.3 V

2.51.6f

1.50.7f

2.01.3f

1.50.2f

2.00.5f

1.00.7f

in the I/O

(1)

UnitMax

LSB2.01.1f

= 4 MHz

ADC

|EL|

(1)

Data based on characterisation results, not tested in production.

(2)

ADC accuracy vs. negative injection current: Injecting negative current on any of the

(2)

ADC

= 2 MHzIntegral linearity error

= 4 MHz

1.00.7f

1.50.6f

INJ(PIN)

and ΣI

INJ(PIN)

in I/O port

pin characteristics does not affect the ADC accuracy.

DocID14771 Rev 1298/124

Figure 45: ADC accuracy characteristics

STM8

10-bit A/D

conversion

AIN

AINx

0.6 V

± 1 µA

ADC

1. Example of an actual transfer curve.

2. The ideal transfer curve

3. End point correlation line

Electrical characteristicsSTM8S105xx

ET= Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.

EO= Offset error: deviation between the first actual transition and the first ideal one.

EG= Gain error: deviation between the last ideal transition and the last actual one.

ED= Differential linearity error: maximum deviation between actual steps and the ideal one.

EL= Integral linearity error: maximum deviation between any actual transition and the end point correlation line.

Figure 46: Typical application with ADC

EMC characteristics10.3.12

Susceptibility tests are performed on a sample basis during product characterization.

99/124DocID14771 Rev 12

STM8S105xxElectrical characteristics

Functional EMS (electromagnetic susceptibility)10.3.12.1

While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).

FESD: Functional electrostatic discharge (positive and negative) is applied on all pins of

•

the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2 standard.

FTB: A burst of fast transient voltage (positive and negative) is applied to VDDand V

•

through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 (EMC design guide for STMicrocontrollers).

Designing hardened software to avoid noise problems10.3.12.2

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

Corrupted program counter

•

Unexpected reset

•

Critical data corruption (control registers...)

•

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring. See application note AN1015 (Software techniques for improving microcontroller EMC performance).

Table 48: EMS data

Level/ class

(1)

2/B

FESD

Voltage limits to be applied on any I/O pin to induce a functional disturbance

ConditionsParameterSymbol

VDD= 5 V, TA= 25 °C, f conforming to IEC 1000-4-2

MASTER

= 16 MHz,

EFTB

Fast transient voltage burst limits to be applied through 100 pF on V

DocID14771 Rev 12100/124

VDD= 5 V, TA= 25 °C ,f MHz,conforming to IEC 1000-4-4

MASTER

= 16

4/A

(1)

ST STM8S105K4, STM8S105K6, STM8S105S4, STM8S105S6, STM8S105C4 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

STM8S105xxIntroduction

DescriptionSTM8S105xx

STM8S105xxBlock diagram

Product overviewSTM8S105xx

Central processing unit STM84.1

Single wire interface module (SWIM) and debug module (DM)4.2

Interrupt controller4.3

Flash program and data EEPROM memory4.4

Clock controller4.5

Power management4.6

Watchdog timers4.7

Auto wakeup counter4.8

Beeper4.9

TIM1 - 16-bit advanced control timer4.10

TIM2, TIM3 - 16-bit general purpose timers4.11

TIM4 - 8-bit basic timer4.12

Analog-to-digital converter (ADC1)4.13

Communication interfaces4.14

UART24.14.1

STM8S105xxPinout and pin description

STM8S105 pinouts and pin description5.1

Alternate function remapping5.1.1

Memory and register mapSTM8S105xx

Memory map6.1

Register map6.2

I/O port hardware register map6.2.1

General hardware register map6.2.2

CPU/SWIM/debug module/interrupt controller registers6.2.3

Interrupt vector mappingSTM8S105xx

Option bytesSTM8S105xx

STM8S105xxUnique ID

Electrical characteristicsSTM8S105xx

Parameter conditions10.1

Minimum and maximum values10.1.1

Typical values10.1.2

Typical curves10.1.3

Typical current consumption10.1.4

Loading capacitor10.1.5

Pin input voltage10.1.6

Absolute maximum ratings10.2

Operating conditions10.3

VCAP external capacitor10.3.1

Supply current characteristics10.3.2

Total current consumption in run mode10.3.2.1

Total current consumption in wait mode10.3.2.2

Total current consumption in active halt mode10.3.2.3

Total current consumption in halt mode10.3.2.4

Low power mode wakeup times10.3.2.5

Total current consumption and timing in forced reset state10.3.2.6

Current consumption of on-chip peripherals10.3.2.7

Current consumption curves10.3.2.8

External clock sources and timing characteristics10.3.3

Internal clock sources and timing characteristics10.3.4

Memory characteristics10.3.5

I/O port pin characteristics10.3.6

Typical output level curves10.3.7

Reset pin characteristics10.3.8

SPI serial peripheral interface10.3.9

I2C interface characteristics10.3.10

10-bit ADC characteristics10.3.11

EMC characteristics10.3.12

Functional EMS (electromagnetic susceptibility)10.3.12.1

Designing hardened software to avoid noise problems10.3.12.2