ST STM8S105K4, STM8S105K6, STM8S105S4, STM8S105S6, STM8S105C4 User Manual
...
Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbytes Flash,
LQFP48 7x7
LQFP44 10x10
LQFP32 7x7
SDIP32 400 ml
UFQFPN32 5x5
integrated EEPROM,10-bit ADC, timers, UART, SPI, I²C
Features
Core
16 MHz advanced STM8 core with Harvard
•
architecture and 3-stage pipeline
Extended instruction set
•
Memories
Medium-density Flash/EEPROM:
•
Program memory up to 32 Kbytes; data
-
retention 20 years at 55°C after 10 kcycles
Data memory up to 1 Kbytes true data
-
EEPROM; endurance 300 kcycles
RAM: Up to 2 Kbytes
•
Clock, reset and supply management
2.95 V to 5.5 V operating voltage
•
Flexible clock control, 4 master clock sources:
•
Low power crystal resonator oscillator
-
External clock input
-
Internal, user-trimmable 16 MHz RC
-
Internal low power 128 kHz RC
-
Clock security system with clock monitor
•
Power management:
•
Low power modes (wait, active-halt, halt)
-
Switch-off peripheral clocks individually
-
Permanently active, low consumption power-on
•
and power-down reset
STM8S105xx
Interrupt management
Nested interrupt controller with 32 interrupts
•
Up to 37 external interrupts on 6 vectors
•
Timers
2x 16-bit general purpose timers, with 2+3
•
CAPCOM channels (IC, OC or PWM)
Advanced control timer: 16-bit, 4 CAPCOM
•
channels, 3 complementary outputs, dead-time
insertion and flexible synchronization
8-bit basic timer with 8-bit prescaler
•
Auto wake-up timer
•
Window and independent watchdog timers
•
Communications interfaces
UART with clock output for synchronous
•
operation, Smartcard, IrDA, LIN
SPI interface up to 8 Mbit/s
•
I2C interface up to 400 Kbit/s
•
Analog-to-digital converter (ADC)
10-bit, ±1 LSB ADC with up to 10 multiplexed
•
channels, scan mode and analog watchdog
I/Os
Up to 38 I/Os on a 48-pin package including 16
•
high sink outputs
Highly robust I/O design, immune against current
•
injection
Development support
Embedded single wire interface module (SWIM)
•
for fast on-chip programming and non intrusive
debugging
Unique ID
96-bit unique key for each device
•
Table 1: Device summary
Part numberReference
STM8S105xx
STM8S105K4, STM8S105K6, STM8S105S4,
STM8S105S6, STM8S105C4, STM8S105C6
June 2012
DocID14771 Rev 12
1/124
www.st.com
STM8S105xxContents
Contents
1 Introduction ..............................................................................................................8
2 Description ...............................................................................................................9
3 Block diagram ........................................................................................................10
4 Product overview ...................................................................................................11
4.1 Central processing unit STM8 .....................................................................................11
4.2 Single wire interface module (SWIM) and debug module (DM) ..................................11
4.3 Interrupt controller .......................................................................................................12
4.4 Flash program and data EEPROM memory ................................................................12
4.5 Clock controller ............................................................................................................13
4.6 Power management ....................................................................................................14
4.7 Watchdog timers ..........................................................................................................15
4.8 Auto wakeup counter ...................................................................................................15
4.9 Beeper ........................................................................................................................15
4.10 TIM1 - 16-bit advanced control timer .........................................................................16
4.11 TIM2, TIM3 - 16-bit general purpose timers ..............................................................16
4.12 TIM4 - 8-bit basic timer ..............................................................................................16
4.13 Analog-to-digital converter (ADC1) ............................................................................17
4.14 Communication interfaces .........................................................................................17
4.14.1 UART2 ...............................................................................................17
4.14.2 SPI .....................................................................................................18
4.14.3 I²C ......................................................................................................19
5 Pinout and pin description ...................................................................................20
5.1 STM8S105 pinouts and pin description .......................................................................21
5.1.1 Alternate function remapping ...............................................................27
6 Memory and register map .....................................................................................29
6.1 Memory map ................................................................................................................29
6.2 Register map ...............................................................................................................30
6.2.1 I/O port hardware register map ............................................................30
6.2.2 General hardware register map ...........................................................33
6.2.3 CPU/SWIM/debug module/interrupt controller registers ......................44
7 Interrupt vector mapping ......................................................................................47
8 Option bytes ...........................................................................................................49
9 Unique ID ................................................................................................................54
10 Electrical characteristics ....................................................................................55
10.1 Parameter conditions .................................................................................................55
10.1.1 Minimum and maximum values .........................................................55
10.1.2 Typical values .....................................................................................55
DocID14771 Rev 122/124
ContentsSTM8S105xx
10.1.3 Typical curves ....................................................................................55
10.1.4 Typical current consumption ..............................................................55
10.1.5 Loading capacitor ...............................................................................56
10.1.6 Pin input voltage .................................................................................56
10.2 Absolute maximum ratings ........................................................................................56
10.3 Operating conditions ..................................................................................................58
10.3.1 VCAP external capacitor ....................................................................61
10.3.2 Supply current characteristics ............................................................61
10.3.3 External clock sources and timing characteristics .............................73
10.3.4 Internal clock sources and timing characteristics ...............................75
10.3.5 Memory characteristics ......................................................................78
10.3.6 I/O port pin characteristics .................................................................79
10.3.7 Typical output level curves .................................................................83
10.3.8 Reset pin characteristics ....................................................................88
10.3.9 SPI serial peripheral interface ............................................................91
10.3.10 I2C interface characteristics .............................................................94
10.3.11 10-bit ADC characteristics ................................................................96
10.3.12 EMC characteristics .........................................................................99
11 Package information ..........................................................................................103
11.1 48-pin LQFP package mechanical data ...................................................................103
11.2 44-pin LQFP package mechanical data ...................................................................105
11.3 32-pin LQFP package mechanical data ...................................................................106
11.4 32-lead UFQFPN package mechanical data ...........................................................108
11.5 SDIP32 package mechanical data ...........................................................................109
12 Thermal characteristics ....................................................................................111
12.1 Reference document ...............................................................................................112
12.2 Selecting the product temperature range ................................................................112
13 Ordering information .........................................................................................113
13.1 STM8S105 FASTROM microcontroller option list ...................................................113
14 STM8 development tools ..................................................................................118
14.1 Emulation and in-circuit debugging tools .................................................................118
14.2 Software tools ..........................................................................................................118
14.2.1 STM8 toolset ....................................................................................119
14.2.2 C and assembly toolchains ..............................................................119
14.3 Programming tools ..................................................................................................119
15 Revision history .................................................................................................120
3/124DocID14771 Rev 12
STM8S105xxList of tables
List of tables
Table 1. Device summary .........................................................................................................................1
Table 2. STM8S105xx access line features .............................................................................................9
Table 3. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ..................................14
Table 4. TIM timer features ...................................................................................................................16
Table 5. Legend/abbreviations for pinout tables ...................................................................................20
Table 6. Pin description for STM8S105 microcontrollers .......................................................................24
Table 7. Flash, Data EEPROM and RAM boundary addresses ..........................................................105
Table 8. I/O port hardware register map ..............................................................................................108
Table 9. General hardware register map ................................................................................................33
Table 10. CPU/SWIM/debug module/interrupt controller registers ......................................................109
Table 11. Interrupt mapping ....................................................................................................................47
Table 12. Option bytes ..........................................................................................................................54
Table 13. Option byte description ...........................................................................................................50
Table 14. Description of alternate function remapping bits [7:0] of OPT2 ..............................................52
Table 15. Unique ID registers (96 bits) ...................................................................................................54
Table 16. Voltage characteristics ...........................................................................................................56
Table 17. Current characteristics ...........................................................................................................57
Table 18. Thermal characteristics ..........................................................................................................58
Table 19. General operating conditions .................................................................................................59
Table 20. Operating conditions at power-up/power-down ......................................................................60
Table 21. Total current consumption with code execution in run mode at VDD= 5 V .............................61
Table 22. Total current consumption with code execution in run mode at VDD= 3.3 V ..........................73
Table 23. Total current consumption in wait mode at VDD= 5 V ............................................................64
Table 24. Total current consumption in wait mode at VDD= 3.3 V .........................................................65
Table 25. Total current consumption in active halt mode at VDD= 5 V ..................................................65
Table 26. Total current consumption in active halt mode at VDD= 3.3 V ...............................................66
Table 27. Total current consumption in halt mode at VDD= 5 V .............................................................67
Table 28. Total current consumption in halt mode at VDD= 3.3 V ..........................................................68
Table 29. Wakeup times .........................................................................................................................68
Table 30. Total current consumption and timing in forced reset state ..................................................102
Table 31. Peripheral current consumption .............................................................................................69
Table 32. HSE user external clock characteristics .................................................................................73
Table 33. HSE oscillator characteristics .................................................................................................74
Table 34. HSI oscillator characteristics ..................................................................................................75
Table 35. LSI oscillator characteristics ...................................................................................................77
Table 36. RAM and hardware registers ..................................................................................................78
Table 37. Flash program memory/data EEPROM memory ....................................................................78
Table 38. I/O static characteristics .........................................................................................................79
Table 39. Output driving current (standard ports) ..................................................................................82
Table 40. Output driving current (true open drain ports) ........................................................................82
Table 41. Output driving current (high sink ports) ..................................................................................83
Table 42. NRST pin characteristics ........................................................................................................88
Table 43. SPI characteristics ..................................................................................................................91
Table 44. I2C characteristics ..................................................................................................................94
Table 45. ADC characteristics ................................................................................................................96
Table 46. ADC accuracy with R
Table 47. ADC accuracy with R
< 10 kΩ , V
AIN
< 10 kΩ R
AIN
= 5 V .......................................................................97
DDA
AIN
, V
= 3.3 V ............................................................98
DDA
DocID14771 Rev 124/124
List of tablesSTM8S105xx
Table 48. EMS data ..............................................................................................................................100
Table 49. EMI data ...............................................................................................................................101
Table 50. ESD absolute maximum ratings ...........................................................................................102
Table 51. Electrical sensitivities ...........................................................................................................102
Table 52. 48-pin low profile quad flat package mechanical data .........................................................103
Table 53. 44-pin low profile quad flat package mechanical data .........................................................105
Table 54. 32-pin low profile quad flat package mechanical data .........................................................120
Table 55. 32-lead, ultra thin, fine pitch quad flat no-lead package mechanical data ...........................108
Table 56. 32-lead shrink plastic DIP (400 ml) package mechanical data ............................................109
Table 57. Thermal characteristics
(1)
....................................................................................................111
Table 58. Document revision history ...................................................................................................120
5/124DocID14771 Rev 12
STM8S105xxList of figures
List of figures
Figure 1. STM8S105xx access line block diagram ................................................................................10
Figure 2. Flash memory organisation ....................................................................................................13
Figure 3. LQFP 48-pin pinout .................................................................................................................21
Figure 4. LQFP 44-pin pinout .................................................................................................................22
Figure 5. LQFP/UFQFPN 32-pin pinout ................................................................................................23
Figure 6. SDIP 32-pin pinout ..................................................................................................................24
Figure 7. Memory map ...........................................................................................................................29
Figure 8. Supply current measurement conditions ................................................................................55
Figure 9. Pin loading conditions .............................................................................................................56
Figure 10. Pin input voltage ...................................................................................................................56
Figure 11. f
CPUmax
Figure 12. External capacitor C
Figure 13. Typ. I
Figure 14. Typ. I
Figure 15. Typ. I
Figure 16. Typ. I
Figure 17. Typ. I
Figure 18. Typ. I
Figure 19. HSE external clocksource .....................................................................................................74
Figure 20. HSE oscillator circuit diagram ...............................................................................................75
Figure 21. Typical HSI accuracy at VDD= 5 V vs 5 temperatures ..........................................................76
Figure 22. Typical HSI accuracy vs VDD@ 4 temperatures ..................................................................77
Figure 23. Typical LSI accuracy vs VDD@ 4 temperatures ...................................................................78
Figure 24. Typical VILand VIHvs VDD@ 4 temperatures ......................................................................81
Figure 25. Typical pull-up resistance vs VDD@ 4 temperatures ............................................................81
Figure 26. Typical pull-up current vs VDD@ 4 temperatures .................................................................82
Figure 27. Typ. VOL@ VDD= 5 V (standard ports) ................................................................................84
Figure 28. Typ. VOL@ VDD= 3.3 V (standard ports) .............................................................................84
Figure 29. Typ. VOL@ VDD= 5 V (true open drain ports) ......................................................................85
Figure 30. Typ. VOL@ VDD= 3.3 V (true open drain ports) ...................................................................85
Figure 31. Typ. VOL@ VDD= 5 V (high sink ports) ................................................................................86
Figure 32. Typ. VOL@ VDD= 3.3 V (high sink ports) .............................................................................86
Figure 33. Typ. VDD- VOH@ VDD= 5 V (standard ports) .......................................................................87
Figure 34. Typ. VDD- VOH@ VDD= 3.3 V (standard ports) ....................................................................87
Figure 35. Typ. VDD- VOH@ VDD= 5 V (high sink ports) ......................................................................88
Figure 36. Typ. VDD- VOH@ VDD= 3.3 V (high sink ports) ...................................................................88
Figure 37. Typical NRST VILand VIHvs VDD@ 4 temperatures ...........................................................89
Figure 38. Typical NRST pull-up resistance vs VDD@ 4 temperatures .................................................90
Figure 39. Typical NRST pull-up current vs VDD@ 4 temperatures ......................................................90
Figure 40. Recommended reset pin protection ......................................................................................91
Figure 41. SPI timing diagram - slave mode and CPHA = 0 ..................................................................93
Figure 42. SPI timing diagram - slave mode and CPHA = 1
Figure 43. SPI timing diagram - master mode
Figure 44. Typical application with I2C bus and timing diagram
Figure 45. ADC accuracy characteristics ...............................................................................................99
Figure 46. Typical application with ADC ................................................................................................99
Figure 47. 48-pin low profile quad flat package (7 x 7) ........................................................................103
versus V
DD(RUN)
DD(RUN)
DD(RUN)
DD(WFI)
DD(WFI)
DD(WFI)
..............................................................................................................60
vs. V
vs. f
vs. V
vs. V
vs. f
DD
DD ,
CPU ,
DD ,
DD ,
CPU
.......................................................................................................61
EXT
HSE user external clock, f
HSE user external clock, VDD= 5 V ..................................................71
HSI RC osc, f
HSE user external clock, f
, HSE user external clock VDD= 5 V ....................................................72
vs. VDD, HSI RC osc, f
= 16 MHz ...........................................70
CPU
= 16 MHz ..............................................................71
CPU
= 16 MHz ................................................................73
CPU
(1)
...................................................................................94
= 16 MHz ............................................72
CPU
(1)
.............................................................93
(1)
.......................................................95
DocID14771 Rev 126/124
List of figuresSTM8S105xx
Figure 48. 44-pin low profile quad flat package ...................................................................................105
Figure 49. 32-pin low profile quad flat package (7 x 7) ........................................................................106
Figure 50. 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) ..........................................108
Figure 51. 32-lead shrink plastic DIP (400 ml) package ......................................................................109
Figure 52. STM8S105xx access line ordering information scheme .....................................................113
7/124DocID14771 Rev 12
STM8S105xxIntroduction
Introduction1
This datasheet contains the description of the device features, pinout, electrical characteristics,
mechanical data and ordering information.
For complete information on the STM8S microcontroller memory, registers and peripherals,
•
please refer to the STM8S microcontroller family reference manual (RM0016).
For information on programming, erasing and protection of the internal Flash memory
•
please refer to the STM8S Flash programming manual (PM0051).
For information on the debug and SWIM (single wire interface module) refer to the STM8
•
SWIM communication protocol and debug module user manual (UM0470).
For information on the STM8 core, please refer to the STM8 CPU programming manual
•
(PM0044).
DocID14771 Rev 128/124
DescriptionSTM8S105xx
Description2
The STM8S105xx access line 8-bit microcontrollers offer from 16 to 32 Kbytes Flash program
memory, plus integrated true data EEPROM. They are referred to as medium-density devices
in the STM8S microcontroller family reference manual (RM0016).
All devices of the STM8S105xx access line provide the following benefits: reduced system
cost, performance and robustness, short development cycles, and product longevity.
The system cost is reduced thanks to an integrated true data EEPROM for up to 300
kwrite/erase cycles and a high system integration level with internal clock oscillators, watchdog,
and brown-out reset.
Device performance is ensured by a 16 MHz CPU clock frequency and enhanced
characteristics which include robust I/O, independent watchdogs (with a separate clock
source), and a clock security system.
Short development cycles are guaranteed due to application scalability across a common
family product architecture with compatible pinout, memory map and and modular peripherals.
Full documentation is offered with a wide choice of development tools.
Product longevity is ensured in the STM8S family thanks to their advanced core which is
made in a state-of-the art technology for applications with 2.95 V to 5.5 V operating supply.
Table 2: STM8S105xx access line features
STM8S105K4STM8S105K6STM8S105S4STM8S105S6STM8S105C4STM8S105C6Device
323244444848Pin count
of GPIOs
channels
complementary
outputs
channels
Flash Program
memory (bytes)
(bytes)
Peripheral set
252534343838Maximum number
232331313535Ext. Interrupt pins
888899Timer CAPCOM
333333Timer
77991010A/D Converter
121215151616High sink I/Os
16K32K16K32K16K32KMedium density
102410241024102410241024Data EEPROM
2K2K2K2K2K2KRAM (bytes)
Advanced control timer (TIM1), General-purpose timers (TIM2 and TIM3), Basic timer (TIM4) SPI, I2C, UART,
Window WDG, Independent WDG, ADC
9/124DocID14771 Rev 12
XTAL 1-16 MHz
RC int. 16 MHz
RC int. 128 kHz
STM8 core
Debug/SWIM
I2C
SPI
UART2
16-bit general purpose
AWU timer
Reset block
Reset
POR
BOR
Clock controller
Detector
Clock to peripherals and core
8 Mbit/s
Address and data bus
Window WDG
Independent WDG
Up to 32 Kbytes
1 Kbytes
Up to 2 Kbytes
Boot ROM
ADC1
Reset
400 Kbit/s
Single wire
debug interf.
program Flash
16-bit advanced control
timer (TIM1)
timers (TIM2, TIM3)
8-bit basic timer
(TIM4)
data EEPROM
RAM
Master/slave
autosynchro
LIN master
SPI emul.
Beeper
1/2/4 kHz
beep
5 CAPCOM
channels
Up to
4 CAPCOM
channels +3
Up to
complementary
outputs
STM8S105xxBlock diagram
Block diagram3
Figure 1: STM8S105xx access line block diagram
DocID14771 Rev 1210/124
Product overviewSTM8S105xx
Product overview4
The following section intends to give an overview of the basic features of the device functional
modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).
Central processing unit STM84.1
The 8-bit STM8 core is designed for code efficiency and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers
Harvard architecture
•
3-stage pipeline
•
32-bit wide program memory bus - single cycle fetching for most instructions
•
X and Y 16-bit index registers - enabling indexed addressing modes with or without offset
•
and read-modify-write type data manipulations
8-bit accumulator
•
24-bit program counter - 16-Mbyte linear memory space
•
16-bit stack pointer - access to a 64 K-level stack
•
8-bit condition code register - 7 condition flags for the result of the last instruction
•
Addressing
20 addressing modes
•
Indexed indirect addressing mode for look-up tables located anywhere in the address
•
space
Stack pointer relative addressing mode for local variables and parameter passing
•
Instruction set
80 instructions with 2-byte average instruction size
•
Standard data movement and logic/arithmetic functions
•
8-bit by 8-bit multiplication
•
16-bit by 8-bit and 16-bit by 16-bit division
•
Bit manipulation
•
Data transfer between stack and accumulator (push/pop) with direct stack access
•
Data transfer using the X and Y registers or direct memory-to-memory transfers
•
Single wire interface module (SWIM) and debug module (DM)4.2
The single wire interface module and debug module permits non-intrusive, real-time in-circuit
debugging and fast memory programming.
11/124DocID14771 Rev 12
STM8S105xxProduct overview
SWIM
Single wire interface module for direct access to the debug module and memory programming.
The interface can be activated in all device operation modes. The maximum data transmission
speed is 145 bytes/ms.
Debug module
The non-intrusive debugging module features a performance close to a full-featured emulator.
Beside memory and peripherals, also CPU operation can be monitored in real-time by means
of shadow registers.
R/W to RAM and peripheral registers in real-time
•
R/W access to all resources by stalling the CPU
•
Breakpoints on all program-memory instructions (software breakpoints)
•
Two advanced breakpoints, 23 predefined configurations
•
Interrupt controller4.3
Nested interrupts with three software priority levels
•
32 interrupt vectors with hardware priority
•
Up to 37 external interrupts on 6 vectors including TLI
•
Trap and reset interrupts
•
Flash program and data EEPROM memory4.4
Up to 32 Kbytes of Flash program single voltage Flash memory
•
Up to 1 Kbytes true data EEPROM
•
Read while write: Writing in data memory possible while executing code in program memory
•
User option byte area
•
Write protection (WP)
Write protection of Flash program memory and data EEPROM is provided to avoid unintentional
overwriting of memory that could result from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (memory access
security system). MASS is always enabled and protects the main Flash program memory,
data EEPROM and option bytes.
To perform in-application programming (IAP), this write protection can be removed by writing
a MASS key sequence in a control register. This allows the application to write to data
EEPROM, modify the contents of main program memory or the device option bytes.
A second level of write protection, can be enabled to further protect a specific area of memory
known as UBC (user boot code). Refer to the figure below.
The size of the UBC is programmable through the UBC option byte, in increments of 1 page
(512 bytes) by programming the UBC option byte in ICP mode.
This divides the program memory into two areas:
Main program memory: Up to 32 Kbytes minus UBC
•
User-specific boot code (UBC): Configurable up to 32 Kbytes
•
DocID14771 Rev 1212/124
Programmable area
Data
Program memory area
Data memory area ( 1 Kbyte)
EEPROM
UBC area
Remains write protected during IAP
memory
Write access possible for IAP
(1 page steps)
Option bytes
(2 first pages) up to
Medium density
Flash program memory
(up to 32 Kbytes)
from 1 Kbyte
32 Kbytes
Product overviewSTM8S105xx
The UBC area remains write-protected during in-application programming. This means that
the MASS keys do not unlock the UBC area. It protects the memory used to store the boot
program, specific code libraries, reset and interrupt vectors, the reset routine and usually the
IAP and communication routines.
Figure 2: Flash memory organisation
Read-out protection (ROP)
The read-out protection blocks reading and writing the Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated,
any attempt to toggle its status triggers a global erase of the program and data memory. Even
if no protection can be considered as totally unbreakable, the feature provides a very high
level of protection for a general purpose microcontroller.
Clock controller4.5
The clock controller distributes the system clock (f
to the core and the peripherals. It also manages clock gating for low power modes and ensures
clock robustness.
Features
Clock prescaler: To get the best compromise between speed and current consumption
•
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
Safe clock switching: Clock sources can be changed safely on the fly in run mode
•
through a configuration register. The clock signal is not switched until the new clock source
is ready. The design guarantees glitch-free switching.
Clock management: To reduce power consumption, the clock controller can stop the
•
clock to the core, individual peripherals or memory.
Master clock sources: Four different clock sources can be used to drive the master
•
clock:
1-16 MHz high-speed external crystal (HSE)
-
Up to 16 MHz high-speed user-external clock (HSE user-ext)
-
MASTER
) coming from different oscillators
13/124DocID14771 Rev 12
STM8S105xxProduct overview
16 MHz high-speed internal RC oscillator (HSI)
-
128 kHz low-speed internal RC (LSI)
-
Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz
•
clock (HSI/8). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
Clock security system (CSS): This feature can be enabled by software. If an HSE clock
•
failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an
interrupt can optionally be generated.
Configurable main clock output (CCO): This outputs an external clock for use by the
•
application.
Table 3: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers
Bit
Peripheral
clock
ADCPCKEN2 3ReservedPCKEN2 7UART2PCKEN1 3TIM1PCKEN1 7
AWUPCKEN2 2ReservedPCKEN2 6ReservedPCKEN1 2TIM3PCKEN1 6
ReservedPCKEN2 1ReservedPCKEN2 5SPIPCKEN1 1TIM2PCKEN1 5
ReservedPCKEN2 0ReservedPCKEN2 4I2CPCKEN1 0TIM4PCKEN1 4
clock
BitPeripheral
clock
BitPeripheral
clock
BitPeripheral
Power management4.6
For efficent power management, the application can be put in one of four different low-power
modes. You can configure each mode to obtain the best compromise between lowest power
consumption, fastest start-up time and available wakeup sources.
Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The
•
wakeup is performed by an internal or external interrupt or reset.
Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are
•
stopped. An internal wakeup is generated at programmable intervals by the auto wake up
unit (AWU). The main voltage regulator is kept powered on, so current consumption is
higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup
is triggered by the internal AWU interrupt, external interrupt or reset.
Active halt mode with regulator off: This mode is the same as active halt with regulator
•
on, except that the main voltage regulator is powered off, so the wake up time is slower.
Halt mode: In this mode the microcontroller uses the least power. The CPU and peripheral
•
clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by
external event or reset.
DocID14771 Rev 1214/124
Product overviewSTM8S105xx
Watchdog timers4.7
The watchdog system is based on two independent timers providing maximum security to
the applications.
Activation of the watchdog timers is controlled by option bytes or by software. Once activated,
the watchdogs cannot be disabled by the user program without performing a reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually generated
by external interferences or by unexpected logical conditions, which cause the application
program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application
perfectly.
The application software must refresh the counter before time-out and during a limited time
window.
A reset is generated in two situations:
1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to
64 ms.
2. Refresh out of window: The downcounter is refreshed before its value is lower than the
one stored in the window register.
Independent watchdog timer
The independent watchdog peripheral can be used to resolve processor malfunctions due to
hardware or software failures.
It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure
The IWDG time base spans from 60 µs to 1 s.
Auto wakeup counter4.8
Used for auto wakeup from active halt mode
•
Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock
•
LSI clock can be internally connected to TIM3 input capture channel 1 for calibration
•
Beeper4.9
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.
The beeper output port is only available through the alternate function remap option bit AFR7.
15/124DocID14771 Rev 12
STM8S105xxProduct overview
TIM1 - 16-bit advanced control timer4.10
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver
16-bit up, down and up/down autoreload counter with 16-bit prescaler
•
Four independent capture/compare channels (CAPCOM) configurable as input capture,
•
output compare, PWM generation (edge and center aligned mode) and single pulse mode
output
Synchronization module to control the timer with external signals
•
Break input to force the timer outputs into a defined state
•
Three complementary outputs with adjustable dead time
•
Encoder mode
•
Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break
•
TIM2, TIM3 - 16-bit general purpose timers4.11
16-bit autoreload (AR) up-counter
•
15-bit prescaler adjustable to fixed power of 2 ratios 1…32768
•
Timers with 3 or 2 individually configurable capture/compare channels
•
PWM mode
•
Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update
•
Timer
size
(bits)
16TIM1
16TIM2
16TIM3
TIM4 - 8-bit basic timer4.12
8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128
•
Clock source: CPU clock
•
Interrupt source: 1 x overflow/update
•
Table 4: TIM timer features
PrescalerCounter
Any integer from 1 to
65536
1 to 32768
1 to 32768
Counting
mode
down
CAPCOM
channels
Complem.
outputs
Ext.
trigger
No03UpAny power of 2 from
No02UpAny power of 2 from
Timer
synchronization/
chaining
NoYes34Up/
DocID14771 Rev 1216/124
Product overviewSTM8S105xx
Timer
Timer
synchronization/
chaining
size
(bits)
8TIM4
PrescalerCounter
1 to 128
Counting
mode
CAPCOM
channels
Complem.
outputs
Ext.
trigger
No00UpAny power of 2 from
Analog-to-digital converter (ADC1)4.13
The STM8S105xx products contain a 10-bit successive approximation A/D converter (ADC1)
with up to 10 multiplexed input channels and the following main features:
Input voltage range: 0 to V
•
Conversion time: 14 clock cycles
•
Single and continuous and buffered continuous conversion modes
•
Buffer size (n x 10 bits) where n = number of input channels
•
Scan mode for single and continuous conversion of a sequence of channels
•
Analog watchdog capability with programmable upper and lower thresholds
•
Analog watchdog interrupt
•
External trigger input
•
Trigger from TIM1 TRGO
•
End of conversion (EOC) interrupt
•
DDA
Note: Additional AIN12 analog input is not selectable in ADC scan mode or with analog
watchdog. Values converted from AIN12 are stored only into the ADC_DRH/ADC_DRL
registers.
Communication interfaces4.14
The following communication interfaces are implemented:
UART2: Full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA
•
mode, LIN2.1 master/slave capability
SPI : Full and half-duplex, 8 Mbit/s
•
I²C: Up to 400 Kbit/s
•
UART24.14.1
Main features
One Mbit/s full duplex SCI
•
SPI emulation
•
High precision baud rate generator
•
Smartcard emulation
•
IrDA SIR encoder decoder
•
17/124DocID14771 Rev 12
LIN master mode
•
LIN slave mode
•
Asynchronous communication (UART mode)
Full duplex communication - NRZ standard format (mark/space)
•
Programmable transmit and receive baud rates up to 1 Mbit/s (f
•
following any standard baud rate regardless of the input frequency
Separate enable bits for transmitter and receiver
•
Two receiver wakeup modes:
•
Address bit (MSB)
-
Idle line (interrupt)
-
Transmission error detection with interrupt generation
•
Parity control
•
Synchronous communication
Full duplex synchronous transfers
•
SPI master operation
•
8-bit data communication
•
Maximum speed: 1 Mbit/s at 16 MHz (f
•
CPU
/16)
STM8S105xxProduct overview
/16) and capable of
CPU
LIN master mode
Emission: Generates 13-bit synch break frame
•
Reception: Detects 11-bit break frame
•
LIN slave mode
Autonomous header handling - one single interrupt per valid message header
•
Automatic baud rate synchronization - maximum tolerated initial clock deviation ±15 %
•
Synch delimiter checking
•
11-bit LIN synch break detection - break detection always active
•
Parity check on the LIN identifier field
•
LIN error management
•
Hot plugging support
•
SPI4.14.2
Maximum speed: 8 Mbit/s (f
•
Full duplex synchronous transfers
•
Simplex synchronous transfers on two lines with a possible bidirectional data line
•
Master or slave operation - selectable by hardware or software
•
CRC calculation
•
1 byte Tx and Rx buffer
•
Slave/master selection input pin
•
MASTER
/2) both for master and slave
DocID14771 Rev 1218/124
I²C4.14.3
I²C master features:
•
Clock generation
-
Start and stop generation
-
I²C slave features:
•
Programmable I2C address detection
-
Stop bit detection
-
Generation and detection of 7-bit/10-bit addressing and general call
•
Supports different communication speeds:
•
Standard speed (up to 100 kHz)
-
Fast speed (up to 400 kHz)
-
Product overviewSTM8S105xx
19/124DocID14771 Rev 12
STM8S105xxPinout and pin description
Pinout and pin description5
Table 5: Legend/abbreviations for pinout tables
I= Input, O = Output, S = Power supplyType
Output speed
configuration
Reset state
InputLevel
O1 = Slow (up to 2 MHz)
O2 = Fast (up to 10 MHz)
O3 = Fast/slow programmability with slow as default state after reset
O4 = Fast/slow programmability with fast as default state after reset
Output
Bold X (pin state after internal reset release).
Unless otherwise specified, the pin state is the same during the reset
phase and after the internal reset release.
CM = CMOS
HS = High sinkOutput
float = floating, wpu = weak pull-upInputPort and control
T = True open drain, OD = Open drain, PP =
Push pull
DocID14771 Rev 1220/124
44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
12
13 14 15 16 17 18
19 20 21 22
1
2
3
4
5
6
7
8
9
10
11
48 47 46 45
(HS) PA6
AIN8/PE7
PC1 (HS)/TIM1_CH1/UART2_CK
PE5/SPI_NSS
PG1
AIN9/PE6
PD3 (HS)/TIM2_CH2 [ADC_ETR]
PD2 (HS)/TIM3_CH1 [TIM2_CH3]
PE0 (HS)/CLK_CCO
PE1 (T)/I2C_SCL
PE2 (T)/I2C_SDAA
PE3/TIM1_BKIN
PD7/TLI [TIM1_CH4]
PD6/UART2_RX
PD5/UART2_TX
PD4 (HS)/TIM2_CH1 [BEEP]
PD1 (HS)/SWIM
PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO]
VSSIO_2
PC5 (HS)/SPI_SCK
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PG0
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
VDDIO_2
AIN7/PB7
AIN6/PB6
[I2C_SDA] AIN5/PB5
[TIM1_ETR] AIN3/PB3
[TIM1_CH3N] AIN2/PB2
[TIM1_CH2N] AIN1/PB1
[TIM1_CH1N] AIN0/PB0
VDDA
VSSA
VSS
VCAP
VDD
VDDIO_1
[TIM3_CH1] TIM2_CH3/PA3
(HS) PA4
(HS) PA5
NRST
OSCIN/PA1
OSCOUT/PA2
VSSIO_1
[I2C_SCL] AIN4/PB4
Pinout and pin descriptionSTM8S105xx
STM8S105 pinouts and pin description5.1
Figure 3: LQFP 48-pin pinout
1. (HS) high sink capability.
2. (T) True open drain (P-buffer and protection diode to VDDnot implemented).
3. [ ] alternate function remapping option (If the same alternate function is shown twice, it
indicates an exclusive choice not a duplication of the function).
21/124DocID14771 Rev 12
Figure 4: LQFP 44-pin pinout
AIN6/PB6
[I2C_SDA] AIN5/PB5
[TIM1_ETR] AIN3/PB3
[TIM1_CH3N] AIN2/PB2
[TIM1_CH2N] AIN1/PB1
[TIM1_CH1N] AIN0/PB0
AIN9/PE6
VDDA
VSSA
AIN7/PB7
44 43 42 41 40 39 38 37 36 35 34
33
32
31
30
29
28
27
26
25
24
23
12 13 14 15 16 17 18
19 20 21 22
1
2
3
4
5
6
7
8
9
10
11
VSS
VCAP
VDD
VDDIO_1
(HS) PA4
(HS) PA5
(HS) PA6
NRST
OSCIN/PA1
OSCOUT/PA2
VSSIO_1
VDDIO_2
VSSIO_2
PC5 (HS)/SPI_SCK
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1
PE5/SPI_NSS/UART2_CK
PG1
PG0
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
PD3 (HS)/TIM2_CH2 [ADC_ETR]
PD2 (HS)/TIM3_CH1 [TIM2_CH3]
PD1 (HS)/SWIM
PE1 (T)/I2C_SCL
PE2 (T)/I2C_SDA
PD7/TLI [TIM1_CH4]
PD6/UART2_RX
PD5/UART2_TX
PD4 (HS)/TIM2_CH1 [BEEP]
PE0 (HS)/CLK_CCO
PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO]
[I2C_SCL] AIN4/PB4
STM8S105xxPinout and pin description
1. (HS) high sink capability.
2. (T) True open drain (P-buffer and protection diode to VDDnot implemented).
3. [ ] alternate function remapping option (If the same alternate function is shown twice, it
indicates an exclusive choice not a duplication of the function).
DocID14771 Rev 1222/124
[TIM1_ETR] AIN3/PB3
[TIM1_CH3N] AIN2/PB2
[TIM1_CH2N] AIN1/PB1
[TIM1_CH1N] AIN0/PB0
VDDA
VSSA
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
9 10 11 12 13 14 15
16
1
2
3
4
5
6
7
8
VCAP
VDD
VDDIO
AIN12/PF4
NRST
OSCIN/PA1
OSCOUT/PA2
VSS
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1/UART2_CK
PE5/SPI_NSS
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
PC5 (HS)/SPI_SCK
PC4 (HS)/TIM1_CH4
PD3 (HS)/TIM2_CH2 [ADC_ETR]
PD2 (HS)/TIM3_CH1 [TIM2_CH3]
PD1 (HS)/SWIM
PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO]
PD7/TLI [TIM1_CH4]
PD6/UART2_RX
PD5/UART2_TX
PD4 (HS)/TIM2_CH1 [BEEP]
[I2C_SDA] AIN5/PB5
[I2C_SCL] AIN4/PB4
Pinout and pin descriptionSTM8S105xx
Figure 5: LQFP/UFQFPN 32-pin pinout
1. (HS) high sink capability.
2. [ ] alternate function remapping option (If the same alternate function is shown twice, it
indicates an exclusive choice not a duplication of the function).
23/124DocID14771 Rev 12
8
1
2
3
4
5
6
7
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
ADC_ETR/TIM2_CH2/(HS) PD3
[BEEP] TIM2_CH1/(HS) PD4
UART2_TX/PD5
UART2_RX/PD6
[TIM1_CH4] TLI/PD7
NRST
OSCIN/PA1
OSCOUT/PA2
VSS
VCAP
VDD
AIN12/PF4
[I2C_SDA] AIN5/PB5 PB4/AIN4[ I2C_SCL]
PB3/AIN3 [TIM1_ETR]
PB2/AIN2 [TIM1_CH3N]
PB1/AIN1 [TIM1_CH2N]
PB0/AIN0 [TIM1_CH1N]
PE5/SPI_NSS
PC1 (HS)/TIM1_CH1/UART2_CK
PC2 (HS)/TIM1_CH2
PC3 (HS)/TIM1_CH3
PC4 (HS)/TIM1_CH4
PC5 (HS)/SPI_SCK
PC6 (HS)/SPI_MOSI
PC7 (HS)/SPI_MISO
PD0 (HS)/TIM3_CH2 [TIM1_BKIN][CLK_CCO]
PD1 (HS)/SWIM
PD2 (HS)/TIM3_CH1 [TIM2_CH3]
105_ai15057
VDDIO
VDDA
VSSA
STM8S105xxPinout and pin description
Figure 6: SDIP 32-pin pinout
1. (HS) high sink capability.
2. (T) True open drain (P-buffer and protection diode to VDDnot implemented).
3. [ ] alternate function remapping option (If the same alternate function is shown twice, it
indicates an exclusive choice not a duplication of the function).
LQFP44LQFP48
UFQFPN32
Table 6: Pin description for STM8S105 microcontrollers
PPODSpeedHigh
Main function
(after reset)
ResetXI/ONRST6111
I/O groundSV
Digital groundSV
1.8 V regulator capacitorSVCAP10566
Digital power supplySV
I/O power supplySV
7222
OSC IN
8333
OSC
OUT
--44
SSIO_1
9455
SS
11677
DD
12788
DDIO_1
OutputInputTypePin namePin number
Ext.
wpufloatingSDIP32LQFP32/
interrupt
sink
DocID14771 Rev 1224/124
Default alternate
function
Resonator/Port A1XXO1XXI/OPA1/
crystal in
Resonator/Port A2XXO1XXXI/OPA2/
crystal out
Alternate
function after
remap
[option bit]
Pinout and pin descriptionSTM8S105xx
Default alternate
function
Timer 2 -
channel 3
Analog input 12
(2)
Analog input 7Port B7XXO1XXXI/OPB7/
Analog input 6Port B6XXO1XXXI/OPB6/
PPODSpeedHigh
Main function
(after reset)
Port A3XXO1XXXI/OPA3/
Port A4XXO3HSXXXI/OPA4--910
Port A5XXO3HSXXXI/OPA5--1011
Port A6XXO3HSXXXI/OPA6--1112
Port F4XXO1XXI/OPF4/
Analog power supplySV
Analog groundSV
OutputInputTypePin namePin number
Ext.
LQFP44LQFP48
UFQFPN32
---9
TIM2
_CH3
[TIM3
_CH1]
138--
AIN12
(1)
1491213
DDA
15101314
SSA
--1415
AIN7
--1516
AIN6
wpufloatingSDIP32LQFP32/
interrupt
sink
Alternate
function after
remap
[option bit]
TIM3_ CH1
[AFR1]
16111617
AIN5
[I2C_
SDA]
17121718
AIN4
[I2C_
SCL]
18131819
AIN3
[TIM1_
ETR]
19141920
AIN2
[TIM1_
CH3N]
20152021
AIN1
[TIM1_
CH2N]
21162122
AIN0
[TIM1_
CH1N]
---23
AIN8
Analog input 5Port B5XXO1XXXI/OPB5/
Analog input 4Port B4XXO1XXXI/OPB4/
Analog input 3Port B3XXO1XXXI/OPB3/
Analog input 2Port B2XXO1XXXI/OPB2/
Analog input 1Port B1XXO1XXXI/OPB1/
Analog input 0Port B0XXO1XXXI/OPB0/
Analog input 8Port E7XXO1XXXI/OPE7/
I2C_SDA
[AFR6]
I2C_SCL
[AFR6]
TIM1_ ETR
[AFR5]
TIM1_ CH3N
[AFR5]
TIM1_ CH2N
[AFR5]
TIM1_ CH1N
[AFR5]
25/124DocID14771 Rev 12
STM8S105xxPinout and pin description
(3)
Alternate
function after
remap
[option bit]
Default alternate
function
Analog input 9
SPI master/slave
select
Timer 1 -Port C1XXO3HSXXXI/OPC1/
channel 1/ UART2
synchronous clock
Timer 1-Port C2XXO3HSXXXI/OPC2/
channel 2
Timer 1 -Port C3XXO3HSXXXI/OPC3/
channel 3
Timer 1 -Port C4XXO3HSXXXI/OPC4/
channel 4
SPI clockPort C5XXO3HSXXXI/OPC5/
PPODSpeedHigh
Main function
(after reset)
Port E6XXO1XXXI/OPE6/
Port E5XXO1XXXI/OPE5/SPI_
OutputInputTypePin namePin number
Ext.
LQFP44LQFP48
UFQFPN32
--2224
AIN9
22172325
NSS
23182426
TIM1_
CH1/
UART2_CK
24192527
TIM1_
CH2
25202628
TIM1_
CH3
2621-29
TIM1_
CH4
27222730
SPI_
SCK
wpufloatingSDIP32LQFP32/
interrupt
sink
--2831
SSIO_2
--2932
DDIO_2
28233033
SPI_
MOSI
29243134
SPI_
MISO
---37
TIM1_
BKIN
(4)
--3438
I2C_
SDA
--3539
I2C_
SCL
--3640
CLK_
CCO
O1XXI/OPE2/
T
(4)
O1XXI/OPE1/
T
I/O groundSV
I/O power supplySV
Port C6XXO3HSXXXI/OPC6/
Port C7XXO3HSXXXI/OPC7/
Port G0XXO1XXI/OPG0--3235
Port G1XXO1XXI/OPG1--3336
Port E3XXO1XXXI/OPE3/
Port E0XXO3HSXXXI/OPE0/
SPI master
out/slave in
SPI master in/
slave out
Timer 1 - break
input
I2C dataPort E2
I2C clockPort E1
Configurable clock
output
DocID14771 Rev 1226/124
Pinout and pin descriptionSTM8S105xx
Default alternate
function
Timer 3 -
channel 2
SWIM data
interface
Timer 3 -
channel 1
Timer 2 -
channel 2
Timer 2 -
channel 1
PPODSpeedHigh
Main function
(after reset)
Port D0XXO3HSXXXI/OPD0/
Port D1XXO4HSXXXI/OPD1/
Port D2XXO3HSXXXI/OPD2/
Port D3XXO3HSXXXI/OPD3/
Port D4XXO3HSXXXI/OPD4/
OutputInputTypePin namePin number
Ext.
LQFP44LQFP48
UFQFPN32
30253741
TIM3_
CH2
[TIM1_
BKIN]
[CLK_
CCO]
31263842
32273943
1284044
2294145
SWIM
TIM3_
CH1
[TIM2_
CH3]
TIM2_
CH2
[ADC_
ETR]
TIM2_
CH1
[BEEP]
(5)
wpufloatingSDIP32LQFP32/
interrupt
sink
Alternate
function after
remap
[option bit]
TIM1_ BKIN
[AFR3]/
CLK_ CCO
[AFR2]
TIM2_CH3
[AFR1]
ADC_ ETR
[AFR0]
BEEP output
[AFR7]
3304246
UART2_
TX
4314347
UART2_
RX
5324448
[TIM1_
CH4]
(1)
A pull-up is applied to PF4 during the reset phase. This pin is input floating after reset release.
(2)
AIN12 is not selectable in ADC scan mode or with analog watchdog.
(3)
In 44-pin package, AIN9 cannot be used by ADC scan mode.
(4)
In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to VDDare not implemented).
(5)
The PD1 pin is in input pull-up during the reset phase and after internal reset release.
Port D5XXO1XXXI/OPD5/
Port D6XXO1XXXI/OPD6/
Alternate function remapping5.1.1
As shown in the rightmost column of the pin description table, some alternate functions can
be remapped at different I/O ports by programming one of eight AFR (alternate function
remap) option bits. When the remapping option is active, the default alternate function is no
longer available.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral
registers.
UART2 data
transmit
UART2 data
receive
Top level interruptPort D7XXO1XXXI/OPD7/TLI
TIM1_ CH4
[AFR4]
27/124DocID14771 Rev 12
STM8S105xxPinout and pin description
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO
section of the family reference manual, RM0016).
DocID14771 Rev 1228/124
0x00 FFFF
Flash program memory
(16to 32 Kbytes)
0x00 8000
Reserved
0x01 0000
0x02 7FFF
0x00 0000
RAM
0x00 07FF
(2 Kbytes)
0x00 4000
0x00 43FF
1 Kbyte data EEPROM
Reserved
Reserved
0x00 4400
0x00 47FF
32 interrupt vectors
0x00 807F
GPIO and periph. reg.
0x00 5000
0x00 57FF
0x00 5800
0x00 7FFF
0x00 4900
0x00 4FFF
2 Kbytes boot ROM
0x00 6000
0x00 67FF
0x00 6800
0x00 7EFF
CPU/SWIM/debug/ITC
registers
0x00 7F00
0x00 5FFF
Reserved
Reserved
Reserved
Option bytes
0x00 4800
0x00 487F
512 bytes stack
Memory and register mapSTM8S105xx
Memory and register map6
Memory map6.1
Figure 7: Memory map
The following table lists the boundary addresses for each memory size. The top of the stack
is at the RAM end address in each case.
29/124DocID14771 Rev 12
STM8S105xxMemory and register map
Table 7: Flash, Data EEPROM and RAM boundary addresses
End addressStart addressSize (bytes)Memory area
0x00 FFFF0x00 800032KFlash program memory
0x00 BFFF0x00 800016K
0x00 07FF0x00 00002KRAM
0x00 43FF0x00 40001024Data EEPROM
Register map6.2
I/O port hardware register map6.2.1
Table 8: I/O port hardware register map
Register nameRegister labelBlockAddress
Reset
status
0x00Port A data output latch registerPA_ODRPort A0x00 5000
0xXXPort A input pin value registerPA_IDR0x00 5001
0x00Port A data direction registerPA_DDR0x00 5002
0x00Port A control register 1PA_CR10x00 5003
0x00Port A control register 2PA_CR20x00 5004
0x00Port B data output latch registerPB_ODRPort B0x00 5005
0xXXPort B input pin value registerPB_IDR0x00 5006
0x00Port B data direction registerPB_DDR0x00 5007
0x00Port B control register 1PB_CR10x00 5008
0x00Port B control register 2PB_CR20x00 5009
DocID14771 Rev 1230/124
Loading...