ST STM8S103K3, STM8S103F3, STM8S103F2 User Manual

STM8S103K3 STM8S103F3 STM8S103F2

LQFP32 7x7

UFQFPN32 5x5

TSSOP20

SO20W 300 mils

SDIP32 400 mils

Access line, 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, data

EEPROM,10-bit ADC, 3 timers, UART, SPI, I²C

Interrupt management

Nested interrupt controller with 32 interrupts

•

Up to 27 external interrupts on 6 vectors

•

Timers

Advanced control timer: 16-bit, 4 CAPCOM

•

channels, 3 complementary outputs, dead-time insertion and flexible synchronization

16-bit general purpose timer, with 3 CAPCOM

•

channels (IC, OC or PWM)

8-bit basic timer with 8-bit prescaler

Features

Core

16 MHz advanced STM8 core with Harvard

•

architecture and 3-stage pipeline

Extended instruction set

•

Memories

Program memory: 8 Kbytes Flash; data retention

•

20 years at 55 °C after 10 kcycles

Data memory: 640 bytes true data EEPROM;

•

endurance 300 kcycles

RAM: 1 Kbytes

•

Auto wake-up timer

•

Window watchdog and independent watchdog

•

timers

Communications interfaces

UART with clock output for synchronous

•

operation, Smartcard, IrDA, LIN master mode

SPI interface up to 8 Mbit/s

•

I2C interface up to 400 Kbit/s

•

Analog to digital converter (ADC)

10-bit, ±1 LSB ADC with up to 5 multiplexed

•

channels, scan mode and analog watchdog

Clock, reset and supply management

2.95 to 5.5 V operating voltage

•

Flexible clock control, 4 master clock sources:

•

Low power crystal resonator oscillator

External clock input

Internal, user-trimmable 16 MHz RC

Internal low power 128 kHz RC

Clock security system with clock monitor

•

Power management:

•

Low power modes (wait, active-halt, halt)

Switch-off peripheral clocks individually

Permanently active, low consumption power-on

•

and power-down reset

June 2012

I/Os

Up to 28 I/Os on a 32-pin package including 21

•

high sink outputs

Highly robust I/O design, immune against current

•

injection

Development support

Embedded single wire interface module (SWIM)

•

for fast on-chip programming and non intrusive debugging

Unique ID

96-bit unique key for each device

•

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www.st.com

STM8S103K3 STM8S103F3 STM8S103F2Contents

1 Introduction ..............................................................................................................8

2 Description ...............................................................................................................9

3 Block diagram ........................................................................................................10

4 Product overview ...................................................................................................11

4.1 Central processing unit STM8 .....................................................................................11

4.2 Single wire interface module (SWIM) and debug module (DM) ..................................11

4.3 Interrupt controller .......................................................................................................12

4.4 Flash program and data EEPROM memory ................................................................12

4.5 Clock controller ............................................................................................................13

4.6 Power management ....................................................................................................14

4.7 Watchdog timers ..........................................................................................................14

4.8 Auto wakeup counter ...................................................................................................15

4.9 Beeper ........................................................................................................................15

4.10 TIM1 - 16-bit advanced control timer .........................................................................15

4.11 TIM2 - 16-bit general purpose timer ..........................................................................16

4.12 TIM4 - 8-bit basic timer ..............................................................................................16

4.13 Analog-to-digital converter (ADC1) ............................................................................16

4.14 Communication interfaces .........................................................................................17

4.14.1 UART1 ...............................................................................................17

4.14.2 SPI .....................................................................................................18

4.14.3 I²C ......................................................................................................18

5 Pinout and pin description ...................................................................................19

5.1 STM8S103Kx UFQFPN32/LQFP32/SDIP32 pinout and pin description .....................20

5.2 STM8S103Fx TSSOP20/SO20/UFQFPN20 pinout and pin description .....................24

5.2.1 STM8S103Fx TSSOP20/SO20 pinout .................................................24

5.2.2 STM8S103Fx UFQFPN20 pinout ........................................................25

5.2.3 STM8S103Fx TSSOP20/SO20/UFQFPN20 pin description ................25

5.3 Alternate function remapping .......................................................................................27

6 Memory and register map .....................................................................................28

6.1 Memory map ................................................................................................................28

6.2 Register map ...............................................................................................................29

6.2.1 I/O port hardware register map ............................................................29

6.2.2 General hardware register map ..........................................................30

6.2.3 CPU/SWIM/debug module/interrupt controller registers .....................40

7 Interrupt vector mapping ......................................................................................42

8 Option bytes ...........................................................................................................44

8.1 Alternate function remapping bits ................................................................................46

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ContentsSTM8S103K3 STM8S103F3 STM8S103F2

9 Unique ID ................................................................................................................49

10 Electrical characteristics ....................................................................................50

10.1 Parameter conditions .................................................................................................50

10.1.1 Minimum and maximum values .........................................................50

10.1.2 Typical values .....................................................................................50

10.1.3 Typical curves ....................................................................................50

10.1.4 Loading capacitor ...............................................................................50

10.1.5 Pin input voltage .................................................................................51

10.2 Absolute maximum ratings ........................................................................................51

10.3 Operating conditions ..................................................................................................53

10.3.1 VCAP external capacitor ....................................................................54

10.3.2 Supply current characteristics ............................................................55

10.3.3 External clock sources and timing characteristics .............................65

10.3.4 Internal clock sources and timing characteristics ...............................67

10.3.5 Memory characteristics ......................................................................70

10.3.6 I/O port pin characteristics .................................................................71

10.3.7 Reset pin characteristics ....................................................................79

10.3.8 SPI serial peripheral interface ............................................................82

10.3.9 I2C interface characteristics ...............................................................85

10.3.10 10-bit ADC characteristics ................................................................86

10.3.11 EMC characteristics .........................................................................90

11 Package information ............................................................................................94

11.1 32-pin LQFP package mechanical data .....................................................................94

11.2 32-lead UFQFPN package mechanical data .............................................................96

11.3 20-lead UFQFPN package mechanical data .............................................................97

11.4 SDIP32 package mechanical data .............................................................................98

11.5 20-pin TSSOP package mechanical data ................................................................100

11.6 20-pin SO package mechanical data .......................................................................101

11.7 UFQFPN recommended footprint ............................................................................102

12 Thermal characteristics ....................................................................................104

12.1 Reference document ...............................................................................................105

12.2 Selecting the product temperature range ................................................................105

13 Ordering information .........................................................................................106

13.1 STM8S103 FASTROM microcontroller option list ...................................................106

14 STM8 development tools ..................................................................................111

14.1 Emulation and in-circuit debugging tools .................................................................111

14.2 Software tools ..........................................................................................................111

14.2.1 STM8 toolset ....................................................................................112

14.2.2 C and assembly toolchains ..............................................................112

14.3 Programming tools ..................................................................................................112

15 Revision history .................................................................................................113

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STM8S103K3 STM8S103F3 STM8S103F2List of tables

List of tables

Table 1. STM8S103xx access line features .............................................................................................9

Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ..................................14

Table 3. TIM timer features ....................................................................................................................16

Table 4. Legend/abbreviations for pinout tables ...................................................................................19

Table 5. UFQFPN32/LQFP32/SDIP32 pin description ...........................................................................21

Table 6. STM8S103Fx pin description ...................................................................................................25

Table 7. I/O port hardware register map ................................................................................................29

Table 8. General hardware register map ...............................................................................................30

Table 9. CPU/SWIM/debug module/interrupt controller registers .........................................................40

Table 10. Interrupt mapping ...................................................................................................................42

Table 11. Option bytes .........................................................................................................................113

Table 12. Option byte description ...........................................................................................................44

Table 13. STM8S103K alternate function remapping bits for 32-pin devices ........................................46

Table 14. STM8S103F alternate function remapping bits for 20-pin devices ........................................47

Table 15. Unique ID registers (96 bits) .................................................................................................113

Table 16. Voltage characteristics ...........................................................................................................51

Table 17. Current characteristics ...........................................................................................................52

Table 18. Thermal characteristics ..........................................................................................................52

Table 19. General operating conditions .................................................................................................53

Table 20. Operating conditions at power-up/power-down ......................................................................54

Table 21. Total current consumption with code execution in run mode at VDD= 5 V .............................55

Table 22. Total current consumption with code execution in run mode at VDD= 3.3 V ..........................56

Table 23. Total current consumption in wait mode at VDD= 5 V ............................................................57

Table 24. Total current consumption in wait mode at VDD= 3.3 V .........................................................57

Table 25. Total current consumption in active halt mode at VDD= 5 V ..................................................58

Table 26. Total current consumption in active halt mode at VDD= 3.3 V ...............................................59

Table 27. Total current consumption in halt mode at VDD= 5 V .............................................................60

Table 28. Total current consumption in halt mode at VDD= 3.3 V ..........................................................60

Table 29. Wakeup times .........................................................................................................................60

Table 30. Total current consumption and timing in forced reset state ....................................................61

Table 31. Peripheral current consumption .............................................................................................62

Table 32. HSE user external clock characteristics .................................................................................65

Table 33. HSE oscillator characteristics .................................................................................................66

Table 34. HSI oscillator characteristics ..................................................................................................67

Table 35. LSI oscillator characteristics ...................................................................................................69

Table 36. RAM and hardware registers ..................................................................................................70

Table 37. Flash program memory/data EEPROM memory ....................................................................70

Table 38. I/O static characteristics .........................................................................................................71

Table 39. Output driving current (standard ports) ..................................................................................73

Table 40. Output driving current (true open drain ports) ........................................................................74

Table 41. Output driving current (high sink ports) ..................................................................................74

Table 42. NRST pin characteristics ........................................................................................................79

Table 43. SPI characteristics ..................................................................................................................82

Table 44. I2C characteristics ..................................................................................................................85

Table 45. ADC characteristics ................................................................................................................87

Table 46. ADC accuracy with R Table 47. ADC accuracy with R

< 10 kΩ , VDD= 5 V .........................................................................87

AIN

< 10 kΩ R

AIN

, VDD= 3.3 V ..............................................................88

AIN

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List of tablesSTM8S103K3 STM8S103F3 STM8S103F2

Table 48. EMS data ................................................................................................................................91

Table 49. EMI data .................................................................................................................................91

Table 50. ESD absolute maximum ratings .............................................................................................92

Table 51. Electrical sensitivities .............................................................................................................93

Table 52. 32-pin low profile quad flat package mechanical data ............................................................94

Table 53. 32-lead, ultra thin, fine pitch quad flat no-lead package mechanical data .............................96

Table 54. 20-lead, ultra thin, fine pitch quad flat no-lead package (3 x 3) package mechanical data ....98

Table 55. 32-lead shrink plastic DIP (400 ml) package mechanical data ..............................................98

Table 56. 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data .......................................................101

Table 57. 20-lead, plastic small outline (300 mils) mechanical data ....................................................101

Table 58. Thermal characteristics ........................................................................................................104

Table 59. Document revision history ....................................................................................................113

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STM8S103K3 STM8S103F3 STM8S103F2List of figures

List of figures

Figure 1. Block diagram .........................................................................................................................10

Figure 2. Flash memory organization ....................................................................................................13

Figure 3. STM8S103Kx UFQFPN32/LQFP32 pinout .............................................................................20

Figure 4. STM8S103Kx SDIP32 pinout .................................................................................................21

Figure 5. STM8S103Fx TSSOP20/SO20 pinout ....................................................................................24

Figure 6. STM8S103Fx UFQFPN20-pin pinout .....................................................................................25

Figure 7. Memory map ...........................................................................................................................28

Figure 8. Pin loading conditions .............................................................................................................50

Figure 9. Pin input voltage .....................................................................................................................51

Figure 10. f

CPUmax

Figure 11. External capacitor C Figure 12. Typ I Figure 13. Typ I Figure 14. Typ I Figure 15. Typ I Figure 16. Typ I Figure 17. Typ I

Figure 18. HSE external clocksource .....................................................................................................66

Figure 19. HSE oscillator circuit diagram ...............................................................................................67

Figure 20. Typical HSI frequency variation vs VDD@ 4 temperatures ..................................................69

Figure 21. Typical LSI frequency variation vs VDD@ 4 temperatures ...................................................69

Figure 22. Typical VILand VIHvs VDD@ 4 temperatures ......................................................................72

Figure 23. Typical pull-up resistance vs VDD@ 4 temperatures ............................................................73

Figure 24. Typical pull-up current vs VDD@ 4 temperatures .................................................................73

Figure 25. Typ. VOL@ VDD= 5 V (standard ports) ................................................................................75

Figure 26. Typ. VOL@ VDD= 3.3 V (standard ports) .............................................................................75

Figure 27. Typ. VOL@ VDD= 5 V (true open drain ports) ......................................................................76

Figure 28. Typ. VOL@ VDD= 3.3 V (true open drain ports) ...................................................................76

Figure 29. Typ. VOL@ VDD= 5 V (high sink ports) ................................................................................77

Figure 30. Typ. VOL@ VDD= 3.3 V (high sink ports) .............................................................................77

Figure 31. Typ. VDD- VOH@ VDD= 5 V (standard ports) .......................................................................78

Figure 32. Typ. VDD- VOH@ VDD= 3.3 V (standard ports) ...................................................................78

Figure 33. Typ. VDD- VOH@ VDD= 5 V (high sink ports) .......................................................................79

Figure 34. Typ. VDD- VOH@ VDD= 3.3 V (high sink ports) ....................................................................79

Figure 35. Typical NRST VILand VIHvs VDD@ 4 temperatures ...........................................................80

Figure 36. Typical NRST pull-up resistance vs VDD@ 4 temperatures .................................................81

Figure 37. Typical NRST pull-up current vs VDD@ 4 temperatures ......................................................81

Figure 38. Recommended reset pin protection ......................................................................................82

Figure 39. SPI timing diagram - slave mode and CPHA = 0 ..................................................................84

Figure 40. SPI timing diagram - slave mode and CPHA = 1 ..................................................................84

Figure 41. SPI timing diagram - master mode

Figure 42. Typical application with I2C bus and timing diagram ............................................................89

Figure 43. ADC accuracy characteristics ...............................................................................................89

Figure 44. Typical application with ADC ................................................................................................90

Figure 45. 32-pin low profile quad flat package (7 x 7) ..........................................................................94

Figure 46. 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) ............................................96

Figure 47. 20-lead, ultra thin, fine pitch quad flat no-lead package outline (3 x 3) ................................97

versus V

DD(RUN)

DD(WFI)

..............................................................................................................54

.......................................................................................................55

EXT

vs. VDDHSE user external clock, f vs. f vs. VDDHSI RC osc, f

HSE user external clock, VDD= 5 V ....................................................63

CPU

= 16 MHz .................................................................64

CPU

vs. VDDHSE user external clock, f vs. f vs. VDDHSI RC osc, f

HSE user external clock, VDD= 5 V .....................................................65

CPU

= 16 MHz .................................................................65

CPU

(1)

...................................................................................85

= 16 MHz .............................................63

CPU

= 16 MHz ..............................................64

CPU

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List of figuresSTM8S103K3 STM8S103F3 STM8S103F2

Figure 48. 32-lead shrink plastic DIP (400 ml) package ........................................................................98

Figure 49. 20-pin, 4.40 mm body, 0.65 mm pitch .................................................................................101

Figure 50. 20-lead, plastic small outline (300 mils) package ...............................................................101

Figure 51. Recommended footprint for on-board emulation ................................................................102

Figure 52. Recommended footprint without on-board emulation .........................................................103

Figure 53. STM8S103x access line ordering information scheme ......................................................106

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STM8S103K3 STM8S103F3 STM8S103F2Introduction

Introduction1

This datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information.

For complete information on the STM8S microcontroller memory, registers and peripherals,

•

please refer to the STM8S microcontroller family reference manual (RM0016).

For information on programming, erasing and protection of the internal Flash memory

•

please refer to the STM8S Flash programming manual (PM0051).

For information on the debug and SWIM (single wire interface module) refer to the STM8

•

SWIM communication protocol and debug module user manual (UM0470).

For information on the STM8 core, please refer to the STM8 CPU programming manual

•

(PM0044).

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DescriptionSTM8S103K3 STM8S103F3 STM8S103F2

Description2

The STM8S103x access line 8-bit microcontrollers offer 8 Kbytes Flash program memory, plus integrated true data EEPROM. The STM8S microcontroller family reference manual (RM0016) refers to devices in this family as low-density. They provide the following benefits: performance, robustness, and reduced system cost.

Device performance and robustness are ensured by advanced core and peripherals made in a state-of-the art technology, a 16 MHz clock frequency, robust I/Os, independent watchdogs with separate clock source, and a clock security system.

The system cost is reduced thanks to an integrated true data EEPROM for up to 300 kwrite/erase cycles and a high system integration level with internal clock oscillators, watchdog and brown-out reset.

Full documentation is offered as well as a wide choice of development tools.

Table 1: STM8S103xx access line features

STM8S103F2STM8S103F3STM8S103K3Device

202032Pin count

161628Maximum number of GPIOs (I/Os)

161627Ext. interrupt pins

Low density Flash program memory (bytes)

Data EEPROM (bytes)

Peripheral set

(1)

No read-while-write (RWW) capability

777Timer CAPCOM channels

223Timer complementary outputs

554A/D converter channels

121221High sink I/Os

4K8K8K

640

(1)

640

(1)

640

(1)

1K1K1KRAM (bytes)

Multipurpose timer (TIM1), SPI, I2C, UART window WDG,independent WDG, ADC, PWM timer (TIM2), 8-bit timer (TIM4)

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XTAL 1-16 MHz

RC int. 16MHz

RC int. 128kHz

STM8 core

Debug/SWIM

SPI

UART1

16-bit general purpose

AWU timer

Reset block

Reset

POR

BOR

Clock controller

Detector

Clock to peripherals and core

8 Mbit/s

LIN master

Address and databus

Window WDG

8 Kbytes

640 bytes

1 Kbyte

ADC1

4 CAPCOM

Reset

400 Kbit/s

Single wire

debug interf.

SPI emul.

channels +3

program

Flash

16-bit advanced

control timer (TIM1)

8-bit basic timer

data EEPROM

RAM

Up to

Beeper

1/2/4 kHz

beep

Independent WDG

(TIM4)

3 CAPCOM channels

Up to

complementary outputs

timer (TIM2)

Up to 5

channels

I2C

STM8S103K3 STM8S103F3 STM8S103F2Block diagram

Block diagram3

Figure 1: Block diagram

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Product overviewSTM8S103K3 STM8S103F3 STM8S103F2

Product overview4

The following section intends to give an overview of the basic features of the device functional modules and peripherals.

For more detailed information please refer to the corresponding family reference manual (RM0016).

Central processing unit STM84.1

The 8-bit STM8 core is designed for code efficiency and performance.

It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions.

Architecture and registers

Harvard architecture

•

3-stage pipeline

•

32-bit wide program memory bus - single cycle fetching for most instructions

•

X and Y 16-bit index registers - enabling indexed addressing modes with or without offset

•

and read-modify-write type data manipulations

8-bit accumulator

•

24-bit program counter - 16-Mbyte linear memory space

•

16-bit stack pointer - access to a 64 K-level stack

•

8-bit condition code register - 7 condition flags for the result of the last instruction

•

Addressing

20 addressing modes

•

Indexed indirect addressing mode for look-up tables located anywhere in the address

•

space

Stack pointer relative addressing mode for local variables and parameter passing

•

Instruction set

80 instructions with 2-byte average instruction size

•

Standard data movement and logic/arithmetic functions

•

8-bit by 8-bit multiplication

•

16-bit by 8-bit and 16-bit by 16-bit division

•

Bit manipulation

•

Data transfer between stack and accumulator (push/pop) with direct stack access

•

Data transfer using the X and Y registers or direct memory-to-memory transfers

•

Single wire interface module (SWIM) and debug module (DM)4.2

The single wire interface module and debug module permits non-intrusive, real-time in-circuit debugging and fast memory programming.

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STM8S103K3 STM8S103F3 STM8S103F2Product overview

SWIM

Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms.

Debug module

The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in real-time by means of shadow registers.

R/W to RAM and peripheral registers in real-time

•

R/W access to all resources by stalling the CPU

•

Breakpoints on all program-memory instructions (software breakpoints)

•

Two advanced breakpoints, 23 predefined configurations

•

Interrupt controller4.3

Nested interrupts with three software priority levels

•

32 interrupt vectors with hardware priority

•

Up to 27 external interrupts on 6 vectors including TLI

•

Trap and reset interrupts

•

Flash program and data EEPROM memory4.4

8 Kbytes of Flash program single voltage Flash memory

•

640 bytes true data EEPROM

•

User option byte area

•

Write protection (WP)

Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction.

There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, data EEPROM and option bytes.

To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to write to data EEPROM, modify the contents of main program memory or the device option bytes.

A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code). Refer to the figure below.

The size of the UBC is programmable through the UBC option byte, in increments of 1 page (64-byte block) by programming the UBC option byte in ICP mode.

This divides the program memory into two areas:

Main program memory: Up to 8 Kbytes minus UBC

•

User-specific boot code (UBC): Configurable up to 8 Kbytes

•

The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot

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UBC area

Program memory area

Data memory area ( 640 bytes)

Remains write protected during IAP

Data EEPROM memory

Write access possible for IAP

Option bytes

Programmable bytes(1 page)

up to 8 Kbytes (in 1 page steps)

area from 64

Low density Flash program memory (8 Kbytes)

Product overviewSTM8S103K3 STM8S103F3 STM8S103F2

program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines.

Figure 2: Flash memory organization

Read-out protection (ROP)

The read-out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program and data memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.

Clock controller4.5

The clock controller distributes the system clock (f to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness.

Features

Clock prescaler: To get the best compromise between speed and current consumption

•

the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.

Safe clock switching: Clock sources can be changed safely on the fly in run mode

•

through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching.

Clock management: To reduce power consumption, the clock controller can stop the

•

clock to the core, individual peripherals or memory.

Master clock sources: Four different clock sources can be used to drive the master

•

clock:

1-16 MHz high-speed external crystal (HSE)

MASTER

) coming from different oscillators

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Bit

STM8S103K3 STM8S103F3 STM8S103F2Product overview

Up to 16 MHz high-speed user-external clock (HSE user-ext)

16 MHz high-speed internal RC oscillator (HSI)

128 kHz low-speed internal RC (LSI)

Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz

•

clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.

Clock security system (CSS): This feature can be enabled by software. If an HSE clock

•

failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated.

Configurable main clock output (CCO): This outputs an external clock for use by the

•

application.

Table 2: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers

Peripheral clock

ADCPCKEN23ReservedPCKEN27UART1PCKEN13TIM1PCKEN17

AWUPCKEN22ReservedPCKEN26ReservedPCKEN12ReservedPCKEN16

ReservedPCKEN21ReservedPCKEN25SPIPCKEN11TIM2PCKEN15

clock

BitPeripheral

clock

BitPeripheral

clock

BitPeripheral

ReservedPCKEN20ReservedPCKEN24I2CPCKEN10TIM4PCKEN14

Power management4.6

For efficent power management, the application can be put in one of four different low-power modes. You can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources.

Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The

•

wakeup is performed by an internal or external interrupt or reset.

Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are

•

stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.

Active halt mode with regulator off: This mode is the same as active halt with regulator

•

on, except that the main voltage regulator is powered off, so the wake up time is slower.

Halt mode: In this mode the microcontroller uses the least power. The CPU and peripheral

•

clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset.

Watchdog timers4.7

The watchdog system is based on two independent timers providing maximum security to the applications.

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Product overviewSTM8S103K3 STM8S103F3 STM8S103F2

Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset.

Window watchdog timer

The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence.

The window function can be used to trim the watchdog behavior to match the application perfectly.

The application software must refresh the counter before time-out and during a limited time window.

A reset is generated in two situations:

1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to 64 ms.

2. Refresh out of window: The downcounter is refreshed before its value is lower than the one stored in the window register.

Independent watchdog timer

The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures.

It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case of a CPU clock failure

The IWDG time base spans from 60 µs to 1 s.

Auto wakeup counter4.8

Used for auto wakeup from active halt mode

•

Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock

•

LSI clock can be internally connected to TIM1 input capture channel 1 for calibration

•

Beeper4.9

The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz.

The beeper output port is only available through the alternate function remap option bit AFR7.

TIM1 - 16-bit advanced control timer4.10

This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver

16-bit up, down and up/down autoreload counter with 16-bit prescaler

•

Four independent capture/compare channels (CAPCOM) configurable as input capture,

•

output compare, PWM generation (edge and center aligned mode) and single pulse mode output

Synchronization module to control the timer with external signals

•

15/117DocID15441 Rev 9

STM8S103K3 STM8S103F3 STM8S103F2Product overview

Break input to force the timer outputs into a defined state

•

Three complementary outputs with adjustable dead time

•

Encoder mode

•

Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break

•

TIM2 - 16-bit general purpose timer4.11

16-bit autoreload (AR) up-counter

•

15-bit prescaler adjustable to fixed power of 2 ratios 1…32768

•

3 individually configurable capture/compare channels

•

PWM mode

•

Interrupt sources: 3 x input capture/output compare, 1 x overflow/update

•

TIM4 - 8-bit basic timer4.12

8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128

•

Clock source: CPU clock

•

Interrupt source: 1 x overflow/update

•

Timer

Table 3: TIM timer features

Counter size (bits)

16TIM1

16TIM2

8TIM4

Prescaler

Any integer from 1 to 65536

Any power of 2 from 1 to 32768

Any power of 2 from 1 to 128

Counting mode

CAPCOM channels

Complem. outputs

Ext. trigger

Yes34Up/down

No03Up

No00Up

Timer synchronization/ chaining

Analog-to-digital converter (ADC1)4.13

The STM8S103xx family products contain a 10-bit successive approximation A/D converter (ADC1) with up to 5 external multiplexed input channels and the following main features:

Input voltage range: 0 to V

•

Conversion time: 14 clock cycles

•

Single and continuous and buffered continuous conversion modes

•

Buffer size (n x 10 bits) where n = number of input channels

•

Scan mode for single and continuous conversion of a sequence of channels

•

DocID15441 Rev 916/117

Product overviewSTM8S103K3 STM8S103F3 STM8S103F2

Analog watchdog capability with programmable upper and lower thresholds

•

Analog watchdog interrupt

•

External trigger input

•

Trigger from TIM1 TRGO

•

End of conversion (EOC) interrupt

•

Communication interfaces4.14

The following communication interfaces are implemented:

UART1: Full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA

•

mode, single wire mode, LIN2.1 master capability

SPI : Full and half-duplex, 8 Mbit/s

•

I²C: Up to 400 Kbit/s

•

UART14.14.1

Main features

One Mbit/s full duplex SCI

•

SPI emulation

•

High precision baud rate generator

•

Smartcard emulation

•

IrDA SIR encoder decoder

•

LIN master mode

•

Single wire half duplex mode

•

Asynchronous communication (UART mode)

Full duplex communication - NRZ standard format (mark/space)

•

Programmable transmit and receive baud rates up to 1 Mbit/s (f

•

following any standard baud rate regardless of the input frequency

Separate enable bits for transmitter and receiver

•

Two receiver wakeup modes:

•

Address bit (MSB)

Idle line (interrupt)

Transmission error detection with interrupt generation

•

Parity control

•

Synchronous communication

Full duplex synchronous transfers

•

SPI master operation

•

8-bit data communication

•

Maximum speed: 1 Mbit/s at 16 MHz (f

•

CPU

/16)

/16) and capable of

CPU

17/117DocID15441 Rev 9

STM8S103K3 STM8S103F3 STM8S103F2Product overview

LIN master mode

Emission: Generates 13-bit synch break frame

•

Reception: Detects 11-bit break frame

•

SPI4.14.2

Maximum speed: 8 Mbit/s (f

•

Full duplex synchronous transfers

•

Simplex synchronous transfers on two lines with a possible bidirectional data line

•

Master or slave operation - selectable by hardware or software

•

CRC calculation

•

1 byte Tx and Rx buffer

•

Slave/master selection input pin

•

I²C4.14.3

I²C master features:

•

Clock generation

Start and stop generation

MASTER

/2) both for master and slave

I²C slave features:

•

Programmable I2C address detection

Stop bit detection

Generation and detection of 7-bit/10-bit addressing and general call

•

Supports different communication speeds:

•

Standard speed (up to 100 kHz)

Fast speed (up to 400 kHz)

DocID15441 Rev 918/117

Pinout and pin descriptionSTM8S103K3 STM8S103F3 STM8S103F2

Pinout and pin description5

Table 4: Legend/abbreviations for pinout tables

I= Input, O = Output, S = Power supplyType

Output speed

configuration

Reset state

InputLevel

O1 = Slow (up to 2 MHz)

O2 = Fast (up to 10 MHz)

O3 = Fast/slow programmability with slow as default state after reset

O4 = Fast/slow programmability with fast as default state after reset

Output

Bold X (pin state after internal reset release).

Unless otherwise specified, the pin state is the same during the reset phase and after the internal reset release.

CM = CMOS

HS = High sinkOutput

float = floating, wpu = weak pull-upInputPort and control

T = True open drain, OD = Open drain, PP = Push pull

19/117DocID15441 Rev 9

I2C_SCL/(T) PB4

TIM1_ETR/AIN3/(HS) PB3

TIM1_CH3N/ AIN2/(HS) PB2

TIM1_CH2N/ AIN1/(HS) PB1

TIM1_CH1N/AIN0/(HS) PB0

PB7

PB6

I2C_SDA/ (T) PB5

32 31 30 29 28 27 26 25

24 23 22 21 20 19 18 17

9 10 11 12 13 14 15

1 2 3 4 5 6 7 8

VCAP

VDD

[SPI_NSS] TIM2_CH3/(HS) PA3

PF4

NRST

OSCIN/PA1

OSCOUT/PA2

VSS

PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2 PC1 (HS)/TIM1_CH1/UART1_CK PE5 (HS)/SPI_NSS

PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI PC5 (HS)/SPI_SCK PC4 (HS)/TIM1_CH4/CLK_CCO

PD3 (HS)/TIM2_CH2/ADC_ETR

PD2 (HS) [TIM2_CH3]

PD1 (HS)/SWIM

PD0 (HS)/ TIM1_BKIN [CLK_CCO]

PD7 (HS)/TLI [TIM1_CH4]

PD6 (HS)/UART1_RX

PD5 (HS)/UART1_TX

PD4 (HS)/BEEP/TIM2_CH1

STM8S103K3 STM8S103F3 STM8S103F2Pinout and pin description

5.1

STM8S103Kx UFQFPN32/LQFP32/SDIP32 pinout and pin description

Figure 3: STM8S103Kx UFQFPN32/LQFP32 pinout

1. (HS) high sink capability.

2. (T) True open drain (P-buffer and protection diode to VDDnot implemented).

3. [ ] alternate function remapping option (if the same alternate function is shown twice, it

indicates an exclusive choice not a duplication of the function).

DocID15441 Rev 920/117

1 2 3 4 5 6 7

9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

[TIM2_CH2] ADC_ETR/(HS) PD3

BEEP/TIM2_CH1/(HS) PD4

UART1_TX(/HS)PD5 UART1_RX/(HS)PD6

[TIM1_CH4] TLI/(HS) PD7

OSCIN/PA1

OSCOUT/PA2

VSS

VCAP

VDD

[SPI_NSS] TIM2_CH3/(HS) PA3

PB6

PB3 (HS)/TIM1_ETR/AIN3

PB2 (HS)/TIM1_CH3N/AIN2

PB1 (HS)/TIM1_CH2N/AIN1

PB0 (HS)/TIM1_CH1N/AIN0

PE5/SPI_NSS

PC1 (HS)/TIM1_CH1/UART1_CK

PC2( HS)/TIM1_CH2

PC3 (HS)/TIM1_CH3

PC4( HS)/TIM1_CH4/CLK_CCO

PC5 (HS)/SPI_SCK

PC6 (HS)/SPI_MOSI

PC7 (HS)/SPI_MISO

PD0 (HS)/TIM1_BKIN [CLK_CCO]

PD1 (HS)/SWIM

PD2 (HS) [TIM2_CH3]

PB7

I2C_SDA/(T) PB5

NRST

PF4

PB4 (T)/I2C_SCL

Pinout and pin descriptionSTM8S103K3 STM8S103F3 STM8S103F2

Figure 4: STM8S103Kx SDIP32 pinout

1. (HS) high sink capability.

2. (T) True open drain (P-buffer and protection diode to VDDnot implemented).

3. [ ] alternate function remapping option (if the same alternate function is shown twice, it

indicates an exclusive choice not a duplication of the function).

LQFP/

SDIP

UFQFP

611

712

name

OSCIN

OSCOUT

TIM2_CH3 [SPI_NSS]

Table 5: UFQFPN32/LQFP32/SDIP32 pin description

(2)

Type

wpufloating

Ext. interrupt

OutputInput

High sink

(1)

PPODSpeed

Main function (after reset)

ResetXI/ONRST16

Digital groundSV

1.8 V regulator capacitorSVCAP510

Digital power supplySV

Default alternate function

Resonator/ crystal inPort A1XXO1XXXI/OPA1/

Resonator/ crystal outPort A2XXO1XXXI/OPA2/

Timer 2 channel 3Port A3XXO3HSXXXI/OPA3/

Alternate function after remap [option bit]

SPI master/ slave select [AFR1]

21/117DocID15441 Rev 9

STM8S103K3 STM8S103F3 STM8S103F2Pinout and pin description

SDIP

LQFP/

UFQFP

1116

1217

1318

1419

1520

name

I2C_SDA

I2C_SCL

TIM1_ETR

TIM1_CH3N

TIM1_CH2N

Type

wpufloating

Ext. interrupt

OutputInput

High sink

(1)

Main function (after

PPODSpeed

reset)

Port F4XXO1XXI/OPF4813

Port B7XXO1XXXI/OPB7914

Port B6XXO1XXXI/OPB61015

(3)

O1XXI/OPB5/

(3)

O1XXI/OPB4/

Port B3XXO3HSXXXI/OPB3/AIN3/

Port B2XXO3HSXXXI/OPB2/AIN2/

Port B1XXO3HSXXXI/OPB1/AIN1/

Default alternate function

I2C dataPort B5

I2C clockPort B4

Analog input 3/ Timer 1 external trigger

Analog input 2/ Timer 1 - inverted channel 3

Analog input 1/ Timer 1 - inverted channel 2

Alternate function after remap [option bit]

1621

TIM1_CH1N

1722

SPI_NSS

1823

TIM1_CH1/ UART1_CK

1924

TIM1_CH2

2025

TIM1_CH3

2126

TIM1_CH4/ CLK_CCO

2227

SPI_SCK

2328

SPI_MOSI

Port B0XXO3HSXXXI/OPB0/AIN0/

Port E5XXO3HSXXXI/OPE5/

Port C1XXO3HSXXXI/OPC1/

Port C4XXO3HSXXXI/OPC4/

Port C6XXO3HSXXXI/OPC6/

Analog input 0/ Timer 1 - inverted channel 1

SPI master/slave select

Timer 1 - channel 1 UART1 clock

Timer 1 - channel 2Port C2XXO3HSXXXI/OPC2/

Timer 1 - channel 3Port C3XXO3HSXXXI/OPC3/

Timer 1 - channel 4 /configurable clock output

SPI clockPortC5XXO3HSXXXI/OPC5/

SPI master out/slave in

DocID15441 Rev 922/117

Pinout and pin descriptionSTM8S103K3 STM8S103F3 STM8S103F2

SDIP

LQFP/

UFQFP

2429

2530

2631

2732

281

292

name

SPI_MISO

TIM1_BKIN [CLK_CCO]

SWIM

(4)

[TIM2_CH3]

TIM2_CH2/ ADC_ETR

TIM2_CH1

Type

wpufloating

Ext. interrupt

OutputInput

High sink

(1)

PPODSpeed

Main function (after reset)

Port C7XXO3HSXXXI/OPC7/

Port D2XXO3HSXXXI/OPD2

Port D3XXO3HSXXXI/OPD3/

Port D4XXO3HSXXXI/OPD4/BEEP/

Default alternate function

SPI master in/ slave out

Timer 1 - break inputPort D0XXO3HSXXXI/OPD0/

SWIM data interfacePort D1XXO4HSXXXI/OPD1/

Timer 2 - channel 2/ADC external trigger

Timer 2 - channel 1/BEEP output

Alternate function after remap [option bit]

Configurable clock output [AFR5]

Timer 2 channel 3[AFR1]

303

314

325

(1)

I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings (see Electrical characteristics). (2)

When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode if Halt/Active-halt is used in the application. (3)

In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDDare not implemented). (4)

The PD1 pin is in input pull-up during the reset phase and after internal reset release.

UART1_TX

UART1_RX

[TIM1_CH4]

UART1 data transmitPort D5XXO3HSXXXI/OPD5/

UART1 data receivePort D6XXO3HSXXXI/OPD6/

Top level interruptPort D7XXO3HSXXXI/OPD7/ TLI

Timer 1 channel 4 [AFR6]

23/117DocID15441 Rev 9

20 19 18 17 16 15 14 13

1 2 3 4 5 6 7 8

UART1_CK/TIM2_CH1/BEEP/(HS)PD4

NRST

VCAP

OSCOUT/PA2

PD3 (HS)/AIN4/TIM2_CH2/ADC_ETR

PD1 (HS)/SWIM

PB4 (T)/I2C_SCL [ADC_ETR]

PC3 (HS)/TIM1_CH3 [TLI] [TIM1_CH1N]

PC4 (HS)/TIM1_CH4/CLK_CCO/AIN2 [TIM1_CH2N]

PC5 (HS)/SPI_SCK [TIM2_CH1]

12 11

9 10

[SPI_NSS] TIM2_CH3/(HS) PA3

PD2 (HS)/AIN3 [TIM2_CH3]

OSCIN/PA1

PB5 (T)/I2C_SDA [TIM1_BKIN]

UART1_TX/AIN5/(HS) PD5 UART1_RX/AIN6/(HS) PD6

PC6 (HS)/SPI_MOSI [TIM1_CH1]

PC7 (HS)/SPI_MISO [TIM1_CH2]

STM8S103K3 STM8S103F3 STM8S103F2Pinout and pin description

5.2

STM8S103Fx TSSOP20/SO20/UFQFPN20 pinout and pin description

STM8S103Fx TSSOP20/SO20 pinout5.2.1

Figure 5: STM8S103Fx TSSOP20/SO20 pinout

1. HS high sink capability.

2. (T) True open drain (P-buffer and protection diode to VDDnot implemented).

3. [ ] alternate function remapping option (If the same alternate function is shown twice, it

indicates an exclusive choice not a duplication of the function).

DocID15441 Rev 924/117

6 7 8

16171819

VCAP

VSS

OSCOUT/PA2

OSCIN/PA1

[SPI_NSS] TIM2_CH3/(HS) PA3

NRST

PD4 (HS)/BEEP / TIM2_CH1/UART1_CK

PD5 (HS)/AIN5/UART1_TX

PD3 (HS)/AIN4/TIM2_CH2/ADC_ETR

PD2 (HS)/AIN3 [TIM2_CH3]

PC4 (HS)/TIM1_CH4/CLK_CCO/AIN2 [TIM1_CH2N]

PC5 (HS)/SPI_SCK [TIM2_CH1]

PC6 (HS)/SPI_MOSI [TIM1_CH1]

PC7 (HS)/SPI_MISO [TIM1_CH2]

PD1(HS)/SWIM

[TIM1_BKIN] I2C_SDA/(T) PB5

[TIM1_CH1N] [TLI] TIM1_CH3/(HS) PC3

PD6 (HS)/AIN6/UART1_RX

[ADC_ETR] I2C_SCL/(T) PB4

Pinout and pin descriptionSTM8S103K3 STM8S103F3 STM8S103F2

STM8S103Fx UFQFPN20 pinout5.2.2

Figure 6: STM8S103Fx UFQFPN20-pin pinout

Pin no.

1. HS high sink capability.

2. (T) True open drain (P-buffer and protection diode to VDDnot implemented).

3. [ ] alternate function remapping option (if the same alternate function is shown twice, it

indicates an exclusive choice not a duplication of the function).

STM8S103Fx TSSOP20/SO20/UFQFPN20 pin description5.2.3

Table 6: STM8S103Fx pin description

181

192

TIM2_ CH1/ UART1 _CK

UART1 _TX

TypePin name

Ext.

wpufloatingUFQFPN20TSSOP/SO20

interr.

OutputInput

High sink

(1)

Main function (after

PPODSpeed

reset)

Port D4XXO3HSXXXI/OPD4/ BEEP/

Port D5XXO3HSXXXI/OPD5/ AIN5/

Default alternate function

Timer 2 channel 1/BEEP output/ UART1 clock

Analog input 5/ UART1 data transmit

Alternate function after remap [option bit]

25/117DocID15441 Rev 9

STM8S103K3 STM8S103F3 STM8S103F2Pinout and pin description

Pin no.

OutputInput

TypePin name

203

710

811

1013

1114

1215

1316

1417

1619

1720

UART1 _RX

PA1/ OSCIN

[SPI_ NSS]

[TIM1_ BKIN]

[TLI] [TIM1_ CH1N]

TIM1_ CH4/AIN2/[TIM1_ CH2N]

[TIM2_ CH1]

[TIM1_ CH1]

[TIM1_ CH2]

CH3]

CH2/ ADC_ ETR

(2)

wpufloatingUFQFPN20TSSOP/SO20

Ext. interr.

High sink

(1)

O1XXI/OPB5/ I2C_ SDA

(3)

O1XXI/OPB4/ I2C_ SCL912

(3)

Main function (after

PPODSpeed

reset)

Port D6XXO3HSXXXI/OPD6/ AIN6/

ResetXI/ONRST14

Port A1XXO1XXXI/O

Port A2XXO1XXXI/OPA2/ OSCOUT36

Digital groundSV

1.8 V regulator capacitorSVCAP58

Digital power supplySV

Port A3XXO3HSXXXI/OPA3/ TIM2_ CH3

Port C3XXO3HSXXXI/OPC3/ TIM1_CH3

Port C4XXO3HSXXXI/OPC4/ CLK_CCO/

Port C6XXO3HSXXXI/OPC6/ SPI_MOSI

Port C7XXO3HSXXXI/OPC7/ SPI_MISO

Port D1XXO4HSXXXI/OPD1/ SWIM1518

Port D3XXO3HSXXXI/OPD3/ AIN4/ TIM2_

Default alternate function

Analog input 6/ UART1 data receive

Resonator/ crystal in

Resonator/ crystal out

Timer 2 channel 3

I2C dataPort B5T

I2C clockPort B4T

Timer 1 channel 3

Configurable clock output/Timer 1

- channel 4/Analog input 2

SPI clockPort C5XXO3HSXXXI/OPC5/ SPI_SCK

SPI master out/slave in

SPI master in/ slave out

SWIM data interface

Analog input 3Port D2XXO3HSXXXI/OPD2/AIN3/[TIM2_

Analog input 4/ Timer 2 channel 2/ADC external trigger

Alternate function after remap [option bit]

SPI master/ slave select [AFR1]

Timer 1 - break input [AFR4]

ADC external trigger [AFR4]

Top level interrupt [AFR3] Timer 1 inverted channel 1 [AFR7]

Timer 1 - inverted channel 2 [AFR7]

Timer 2 - channel 1 [AFR0]

Timer 1 - channel 1 [AFR0]

Timer 1 - channel 2 [AFR0]

Timer 2 - channel 3 [AFR1]

(1)

I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings. (2)

When the MCU is in halt/active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode if halt/active-halt is used in the application. (3)

In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDDare not implemented).

DocID15441 Rev 926/117

Pinout and pin descriptionSTM8S103K3 STM8S103F3 STM8S103F2

Alternate function remapping5.3

As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. When the remapping option is active, the default alternate function is no longer available.

To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers.

Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO section of the family reference manual, RM0016).

27/117DocID15441 Rev 9

0x00 9FFF

Flash program memory

(8 Kbytes)

0x00 0000

RAM

0x00 03FF

(1 Kbyte)

513 bytes stack

0x00 4000 0x00 427F

640 bytes data EEPROM

Reserved

0x00 4280

0x00 A000

0x02 7FFF

0x00 47FF

0x00 8000

32 interrupt vectors

0x00 807F

GPIO and periph. reg.

0x00 5000

0x00 57FF

0x00 5800

0x00 7FFF

0x00 480B

0x00 4FFF

0x00 7EFF

CPU/SWIM/debug/ITC

registers

0x00 7F00

Reserved

Option bytes

0x00 480A

0x00 4800

0x00 0800

0x00 3FFF

0x00 8080

Reserved

Unique ID

0x00 4864 0x00 4865 0x00 4870 0x00 4871

STM8S103K3 STM8S103F3 STM8S103F2Memory and register map

Memory and register map6

Memory map6.1

Figure 7: Memory map

DocID15441 Rev 928/117

Memory and register mapSTM8S103K3 STM8S103F3 STM8S103F2

Register map6.2

I/O port hardware register map6.2.1

Table 7: I/O port hardware register map

0x00 5000

0x00 5005

0x00 500A

Port A

Port B

Port C

Reset status

0x00Port A data output latch registerPA_ODR

(1)

Port A input pin value registerPA_IDR0x00 5001

0xXX

0x00Port A data direction registerPA_DDR0x00 5002

0x00Port A control register 1PA_CR10x00 5003

0x00Port A control register 2PA_CR20x00 5004

0x00Port B data output latch registerPB_ODR

(1)

Port B input pin value registerPB_IDR0x00 5006

0xXX

0x00Port B data direction registerPB_DDR0x00 5007

0x00Port B control register 1PB_CR10x00 5008

0x00Port B control register 2PB_CR20x00 5009

0x00Port C data output latch registerPC_ODR

(1)

Port C input pin value registerPB_IDR0x00 500B

0xXX

0x00Port C data direction registerPC_DDR0x00 500C

0x00 500F

0x00 5014

Port D

Port E

0x00Port C control register 1PC_CR10x00 500D

0x00Port C control register 2PC_CR20x00 500E

0x00Port D data output latch registerPD_ODR

(1)

Port D input pin value registerPD_IDR0x00 5010

0xXX

0x00Port D data direction registerPD_DDR0x00 5011

0x02Port D control register 1PD_CR10x00 5012

0x00Port D control register 2PD_CR20x00 5013

0x00Port E data output latch registerPE_ODR

(1)

Port E input pin value registerPE_IDR0x00 5015

0xXX

0x00Port E data direction registerPE_DDR0x00 5016

0x00Port E control register 1PE_CR10x00 5017

29/117DocID15441 Rev 9

STM8S103K3 STM8S103F3 STM8S103F2Memory and register map

0x00 5019

Port F

(1)

Depends on the external circuitry.

General hardware register map6.2.2

Port F input pin value registerPF_IDR0x00 501A

Table 8: General hardware register map

Reset status

0x00Port E control register 2PE_CR2Port E0x00 5018

0x00Port F data output latch registerPF_ODR

0xXX

0x00Port F data direction registerPF_DDR0x00 501B

0x00Port F control register 1PF_CR10x00 501C

0x00Port F control register 2PF_CR20x00 501D

Reset status

(1)

0x00 5059

0x00 5061

Reserved area (60 bytes)0x00 501E to

Flash0x00 505A

0x00Flash control register 1FLASH_CR1

0x00Flash control register 2FLASH_CR20x00 505B

FLASH_NCR20x00 505C

0xFFFlash complementary control register

0x00Flash protection registerFLASH _FPR0x00 505D

FLASH _NFPR0x00 505E

0xFFFlash complementary protection

FLASH _IAPSR0x00 505F

0x00Flash in-application programming

status register

Reserved area (2 bytes)0x00 5060 to

DocID15441 Rev 930/117

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