ST STM8S007C8 User Manual
Value line, 24 MHz STM8S 8-bit MCU, 64 Kbytes Flash,
LQFP48 7x7
true data EEPROM, 10-bit ADC, timers, 2 UARTs, SPI, I²C
Features
■ Core
–Max f
f
CPU
– Advanced STM8 core with Harvard
architecture and 3-stage pipeline
– Extended instruction set
– Max 20 MIPS @ 24 MHz
■ Memories
– Program: 64 Kbytes Flash; data retention
20 years at 55 °C after 100 cycles
– Data: 128 bytes true data EEPROM;
endurance 100 kcycles
– RAM: 6 Kbytes
■ Clock, reset and supply management
– 2.95 to 5.5 V operating voltage
– Low power crystal resonator oscillator
– External clock input
– Internal, user-trimmable 16 MHz RC
– Internal low power 128 kHz RC
– Clock security system with clock monitor
– Wait, active-halt, & halt low power modes
– Peripheral clocks switched off individually
– Permanently active, low consumption
power-on and power-down reset
■ Interrupt management
– Nested interrupt controller with 32
interrupts
– Up to 37 external interrupts on 6 vectors
■ Timers
– 2x 16-bit general purpose timers, with 2+3
CAPCOM channels (IC, OC or PWM)
– Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-
time insertion and flexible synchronization
– 8-bit basic timer with 8-bit prescaler
– Auto wakeup timer
– Window watchdog, independent watchdog
: up to 24 MHz, 0 wait states @
CPU
≤ 16 MHz
STM8S007C8
Datasheet − production data
■ Communications interfaces
– UART with clock output for synchronous
operation - LIN master mode
– UART with LIN 2.1 compliant, master/slave
modes and automatic resynchronization
– SPI interface up to 10 Mbit/s
2
–I
C interface up to 400 Kbit/s
■ 10-bit ADC with up to 16 channels
■ I/Os
– 38 I/Os including 16 high sink outputs
– Highly robust I/O design, immune against
current injection
– Development support
– Single wire interface module (SWIM) and
debug module (DM)
May 2012 Doc ID 022171 Rev 3 1/90
This is information on a product in full production.
www.st.com
1
Contents STM8S007C8
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 12
4.3 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4 Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . 12
4.5 Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.6 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.7 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.8 Auto wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.9 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.10 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.11 TIM2, TIM3 - 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . 16
4.12 TIM4 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.13 Analog-to-digital converter (ADC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.14 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.14.1 UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.14.2 UART3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.14.3 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.14.4 I
2
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1 Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/90 Doc ID 022171 Rev 3
STM8S007C8 Contents
7 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.1.4 Typical current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.1.5 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.1.6 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.1.7 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.3.1 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.3.2 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.3.3 External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 55
9.3.4 Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 57
9.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.3.7 Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.3.8 SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
9.3.9 I
9.3.10 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
9.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
2
C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
10.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
10.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
10.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 85
11 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Doc ID 022171 Rev 3 3/90
Contents STM8S007C8
11.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4/90 Doc ID 022171 Rev 3
STM8S007C8 List of tables
List of tables
Table 1. STM8S007xx value line features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers . . . . . . . . . . . . . . . 14
Table 3. TIM timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Legend/abbreviations for LQFP48 pin description table . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 5. LQFP48 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 6. Flash, Data EEPROM and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 7. I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 8. General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 9. CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 10. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 11. Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 12. Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 13. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 14. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 15. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 16. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 17. Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 18. Total current consumption with code execution in run mode at V
Table 19. Total current consumption with code execution in run mode at V
Table 20. Total current consumption in wait mode at V
Table 21. Total current consumption in wait mode at V
Table 22. Total current consumption in active halt mode at V
Table 23. Total current consumption in active halt mode at V
Table 24. Total current consumption in halt mode at V
Table 25. Total current consumption in halt mode at V
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
DD
= 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
DD
DD
DD
= 5 V, TA -40 to 85° C . . . . . . . . . . 51
DD
= 3.3 V . . . . . . . . . . . . . . . . . . . . . . 51
DD
= 5 V, TA -40 to 85° C . . . . . . . . . . . . . . . 52
= 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 26. Wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 27. Total current consumption and timing in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 28. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 29. HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 30. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 31. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 32. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 33. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 34. Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 35. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 36. Output driving current (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 37. Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 38. Output driving current (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 39. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 40. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 41. I
2
C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 42. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 43. ADC accuracy with R
Table 44. ADC accuracy with R
< 10 kΩ , V
AIN
< 10 kΩ R
AIN
= 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
DDA
AIN
, V
= 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
DDA
Table 45. EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 46. EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 47. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 48. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
= 5 V. . . . . . . . . . . . . 48
DD
= 3.3 V . . . . . . . . . . . 49
DD
Doc ID 022171 Rev 3 5/90
List of tables STM8S007C8
Table 49. 48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 50. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 51. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6/90 Doc ID 022171 Rev 3
STM8S007C8 List of figures
List of figures
Figure 1. STM8S007xx value line block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 2. Flash memory organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3. LQFP 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 4. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 5. Supply current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 6. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 7. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 8. f
CPUmax
Figure 9. External capacitor C
Figure 10. Typ. I
Figure 11. Typ. I
Figure 12. HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 13. HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 14. Typical HSI frequency variation vs V
Figure 15. Typical LSI frequency variation vs V
Figure 16. Typical V
Figure 17. Typical pull-up resistance vs V
Figure 18. Typical pull-up current vs V
Figure 19. Typ. V
Figure 20. Typ. V
Figure 21. Typ. V
Figure 22. Typ. V
Figure 23. Typ. V
Figure 24. Typ. V
Figure 25. Typ. V
Figure 26. Typ. V
Figure 27. Typ. V
Figure 28. Typ. V
Figure 29. Typical NRST V
Figure 30. Typical NRST pull-up resistance vs V
Figure 31. Typical NRST pull-up current vs V
Figure 32. Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 33. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 34. SPI timing diagram - slave mode and CPHA = 1
Figure 35. SPI timing diagram - master mode
Figure 36. Typical application with I
Figure 37. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 38. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 39. 48-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 40. STM8S007xx value line ordering information scheme
versus V
DD(RUN)
DD(WFI)
IL
@ VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
OL
@ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
OL
@ VDD = 5 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
OL
@ VDD = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
OL
@ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
OL
@ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
OL
- V
DD
- V
DD
- V
DD
- V
DD
DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
vs VDD, HSI RC osc, f
vs VDD, HSI RC osc, f
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
EXT
= 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
CPU
= 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
CPU
at 3 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . 57
DD
@ 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DD
and VIH vs VDD @ 3 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
@ 3 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
DD
@ 3 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DD
@ VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
OH
@ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
OH
@ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
OH
@ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
OH
and VIH vs VDD @ 3 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
IL
2
C bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
@ 3 temperatures. . . . . . . . . . . . . . . . . . . . . . . . 69
DD
@ 3 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 70
DD
(1)
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . 88
Doc ID 022171 Rev 3 7/90
Introduction STM8S007C8
1 Introduction
This datasheet contains the description of the STM8S007xx value line features, pinout,
electrical characteristics, mechanical data and ordering information.
● For complete information on the STM8S microcontroller memory, registers and
peripherals, please refer to the STM8S and STM8A microcontroller families reference
manual (RM0016).
● For information on programming, erasing and protection of the internal Flash memory
please refer to the PM0051 (How to program STM8S and STM8A Flash program
memory and data EEPROM).
● For information on the debug and SWIM (single wire interface module) refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
● For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
8/90 Doc ID 022171 Rev 3
STM8S007C8 Description
2 Description
The STM8S007xx value line 8-bit microcontrollers offer 64 Kbytes Flash program memory.
They are referred to as high-density devices in the STM8S microcontroller family reference
manual.
All devices of the STM8S007xx value line provide the following benefits: reduced system
cost, performance robustness, short development cycles, and product longevity.
The system cost is reduced thanks to a true data EEPROM for up to 100 k write/erase
cycles and a high system integration level with internal clock oscillators, watchdog, and
brown-out reset.
Device performance is ensured by 20 MIPS at 24 MHz CPU clock frequency and enhanced
characteristics which include robust I/O, independent watchdogs (with a separate clock
source), and a clock security system.
Short development cycles are guaranteed due to application scalability across a common
family product architecture with compatible pinout, memory map and modular peripherals.
Full documentation is offered with a wide choice of development tools.
Product longevity is ensured in the STM8S family thanks to their advanced core which is
made in a state-of-the art technology for applications with 2.95 V to 5.5 V operating supply.
Table 1. STM8S007xx value line features
Features STM8S007C8
Pin count 48
Max. number of GPIOs (I/O) 38
External interrupt pins 35
Timer CAPCOM channels 9
Timer complementary outputs 3
A/D converter channels 10
HIgh sink I/Os 16
High density Flash program memory 64 Kbytes
Data EEPROM 128 bytes
RAM 6 Kbytes
Doc ID 022171 Rev 3 9/90
Block diagram STM8S007C8
XTAL 1-24 MHz
RC int. 16 MHz
RC int. 128 kHz
STM8 core
Debug/SWIM
I
2
C
SPI
UART1
UART3
AWU ti mer
Reset block
Reset
POR
BOR
Clock controller
Detector
Clock to peripherals and core
10 Mbit/s
LIN master
16 channels
Address and data bus
Window WDG
64 Kbytes high
128 bytes
6 Kbytes RAM
Boot ROM
ADC2
Reset
400 Kbit/s
Master/slave
Single wire
autosynchro
debug interf.
SPI emul.
density program Flash
data EEPROM
16-bit general purpose
16-bit advanced control
timer (TIM1)
timers (TIM2, TIM3)
8-bit basic timer
(TIM4)
Beeper
1/2/4 kHz
beep
Independent WDG
4 CAPCOM
channels
Up to
5 CAPCOM
channels
Up to
+ 3 complementary
outputs
3 Block diagram
Figure 1. STM8S007xx value line block diagram
10/90 Doc ID 022171 Rev 3
STM8S007C8 Product overview
4 Product overview
The following section intends to give an overview of the basic features of the STM8S007xx
value line functional modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).
4.1 Central processing unit STM8
The 8-bit STM8 core is designed for code efficiency and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers
● Harvard architecture
● 3-stage pipeline
● 32-bit wide program memory bus - single cycle fetching for most instructions
● X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
● 8-bit accumulator
● 24-bit program counter - 16-Mbyte linear memory space
● 16-bit stack pointer - access to a 64 K-level stack
● 8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
● 20 addressing modes
● Indexed indirect addressing mode for look-up tables located anywhere in the address
space
● Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
● 80 instructions with 2-byte average instruction size
● Standard data movement and logic/arithmetic functions
● 8-bit by 8-bit multiplication
● 16-bit by 8-bit and 16-bit by 16-bit division
● Bit manipulation
● Data transfer between stack and accumulator (push/pop) with direct stack access
● Data transfer using the X and Y registers or direct memory-to-memory transfers
Doc ID 022171 Rev 3 11/90
Product overview STM8S007C8
4.2 Single wire interface module (SWIM) and debug module (DM)
The single wire interface module and debug module permits non-intrusive, real-time incircuit debugging and fast memory programming.
SWIM
Single wire interface module for direct access to the debug module and memory
programming. The interface can be activated in all device operation modes. The maximum
data transmission speed is 145 bytes/ms.
Debug module
The non-intrusive debugging module features a performance close to a full-featured
emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers.
● R/W to RAM and peripheral registers in real-time
● R/W access to all resources by stalling the CPU
● Breakpoints on all program-memory instructions (software breakpoints)
● Two advanced breakpoints, 23 predefined configurations
4.3 Interrupt controller
● Nested interrupts with three software priority levels
● 32 interrupt vectors with hardware priority
● Up to 33 external interrupts on six vectors including TLI
● Trap and reset interrupts
4.4 Flash program and data EEPROM memory
● 64 Kbytes of high density Flash program single voltage Flash memory
● 128 bytes true data EEPROM
● Read while write: Writing in data memory possible while executing code in program
memory.
● User option byte area
Write protection (WP)
Write protection of Flash program memory and data EEPROM is provided to avoid
unintentional overwriting of memory that could result from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (memory access
security system). MASS is always enabled and protects the main Flash program memory,
data EEPROM and option bytes.
To perform in-application programming (IAP), this write protection can be removed by writing
a MASS key sequence in a control register. This allows the application to write to data
EEPROM, modify the contents of main program memory or the device option bytes.
A second level of write protection, can be enabled to further protect a specific area of
memory known as UBC (user boot code). Refer to Figure 2.
12/90 Doc ID 022171 Rev 3
STM8S007C8 Product overview
Programmable area from 1 Kbyte
Data
UBC area
Program memory area
Data memory area (up to 2 Kbytes)
(2 first pages) up to 64 Kbytes
EEPROM
Remains write protected during IAP
memory
64 Kbytes
Flash
Write access possible for IAP
program
memory
(1 page steps)
Option bytes
The size of the UBC is programmable through the UBC option byte (Ta b le 1 2), in increments
of 1 page (512 bytes) by programming the UBC option byte in ICP mode.
This divides the program memory into two areas:
● Main program memory: 64 Kbytes minus UBC
● User-specific boot code (UBC): Configurable up to 64 Kbytes
The UBC area remains write-protected during in-application programming. This means that
the MASS keys do not unlock the UBC area. It protects the memory used to store the boot
program, specific code libraries, reset and interrupt vectors, the reset routine and usually the
IAP and communication routines.
Figure 2. Flash memory organisation
Read-out protection (ROP)
The read-out protection blocks reading and writing the Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Once the read-out protection is
activated, any attempt to toggle its status triggers a global erase of the program and data
memory. Even if no protection can be considered as totally unbreakable, the feature
provides a very high level of protection for a general purpose microcontroller.
Doc ID 022171 Rev 3 13/90
Product overview STM8S007C8
4.5 Clock controller
The clock controller distributes the system clock (f
MASTER)
coming from different oscillators
to the core and the peripherals. It also manages clock gating for low power modes and
ensures clock robustness.
Features
● Clock prescaler: To get the best compromise between speed and current
consumption the clock frequency to the CPU and peripherals can be adjusted by a
programmable prescaler.
● Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock
source is ready. The design guarantees glitch-free switching.
● Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
● Master clock sources: Four different clock sources can be used to drive the master
clock:
– 1-24 MHz high-speed external crystal (HSE)
– Up to 24 MHz high-speed user-external clock (HSE user-ext)
– 16 MHz high-speed internal RC oscillator (HSI)
– 128 kHz low-speed internal RC (LSI)
● Startup clock: After reset, the microcontroller restarts by default with an internal 2
MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the
application program as soon as the code execution starts.
● Clock security system (CSS): This feature can be enabled by software. If an HSE
clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS
and an interrupt can optionally be generated.
● Configurable main clock output (CCO): This outputs an external clock for use by the
application.
Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers
Bit
PCKEN17 TIM1 PCKEN13 UART3 PCKEN27 Reserved PCKEN23 ADC
PCKEN16 TIM3 PCKEN12 UART1 PCKEN26 Reserved PCKEN22 AWU
PCKEN15 TIM2 PCKEN11 SPI PCKEN25 Reserved PCKEN21 Reserved
PCKEN14 TIM4 PCKEN10 I
14/90 Doc ID 022171 Rev 3
Peripheral
clock
Bit
Peripheral
clock
2
C PCKEN24 Reserved PCKEN20 Reserved
Bit
Peripheral
clock
Bit
Peripheral
clock
STM8S007C8 Product overview
4.6 Power management
For efficent power management, the application can be put in one of four different low-power
modes. You can configure each mode to obtain the best compromise between lowest power
consumption, fastest start-up time and available wakeup sources.
● Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The
wakeup is performed by an internal or external interrupt or reset.
● Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are
stopped. An internal wakeup is generated at programmable intervals by the auto wake
up unit (AWU). The main voltage regulator is kept powered on, so current consumption
is higher than in active halt mode with regulator off, but the wakeup time is faster.
Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.
● Active halt mode with regulator off: This mode is the same as active halt with
regulator on, except that the main voltage regulator is powered off, so the wake up time
is slower.
● Halt mode: In this mode the microcontroller uses the least power. The CPU and
peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is
triggered by external event or reset.
4.7 Watchdog timers
The watchdog system is based on two independent timers providing maximum security to
the applications.
Activation of the watchdog timers is controlled by option bytes or by software. Once
activated, the watchdogs cannot be disabled by the user program without performing a
reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application
perfectly.
The application software must refresh the counter before time-out and during a limited time
window.
A reset is generated in two situations:
1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up
to 64 ms.
2. Refresh out of window: The downcounter is refreshed before its value is lower than the
one stored in the window register.
Doc ID 022171 Rev 3 15/90
Product overview STM8S007C8
Independent watchdog timer
The independent watchdog peripheral can be used to resolve processor malfunctions due to
hardware or software failures.
It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure
The IWDG time base spans from 60 µs to 1 s.
4.8 Auto wakeup counter
● Used for auto wakeup from active halt mode
● Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock
● LSI clock can be internally connected to TIM3 input capture channel 1 for calibration
4.9 Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.
4.10 TIM1 - 16-bit advanced control timer
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver
● 16-bit up, down and up/down autoreload counter with 16-bit prescaler
● Four independent capture/compare channels (CAPCOM) configurable as input
capture, output compare, PWM generation (edge and center aligned mode) and single
pulse mode output
● Synchronization module to control the timer with external signals
● Break input to force the timer outputs into a defined state
● Three complementary outputs with adjustable dead time
● Encoder mode
● Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break
4.11 TIM2, TIM3 - 16-bit general purpose timers
● 16-bit autoreload (AR) up-counter
● 15-bit prescaler adjustable to fixed power of 2 ratios 1…32768
● Timers with 3 or 2 individually configurable capture/compare channels
● PWM mode
● Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update
16/90 Doc ID 022171 Rev 3
STM8S007C8 Product overview
4.12 TIM4 - 8-bit basic timer
● 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128
● Clock source: CPU clock
● Interrupt source: 1 x overflow/update
Table 3. TIM timer features
Counter
Timer
TIM1 16 Any integer from 1 to 65536 Up/down 4 3 Yes
TIM2 16 Any power of 2 from 1 to 32768 Up 3 0 No
TIM3 16 Any power of 2 from 1 to 32768 Up 2 0 No
TIM4 8 Any power of 2 from 1 to 128 Up 0 0 No
size
(bits)
Prescaler
Counting
mode
CAPCOM
channels
Complem.
outputs
4.13 Analog-to-digital converter (ADC2)
STM8S007xx value line products contain a 10-bit successive approximation A/D converter
(ADC2) with up to 10 multiplexed input channels and the following main features:
● Input voltage range: 0 to V
●
Conversion time: 14 clock cycles
● Single and continuous modes
● External trigger input
● Trigger from TIM1 TRGO
● End of conversion (EOC) interrupt
DDA
Ext.
trigger
Timer
synchr-
onization/
chaining
No
4.14 Communication interfaces
The following communication interfaces are implemented:
● UART1: Full feature UART, SPI emulation, LIN2.1 master capability, Smartcard mode,
IrDA mode, single wire mode.
● UART3: Full feature UART, LIN2.1 master/slave capability
● SPI : Full and half-duplex, 10 Mbit/s
● I²C: Up to 400 Kbit/s
Doc ID 022171 Rev 3 17/90
Product overview STM8S007C8
4.14.1 UART1
Main features
● One Mbit/s full duplex SCI
● SPI emulation
● High precision baud rate generator
● Smartcard emulation
● IrDA SIR encoder decoder
● LIN master mode
● Single wire half duplex mode
Asynchronous communication (UART mode)
● Full duplex communication - NRZ standard format (mark/space)
● Programmable transmit and receive baud rates up to 1 Mbit/s (f
following any standard baud rate regardless of the input frequency
● Separate enable bits for transmitter and receiver
● Two receiver wakeup modes:
– Address bit (MSB)
– Idle line (interrupt)
● Transmission error detection with interrupt generation
● Parity control
/16) and capable of
CPU
Synchronous communication
● Full duplex synchronous transfers
● SPI master operation
● 8-bit data communication
● Maximum speed: 1 Mbit/s at 16 MHz (f
LIN master mode
● Emission: Generates 13-bit synch break frame
● Reception: Detects 11-bit break frame
4.14.2 UART3
Main features
● 1 Mbit/s full duplex SCI
● LIN master capable
● High precision baud rate generator
CPU
/16)
18/90 Doc ID 022171 Rev 3
STM8S007C8 Product overview
Asynchronous communication (UART mode)
● Full duplex communication - NRZ standard format (mark/space)
● Programmable transmit and receive baud rates up to 1 Mbit/s (f
/16) and capable of
CPU
following any standard baud rate regardless of the input frequency
● Separate enable bits for transmitter and receiver
● Two receiver wakeup modes:
– Address bit (MSB)
– Idle line (interrupt)
● Transmission error detection with interrupt generation
● Parity control
LIN master capability
● Emission: Generates 13-bit synch break frame
● Reception: Detects 11-bit break frame
LIN slave mode
● Autonomous header handling - one single interrupt per valid message header
● Automatic baud rate synchronization - maximum tolerated initial clock deviation ±15 %
● Synch delimiter checking
● 11-bit LIN synch break detection - break detection always active
● Parity check on the LIN identifier field
● LIN error management
● Hot plugging support
4.14.3 SPI
● Maximum speed: 10 Mbit/s (f
● Full duplex synchronous transfers
● Simplex synchronous transfers on two lines with a possible bidirectional data line
● Master or slave operation - selectable by hardware or software
● CRC calculation
● 1 byte Tx and Rx buffer
● Slave/master selection input pin
MASTER
/2) both for master and slave
Doc ID 022171 Rev 3 19/90
Product overview STM8S007C8
4.14.4 I2C
2
● I
C master features:
– Clock generation
– Start and stop generation
2
● I
C slave features:
– Programmable I
– Stop bit detection
● Generation and detection of 7-bit/10-bit addressing and general call
● Supports different communication speeds:
– Standard speed (up to 100 kHz)
– Fast speed (up to 400 kHz)
2
C address detection
20/90 Doc ID 022171 Rev 3
STM8S007C8 Pinouts and pin description
44 43 42 41 4039 38 37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
12
13 14 1516 1718 1920 21 22
1
2
3
4
5
6
7
8
9
10
11
48 47 46 45
UART1_CK/(HS) PA6
AIN8/PE7
PC1 (HS)/TIM1_CH1
PE5/SPI_NSS
PG1
AIN9/PE6
PD3 (HS)/TIM2_CH2 [ADC_ETR]
PD2 (HS)/TIM3_CH1 [TIM2_CH3]
PE0 (HS)/CLK_CCO
PE1 (T)/I2C_SCL
PE2 (T)/I2C_SDA
PE3/TIM1_BKIN
PD7/TLI
PD6/UART3_RX
PD5/UART3_TX
PD4 (HS)/TIM2_CH1 [BEEP]
PD1 (HS)/SWIM
PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO]
V
SSIO_2
PC5 (HS)/SPI_SCK
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PG0
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
V
DDIO_2
AIN7/PB7
AIN6/PB6
[I2C_SDA] AIN5/PB5
[I2C_SCL] AIN4/PB4
[TIM1_ETR/AIN3/PB3
[TIM1_CH3N] AIN2/PB2
[TIM1_CH2N] AIN1/PB1
[TIM1_CH1N] AIN0/PB0
V
DDA
V
SSA
V
SS
VCAP
V
DD
V
DDIO_1
[TIM3_CH1] TIM2_CH3/PA3
UART1_RX/(HS) PA4
UART1_TX/(HS) PA5
NRST
OSCIN/PA1
OSCOUT/PA2
V
SSIO_1
5 Pinouts and pin description
Figure 3. LQFP 48-pin pinout
1. (HS) high sink capability.
2. (T) True open drain (P-buffer and protection diode to V
3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).
Doc ID 022171 Rev 3 21/90
not implemented).
DD
Pinouts and pin description STM8S007C8
Table 4. Legend/abbreviations for LQFP48 pin description table
Typ e I = input, O = output, S = power supply
floating
Input
wpu = weak pull-up
Ext. interrupt = external interrupt
HS = high sink
O1 = Slow (up to 2 MHz)
Speed
O3 = Fast/slow programmability with slow as default state after reset
Output
O4 = Fast/slow programmability with fast as default state after reset
OD = open drain
PP = push pull
Reset state Bold X
(pin state after internal reset release)
Unless otherwise specified, the pin state is the same during the reset phase and
after the internal reset release.
Table 5. LQFP48 pin description
Input Output
Default
Pin number
Pin name
Typ e
wpu
floating
Ext. interrupt
High sink
OD
Speed
PP
Main function
alternate
function
(after reset)
1 NRST I/O X Reset
2 PA1/OSCIN I/O X XO1XXPort A1
3 PA2/OSCOUT I/O X
4V
SSIO_1
5V
SS
S I/O ground
S Digital ground
XX O1XXPort A2
Resonator/
crystal in
Resonator/
crystal out
6 VCAP S 1.8 V regulator capacitor
Alternate
function
after remap
[option bit]
7V
DD
8V
DDIO_1
S Digital power supply
S I/O power supply
9 PA3/TIM2_CH3 I/O X XX O1XXPort A3
(1)
10 PA4/UART1_RX
I/O X XXHSO3XXPort A4 UART1 receive
11 PA5/UART1_TX I/O X XXHSO3XXPort A5
12 PA6/UART1_CK I/O X
13 V
DDA
S Analog power supply
XXHSO3XXPort A6
22/90 Doc ID 022171 Rev 3
Timer 2 channel3
UART1
transmit
UART1
synchronous
clock
TIM3_CH1
[AFR1]
STM8S007C8 Pinouts and pin description
Table 5. LQFP48 pin description (continued)
Input Output
Alternate
function
after remap
[option bit]
Pin number
14 V
Pin name
SSA
Typ e
wpu
floating
Speed
High sink
Ext. interrupt
OD
PP
Main function
S Analog ground
15 PB7/AIN7 I/O X XX O1XXPort B7
Default
alternate
function
(after reset)
Analog
input 7
16 PB6/AIN6 I/O X
17 PB5/AIN5 I/O X
18 PB4/AIN4 I/O X
19 PB3/AIN3 I/O X
XX O1XXPort B6
XX O1XXPort B5
XX O1XXPort B4
XX O1XXPort B3
20 PB2/AIN2 I/O X XX O1XXPort B2
21 PB1/AIN1 I/O X
22 PB0/AIN0 I/O X
23 PE7/AIN8 I/O X
24 PE6/AIN9 I/O X
25 PE5/SPI_NSS I/O X
26 PC1/TIM1_CH1 I/O X
27 PC2/TIM1_CH2 I/O X
XX O1XXPort B1
XX O1XXPort B0
XX O1XXPort E7 Analog input 8
XX O1XXPort E6 Analog input 9
XX O1XXPort E5
XXHSO3XXPort C1
XXHSO3XXPort C2
Analog
input 6
Analog
input 5
Analog
input 4
Analog
input 3
Analog
input 2
Analog
input 1
Analog
input 0
SPI
master/slave
select
Timer 1 channel 1
Timer 1channel 2
2
C_SDA
I
[AFR6]
2
C_SCL
I
[AFR6]
TIM1_ETR
[AFR5]
TIM1_
CH3N
[AFR5]
TIM1_
CH2N
[AFR5]
TIM1_
CH1N
[AFR5]
28 PC3/TIM1_CH3 I/O X
29 PC4/TIM1_CH4 I/O X
30 PC5/SPI_SCK I/O X
31 V
32 V
SSIO_2
DDIO_2
S I/O ground
S I/O power supply
XXHSO3XXPort C3
XXHSO3XXPort C4
Timer 1 channel 3
Timer 1 channel 4
XXHSO3XXPort C5 SPI clock
Doc ID 022171 Rev 3 23/90
Pinouts and pin description STM8S007C8
Table 5. LQFP48 pin description (continued)
Input Output
Alternate
function
after remap
[option bit]
Pin name
Pin number
Typ e
wpu
floating
Speed
High sink
Ext. interrupt
OD
PP
Main function
33 PC6/SPI_MOSI I/O X XXHSO3XXPort C6
Default
alternate
function
(after reset)
SPI master
out/
slave in
34 PC7/SPI_MISO I/O X XXHSO3XXPort C7
35 PG0 I/O X XO1XXPort G0
36 PG1 I/O X
XO1XXPort G1
37 PE3/TIM1_BKIN I/O X XX O1XXPort E3
38 PE2/I
39 PE1/I
2
C_SDA I/O X XO1T
2
C_SCL I/O X XO1T
(2)
(2)
Port E2 I2C data
Port E1 I2C clock
40 PE0/CLK_CCO I/O X XXHSO3XXPort E0
41 PD0/TIM3_CH2 I/O X
42 PD1/SWIM
(3)
I/O X X XHSO4X XPort D1
43 PD2/TIM3_CH1 I/O X
44 PD3/TIM2_CH2 I/O X
PD4/TIM2_CH1/B
45
EEP
I/O X
46 PD5/ UART3_TX I/O X
47
PD6/
UART3_RX
(1)
I/O X XX O1XXPor t D6
XXHSO3XXPort D0
XXHSO3XXPort D2
XXHSO3XXPort D3
XXHSO3XXPort D4
XX O1XXPort D5
SPI master in/
slave out
Timer 1 break input
Configurable
clock output
Timer 3 channel 2
SWIM data
interface
Timer 3 channel 1
Timer 2 channel 2
Timer 2 channel 1
UART3 data
transmit
UART3 data
receive
TIM1_BKIN
[AFR3]/
CLK_CCO
[AFR2]
TIM2_CH3
[AFR1]
ADC_ETR
[AFR0]
BEEP output
[AFR7]
48 PD7/TLI I/O X
1. The default state of UART1_RX and UART3_RX pins is controlled by the ROM bootloader. These pins are
pulled up as part of the bootloader activation process and returned to the floating state before a return from
the bootloader.
2. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection
diode to V
3. The PD1 pin is in input pull-up during the reset phase and after the internal reset release.
are not implemented).
DD
XX O1XXPort D7
Top lev e l
interrupt
Note: The slope control of true open drain pins cannot be programmed and by default is limited to
2 MHz.
24/90 Doc ID 022171 Rev 3
STM8S007C8 Pinouts and pin description
5.1 Alternate function remapping
As shown in the rightmost column of the pin description table, some alternate functions can
be remapped at different I/O ports by programming one of eight AFR (alternate function
remap) option bits. Refer to Section 8: Option bytes. When the remapping option is active,
the default alternate function is no longer available.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral
registers.
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the
GPIO section of the family reference manual, RM0016).
Doc ID 022171 Rev 3 25/90
Memory and register map STM8S007C8
0x0 0 000 0
0x
00 17 FF
0x
00 180 0
0x
00 400 0
0x
00 3F FF
0x
00 407F
0x
00 4080
0x
00 47FF
0x
00 480 0
0x
00 4 87F
0x
00 490 0
0x
00 500 0
0x
00 4F FF
0x
00 57 FF
0x
00 580 0
0x
00 600 0
0x
00 5F FF
0x
00 67 FF
0x
00 680 0
0x
00 7EFF
0x
00 7 F0 0
0x
00 7F FF
0x
00 800 0
0x
00 808 0
0x
00 8 07F
0 x01 7FFF
MS19412V1
(see Table 8 and Table 9)
GPIO and peripheral registers
Reserved
Reserved
Reserved
Reserved
Reserved
1024 bytes stack
128 bytes data EEPROM
Option bytes
RAM
(6 Kbytes)
2 Kbytes boot ROM
CPU/SWIM/debug/ITC
register (see Table 10)
32 interrupt vectors
Flash program memory
(64 Kbytes)
6 Memory and register map
6.1 Memory map
Figure 4. Memory map
26/90 Doc ID 022171 Rev 3
STM8S007C8 Memory and register map
Ta bl e 6 lists the boundary addresses for each memory size. The top of the stack is at the
RAM end address in each case.
Table 6. Flash, Data EEPROM and RAM boundary addresses
Memory area Size (bytes) Start address End address
Flash program memory 64 K 0x00 8000 0x01 7FFF
RAM 6 K 0x00 0000 0x00 17FF
Data EEPROM 128 0x00 4000 0x00 407F
6.2 Register map
Table 7. I/O port hardware register map
Address Block Register label Register name
0x00 5000
PA_ODR Port A data output latch register 0x00
Reset
status
0x00 5001 PA_IDR Port A input pin value register 0x00
0x00 5002 PA_DDR Port A data direction register 0x00
Por t A
0x00 5003 PA_CR1 Port A control register 1 0x00
0x00 5004 PA_CR2 Port A control register 2 0x00
0x00 5005
PB_ODR Port B data output latch register 0x00
0x00 5006 PB_IDR Port B input pin value register 0x00
0x00 5007 PB_DDR Port B data direction register 0x00
Por t B
0x00 5008 PB_CR1 Port B control register 1 0x00
0x00 5009 PB_CR2 Port B control register 2 0x00
0x00 500A
PC_ODR Port C data output latch register 0x00
0x00 500B PB_IDR Port C input pin value register 0x00
0x00 500C PC_DDR Port C data direction register 0x00
Por t C
0x00 500D PC_CR1 Port C control register 1 0x00
0x00 500E PC_CR2 Port C control register 2 0x00
0x00 500F
PD_ODR Port D data output latch register 0x00
0x00 5010 PD_IDR Port D input pin value register 0x00
0x00 5011 PD_DDR Port D data direction register 0x00
Por t D
0x00 5012 PD_CR1 Port D control register 1 0x02
0x00 5013 PD_CR2 Port D control register 2 0x00
Doc ID 022171 Rev 3 27/90
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