ST STM8S005K6, STM8S005C6 User Manual

STM8S005K6 STM8S005C6

Value line, 16 MHz STM8S 8-bit MCU, 32 Kbytes Flash, data EEPROM,10-bit ADC, timers, UART, SPI, I²C

LQFP48 7x7	LQFP32 7x7

Features

Core

•16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline

•Extended instruction set

Memories

•Medium-density Flash/EEPROM:

-Program memory: 32 Kbytes of Flash memory; data retention 20 years at 55°C after 100 cycles

-Data memory: 128 bytes of true data EEPROM;enduranceupto100kwrite/erase cycles

•RAM: 2 Kbytes

Clock, reset and supply management

•2.95 V to 5.5 V operating voltage

•Flexible clock control, 4 master clock sources:

-Low power crystal resonator oscillator

-External clock input

-Internal, user-trimmable 16 MHz RC

-Internal low power 128 kHz RC

•Clock security system with clock monitor

•Power management:

-Low power modes (wait, active-halt, halt)

-Switch-off peripheral clocks individually

•Permanentlyactive,lowconsumptionpower-on and power-down reset

Interrupt management

•Nested interrupt controller with 32 interrupts

•Up to 37 external interrupts on 6 vectors

Timers

•2x 16-bit general purpose timers, with 2+3 CAPCOM channels (IC, OC or PWM)

•Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization

•8-bit basic timer with 8-bit prescaler

•Auto wake-up timer

•Window and independent watchdog timers

Communications interfaces

•UART with clock output for synchronous operation, Smartcard, IrDA, LIN

•SPI interface up to 8 Mbit/s

•I2C interface up to 400 Kbit/s

Analog-to-digital converter (ADC)

•10-bit, ±1 LSB ADC with up to 10 multiplexed channels, scan mode and analog watchdog

I/Os

•Up to 38 I/Os on a 48-pin package including 16 high sink outputs

•HighlyrobustI/Odesign,immuneagainstcurrent injection

Development support

•Embeddedsinglewireinterfacemodule(SWIM) for fast on-chip programming and non intrusive debugging

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Contents

STM8S005K6 STM8S005C6

Contents
1 Introduction ..............................................................................................................		7
2 Description ...............................................................................................................		8
3 Block diagram ..........................................................................................................		9
4 Product overview ...................................................................................................		10
4.1	Central processing unit STM8 .....................................................................................	10
4.2	Single wire interface module (SWIM) and debug module (DM) ..................................	10
4.3	Interrupt controller .......................................................................................................	11
4.4	Flash program and data EEPROM memory ................................................................	11
4.5	Clock controller ............................................................................................................	12
4.6	Power management ....................................................................................................	13
4.7 Watchdog timers ..........................................................................................................		14
4.8	Auto wakeup counter ...................................................................................................	14
4.9	Beeper ........................................................................................................................	14
4.10 TIM1 - 16-bit advanced control timer .........................................................................		15
4.11 TIM2, TIM3 - 16-bit general purpose timers ..............................................................		15
4.12 TIM4 - 8-bit basic timer ..............................................................................................		15
4.13 Analog-to-digital converter (ADC1) ............................................................................		16
4.14 Communication interfaces .........................................................................................		16
	4.14.1 UART2 ...............................................................................................	16
	4.14.2 SPI .....................................................................................................	17
	4.14.3 I²C ......................................................................................................	18
5 Pinout and pin description ...................................................................................		19
5.1	STM8S005 pinouts and pin description .......................................................................	20
	5.1.1 Alternate function remapping ...............................................................	24
6 Memory and register map .....................................................................................		25
6.1	Memory map ................................................................................................................	25
6.2 Register map ...............................................................................................................		26
	6.2.1 I/O port hardware register map ............................................................	26
	6.2.2 General hardware register map ...........................................................	29
	6.2.3 CPU/SWIM/debug module/interrupt controller registers ......................	39
7 Interrupt vector mapping ......................................................................................		42
8 Option bytes ...........................................................................................................		44
9 Electrical characteristics ......................................................................................		49
9.1	Parameter conditions ...................................................................................................	49
	9.1.1 Minimum and maximum values ...........................................................	49
	9.1.2 Typical values .......................................................................................	49
	9.1.3 Typical curves ......................................................................................	49

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9.1.4 Typical current consumption ................................................................	49
9.1.5 Loading capacitor .................................................................................	50
9.1.6 Pin input voltage ...................................................................................	50
9.2 Absolute maximum ratings ..........................................................................................	50
9.3 Operating conditions ...................................................................................................	52
9.3.1 VCAP external capacitor ......................................................................	54
9.3.2 Supply current characteristics ..............................................................	55
9.3.3 External clock sources and timing characteristics ...............................	66
9.3.4 Internal clock sources and timing characteristics .................................	68
9.3.5 Memory characteristics ........................................................................	70
9.3.6 I/O port pin characteristics ...................................................................	72
9.3.7 Typical output level curves ...................................................................	75
9.3.8 Reset pin characteristics ......................................................................	79
9.3.9 SPI serial peripheral interface ..............................................................	81
9.3.10 I2C interface characteristics ...............................................................	84
9.3.11 10-bit ADC characteristics ..................................................................	86
9.3.12 EMC characteristics ...........................................................................	89
10 Package information ...........................................................................................	93
10.1 48-pin LQFP package mechanical data ....................................................................	93
10.2 32-pin LQFP package mechanical data ....................................................................	95
11 Thermal characteristics .......................................................................................	97
11.1 Reference document .................................................................................................	97
11.2 Selecting the product temperature range ..................................................................	97
12 Ordering information ...........................................................................................	99
13 STM8 development tools ..................................................................................	100
13.1 Emulation and in-circuit debugging tools .................................................................	100
13.2 Software tools ..........................................................................................................	100
13.2.1 STM8 toolset ....................................................................................	101
13.2.2 C and assembly toolchains ..............................................................	101
13.3 Programming tools ..................................................................................................	101
14 Revision history .................................................................................................	102

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List of tables

STM8S005K6 STM8S005C6

List of tables
Table 1. STM8S005xx value line features ................................................................................................	8
Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ..................................	13
Table 3. TIM timer features ...................................................................................................................	15
Table 4. Legend/abbreviations for pinout tables ...................................................................................	19
Table 5. Pin description for STM8S005 microcontrollers .......................................................................	21
Table 6. Flash, Data EEPROM and RAM boundary addresses ............................................................	26
Table 7. I/O port hardware register map ................................................................................................	26
Table 8. General hardware register map ................................................................................................	29
Table 9. CPU/SWIM/debug module/interrupt controller registers ..........................................................	39
Table 10. Interrupt mapping ...................................................................................................................	42
Table 11. Option bytes ...........................................................................................................................	44
Table 12. Option byte description ...........................................................................................................	45
Table 13. Description of alternate function remapping bits [7:0] of OPT2 ..............................................	47
Table 14. Voltage characteristics ...........................................................................................................	50
Table 15. Current characteristics ...........................................................................................................	51
Table 16. Thermal characteristics ..........................................................................................................	52
Table 17. General operating conditions .................................................................................................	53
Table 18. Operating conditions at power-up/power-down ......................................................................	54
Table 19. Total current consumption with code execution in run mode at VDD = 5 V .............................	55
Table 20. Total current consumption with code execution in run mode at VDD = 3.3 V ..........................	66
Table 21. Total current consumption in wait mode at VDD = 5 V ............................................................	58
Table 22. Total current consumption in wait mode at VDD = 3.3 V .........................................................	58
Table 23. Total current consumption in active halt mode at VDD = 5 V ..................................................	59
Table 24. Total current consumption in active halt mode at VDD = 3.3 V ...............................................	60
Table 25. Total current consumption in halt mode at VDD = 5 V .............................................................	61
Table 26. Total current consumption in halt mode at VDD = 3.3 V ..........................................................	61
Table 27. Wakeup times .........................................................................................................................	61
Table 28. Total current consumption and timing in forced reset state ....................................................	92
Table 29. Peripheral current consumption .............................................................................................	63
Table 30. HSE user external clock characteristics .................................................................................	66
Table 31. HSE oscillator characteristics .................................................................................................	67
Table 32. HSI oscillator characteristics ..................................................................................................	68
Table 33. LSI oscillator characteristics ...................................................................................................	70
Table 34. RAM and hardware registers ..................................................................................................	70
Table 35. Flash program memory/data EEPROM memory ....................................................................	71
Table 36. I/O static characteristics .........................................................................................................	72
Table 37. Output driving current (standard ports) ..................................................................................	74
Table 38. Output driving current (true open drain ports) ........................................................................	74
Table 39. Output driving current (high sink ports) ..................................................................................	74
Table 40. NRST pin characteristics ........................................................................................................	79
Table 41. SPI characteristics ..................................................................................................................	81
Table 42. I2C characteristics ..................................................................................................................	84
Table 43. ADC characteristics ................................................................................................................	86
Table 44. ADC accuracy with RAIN < 10 kΩ , VDDA= 5 V .......................................................................	87
Table 45. ADC accuracy with RAIN < 10 kΩ RAIN, VDDA = 3.3 V ............................................................	88
Table 46. EMS data ................................................................................................................................	90
Table 47. EMI data .................................................................................................................................	91

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List of tables

Table 48. ESD absolute maximum ratings .............................................................................................		92
Table 49. Electrical sensitivities .............................................................................................................		92
Table 50. 48-pin low profile quad flat package mechanical data ............................................................		93
Table 51.	32-pin low profile quad flat package mechanical data .........................................................	102
Table 52.	Thermal characteristics(1) ......................................................................................................	97
Table 53.	Document revision history ...................................................................................................	102

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List of figures

STM8S005K6 STM8S005C6

List of figures
Figure 1. STM8S005xx value line block diagram .....................................................................................	9
Figure 2. Flash memory organization ....................................................................................................	12
Figure 3. LQFP 48-pin pinout .................................................................................................................	20
Figure 4. LQFP 32-pin pinout ................................................................................................................	21
Figure 5. Memory map ...........................................................................................................................	25
Figure 6. Supply current measurement conditions ................................................................................	49
Figure 7. Pin loading conditions .............................................................................................................	50
Figure 8. Pin input voltage .....................................................................................................................	50
Figure 9. fCPUmax versus VDD ................................................................................................................	54
Figure 10. External capacitor CEXT .......................................................................................................	55
Figure 11. Typ. IDD(RUN) vs. VDD , HSE user external clock, fCPU = 16 MHz ...........................................	64
Figure 12. Typ. IDD(RUN) vs. fCPU , HSE user external clock, VDD= 5 V ..................................................	64
Figure 13. Typ. IDD(RUN) vs. VDD , HSI RC osc, fCPU = 16 MHz ..............................................................	65
Figure 14. Typ. IDD(WFI) vs. VDD , HSE user external clock, fCPU = 16 MHz ............................................	65
Figure 15. Typ. IDD(WFI) vs. fCPU, HSE user external clock VDD = 5 V ....................................................	65
Figure 16. Typ. IDD(WFI) vs. VDD, HSI RC osc, fCPU = 16 MHz ................................................................	66
Figure 17. HSE external clocksource .....................................................................................................	67
Figure 18. HSE oscillator circuit diagram ...............................................................................................	68
Figure 19. Typical HSI frequency variation vs VDD @ 3 temperatures ..................................................	69
Figure 20. Typical LSI frequency variation vs VDD @ 3 temperatures ...................................................	70
Figure 21. Typical VIL and VIH vs VDD @ 3 temperatures ......................................................................	73
Figure 22. Typical pull-up resistance vs VDD @ 3 temperatures ............................................................	73
Figure 23. Typical pull-up current vs VDD @ 3 temperatures .................................................................	73
Figure 24. Typ. VOL @ VDD = 5 V (standard ports) ................................................................................	75
Figure 25. Typ. VOL @ VDD = 3.3 V (standard ports) .............................................................................	76
Figure 26. Typ. VOL @ VDD = 5 V (true open drain ports) ......................................................................	76
Figure 27. Typ. VOL @ VDD = 3.3 V (true open drain ports) ...................................................................	76
Figure 28. Typ. VOL @ VDD = 5 V (high sink ports) ................................................................................	77
Figure 29. Typ. VOL @ VDD = 3.3 V (high sink ports) .............................................................................	77
Figure 30. Typ. VDD - VOH @ VDD = 5 V (standard ports) .......................................................................	77
Figure 31. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) ....................................................................	78
Figure 32. Typ. VDD - VOH @ VDD = 5 V (high sink ports) ......................................................................	78
Figure 33. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) ...................................................................	78
Figure 34. Typical NRST VIL and VIH vs VDD @ 3 temperatures ...........................................................	80
Figure 35. Typical NRST pull-up resistance vs VDD @ 3 temperatures .................................................	80
Figure 36. Typical NRST pull-up current vs VDD @ 3 temperatures ......................................................	80
Figure 37. Recommended reset pin protection ......................................................................................	81
Figure 38. SPI timing diagram - slave mode and CPHA = 0 ..................................................................	83
Figure 39. SPI timing diagram - slave mode and CPHA = 1(1) .............................................................	83
Figure 40. SPI timing diagram - master mode(1) ...................................................................................	84
Figure 41. Typical application with I2C bus and timing diagram (1) .......................................................	85
Figure 42. ADC accuracy characteristics ...............................................................................................	89
Figure 43. Typical application with ADC ................................................................................................	89
Figure 44. 48-pin low profile quad flat package (7 x 7) ..........................................................................	93
Figure 45. 32-pin low profile quad flat package (7 x 7) ..........................................................................	95
Figure 46. STM8S005xx value line ordering information scheme .........................................................	99

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Introduction

1Introduction

Thisdatasheetcontainsthedescriptionofthedevicefeatures,pinout,electricalcharacteristics, mechanical data and ordering information.

•ForcompleteinformationontheSTM8Smicrocontrollermemory,registersandperipherals, please refer to the STM8S microcontroller family reference manual (RM0016).

•For information on programming, erasing and protection of the internal Flash memory please refer to the STM8S Flash programming manual (PM0051).

•For information on the debug and SWIM (single wire interface module) refer to the STM8 SWIM communication protocol and debug module user manual (UM0470).

•For information on the STM8 core, please refer to the STM8 CPU programming manual (PM0044).

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Description

STM8S005K6 STM8S005C6

2Description

The STM8S005xx value line 8-bit microcontrollers offer 32 Kbytes of Flash program memory, plus 128 bytes of data EEPROM. They are referred to as medium-density devices in the STM8S microcontroller family reference manual (RM0016). All devices of the STM8S005xx valuelineprovidethefollowingbenefits:performance,robustness,reducedsystemcost,and short develoment cycles.

DeviceperformanceandrobustnessareensuredbytruedataEEPROMsupportingupto100 000 write/erase cycles, advanced core and peripherals made in a state-of-the art technology, a 16 MHz clock frequency, robust I/Os, independent watchdogs with separate clock source, and a clock security system.

The system cost is reduced thanks to high system integration level with internal clock oscillators, watchdog and brown-out reset.

Common family product architecture with compatible pinout, memory map and modular peripherals allow application scalability and reduced development cycles.

All products operate from a 2.95 to 5.5 V supply voltage.

Full documentation is offered as well as a wide choice of development tools.

Table 1: STM8S005xx value line features

Device

Pin count

Maximum number of GPIOs

Ext. Interrupt pins

Timer CAPCOM channels

Timer complementary outputs

A/D Converter channels

High sink I/Os

Medium density Flash Program memory (bytes)

Data EEPROM (bytes)

RAM (bytes)

Peripheral set

STM8S005C6	STM8S005K6
48	32
38	25
35	23
9	8
3	3
10	7
16	12
32K	32K
128	128
2K	2K

Advanced control timer (TIM1), General-purpose timers (TIM2 and TIM3), Basic timer (TIM4) SPI, I2C, UART, Window WDG, Independent WDG, ADC

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Block diagram

3Block diagram

Figure 1: STM8S005xx value line block diagram

	Reset block			XTAL 1-16 MHz
			Clock controller
Reset		Reset		RC int. 16 MHz
	POR/	BOR	Detector
	PDR			RC int. 128 kHz
			Clock to peripherals and core
				Window WDG
	STM8 core
				Independent WDG
Single wire	Debug/SWIM			32 Kbytes
debug interf.
				program Flash
Master/slave
autosynchro	UART2			128 bytes
LIN master
				data EEPROM
SPI emul.
			bus
		I2C
400 Kbit/s			data	2 Kbytes
				RAM
			and
8 Mbit/s		SPI	Address	Boot ROM
					Up to
				16-bit advanced control	4 CAPCOM
					channels +3
				timer (TIM1)
					complementary
					outputs
				16-bit general purpose	Up to
					5 CAPCOM
				timers (TIM2, TIM3)
					channels
Up to 10 channels		ADC1		8-bit basic timer
				(TIM4)
1/2/4 kHz	Beeper
beep				AWU timer

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Product overview

STM8S005K6 STM8S005C6

4Product overview

Thefollowingsectionintendstogiveanoverviewofthebasicfeaturesofthedevicefunctional modules and peripherals.

For more detailed information please refer to the corresponding family reference manual (RM0016).

4.1Central processing unit STM8

The 8-bit STM8 core is designed for code efficiency and performance.

It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions.

Architecture and registers

•Harvard architecture

•3-stage pipeline

•32-bit wide program memory bus - single cycle fetching for most instructions

•X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations

•8-bit accumulator

•24-bit program counter - 16-Mbyte linear memory space

•16-bit stack pointer - access to a 64 K-level stack

•8-bit condition code register - 7 condition flags for the result of the last instruction

Addressing

•20 addressing modes

•Indexed indirect addressing mode for look-up tables located anywhere in the address space

•Stack pointer relative addressing mode for local variables and parameter passing

Instruction set

•80 instructions with 2-byte average instruction size

•Standard data movement and logic/arithmetic functions

•8-bit by 8-bit multiplication

•16-bit by 8-bit and 16-bit by 16-bit division

•Bit manipulation

•Data transfer between stack and accumulator (push/pop) with direct stack access

•Data transfer using the X and Y registers or direct memory-to-memory transfers

4.2Single wire interface module (SWIM) and debug module (DM)

Thesinglewireinterfacemoduleanddebugmodulepermitsnon-intrusive,real-timein-circuit debugging and fast memory programming.

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SWIM

Singlewireinterfacemodulefordirectaccesstothedebugmoduleandmemoryprogramming. Theinterfacecanbeactivatedinalldeviceoperationmodes. Themaximumdatatransmission speed is 145 bytes/ms.

Debug module

Thenon-intrusivedebuggingmodulefeaturesaperformanceclosetoafull-featuredemulator. Besidememoryandperipherals,alsoCPUoperationcanbemonitoredinreal-timebymeans of shadow registers.

•R/W to RAM and peripheral registers in real-time

•R/W access to all resources by stalling the CPU

•Breakpoints on all program-memory instructions (software breakpoints)

•Two advanced breakpoints, 23 predefined configurations

4.3Interrupt controller

•Nested interrupts with three software priority levels

•32 interrupt vectors with hardware priority

•Up to 37 external interrupts on 6 vectors including TLI

•Trap and reset interrupts

4.4Flash program and data EEPROM memory

•32 Kbytes of Flash program single voltage Flash memory

•128 bytes true data EEPROM

•Readwhilewrite:Writingindatamemorypossiblewhileexecutingcodeinprogrammemory

•User option byte area

Write protection (WP)

WriteprotectionofFlashprogrammemoryanddataEEPROMisprovidedtoavoidunintentional overwriting of memory that could result from a user software malfunction.

There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, data EEPROM and option bytes.

To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to write to data EEPROM, modify the contents of main program memory or the device option bytes.

Asecondlevelofwriteprotection,canbeenabledtofurtherprotectaspecificareaofmemory known as UBC (user boot code). Refer to the figure below.

The size of the UBC is programmable through the UBC option byte, in increments of 1 page (512 bytes) by programming the UBC option byte in ICP mode.

This divides the program memory into two areas:

•Main program memory: 32 Kbytes minus UBC

•User-specific boot code (UBC): Configurable up to 32 Kbytes

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The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines.

Figure 2: Flash memory organization

Data EEPROM memory

Medium density

Flash program memory (32 Kbytes)

Data memory area ( 128 bytes)

Option bytes

UBC area

Remains write protected during IAP

Program memory area

Write access possible for IAP

Programmable area from 1 Kbyte

(2 first pages) up to

32 Kbytes

(1 page steps)

Read-out protection (ROP)

The read-out protection blocks reading and writing the Flash program memory and data EEPROMmemoryinICPmode(anddebugmode). Oncetheread-outprotectionisactivated, anyattempttotoggleitsstatustriggersaglobaleraseoftheprogramanddatamemory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.

4.5Clock controller

The clock controller distributes the system clock (fMASTER) coming from different oscillators tothecoreandtheperipherals. Italsomanagesclockgatingforlowpowermodesandensures

clock robustness.

Features

•Clock prescaler: To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.

•Safe clock switching: Clock sources can be changed safely on the fly in run mode throughaconfigurationregister. Theclocksignalisnotswitcheduntilthenewclocksource is ready. The design guarantees glitch-free switching.

•Clock management: To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.

•Master clock sources: Four different clock sources can be used to drive the master clock:

-1-16 MHz high-speed external crystal (HSE)

-Up to 16 MHz high-speed user-external clock (HSE user-ext)

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-16 MHz high-speed internal RC oscillator (HSI)

-128 kHz low-speed internal RC (LSI)

•Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.

•Clock security system (CSS): This feature can be enabled by software. If an HSE clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated.

•Configurable main clock output (CCO): This outputs an external clock for use by the application.

Table 2: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers

Bit	Peripheral	Bit	Peripheral	Bit	Peripheral	Bit	Peripheral
	clock		clock		clock		clock
PCKEN1 7	TIM1	PCKEN1 3	UART2	PCKEN2 7	Reserved	PCKEN2 3	ADC
PCKEN1 6	TIM3	PCKEN1 2	Reserved	PCKEN2 6	Reserved	PCKEN2 2	AWU
PCKEN1 5	TIM2	PCKEN1 1	SPI	PCKEN2 5	Reserved	PCKEN2 1	Reserved
PCKEN1 4	TIM4	PCKEN1 0	I2C	PCKEN2 4	Reserved	PCKEN2 0	Reserved

4.6Power management

For efficent power management, the application can be put in one of four different low-power modes. You can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources.

•Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset.

•Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.

•Active halt mode with regulator off: This mode is the same as active halt with regulator on, except that the main voltage regulator is powered off, so the wake up time is slower.

•Halt mode: Inthismodethemicrocontrollerusestheleastpower. TheCPUandperipheral clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset.

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4.7Watchdog timers

The watchdog system is based on two independent timers providing maximum security to the applications.

Activationofthewatchdogtimersiscontrolledbyoptionbytesorbysoftware. Onceactivated, the watchdogs cannot be disabled by the user program without performing a reset.

Window watchdog timer

The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence.

The window function can be used to trim the watchdog behavior to match the application perfectly.

The application software must refresh the counter before time-out and during a limited time window.

A reset is generated in two situations:

1.Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to 64 ms.

2.Refresh out of window: The downcounter is refreshed before its value is lower than the one stored in the window register.

Independent watchdog timer

The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures.

It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case of a CPU clock failure

The IWDG time base spans from 60 µs to 1 s.

4.8Auto wakeup counter

•Used for auto wakeup from active halt mode

•Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock

•LSI clock can be internally connected to TIM3 input capture channel 1 for calibration

4.9Beeper

The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz.

ThebeeperoutputportisonlyavailablethroughthealternatefunctionremapoptionbitAFR7.

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4.10TIM1 - 16-bit advanced control timer

This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver

•16-bit up, down and up/down autoreload counter with 16-bit prescaler

•Four independent capture/compare channels (CAPCOM) configurable as input capture, outputcompare,PWMgeneration(edgeandcenteralignedmode)andsinglepulsemode output

•Synchronization module to control the timer with external signals

•Break input to force the timer outputs into a defined state

•Three complementary outputs with adjustable dead time

•Encoder mode

•Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break

4.11TIM2, TIM3 - 16-bit general purpose timers

•16-bit autoreload (AR) up-counter

•15-bit prescaler adjustable to fixed power of 2 ratios 1…32768

•Timers with 3 or 2 individually configurable capture/compare channels

•PWM mode

•Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update

4.12TIM4 - 8-bit basic timer

•8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128

•Clock source: CPU clock

•Interrupt source: 1 x overflow/update

		Table 3: TIM timer features
Timer	Counter Prescaler		Counting CAPCOM		Complem. Ext.		Timer
	size		mode	channels	outputs	trigger synchronization/
	(bits)						chaining
TIM1	16	Any integer from 1 to	Up/	4	3	Yes	No
		65536	down
TIM2	16	Any power of 2 from	Up	3	0	No
		1 to 32768
TIM3	16	Any power of 2 from	Up	2	0	No
		1 to 32768

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Product overview						STM8S005K6 STM8S005C6
Timer	Counter Prescaler		Counting CAPCOM		Complem. Ext. Timer
	size		mode	channels	outputs	trigger synchronization/
	(bits)					chaining
TIM4	8	Any power of 2 from	Up	0	0	No
		1 to 128

4.13Analog-to-digital converter (ADC1)

TheSTM8S105xxproductscontaina10-bitsuccessiveapproximationA/Dconverter(ADC1) with up to 10 multiplexed input channels and the following main features:

•Input voltage range: 0 to VDDA

•Conversion time: 14 clock cycles

•Single and continuous and buffered continuous conversion modes

•Buffer size (n x 10 bits) where n = number of input channels

•Scan mode for single and continuous conversion of a sequence of channels

•Analog watchdog capability with programmable upper and lower thresholds

•Analog watchdog interrupt

•External trigger input

•Trigger from TIM1 TRGO

•End of conversion (EOC) interrupt

Note: Additional AIN12 analog input is not selectable in ADC scan mode or with analog watchdog. Values converted from AIN12 are stored only into the ADC_DRH/ADC_DRL registers.

4.14Communication interfaces

The following communication interfaces are implemented:

•UART2: Full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA mode, LIN2.1 master/slave capability

•SPI : Full and half-duplex, 8 Mbit/s

•I²C: Up to 400 Kbit/s

4.14.1UART2

Main features

•One Mbit/s full duplex SCI

•SPI emulation

•High precision baud rate generator

•Smartcard emulation

•IrDA SIR encoder decoder

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DocID022186 Rev 3

STM8S005K6 STM8S005C6

Product overview

•LIN master mode

•LIN slave mode

Asynchronous communication (UART mode)

•Full duplex communication - NRZ standard format (mark/space)

•Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of following any standard baud rate regardless of the input frequency

•Separate enable bits for transmitter and receiver

•Two receiver wakeup modes:

-Address bit (MSB)

-Idle line (interrupt)

•Transmission error detection with interrupt generation

•Parity control

Synchronous communication

•Full duplex synchronous transfers

•SPI master operation

•8-bit data communication

•Maximum speed: 1 Mbit/s at 16 MHz (fCPU/16)

LIN master mode

•Emission: Generates 13-bit synch break frame

•Reception: Detects 11-bit break frame

LIN slave mode

•Autonomous header handling - one single interrupt per valid message header

•Automatic baud rate synchronization - maximum tolerated initial clock deviation ±15 %

•Synch delimiter checking

•11-bit LIN synch break detection - break detection always active

•Parity check on the LIN identifier field

•LIN error management

•Hot plugging support

4.14.2SPI

•Maximum speed: 8 Mbit/s (fMASTER/2) both for master and slave

•Full duplex synchronous transfers

•Simplex synchronous transfers on two lines with a possible bidirectional data line

•Master or slave operation - selectable by hardware or software

•CRC calculation

•1 byte Tx and Rx buffer

•Slave/master selection input pin

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Product overview

STM8S005K6 STM8S005C6

4.14.3I²C

•I²C master features:

-Clock generation

-Start and stop generation

•I²C slave features:

-Programmable I2C address detection

-Stop bit detection

•Generation and detection of 7-bit/10-bit addressing and general call

•Supports different communication speeds:

-Standard speed (up to 100 kHz)

-Fast speed (up to 400 kHz)

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STM8S005K6 STM8S005C6

Pinout and pin description

5Pinout and pin description

	Table 4: Legend/abbreviations for pinout tables
Type	I= Input, O = Output, S = Power supply
Level	Input	CM = CMOS
	Output	HS = High sink
Output speed	O1 = Slow (up to 2 MHz)
	O2 = Fast (up to 10 MHz)
	O3=Fast/slowprogrammabilitywithslowasdefaultstateafterreset
	O4 = Fast/slow programmability with fast as default state after reset
Port and control	Input	float = floating, wpu = weak pull-up
configuration	Output	T = True open drain, OD = Open drain, PP =

Push pull

Reset state

Bold X (pin state after internal reset release).

Unlessotherwisespecified,thepinstateisthesameduringthereset phase and after the internal reset release.

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Pinout and pin description

STM8S005K6 STM8S005C6

5.1STM8S005 pinouts and pin description

Figure 3: LQFP 48-pin pinout

								(HS)/TIM2PD4 CH1 [BEEP]		(HS)/TIM2PD3 CH2 [ADC ETR] (HS)/TIM3PD2 CH1 [TIM2 CH3]					_CCO]
		PD7/TLI[TIM1_CH4]		PD6/UART2_RX		PD5/UART2_TX							(HS)/SWIMPD1		(HS)/TIM3PD0 _CH2 [TIM1_BKIN] [CLK	(HS)PE0/CLK_CCO		(T)/IPE1	(T)/IPE2	PE3/TIM1_BKIN
																		_ SCL C	_ SDA C
																		2	2
		48 47 46 45								44 43 42 41 40 39 38 37
	NRST	1																		36	PG1
	OSCIN/PA1	2																		35	PG0
	OSCOUT/PA2	3																		34	PC7 (HS)/SPI_MISO
	V SSIO_1	4																		33	PC6 (HS)/SPI_MOSI
	VSS	5																		32	VDDIO_2
	VCAP	6																		31	VSSIO_2
	VDD	7																		30	PC5 (HS)/SPI_SCK
	VDDIO_1	8																		29	PC4 (HS)/TIM1_CH4
	[TIM3_CH1] TIM2_CH3/PA3	9																		28	PC3 (HS)/TIM1_CH3
	(HS) PA4	10																		27	PC2 (HS)/TIM1_CH2
	(HS) PA5	11																		26	PC1 (HS)/TIM1_CH1/UART2_CK
	(HS) PA6	12																		25	PE5/SPI_NSS
		13	14		15		16		17		18	19		20		21	22 23 24
		DDA		SSA		AIN7/PB7		AIN6/PB6		AIN5/PB5	AIN4/PB4		[TIM1ETR/AIN3/PB3		[TIM1CH3N] AIN2/PB2	[TIM1CH2N] AIN1/PB1		[TIM1CH1N] AIN0/PB0	AIN8/PE7	AIN9/PE6
		V		V						[I	[I
										_SDA]C	_SCL]C
								2			2

1.(HS) high sink capability.

2.(T) True open drain (P-buffer and protection diode to VDD not implemented).

3.[ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function).

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STM8S005K6 STM8S005C6

Pinout and pin description

Figure 4: LQFP 32-pin pinout

	PD7/TLI [TIM1 CH4]	PD6/UART2 RX	PD5/UART2 TX	PD4 (HS)/TIM2 CH1 [BEEP]	PD3 (HS)/TIM2 CH2 [ADC ETR]	PD2 (HS)/TIM3 CH1[TIM2 CH3]	PD1 (HS)/SWIM	PD0 (HS)/TIM3 CH2 [TIM1 BKIN] [CLK CCO]
	32	31	30	29	28	27	26	25
NRST	1							24	PC7 (HS)/SPI_MISO
OSCIN/PA1	2							23	PC6 (HS)/SPI_MOSI
OSCOUT/PA2	3							22	PC5 (HS)/SPI_SCK
V SS	4							21	PC4 (HS)/TIM1_CH4
VCAP	5							20	PC3 (HS)/TIM1_CH3
V DD	6							19	PC2 (HS)/TIM1_CH2
V DDIO	7							18	PC1 (HS)/TIM1_CH1/UART2_CK
AIN12/PF4	8							17	PE5/SPI_NSS
	9	10	11 12		13	14	15 16
	V	VSSA	[I	[I	ETR][TIM1AIN3/PB3	CH3N][TIM1AIN2/PB2	CH2N][TIM1AIN1/PB1	CH1N][TIM1AIN0/PB0
	DDA		AIN5/PB5SDA]	AIN4/PB4SCL]C
			C_	2
			2

1.(HS) high sink capability.

2.[ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function).

Table 5: Pin description for STM8S005 microcontrollers

Pin number

Pin name

Type

Input

Output

Main function

Default alternate

Alternate

(after reset)

function

function after

LQFP48

LQFP32

floating

wpu

Ext.

High Speed

OD

PP

remap [option

bit]

interrupt

sink

1

1

NRST

I/O

X

Reset

2

2

PA1/ OSC

I/O

X

X

O1

X

X

Port A1

Resonator/

IN

crystal in

3

3

PA2/ OSC

I/O

X

X

X

O1

X

X

Port A2

Resonator/

OUT

crystal out

4

-

VSSIO_1

S

I/O ground

5

4

VSS

S

Digital ground

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Pinout and pin description

STM8S005K6 STM8S005C6

Pin number

Pin name

Type

Input

Output

Main function

Default alternate

Alternate

(after reset)

function

function after

LQFP48

LQFP32

floating

wpu

Ext.

High

Speed

OD

PP

remap [option

bit]

interrupt

sink

6

5

VCAP

S

1.8 V regulator capacitor

7

6

VDD

S

Digital power supply

8

7

VDDIO_1

S

I/O power supply

9

-

PA3/TIM2

I/O

X

X

X

O1

X

X

Port A3

Timer 2 -

TIM3_ CH1

_CH3

channel 3

[AFR1]

[TIM3

_CH1]

10

-

PA4

I/O

X

X

X

HS

O3

X

X

Port A4

11

-

PA5

I/O

X

X

X

HS

O3

X

X

Port A5

12

-

PA6

I/O

X

X

X

HS

O3

X

X

Port A6

-

8

PF4/

I/O

X

X

O1

X

X

Port F4

Analog input 12 (2)

AIN12 (1)

13

9

VDDA

S

Analog power supply

14

10

VSSA

S

Analog ground

15

-

PB7/AIN7

I/O

X

X

X

O1

X

X

Port B7

Analog input 7

16

-

PB6/AIN6

I/O

X

X

X

O1

X

X

Port B6

Analog input 6

17

11

PB5/AIN5

I/O

X

X

X

O1

X

X

Port B5

Analog input 5

I2C_SDA

[I2C_

[AFR6]

SDA]

18

12

PB4/AIN4

I/O

X

X

X

O1

X

X

Port B4

Analog input 4

I2C_SCL

[I2C_

[AFR6]

SCL]

19

13

PB3/AIN3

I/O

X

X

X

O1

X

X

Port B3

Analog input 3

TIM1_ ETR

[TIM1_

[AFR5]

ETR]

20

14

PB2/AIN2

I/O

X

X

X

O1

X

X

Port B2

Analog input 2

TIM1_ CH3N

[TIM1_

[AFR5]

CH3N]

21

15

PB1/AIN1

I/O

X

X

X

O1

X

X

Port B1

Analog input 1

TIM1_ CH2N

[TIM1_

[AFR5]

CH2N]

22

16

PB0/AIN0

I/O

X

X

X

O1

X

X

Port B0

Analog input 0

TIM1_ CH1N

[TIM1_

[AFR5]

CH1N]

23

-

PE7/AIN8

I/O

X

X

X

O1

X

X

Port E7

Analog input 8

24

-

PE6/AIN9

I/O

X

X

X

O1

X

X

Port E6

Analog input 9

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STM8S005K6 STM8S005C6

Pinout and pin description

Pin number

Pin name

Type

Input

Output

Main function

Default alternate

Alternate

(after reset)

function

function after

LQFP48

LQFP32

floating

wpu

Ext.

High

Speed

OD

PP

remap [option

bit]

interrupt

sink

25

17

PE5/SPI_

I/O

X

X

X

O1

X

X

Port E5

SPI master/slave

NSS

select

26

18

PC1/

I/O

X

X

X

HS

O3

X

X

Port C1

Timer 1 -

TIM1_

channel 1/ UART2

CH1/

synchronous clock

UART2_CK

27

19

PC2/

I/O

X

X

X

HS

O3

X

X

Port C2

Timer 1-

TIM1_

channel 2

CH2

28

20

PC3/

I/O

X

X

X

HS

O3

X

X

Port C3

Timer 1 -

TIM1_

channel 3

CH3

29

21

PC4/

I/O

X

X

X

HS

O3

X

X

Port C4

Timer 1 -

TIM1_

channel 4

CH4

30

22

PC5/SPI_

I/O

X

X

X

HS

O3

X

X

Port C5

SPI clock

SCK

31

-

VSSIO_2

S

I/O ground

32

-

VDDIO_2

S

I/O power supply

33

23

PC6/SPI_

I/O

X

X

X

HS

O3

X

X

Port C6

SPI master out/slave

MOSI

in

34

24

PC7/SPI_

I/O

X

X

X

HS

O3

X

X

Port C7

SPI master in/ slave

MISO

out

35

-

PG0

I/O

X

X

O1

X

X

Port G0

36

-

PG1

I/O

X

X

O1

X

X

Port G1

37

-

PE3/

I/O

X

X

X

O1

X

X

Port E3

Timer 1 - break input

TIM1_

BKIN

38

-

PE2/ I2C_

I/O

X

X

O1

T(3)

Port E2

I2C data

SDA

39

-

PE1/ I2C_

I/O

X

X

O1

T(3)

Port E1

I2C clock

SCL

40

-

PE0/

I/O

X

X

X

HS

O3

X

X

Port E0

Configurable clock

CLK_

output

CCO

41

25

PD0/

I/O

X

X

X

HS

O3

X

X

Port D0

Timer 3 -

TIM1_ BKIN

TIM3_

channel 2

[AFR3]/ CLK_

CH2

CCO [AFR2]

[TIM1_ BKIN] [CLK_ CCO]

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Pinout and pin description

STM8S005K6 STM8S005C6

Pin number		Pin name	Type
LQFP48	LQFP32
42	26	PD1/	I/O
		SWIM(4)
43	27	PD2/	I/O
		TIM3_
		CH1
		[TIM2_
		CH3]
44	28	PD3/	I/O
		TIM2_
		CH2
		[ADC_
		ETR]
45	29	PD4/	I/O
		TIM2_
		CH1
		[BEEP]
46	30	PD5/	I/O
		UART2_
		TX
47	31	PD6/	I/O
		UART2_
		RX
48	32	PD7/ TLI	I/O
		[TIM1_
		CH4]

Input			Output				Main function	Default alternate	Alternate
							(after reset)	function	function after
floating	wpu	Ext.	High	Speed	OD	PP			remap [option
									bit]
		interrupt	sink
X	X	X	HS	O4	X	X	Port D1	SWIM data interface
X	X	X	HS	O3	X	X	Port D2	Timer 3 -	TIM2_CH3
								channel 1	[AFR1]
X	X	X	HS	O3	X	X	Port D3	Timer 2 -	ADC_ ETR
								channel 2	[AFR0]
X	X	X	HS	O3	X	X	Port D4	Timer 2 -	BEEP output
								channel 1	[AFR7]
X	X	X		O1	X	X	Port D5	UART2 data transmit
X	X	X		O1	X	X	Port D6	UART2 data receive
X	X	X		O1	X	X	Port D7	Top level interrupt	TIM1_ CH4
									[AFR4]

(1) A pull-up is applied to PF4 during the reset phase. This pin is input floating after reset release.

(2)AIN12 is not selectable in ADC scan mode or with analog watchdog.

(3) In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are not implemented).

(4)The PD1 pin is in input pull-up during the reset phase and after internal reset release.

5.1.1Alternate function remapping

As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. When the remapping option is active, the default alternate function is no longer available.

To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers.

AlternatefunctionremappingdoesnoteffectGPIOcapabilitiesoftheI/Oports(seetheGPIO section of the family reference manual, RM0016).

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STM8S005K6 STM8S005C6

Memory and register map

6Memory and register map

6.1Memory map

Figure 5: Memory map

0x00 0000			RAM
			(2 Kbytes)
0x00 07FF			512 bytes stack
			Reserved
0x00 4000
	128-byte data EEPROM
0x00 407F
0x00 4080			Reserved
0x00 47FF
0x00 4800
0x00 487F			Option bytes
0x00 4900
			Reserved
0x00 4FFF
0x00 5000		GPIO and periph. reg.
0x00 57FF
0x00 5800
			Reserved
0x00 5FFF
0x00 6000		2 Kbytes boot ROM
0x00 67FF
0x00 6800
			Reserved
0x00 7EFF
0x00 7F00	CPU/SWIM/debug/ITC
0x00 7FFF			registers
0x00 8000			32 interrupt vectors
0x00 807F
	Flash program memory
			(32 Kbytes)
0x00 FFFF
0x01 0000

Reserved

0x02 7FFF

The following table lists the boundary addresses for each memory size. The top of the stack is at the RAM end address in each case.

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Memory and register map		STM8S005K6 STM8S005C6
Table 6: Flash, Data EEPROM and RAM boundary addresses
Memory area	Size (bytes)	Start address	End address
Flash program memory	32K	0x00 8000	0x00 FFFF
RAM	2K	0x00 0000	0x00 07FF
Data EEPROM	128	0x00 4000	0x00 407F

6.2Register map

6.2.1I/O port hardware register map

Table 7: I/O port hardware register map

Address		Block	Register label	Register name	Reset
					status
0x00	5000	Port A	PA_ODR	Port A data output latch register	0x00
0x00	5001		PA_IDR	Port A input pin value register	0xXX (1)
0x00	5002		PA_DDR	Port A data direction register	0x00
0x00	5003		PA_CR1	Port A control register 1	0x00
0x00	5004		PA_CR2	Port A control register 2	0x00
0x00	5005	Port B	PB_ODR	Port B data output latch register	0x00
0x00	5006		PB_IDR	Port B input pin value register	0xXX (1)
0x00	5007		PB_DDR	Port B data direction register	0x00
0x00	5008		PB_CR1	Port B control register 1	0x00
0x00	5009		PB_CR2	Port B control register 2	0x00
0x00	500A	Port C	PC_ODR	Port C data output latch register	0x00

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STM8S005K6 STM8S005C6

Memory and register map

Address		Block	Register label
0x00	500B		PC_IDR
0x00 500C			PC_DDR
0x00 500D			PC_CR1
0x00	500E		PC_CR2
0x00	500F	Port D	PD_ODR
0x00	5010		PD_IDR
0x00	5011		PD_DDR
0x00	5012		PD_CR1
0x00	5013		PD_CR2
0x00	5014	Port E	PE_ODR
0x00	5015		PE_IDR
0x00	5016		PE_DDR
0x00	5017		PE_CR1
0x00	5018		PE_CR2
0x00	5019	Port F	PF_ODR
0x00	501A		PF_IDR
0x00	501B		PF_DDR
0x00 501C			PF_CR1
0x00 501D			PF_CR2

Register name	Reset
	status
Port C input pin value register	0xXX (1)
Port C data direction register	0x00
Port C control register 1	0x00
Port C control register 2	0x00
Port D data output latch register	0x00
Port D input pin value register	0xXX (1)
Port D data direction register	0x00
Port D control register 1	0x02
Port D control register 2	0x00
Port E data output latch register	0x00
Port E input pin value register	0xXX (1)
Port E data direction register	0x00
Port E control register 1	0x00
Port E control register 2	0x00
Port F data output latch register	0x00
Port F input pin value register	0xXX (1)
Port F data direction register	0x00
Port F control register 1	0x00
Port F control register 2	0x00

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Memory and register map				STM8S005K6 STM8S005C6
Address		Block	Register label	Register name	Reset
					status
0x00	501E	Port G	PG_ODR	Port G data output latch register	0x00
0x00 501F			PG_IDR	Port G input pin value register	0xXX (1)
0x00	5020		PG_DDR	Port G data direction register	0x00
0x00	5021		PG_CR1	Port G control register 1	0x00
0x00	5022		PG_CR2	Port G control register 2	0x00
0x00	5023	Port H	PH_ODR	Port H data output latch register	0x00
0x00	5024		PH_IDR	Port H input pin value register	0xXX (1)
0x00	5025		PH_DDR	Port H data direction register	0x00
0x00	5026		PH_CR1	Port H control register 1	0x00
0x00	5027		PH_CR2	Port H control register 2	0x00
0x00	5028	Port I	PI_ODR	Port I data output latch register	0x00
0x00	5029		PI_IDR	Port I input pin value register	0xXX (1)
0x00	502A		PI_DDR	Port I data direction register	0x00
0x00	502B		PI_CR1	Port I control register 1	0x00
0x00 502C			PI_CR2	Port I control register 2	0x00

(1) Depends on the external circuitry.

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STM8S005K6 STM8S005C6

Memory and register map

6.2.2General hardware register map

Table 8: General hardware register map

Address		Block	Register label	Register name	Reset status
0x00	5050 to	Reserved area (10 bytes)
0x00	5059
0x00	505A	Flash	FLASH_CR1	Flash control register 1	0x00
0x00	505B		FLASH_CR2	Flash control register 2	0x00
0x00	505C		FLASH_NCR2	Flash complementary control	0xFF
				register 2
0x00	505D		FLASH _FPR	Flash protection register	0x00
0x00	505E		FLASH _NFPR	Flashcomplementaryprotectionregister	0xFF
0x00	505F		FLASH _IAPSR	Flashin-applicationprogrammingstatus	0x00
				register
0x00	5060 to	Reserved area (2 bytes)
0x00	5061
0x00	5062	Flash	FLASH _PUKR	Flash program memory unprotection	0x00
				register
0x00	5063	Reserved area (1 byte)
0x00	5064	Flash	FLASH _DUKR	Data EEPROM unprotection register	0x00
0x00	5065 to	Reserved area (59 bytes)
0x00	509F
0x00	50A0	ITC	EXTI_CR1	External interrupt control register 1	0x00
0x00	50A1		EXTI_CR2	External interrupt control register 2	0x00
0x00	50A2 to	Reserved area (17 bytes)
0x00	50B2

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Memory and register map				STM8S005K6 STM8S005C6
Address		Block	Register label	Register name	Reset status
0x00	50B3	RST	RST_SR	Reset status register	0xXX(1)
0x00	50B4 to	Reserved area (12 bytes)
0x00	50BF
0x00	50C0	CLK	CLK_ICKR	Internal clock control register	0x01
0x00	50C1		CLK_ECKR	External clock control register	0x00
0x00	50C2	Reserved area (1 byte)
0x00	50C3	CLK	CLK_CMSR	Clock master status register	0xE1
0x00	50C4		CLK_SWR	Clock master switch register	0xE1
0x00	50C5		CLK_SWCR	Clock switch control register	0xXX
0x00	50C6		CLK_CKDIVR	Clock divider register	0x18
0x00	50C7		CLK_PCKENR1	Peripheral clock gating register 1	0xFF
0x00	50C8		CLK_CSSR	Clock security system register	0x00
0x00	50C9		CLK_CCOR	Configurable clock control register	0x00
0x00	50CA		CLK_PCKENR2	Peripheral clock gating register 2	0xFF
0x00	50CC		CLK_HSITRIMR	HSI clock calibration trimming register	0x00
0x00	50CD		CLK_SWIMCCR	SWIM clock control register	0bXXXX
					XXX0
0x00	50CE to	Reserved area (3 bytes)
0x00	50D0
0x00	50D1	WWDG	WWDG_CR	WWDG control register	0x7F
0x00	50D2		WWDG_WR	WWDR window register	0x7F

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