ST STM8S003K3, STM8S003F3 User Manual

STM8S003K3 STM8S003F3

LQFP32 7x7

TSSOP20

UFQFPN20 3x3

Value line, 16 MHz STM8S 8-bit MCU, 8 Kbytes Flash, 128 bytes

data EEPROM, 10-bit ADC, 3 timers, UART, SPI, I²C

Interrupt management

Nested interrupt controller with 32 interrupts

•

Up to 27 external interrupts on 6 vectors

•

Timers

Advanced control timer: 16-bit, 4 CAPCOM

•

channels, 3 complementary outputs, dead-time insertion and flexible synchronization

16-bit general purpose timer, with 3 CAPCOM

•

channels (IC, OC or PWM)

8-bit basic timer with 8-bit prescaler

Features

Core

16 MHz advanced STM8 core with Harvard

•

architecture and 3-stage pipeline

Extended instruction set

•

Memories

Program memory: 8 Kbytes Flash; data retention

•

20 years at 55 °C after 100 cycles

RAM: 1 Kbytes

•

Data memory: 128 bytes of true data EEPROM;

•

endurance up to 100 000 write/erase cycles

Clock, reset and supply management

2.95 to 5.5 V operating voltage

•

Flexible clock control, 4 master clock sources:

•

Low power crystal resonator oscillator

External clock input

Internal, user-trimmable 16 MHz RC

Internal low power 128 kHz RC

Clock security system with clock monitor

•

Power management:

•

Low power modes (wait, active-halt, halt)

Switch-off peripheral clocks individually

•

Auto wake-up timer

•

Window watchdog and independent watchdog

•

timers

Communications interfaces

UART with clock output for synchronous

•

operation, Smartcard, IrDA, LIN master mode

SPI interface up to 8 Mbit/s

•

I2C interface up to 400 Kbit/s

•

Analog to digital converter (ADC)

10-bit, ±1 LSB ADC with up to 5 multiplexed

•

channels, scan mode and analog watchdog

I/Os

Up to 28 I/Os on a 32-pin package including 21

•

high sink outputs

Highly robust I/O design, immune against current

•

injection

Development support

Embedded single wire interface module (SWIM)

•

for fast on-chip programming and non intrusive debugging

Permanently active, low consumption power-on

•

and power-down reset

June 2012

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STM8S003K3 STM8S003F3Contents

1 Introduction ..............................................................................................................7

2 Description ...............................................................................................................8

3 Block diagram ..........................................................................................................9

4 Product overview ...................................................................................................10

4.1 Central processing unit STM8 .....................................................................................10

4.2 Single wire interface module (SWIM) and debug module (DM) ..................................10

4.3 Interrupt controller .......................................................................................................11

4.4 Flash program memory and data EEPROM ................................................................11

4.5 Clock controller ............................................................................................................12

4.6 Power management ....................................................................................................13

4.7 Watchdog timers ..........................................................................................................13

4.8 Auto wakeup counter ...................................................................................................14

4.9 Beeper ........................................................................................................................14

4.10 TIM1 - 16-bit advanced control timer .........................................................................14

4.11 TIM2 - 16-bit general purpose timer ..........................................................................15

4.12 TIM4 - 8-bit basic timer ..............................................................................................15

4.13 Analog-to-digital converter (ADC1) ............................................................................15

4.14 Communication interfaces .........................................................................................16

4.14.1 UART1 ...............................................................................................16

4.14.2 SPI .....................................................................................................17

4.14.3 I²C ......................................................................................................17

5 Pinout and pin description ...................................................................................18

5.1 STM8S003K3 LQFP32 pinout and pin description ......................................................18

5.2 STM8S003F3 TSSOP20/UFQFPN20 pinout and pin description ...............................21

5.2.1 STM8S003F3 TSSOP20 pinout and pin description ............................21

5.2.2 STM8S003F3 UFQFPN20 pinout ........................................................22

5.2.3 STM8S003F3 TSSOP20/UFQFPN20 pin description ..........................22

5.3 Alternate function remapping .......................................................................................24

6 Memory and register map .....................................................................................25

6.1 Memory map ................................................................................................................25

6.2 Register map ...............................................................................................................26

6.2.1 I/O port hardware register map ............................................................26

6.2.2 General hardware register map ..........................................................27

6.2.3 CPU/SWIM/debug module/interrupt controller registers .....................36

7 Interrupt vector mapping ......................................................................................39

8 Option bytes ...........................................................................................................41

8.1 Alternate function remapping bits ................................................................................43

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ContentsSTM8S003K3 STM8S003F3

9 Electrical characteristics ......................................................................................46

9.1 Parameter conditions ...................................................................................................46

9.1.1 Minimum and maximum values ...........................................................46

9.1.2 Typical values .......................................................................................46

9.1.3 Typical curves ......................................................................................46

9.1.4 Loading capacitor .................................................................................46

9.1.5 Pin input voltage ...................................................................................46

9.2 Absolute maximum ratings ..........................................................................................47

9.3 Operating conditions ....................................................................................................49

9.3.1 VCAP external capacitor ......................................................................50

9.3.2 Supply current characteristics ..............................................................51

9.3.3 External clock sources and timing characteristics ...............................60

9.3.4 Internal clock sources and timing characteristics .................................62

9.3.5 Memory characteristics ........................................................................64

9.3.6 I/O port pin characteristics ...................................................................66

9.3.7 Reset pin characteristics ......................................................................74

9.3.8 SPI serial peripheral interface ..............................................................77

9.3.9 I2C interface characteristics .................................................................80

9.3.10 10-bit ADC characteristics ..................................................................81

9.3.11 EMC characteristics ...........................................................................85

10 Package information ...........................................................................................89

10.1 32-pin LQFP package mechanical data ....................................................................89

10.2 20-pin TSSOP package mechanical data ..................................................................90

10.3 20-lead UFQFPN package mechanical data .............................................................92

11 Thermal characteristics .......................................................................................94

11.1 Reference document .................................................................................................94

11.2 Selecting the product temperature range ..................................................................94

12 Ordering information ...........................................................................................96

13 STM8 development tools ....................................................................................97

13.1 Emulation and in-circuit debugging tools ...................................................................97

13.2 Software tools ............................................................................................................97

13.2.1 STM8 toolset ......................................................................................98

13.2.2 C and assembly toolchains ................................................................98

13.3 Programming tools ....................................................................................................98

14 Revision history ...................................................................................................99

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STM8S003K3 STM8S003F3List of tables

List of tables

Table 1. STM8S003xx value line features ................................................................................................8

Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ..................................13

Table 3. TIM timer features ....................................................................................................................15

Table 4. Legend/abbreviations for pinout tables ...................................................................................18

Table 5. LQFP32 pin description ............................................................................................................19

Table 6. STM8S003F3 pin description ...................................................................................................22

Table 7. I/O port hardware register map ................................................................................................26

Table 8. General hardware register map ...............................................................................................27

Table 9. CPU/SWIM/debug module/interrupt controller registers .........................................................36

Table 10. Interrupt mapping ...................................................................................................................39

Table 11. Option bytes ...........................................................................................................................99

Table 12. Option byte description ...........................................................................................................41

Table 13. STM8S003K3 alternate function remapping bits for 32-pin devices ......................................43

Table 14. STM8S003F3 alternate function remapping bits for 20-pin devices ......................................44

Table 15. Voltage characteristics ...........................................................................................................47

Table 16. Current characteristics ...........................................................................................................47

Table 17. Thermal characteristics ..........................................................................................................48

Table 18. General operating conditions .................................................................................................49

Table 19. Operating conditions at power-up/power-down ......................................................................50

Table 20. Total current consumption with code execution in run mode at VDD= 5 V .............................51

Table 21. Total current consumption with code execution in run mode at VDD= 3.3 V ..........................52

Table 22. Total current consumption in wait mode at VDD= 5 V ............................................................53

Table 23. Total current consumption in wait mode at VDD= 3.3 V .........................................................53

Table 24. Total current consumption in active halt mode at VDD= 5 V ..................................................54

Table 25. Total current consumption in active halt mode at VDD= 3.3 V ...............................................54

Table 26. Total current consumption in halt mode at VDD= 5 V .............................................................55

Table 27. Total current consumption in halt mode at VDD= 3.3 V ..........................................................55

Table 28. Wakeup times .........................................................................................................................56

Table 29. Total current consumption and timing in forced reset state ....................................................57

Table 30. Peripheral current consumption .............................................................................................57

Table 31. HSE user external clock characteristics .................................................................................60

Table 32. HSE oscillator characteristics .................................................................................................61

Table 33. HSI oscillator characteristics ..................................................................................................62

Table 34. LSI oscillator characteristics ...................................................................................................64

Table 35. RAM and hardware registers ..................................................................................................64

Table 36. Flash program memory and data EEPROM ...........................................................................65

Table 37. I/O static characteristics .........................................................................................................66

Table 38. Output driving current (standard ports) ..................................................................................68

Table 39. Output driving current (true open drain ports) ........................................................................68

Table 40. Output driving current (high sink ports) ..................................................................................69

Table 41. NRST pin characteristics ........................................................................................................74

Table 42. SPI characteristics ..................................................................................................................78

Table 43. I2C characteristics ..................................................................................................................80

Table 44. ADC characteristics ................................................................................................................82

Table 45. ADC accuracy with R Table 46. ADC accuracy with R

Table 47. EMS data ................................................................................................................................86

< 10 kΩ , VDD= 5 V .........................................................................82

AIN

< 10 kΩ R

AIN

, VDD= 3.3 V ..............................................................83

AIN

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List of tablesSTM8S003K3 STM8S003F3

Table 48. EMI data .................................................................................................................................86

Table 49. ESD absolute maximum ratings .............................................................................................87

Table 50. Electrical sensitivities .............................................................................................................88

Table 51. 32-pin low profile quad flat package mechanical data ............................................................89

Table 52. 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data .........................................................91

Table 53. 20-lead ultra thin fine pitch quad flat no-lead package (3x3) mechanical data ......................92

Table 54. Thermal characteristics ..........................................................................................................94

Table 55. Document revision history ......................................................................................................99

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STM8S003K3 STM8S003F3List of figures

List of figures

Figure 1. Block diagram ...........................................................................................................................9

Figure 2. Flash memory organization ....................................................................................................12

Figure 3. STM8S003K3 LQFP32 pinout ................................................................................................18

Figure 4. STM8S003F3 TSSOP20 pinout ..............................................................................................21

Figure 5. STM8S003F3 UFQFPN20-pin pinout .....................................................................................22

Figure 6. Memory map ...........................................................................................................................25

Figure 7. Pin loading conditions .............................................................................................................46

Figure 8. Pin input voltage .....................................................................................................................47

Figure 9. f

CPUmax

Figure 10. External capacitor C Figure 11. Typ I Figure 12. Typ I Figure 13. Typ I Figure 14. Typ I Figure 15. Typ I Figure 16. Typ I

Figure 17. HSE external clock source ....................................................................................................61

Figure 18. HSE oscillator circuit diagram ...............................................................................................62

Figure 19. Typical HSI frequency variation vs VDD@ 4 temperatures ..................................................63

Figure 20. Typical LSI frequency variation vs VDD@ 4 temperatures ...................................................64

Figure 21. Typical VILand VIHvs VDD@ 4 temperatures ......................................................................67

Figure 22. Typical pull-up resistance vs VDD@ 4 temperatures ............................................................67

Figure 23. Typical pull-up current vs VDD@ 4 temperatures .................................................................68

Figure 24. Typ. VOL@ VDD= 5 V (standard ports) ................................................................................70

Figure 25. Typ. VOL@ VDD= 3.3 V (standard ports) .............................................................................70

Figure 26. Typ. VOL@ VDD= 5 V (true open drain ports) ......................................................................71

Figure 27. Typ. VOL@ VDD= 3.3 V (true open drain ports) ...................................................................71

Figure 28. Typ. VOL@ VDD= 5 V (high sink ports) ................................................................................72

Figure 29. Typ. VOL@ VDD= 3.3 V (high sink ports) .............................................................................72

Figure 30. Typ. VDD- VOH@ VDD= 5 V (standard ports) .......................................................................73

Figure 31. Typ. VDD- VOH@ VDD= 3.3 V (standard ports) ...................................................................73

Figure 32. Typ. VDD- VOH@ VDD= 5 V (high sink ports) .......................................................................74

Figure 33. Typ. VDD- VOH@ VDD= 3.3 V (high sink ports) ....................................................................74

Figure 34. Typical NRST VILand VIHvs VDD@ 4 temperatures ...........................................................76

Figure 35. Typical NRST pull-up resistance vs VDD@ 4 temperatures .................................................76

Figure 36. Typical NRST pull-up current vs VDD@ 4 temperatures ......................................................77

Figure 37. Recommended reset pin protection ......................................................................................77

Figure 38. SPI timing diagram - slave mode and CPHA = 0 ..................................................................79

Figure 39. SPI timing diagram - slave mode and CPHA = 1 ..................................................................79

Figure 40. SPI timing diagram - master mode

Figure 41. Typical application with I2C bus and timing diagram ............................................................84

Figure 42. ADC accuracy characteristics ...............................................................................................84

Figure 43. Typical application with ADC ................................................................................................85

Figure 44. 32-pin low profile quad flat package (7 x 7) ..........................................................................89

Figure 45. 20-pin, 4.40 mm body, 0.65 mm pitch ...................................................................................90

Figure 46. 20-lead ultra thin fine pitch quad flat no-lead package outline (3x3) ....................................92

Figure 47. STM8S003x value line ordering information scheme ...........................................................96

versus V

DD(RUN)

DD(WFI)

................................................................................................................50

.......................................................................................................50

EXT

vs. VDDHSE user external clock, f vs. f vs. VDDHSI RC osc, f

HSE user external clock, VDD= 5 V ....................................................58

CPU

= 16 MHz .................................................................59

CPU

vs. VDDHSE user external clock, f vs. f vs. VDDHSI RC osc, f

HSE user external clock, VDD= 5 V .....................................................60

CPU

= 16 MHz .................................................................60

CPU

(1)

...................................................................................80

= 16 MHz .............................................58

CPU

= 16 MHz ..............................................59

CPU

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IntroductionSTM8S003K3 STM8S003F3

Introduction1

This datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information.

For complete information on the STM8S microcontroller memory, registers and peripherals,

•

please refer to the STM8S microcontroller family reference manual (RM0016).

For information on programming, erasing and protection of the internal Flash memory

•

please refer to the STM8S Flash programming manual (PM0051).

For information on the debug and SWIM (single wire interface module) refer to the STM8

•

SWIM communication protocol and debug module user manual (UM0470).

For information on the STM8 core, please refer to the STM8 CPU programming manual

•

(PM0044).

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STM8S003K3 STM8S003F3Description

Description2

The STM8S003x value line 8-bit microcontrollers feature 8 Kbytes Flash program memory, plus integrated true data EEPROM. The STM8S microcontroller family reference manual (RM0016) refers to devices in this family as low-density. They provide the following benefits: performance, robustness, and reduced system cost.

Device performance and robustness are ensured by integrated true data EEPROM supporting up to 100000 write/erase cycles, advanced core and peripherals made in a state-of-the art technology, a 16 MHz clock frequency, robust I/Os, independent watchdogs with separate clock source, and a clock security system.

The system cost is reduced thanks to high system integration level with internal clock oscillators, watchdog and brown-out reset.

Full documentation is offered as well as a wide choice of development tools.

Table 1: STM8S003xx value line features

STM8S003F3STM8S003K3Device

2032Pin count

1628Maximum number of GPIOs (I/Os)

1627Ext. interrupt pins

True data EEPROM (bytes)

Peripheral set

(1)

Without read-while-write capability.

77Timer CAPCOM channels

23Timer complementary outputs

54A/D converter channels

1221High sink I/Os

8K8KLow density Flash program memory (bytes)

1K1KRAM (bytes)

128

(1)

128

(1)

Multipurpose timer (TIM1), SPI, I2C, UART window WDG,independent WDG, ADC, PWM timer (TIM2), 8-bit timer (TIM4)

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XTAL 1-16MHz

RC int. 16MHz

RC int. 128kHz

STM8 core

Debug/SWIM

SPI

UART1

16-bit general purpose

AWU timer

Reset block

Reset

POR

BOR

Clock controller

Detector

Clock to peripherals and core

8 Mbit/s

LIN master

Address and databus

Window WDG

8-Kbyte

1-Kbyte

ADC1

4 CAPCOM

Reset

400 Kbit/s

Single wire

debug interf.

SPI emul.

channels +3

program

Flash

16-bit advanced

control timer (TIM1)

8-bit basic timer

RAM

Up to

Beeper

1/2/4 kHz

beep

Independent WDG

(TIM4)

3 CAPCOM channels

Up to

complementary outputs

timer (TIM2)

Up to 5

channels

I2C

128-byte

data EEPROM

Block diagramSTM8S003K3 STM8S003F3

Block diagram3

Figure 1: Block diagram

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STM8S003K3 STM8S003F3Product overview

Product overview4

The following section intends to give an overview of the basic features of the device functional modules and peripherals.

For more detailed information please refer to the corresponding family reference manual (RM0016).

Central processing unit STM84.1

The 8-bit STM8 core is designed for code efficiency and performance.

It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions.

Architecture and registers

Harvard architecture

•

3-stage pipeline

•

32-bit wide program memory bus - single cycle fetching for most instructions

•

X and Y 16-bit index registers - enabling indexed addressing modes with or without offset

•

and read-modify-write type data manipulations

8-bit accumulator

•

24-bit program counter - 16-Mbyte linear memory space

•

16-bit stack pointer - access to a 64 K-level stack

•

8-bit condition code register - 7 condition flags for the result of the last instruction

•

Addressing

20 addressing modes

•

Indexed indirect addressing mode for look-up tables located anywhere in the address

•

space

Stack pointer relative addressing mode for local variables and parameter passing

•

Instruction set

80 instructions with 2-byte average instruction size

•

Standard data movement and logic/arithmetic functions

•

8-bit by 8-bit multiplication

•

16-bit by 8-bit and 16-bit by 16-bit division

•

Bit manipulation

•

Data transfer between stack and accumulator (push/pop) with direct stack access

•

Data transfer using the X and Y registers or direct memory-to-memory transfers

•

Single wire interface module (SWIM) and debug module (DM)4.2

The single wire interface module and debug module permits non-intrusive, real-time in-circuit debugging and fast memory programming.

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Product overviewSTM8S003K3 STM8S003F3

SWIM

Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms.

Debug module

The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in real-time by means of shadow registers.

R/W to RAM and peripheral registers in real-time

•

R/W access to all resources by stalling the CPU

•

Breakpoints on all program-memory instructions (software breakpoints)

•

Two advanced breakpoints, 23 predefined configurations

•

Interrupt controller4.3

Nested interrupts with three software priority levels

•

32 interrupt vectors with hardware priority

•

Up to 27 external interrupts on 6 vectors including TLI

•

Trap and reset interrupts

•

Flash program memory and data EEPROM4.4

8 Kbytes of Flash program single voltage Flash memory

•

128 bytes of true data EEPROM

•

User option byte area

•

Write protection (WP)

Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction.

There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, the data EEPROM, and the option bytes.

To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to modify the content of the main program memory and data EEPROM, or to reprogram the device option bytes.

A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code). Refer to the figure below.

The size of the UBC is programmable through the UBC option byte, in increments of 1 page (64-byte block) by programming the UBC option byte in ICP mode.

This divides the program memory into two areas:

Main program memory: 8 Kbytes minus UBC

•

User-specific boot code (UBC): Configurable up to 8 Kbytes

•

The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot

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UBC area

Program memory area

Remains write protected during IAP

Write access possible for IAP

Option bytes

Programmable bytes(1 page)

up to 8 Kbytes (in 1 page steps)

area from 64

Low density Flash program memory (8 Kbytes)

Data EEPROM (128 bytes)

STM8S003K3 STM8S003F3Product overview

program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines.

Figure 2: Flash memory organization

Read-out protection (ROP)

The read-out protection blocks reading and writing from/to the Flash program memory and the data EEPROM in ICP mode (and debug mode). Once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.

Clock controller4.5

The clock controller distributes the system clock (f to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness.

Features

Clock prescaler: To get the best compromise between speed and current consumption

•

the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.

Safe clock switching: Clock sources can be changed safely on the fly in run mode

•

through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching.

Clock management: To reduce power consumption, the clock controller can stop the

•

clock to the core, individual peripherals or memory.

Master clock sources: Four different clock sources can be used to drive the master

•

clock:

1-16 MHz high-speed external crystal (HSE)

Up to 16 MHz high-speed user-external clock (HSE user-ext)

16 MHz high-speed internal RC oscillator (HSI)

128 kHz low-speed internal RC (LSI)

MASTER

) coming from different oscillators

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Bit

Product overviewSTM8S003K3 STM8S003F3

Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz

•

clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.

Clock security system (CSS): This feature can be enabled by software. If an HSE clock

•

failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated.

Configurable main clock output (CCO): This outputs an external clock for use by the

•

application.

Table 2: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers

Peripheral clock

ADCPCKEN23ReservedPCKEN27UART1PCKEN13TIM1PCKEN17

AWUPCKEN22ReservedPCKEN26ReservedPCKEN12ReservedPCKEN16

ReservedPCKEN21ReservedPCKEN25SPIPCKEN11TIM2PCKEN15

ReservedPCKEN20ReservedPCKEN24I2CPCKEN10TIM4PCKEN14

clock

BitPeripheral

clock

BitPeripheral

clock

BitPeripheral

Power management4.6

For efficent power management, the application can be put in one of four different low-power modes. You can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources.

Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The

•

wakeup is performed by an internal or external interrupt or reset.

Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are

•

stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.

Active halt mode with regulator off: This mode is the same as active halt with regulator

•

on, except that the main voltage regulator is powered off, so the wake up time is slower.

Halt mode: In this mode the microcontroller uses the least power. The CPU and peripheral

•

clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset.

Watchdog timers4.7

The watchdog system is based on two independent timers providing maximum security to the applications.

Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset.

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STM8S003K3 STM8S003F3Product overview

Window watchdog timer

The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence.

The window function can be used to trim the watchdog behavior to match the application perfectly.

The application software must refresh the counter before time-out and during a limited time window.

A reset is generated in two situations:

1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to 64 ms.

2. Refresh out of window: The downcounter is refreshed before its value is lower than the one stored in the window register.

Independent watchdog timer

The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures.

It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case of a CPU clock failure

The IWDG time base spans from 60 µs to 1 s.

Auto wakeup counter4.8

Used for auto wakeup from active halt mode

•

Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock

•

LSI clock can be internally connected to TIM1 input capture channel 1 for calibration

•

Beeper4.9

The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz.

The beeper output port is only available through the alternate function remap option bit AFR7.

TIM1 - 16-bit advanced control timer4.10

This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver

16-bit up, down and up/down autoreload counter with 16-bit prescaler

•

Four independent capture/compare channels (CAPCOM) configurable as input capture,

•

output compare, PWM generation (edge and center aligned mode) and single pulse mode output

Synchronization module to control the timer with external signals

•

Break input to force the timer outputs into a defined state

•

Three complementary outputs with adjustable dead time

•

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Product overviewSTM8S003K3 STM8S003F3

Encoder mode

•

Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break

•

TIM2 - 16-bit general purpose timer4.11

16-bit autoreload (AR) up-counter

•

15-bit prescaler adjustable to fixed power of 2 ratios 1…32768

•

3 individually configurable capture/compare channels

•

PWM mode

•

Interrupt sources: 3 x input capture/output compare, 1 x overflow/update

•

TIM4 - 8-bit basic timer4.12

8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128

•

Clock source: CPU clock

•

Interrupt source: 1 x overflow/update

•

Table 3: TIM timer features

Timer

Counter size (bits)

16TIM1

16TIM2

8TIM4

Prescaler

Any integer from 1 to 65536

Any power of 2 from 1 to 32768

Any power of 2 from 1 to 128

Counting mode

CAPCOM channels

Complem. outputs

Ext. trigger

Yes34Up/down

No03Up

No00Up

Timer synchronization/ chaining

Analog-to-digital converter (ADC1)4.13

The STM8S003xx products contain a 10-bit successive approximation A/D converter (ADC1) with up to 5 external multiplexed inputs channels and the following features:

Input voltage range: 0 to V

•

Conversion time: 14 clock cycles

•

Single and continuous and buffered continuous conversion modes

•

Buffer size (n x 10 bits) where n = number of input channels

•

Scan mode for single and continuous conversion of a sequence of channels

•

Analog watchdog capability with programmable upper and lower thresholds

•

Analog watchdog interrupt

•

15/100DocID018576 Rev 3

STM8S003K3 STM8S003F3Product overview

External trigger input

•

Trigger from TIM1 TRGO

•

End of conversion (EOC) interrupt

•

Communication interfaces4.14

The following communication interfaces are implemented:

UART1: Full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA

•

mode, single wire mode, LIN2.1 master capability

SPI : Full and half-duplex, 8 Mbit/s

•

I²C: Up to 400 Kbit/s

•

UART14.14.1

Main features

One Mbit/s full duplex SCI

•

SPI emulation

•

High precision baud rate generator

•

Smartcard emulation

•

IrDA SIR encoder decoder

•

LIN master mode

•

Single wire half duplex mode

•

Asynchronous communication (UART mode)

Full duplex communication - NRZ standard format (mark/space)

•

Programmable transmit and receive baud rates up to 1 Mbit/s (f

•

following any standard baud rate regardless of the input frequency

Separate enable bits for transmitter and receiver

•

Two receiver wakeup modes:

•

Address bit (MSB)

Idle line (interrupt)

Transmission error detection with interrupt generation

•

Parity control

•

Synchronous communication

Full duplex synchronous transfers

•

SPI master operation

•

8-bit data communication

•

Maximum speed: 1 Mbit/s at 16 MHz (f

•

LIN master mode

Emission: Generates 13-bit synch break frame

•

Reception: Detects 11-bit break frame

•

CPU

/16)

/16) and capable of

CPU

DocID018576 Rev 316/100

Product overviewSTM8S003K3 STM8S003F3

SPI4.14.2

Maximum speed: 8 Mbit/s (f

•

Full duplex synchronous transfers

•

Simplex synchronous transfers on two lines with a possible bidirectional data line

•

Master or slave operation - selectable by hardware or software

•

CRC calculation

•

1 byte Tx and Rx buffer

•

Slave/master selection input pin

•

I²C4.14.3

I²C master features:

•

Clock generation

Start and stop generation

I²C slave features:

•

Programmable I2C address detection

Stop bit detection

MASTER

/2) both for master and slave

Generation and detection of 7-bit/10-bit addressing and general call

•

Supports different communication speeds:

•

Standard speed (up to 100 kHz)

Fast speed (up to 400 kHz)

17/100DocID018576 Rev 3

C_SCL/(T) PB4

TIM1_ETR/AIN3/(HS) PB3

TIM1_CH3N/ AIN2/(HS)PB2

TIM1_CH2N/ AIN1/(HS) PB1

TIM1_CH1N/AIN0/(HS) PB0

PB7

PB6

C_SDA/ (T) PB5

32 31 30 29 28 27 26 25

24 23 22 21 20 19 18 17

9 10 11 12 13 14 15

1 2 3 4 5 6 7 8

VCAP

[SPI_NSS] TIM2_CH3/(HS)PA3

PF4

NRST

OSCIN/PA1

OSCOUT/PA2

PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2

PC1 (HS)/TIM1_CH1/UART1_CK PE5 (HS)/SPI_NSS

PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI PC5 (HS)/SPI_SCK PC4 (HS)/TIM1_CH4/CLK_CCO

PD3 (HS)/TIM2_CH2/ADC_ETR

PD2 (HS) [TIM2_CH3]

PD1 (HS)/SWIM

PD0 (HS)/ TIM1_BKIN [CLK_CCO]

PD7 (HS)/TLI [TIM1_CH4]

PD6 (HS)/UART1_RX

PD5 (HS)/UART1_TX

PD4 (HS)/BEEP/TIM2_CH1

STM8S003K3 STM8S003F3Pinout and pin description

Pinout and pin description5

Table 4: Legend/abbreviations for pinout tables

I= Input, O = Output, S = Power supplyType

Output speed

configuration

Reset state

STM8S003K3 LQFP32 pinout and pin description5.1

InputLevel

CM = CMOS

HS = High sinkOutput

O1 = Slow (up to 2 MHz)

O2 = Fast (up to 10 MHz)

O3 = Fast/slow programmability with slow as default state after reset

O4 = Fast/slow programmability with fast as default state after reset

float = floating, wpu = weak pull-upInputPort and control

Output

T = True open drain, OD = Open drain, PP = Push pull

Bold X (pin state after internal reset release).

Unless otherwise specified, the pin state is the same during the reset phase and after the internal reset release.

Figure 3: STM8S003K3 LQFP32 pinout

DocID018576 Rev 318/100

Pinout and pin descriptionSTM8S003K3 STM8S003F3

1. (HS) high sink capability.

2. (T) True open drain (P-buffer and protection diode to VDDnot implemented).

3. [ ] alternate function remapping option (if the same alternate function is shown twice, it

indicates an exclusive choice not a duplication of the function).

Table 5: LQFP32 pin description

Pin no.

name

PA1/ OSCI

TIM2_CH3 [SPI_NSS]

(2)

Type

OutputInput

Ext.

wpufloating

interrupt

High sink

(1)

PPODSpeed

Main function (after reset)

ResetXI/ONRST1

Port A1XXO1XXXI/O

Port A2XXO1XXXI/OPA2/ OSCOUT3

Digital groundSV

1.8 V regulator capacitorSVCAP5

Digital power supplySV

Port A3XXO3HSXXXI/OPA3/

Port F4XXO1XXI/OPF48

Default alternate function

Resonator/ crystal in

Resonator/ crystal out

Timer 2 channel 3

Alternate function after remap [option bit]

SPI master/ slave select [AFR1]

TIM1_ETR

TIM1_CH3N

Port B7XXO1XXXI/OPB79

Port B6XXO1XXXI/OPB610

O1XXI/OPB5/ I2C_SDA11

O1XXI/OPB4/ I2C_SCL12

(3)

Port B3XXO3HSXXXI/OPB3/AIN3/

Port B2XXO3HSXXXI/OPB2/AIN2/

I2C dataPort B5

I2C clockPort B4

Analog input 3/ Timer 1 external trigger

Analog input 2/ Timer 1 inverted channel 3

19/100DocID018576 Rev 3

STM8S003K3 STM8S003F3Pinout and pin description

Pin no.

name

TIM1_CH2N

TIM1_CH1N

SPI_NSS

TIM1_CH1/ UART1_CK

TIM1_CH2

Type

OutputInput

Ext.

wpufloating

interrupt

High sink

(1)

PPODSpeed

Main function (after reset)

Port B1XXO3HSXXXI/OPB1/AIN1/

Port B0XXO3HSXXXI/OPB0/AIN0/

Port E5XXO3HSXXXI/OPE5/

Port C1XXO3HSXXXI/OPC1/

Port C2XXO3HSXXXI/OPC2/

Default alternate function

Analog input 1/ Timer 1 inverted channel 2

Analog input 0/ Timer 1 inverted channel 1

SPI master/slave select

Timer 1 channel 1 UART1 clock

Timer 1 channel 2

Alternate function after remap [option bit]

TIM1_CH3

TIM1_CH4/ CLK_CCO

TIM1_BKIN [CLK_CCO]

(4)

[TIM2_CH3]

Port C3XXO3HSXXXI/OPC3/

Port C4XXO3HSXXXI/OPC4/

Port C6XXO3HSXXXI/OPC6/ PI_MOSI23

Port C7XXO3HSXXXI/OPC7/ PI_MISO24

Port D0XXO3HSXXXI/OPD0/

Port D1XXO4HSXXXI/OPD1/ SWIM

Port D2XXO3HSXXXI/OPD2

Timer 1 channel 3

Timer 1 channel 4 /configurable clock output

SPI clockPort C5XXO3HSXXXI/OPC5/ SPI_SCK22

SPI master out/slave in

SPI master in/ slave out

Timer 1 - break input

SWIM data interface

Configurable clock output [AFR5]

Timer 2 channel 3[AFR1]

DocID018576 Rev 320/100

20 19 18 17 16 15 14 13

1 2 3 4 5 6 7 8

UART1_CK/TIM2_CH1/BEEP/(HS)PD4

NRST

VCAP

OSCOUT/PA2

PD3 (HS)/AIN4/TIM2_CH2/ADC_ETR

PD1(HS)/SWIM

PB4 (T)/I2C_SCL [ADC_ETR]

PC3 (HS)/TIM1_CH3 [TLI] [TIM1_CH1N]

PC4 (HS)/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N]

PC5 (HS)/SPI_SCK [TIM2_CH1]

12 11

9 10

[SPI_NSS] TIM2_CH3/(HS) PA3

PD2 (HS)/AIN3/[TIM2_CH3]

OSCIN/PA1

PB5 (T)/I2C_SDA [TIM1_BKIN]

UART1_TX/AIN5/(HS) PD5 UART1_RX/AIN6/(HS) PD6

PC6 (HS)/SPI_MOSI [TIM1_CH1]

PC7 (HS)/SPI_MISO [TIM1_CH2]

Pinout and pin descriptionSTM8S003K3 STM8S003F3

Pin no.

name

TIM2_CH2/ ADC_ETR

TIM2_CH1

Type

OutputInput

Ext.

wpufloating

interrupt

High sink

(1)

PPODSpeed

Main function (after reset)

Port D3XXO3HSXXXI/OPD3/

Default alternate function

Timer 2 channel 2/ADC external trigger

Port D4XXO3HSXXXI/OPD4/BEEP/

Timer 2 channel

Alternate function after remap [option bit]

1/BEEP output

UART1_TX

Port D5XXO3HSXXXI/OPD5/

Port D6XXO3HSXXXI/OPD6/

UART1_RX

Port D7XXO3HSXXXI/OPD7/ TLI

[TIM1_CH4]

UART1 data transmit

UART1 data receive

Top level interrupt

Timer 1 channel 4 [AFR6]

(1)

I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings (see Electrical characteristics). (2)

When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode if Halt/Active-halt is used in the application. (3)

In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDDare not implemented). (4)

The PD1 pin is in input pull-up during the reset phase and after internal reset release.

STM8S003F3 TSSOP20/UFQFPN20 pinout and pin description5.2

STM8S003F3 TSSOP20 pinout and pin description5.2.1

Figure 4: STM8S003F3 TSSOP20 pinout

1. HS high sink capability.

21/100DocID018576 Rev 3

6 7 8

16171819

VCAP

OSCOUT/PA2

OSCIN/PA1

[SPI_NSS] TIM2_CH3/(HS) PA3

NRST

PD4 (HS)/BEEP / TIM2_CH1/UART1_CK

PD5(HS)/AIN5/UART1_TX

PD3 (HS)/AIN4/TIM2_CH2/ADC_ETR

PD2(HS)/AIN3/{TIM2_CH3]

PC4(HS)/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N]

PC5 (HS)/SPI_SCK [TIM2_CH1]

PC6(HS)/SPI_MOSI [TIM1_CH1]

PC7(HS)/SPI_MISO[TIM1_CH2]

PD1(HS)/SWIM

[TIM1_BKIN] I

C_SDA/(T)PB5

PD6(HS)/AIN6/UART1_RX

[ADC_ETR] I

C_SCL/(T)PB4

STM8S003K3 STM8S003F3Pinout and pin description

2. (T) True open drain (P-buffer and protection diode to VDDnot implemented).

3. [ ] alternate function remapping option (If the same alternate function is shown twice, it

indicates an exclusive choice not a duplication of the function).

STM8S003F3 UFQFPN20 pinout5.2.2

Figure 5: STM8S003F3 UFQFPN20-pin pinout

Pin no.

1. HS high sink capability.

2. (T) True open drain (P-buffer and protection diode to VDDnot implemented).

3. [ ] alternate function remapping option (if the same alternate function is shown twice, it

indicates an exclusive choice not a duplication of the function).

STM8S003F3 TSSOP20/UFQFPN20 pin description5.2.3

181

TIM2_ CH1/ UART1 _CK

Table 6: STM8S003F3 pin description

OutputInput

TypePin name

wpufloatingUFQFPN20TSSOP20

DocID018576 Rev 322/100

Ext. interr.

High sink

(1)

PPODSpeed

XXO3HSXXXI/OPD4/ BEEP/

Main function (after reset)

Port D4

Default alternate function

Timer 2 channel 1/BEEP output/

Alternate function after remap [option bit]

Pinout and pin descriptionSTM8S003K3 STM8S003F3

Pin no.

OutputInput

TypePin name

192

203

UART1 _TX

UART1 _RX

(2)

OSCOUT

SVCAP58

wpufloatingUFQFPN20TSSOP20

Ext. interr.

High sink

(1)

Main function (after

PPODSpeed

reset)

Port

XXO3HSXXXI/OPD5/ AIN5/

Port

XXO3HSXXXI/OPD6/ AIN6/

ResetXI/ONRST14

Port

XXO1XXXI/OPA1/ OSCIN

Port

XXO1XXXI/OPA2/

Digital groundSV

1.8 V regulator capacitor

Default alternate function

UART1 clock

Analog input 5/ UART1 data transmit

Analog input 6/ UART1 data receive

Resonator/ crystal in

Resonator/ crystal out

Alternate function after remap [option bit]

710

811

912

1013

1114

1215

CH3 [SPI_ NSS]

SDA [TIM1_ BKIN]

SCL

TIM1_CH3 [TLI] [TIM1_ CH1N]

CLK_CCO/ TIM1_ CH4/AIN2/[TIM1_ CH2N]

SPI_SCK [TIM2_ CH1]

O1XXI/OPB5/ I2C_

(3)

O1XXI/OPB4/ I2C_

Digital power supplySV

Port

XXO3HSXXXI/OPA3/ TIM2_

Port

XXO3HSXXXI/OPC3/

Port

XXO3HSXXXI/OPC4/

XXO3HSXXXI/OPC5/

Timer 2 channel 3

I2C dataPort

I2C clockPort

Timer 1 channel 3

Configurable clock output/Timer 1 - channel 4/Analog input 2

SPI clockPort

SPI master/ slave select [AFR1]

Timer 1 break input [AFR4]

ADC external trigger [AFR4]

Top level interrupt [AFR3] Timer 1 - inverted channel 1 [AFR7]

Timer 1 inverted channel 2 [AFR7]

Timer 2 channel 1 [AFR0]

23/100DocID018576 Rev 3

STM8S003K3 STM8S003F3Pinout and pin description

Ext. interr.

OutputInput

High sink

(1)

PPODSpeed

XXO3HSXXXI/OPC6/

XXO3HSXXXI/OPC7/

XXO4HSXXXI/OPD1/

XXO3HSXXXI/OPD2/AIN3/[TIM2_

XXO3HSXXXI/OPD3/ AIN4/

Main function (after reset)

Port C6

Port C7

Port D1

Port D2

Port D3

Default alternate function

SPI master out/slave in

SPI master in/ slave out

SWIM data interface

Analog input 3

Analog input 4/ Timer 2 channel 2/ADC external trigger

Alternate function after remap [option bit]

Timer 1 channel 1 [AFR0]

Timer 1 channel 2 [AFR0]

Timer 2 channel 3 [AFR1]

Pin no.

TypePin name

1316

1417

1518

1619

1720

(1)

I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings. (2)

When the MCU is in halt/active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode if halt/active-halt is used in the application. (3)

In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDDare not implemented). (4)

The PD1 pin is in input pull-up during the reset phase and after internal reset release.

SPI_MOSI [TIM1_ CH1]

SPI_MISO [TIM1_ CH2]

(4)

SWIM

CH3]

TIM2_ CH2/ ADC_ ETR

wpufloatingUFQFPN20TSSOP20

Alternate function remapping5.3

As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. When the remapping option is active, the default alternate function is no longer available.

To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers.

Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO section of the family reference manual, RM0016).

DocID018576 Rev 324/100

0x00 9FFF

Flash program memory

(8 Kbytes)

0x00 0000

RAM

0x00 03FF

(1 Kbyte)

513 bytes stack

Reserved

0x00 A000

0x02 7FFF

0x00 47FF

0x00 8000

32 interrupt vectors

0x00 807F

GPIO and periph. reg.

0x00 5000

0x00 57FF

0x00 5800

0x00 7FFF

0x00 480B

0x00 4FFF

0x00 7EFF

CPU/SWIM/debug/ITC

registers

0x00 7F00

Reserved

Option bytes

0x00 480A

0x00 4800

0x00 0800

0x00 8080

Reserved

0x00 407F

Data EEPROM

0x00 4000

Reserved

Memory and register mapSTM8S003K3 STM8S003F3

Memory and register map6

Memory map6.1

Figure 6: Memory map

25/100DocID018576 Rev 3

STM8S003K3 STM8S003F3Memory and register map

Register map6.2

I/O port hardware register map6.2.1

Table 7: I/O port hardware register map

0x00 5000

0x00 5005

0x00 500A

Port A

Port B

Port C

Reset status

0x00Port A data output latch registerPA_ODR

(1)

Port A input pin value registerPA_IDR0x00 5001

0xXX

0x00Port A data direction registerPA_DDR0x00 5002

0x00Port A control register 1PA_CR10x00 5003

0x00Port A control register 2PA_CR20x00 5004

0x00Port B data output latch registerPB_ODR

(1)

Port B input pin value registerPB_IDR0x00 5006

0xXX

0x00Port B data direction registerPB_DDR0x00 5007

0x00Port B control register 1PB_CR10x00 5008

0x00Port B control register 2PB_CR20x00 5009

0x00Port C data output latch registerPC_ODR

(1)

Port C input pin value registerPB_IDR0x00 500B

0xXX

0x00Port C data direction registerPC_DDR0x00 500C

0x00 500F

0x00 5014

Port D

Port E

0x00Port C control register 1PC_CR10x00 500D

0x00Port C control register 2PC_CR20x00 500E

0x00Port D data output latch registerPD_ODR

(1)

Port D input pin value registerPD_IDR0x00 5010

0xXX

0x00Port D data direction registerPD_DDR0x00 5011

0x02Port D control register 1PD_CR10x00 5012

0x00Port D control register 2PD_CR20x00 5013

0x00Port E data output latch registerPE_ODR

(1)

Port E input pin value registerPE_IDR0x00 5015

0xXX

0x00Port E data direction registerPE_DDR0x00 5016

0x00Port E control register 1PE_CR10x00 5017

DocID018576 Rev 326/100

Memory and register mapSTM8S003K3 STM8S003F3

0x00 5019

Port F

(1)

Depends on the external circuitry.

General hardware register map6.2.2

Port F input pin value registerPF_IDR0x00 501A

Table 8: General hardware register map

Reset status

0x00Port E control register 2PE_CR2Port E0x00 5018

0x00Port F data output latch registerPF_ODR

0xXX

0x00Port F data direction registerPF_DDR0x00 501B

0x00Port F control register 1PF_CR10x00 501C

0x00Port F control register 2PF_CR20x00 501D

Reset status

(1)

0x00 5059

0x00 5061

Reserved area (60 bytes)0x00 501E to

Flash0x00 505A

0x00Flash control register 1FLASH_CR1

0x00Flash control register 2FLASH_CR20x00 505B

0xFFFlash complementary control register 2FLASH_NCR20x00 505C

0x00Flash protection registerFLASH _FPR0x00 505D

0xFFFlash complementary protection registerFLASH _NFPR0x00 505E

FLASH _IAPSR0x00 505F

0x00Flash in-application programming status

Reserved area (2 bytes)0x00 5060 to

FLASH _PUKRFlash0x00 5062

0x00Flash program memory unprotection

27/100DocID018576 Rev 3

STM8S003K3 STM8S003F3Memory and register map

0x00 509F

0x00 50B2

0x00 50BF

Reset status

Reserved area (1 byte)0x00 5063

0x00Data EEPROM unprotection registerFLASH_DUKRFlash0x00 5064

Reserved area (59 bytes)0x00 5065 to

0x00External interrupt control register 1EXTI_CR1ITC0x00 50A0

0x00External interrupt control register 2EXTI_CR20x00 50A1

Reserved area (17 bytes)0x00 50A2 to

(1)

Reset status registerRST_SRRST0x00 50B3

0xXX

Reserved area (12 bytes)0x00 50B4 to

0x01Internal clock control registerCLK_ICKRCLK0x00 50C0

0x00External clock control registerCLK_ECKR0x00 50C1

Reserved area (1 byte)0x00 50C2

0xE1Clock master status registerCLK_CMSRCLK0x00 50C3

0xE1Clock master switch registerCLK_SWR0x00 50C4

0xXXClock switch control registerCLK_SWCR0x00 50C5

0x18Clock divider registerCLK_CKDIVR0x00 50C6

0xFFPeripheral clock gating register 1CLK_PCKENR10x00 50C7

0x00Clock security system registerCLK_CSSR0x00 50C8

0x00Configurable clock control registerCLK_CCOR0x00 50C9

0xFFPeripheral clock gating register 2CLK_PCKENR20x00 50CA

DocID018576 Rev 328/100

Memory and register mapSTM8S003K3 STM8S003F3

0x00 50D0

50DF

Reset status

0x00HSI clock calibration trimming registerCLK_HSITRIMR0x00 50CC

SWIM clock control registerCLK_SWIMCCR0x00 50CD

0bXXXX XXX0

ReservLK ed area (3 bytes)0x00 50CE to

0x7FWWDG control registerWWDG_CRWWDG0x00 50D1

0x7FWWDR window registerWWDG_WR0x00 50D2

Reserved area (13 bytes)0x00 50D3 to 00

(2)

IWDG key registerIWDG_KRIWDG0x00 50E0

0xXX

0x00IWDG prescaler registerIWDG_PR0x00 50E1

0x00 50EF

0x00 50FF

0xFFIWDG reload registerIWDG_RLR0x00 50E2

Reserved area (13 bytes)0x00 50E3 to

0x00AWU control/status register 1AWU_CSR1AWU0x00 50F0

AWU_APR0x00 50F1

0x3FAWU asynchronous prescaler buffer

0x00AWU timebase selection registerAWU_TBR0x00 50F2

0x1FBEEP control/status registerBEEP_CSRBEEP0x00 50F3

Reserved area (12 bytes)0x00 50F4 to

0x00SPI control register 1SPI_CR1SPI0x00 5200

0x00SPI control register 2SPI_CR20x00 5201

29/100DocID018576 Rev 3

STM8S003K3 STM8S003F3Memory and register map

0x00 520F

Reset status

0x00SPI interrupt control registerSPI_ICR0x00 5202

0x02SPI status registerSPI_SR0x00 5203

0x00SPI data registerSPI_DR0x00 5204

0x07SPI CRC polynomial registerSPI_CRCPR0x00 5205

0xFFSPI Rx CRC registerSPI_RXCRCR0x00 5206

0xFFSPI Tx CRC registerSPI_TXCRCR0x00 5207

Reserved area (8 bytes)0x00 5208 to

0x00I2C control register 1I2C_CR1I2C0x00 5210

0x00I2C control register 2I2C_CR20x00 5211

0x00I2C frequency registerI2C_FREQR0x00 5212

0x00I2C Own address register lowI2C_OARL0x00 5213

0x00I2C Own address register highI2C_OARH0x00 5214

Reserved0x00 5215

0x00I2C data registerI2C_DR0x00 5216

0x00I2C status register 1I2C_SR10x00 5217

0x00I2C status register 2I2C_SR20x00 5218

0x0XI2C status register 3I2C_SR30x00 5219

0x00I2C interrupt control registerI2C_ITR0x00 521A

0x00I2C Clock control register lowI2C_CCRL0x00 521B

DocID018576 Rev 330/100

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