ST STM8L052C6 User Manual

STM8L052C6

LQFP48

Value Line, 8-bit ultralow power MCU, 32-KB Flash,

256-byte data EEPROM, RTC, LCD, timers, USART, I2C, SPI, ADC

Datasheet − production data

Features

■ Operating conditions

– Operating power supply: 1.8 V to 3.6 V – Temperature range: -40 °C to 85 °C

■ Low power features

– 5 low power modes: Wait, Low power run

(5.1 µA), Low power wait (3 µA), Active-halt

with full RTC (1.3 µA), Halt (350 nA) – Consumption: 195 µA/MHz + 440 µA – Ultra-low leakage per I/0: 50 nA – Fast wakeup from Halt: 4.7 µs

■ Advanced STM8 core

– Harvard architecture and 3-stage pipeline – Max freq. 16 MHz, 16 CISC MIPS peak – Up to 40 external interrupt sources

■ Reset and supply management

– Low power, ultra-safe BOR reset with 5

selectable thresholds – Ultra low power POR/PDR – Programmable voltage detector (PVD)

■ Clock management

– 32 kHz and 1 to 16 MHz crystal oscillator – Internal 16 MHz factory-trimmed RC – Internal 38 kHz low consumption RC – Clock security system

■ Low power RTC

– BCD calendar with alarm interrupt – Auto-wakeup from Halt w/ periodic interrupt

■ LCD: up to 4x28 segments w/ step-up

converter

■ Memories

– 32 KB Flash program memory and

256 bytes data EEPROM with ECC, RWW – Flexible write and read protection modes – 2 Kbytes of RAM

■ DMA

– 4 channels supporting ADC, SPI, I2C,

USART, timers

– 1 channel for memory-to-memory

■ 12-bit ADC up to 1 Msps/25 channels

– Internal reference voltage

■ Timers

– Two 16-bit timers with 2 channels (used as

IC, OC, PWM), quadrature encoder

– One 16-bit advanced control timer with 3

channels, supporting motor control – One 8-bit timer with 7-bit prescaler – 2 watchdogs: 1 Window, 1 Independent – Beeper timer with 1, 2 or 4 kHz frequencies

■ Communication interfaces

– Synchronous serial interface (SPI)

–Fast I

C 400 kHz SMBus and PMBus

– USART (ISO 7816 interface and IrDA)

■ Up to 41 I/Os, all mappable on interrupt vectors

■ Development support

– Fast on-chip programming and non-

intrusive debugging with SWIM – Bootloader using USART

June 2012 Doc ID 023331 Rev 1 1/102

This is information on a product in full production.

www.st.com

Contents STM8L052C6

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2 Ultra low power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2.1 Advanced STM8 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2.2 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.5 Low power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.6 LCD (Liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.7 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.8 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.9 Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.10 System configuration controller and routing interface . . . . . . . . . . . . . . . 19

3.11 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.11.1 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.11.2 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.11.3 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.12 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.12.1 Window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.12.2 Independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.13 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.14 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.14.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.14.2 I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2/102 Doc ID 023331 Rev 1

STM8L052C6 Contents

3.14.3 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.15 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.16 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.1 System configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

8.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

8.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

8.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

8.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 56

8.3.3 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

8.3.4 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

8.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

8.3.6 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

8.3.7 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

8.3.8 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

8.3.9 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

8.3.10 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

8.3.11 12-bit ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

8.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

8.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Doc ID 023331 Rev 1 3/102

Contents STM8L052C6

9 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

9.1 ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

9.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

9.2.1 48-pin low profile quad flat 7x7mm package (LQFP48) . . . . . . . . . . . . . 98

10 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

4/102 Doc ID 023331 Rev 1

STM8L052C6 List of tables

List of tables

Table 1. Medium density value line STM8L05xxx low power device features and

peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 2. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 3. Legend/abbreviation for Table 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 4. Medium density value line STM8L05xxx pin description . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 5. Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 6. I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 7. General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 8. CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 9. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 10. Option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 11. Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 12. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 13. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 14. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 15. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 16. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 17. Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 18. Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 19. Total current consumption and timing in Low power run mode at VDD = 1.8 V to

3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 20. Total current consumption in Low power wait mode at VDD = 1.8 V to 3.6 V . . . . . . . . . . 63

Table 21. Total current consumption and timing in Active-halt mode at VDD = 1.8 V to 3.6 V. . . . . . 64

Table 22. Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal. . 65

Table 23. Total current consumption and timing in Halt mode at VDD = 1.8 to 3.6 V . . . . . . . . . . . . 65

Table 24. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 25. Current consumption under external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 26. HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 27. LSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 28. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 29. LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 30. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 31. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 32. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 33. Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 34. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 35. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 36. Output driving current (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 37. Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 38. Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 77

Table 39. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 40. SPI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 41. I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 42. LCD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 43. Reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 44. ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 45. ADC1 accuracy with VDDA = 3.3 V to 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 46. ADC1 accuracy with VDDA = 2.4 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

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List of tables STM8L052C6

Table 47. ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 48. R

max for f

AIN

= 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

ADC

Table 49. EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 50. EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 51. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 52. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 53. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 54. LQFP48 48-pin low profile quad flat package, mechanical data. . . . . . . . . . . . . . . . . . . . . 98

Table 55. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

6/102 Doc ID 023331 Rev 1

STM8L052C6 List of figures

List of figures

Figure 1. Medium density value line STM8L05xxx device block diagram . . . . . . . . . . . . . . . . . . . . 12

Figure 2. Medium density value line STM8L05xxx clock tree diagram . . . . . . . . . . . . . . . . . . . . . . 17

Figure 3. STM8L052C6 48-pin LQFP48 package pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 4. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 5. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 6. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 7. POR/BOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 8. Typ. IDD(RUN) vs. VDD, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 9. Typ. IDD(Wait) vs. VDD, fCPU = 16 MHz 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 10. Typ. IDD(LPR) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 11. Typ. IDD(LPW) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 12. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 13. LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 14. Typical HSI frequency vs V

Figure 15. Typical LSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 16. Typical VIL and VIH vs VDD (high sink I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 17. Typical VIL and VIH vs VDD (true open drain I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 18. Typical pull-up resistance R Figure 19. Typical pull-up current I

Figure 20. Typ. VOL @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 21. Typ. VOL @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 22. Typ. VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 23. Typ. VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 24. Typ. VDD - VOH @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 25. Typ. VDD - VOH @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 26. Typical NRST pull-up resistance R Figure 27. Typical NRST pull-up current I

Figure 28. Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 29. SPI1 timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 30. SPI1 timing diagram - slave mode and CPHA=1 Figure 31. SPI1 timing diagram - master mode

Figure 32. Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 33. ADC1 accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 34. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 35. Maximum dynamic current consumption on V

conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 36. Power supply and reference decoupling (V

Figure 37. Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . . 93

Figure 38. LQFP48 48-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 39. LQFP48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 40. Medium density value line STM8L05xxx ordering information scheme . . . . . . . . . . . . . . 100

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

vs VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

vs VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

REF+

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

supply pin during ADC

REF+

not connected to V

). . . . . . . . . . . . . . 93

DDA

Doc ID 023331 Rev 1 7/102

Introduction STM8L052C6

1 Introduction

This document describes the features, pinout, mechanical data and ordering information of

the medium density value line STM8L052C6 microcontroller with 32-Kbyte Flash memory

density. For further details on the whole STMicroelectronics medium density family please

refer to Section 2.2: Ultra low power continuum.

For detailed information on device operation and registers, refer to the reference manual

(RM0031).

For information on to the Flash program memory and data EEPROM, refer to the

programming manual (PM0054).

For information on the debug module and SWIM (single wire interface module), refer to the

STM8 SWIM communication protocol and debug module user manual (UM0470).

For information on the STM8 core, refer to the STM8 CPU programming manual (PM0044).

Medium density value line devices provide the following benefits:

● Integrated system

– 32 Kbytes of medium density embedded Flash program memory – 256 bytes of data EEPROM – 2 Kbytes of RAM – Internal high speed and low-power low speed RC – Embedded reset

● Ultra low power consumption

– 195 µA/MHZ + 440 µA (consumption) – 0.9 µA with LSI in Active-halt mode – Clock gated system and optimized power management – Capability to execute from RAM for Low power wait mode and low power run mode

● Advanced features

– Up to 16 MIPS at 16 MHz CPU clock frequency – Direct memory access (DMA) for memory-to-memory or peripheral-to-memory

access

● Short development cycles

– Application scalability across a common family product architecture with

compatible pinout, memory map and modular peripherals

– Wide choice of development tools

Refer to Table 1: Medium density value line STM8L05xxx low power device features and

peripheral counts and Section 3: Functional overview for an overview of the complete range

of peripherals proposed in this family.

Figure 1 shows the block diagram of the medium density value line STM8L05xxx family.

8/102 Doc ID 023331 Rev 1

STM8L052C6 Description

2 Description

The medium density value line STM8L05xxx devices are members of the STM8L ultra low

power 8-bit family.

The value line STM8L05xxx ultra low power family features the enhanced STM8 CPU core

providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the

advantages of a CISC architecture with improved code density, a 24-bit linear addressing

space and an optimized architecture for low power operations.

The family includes an integrated debug module with a hardware interface (SWIM) which

allows non-intrusive In-application debugging and ultra-fast Flash programming.

Medium density value line STM8L05xxx microcontrollers feature embedded data EEPROM

and low-power, low-voltage, single-supply program Flash memory.

All devices offer 12-bit ADC, real-time clock, 16-bit timers, one 8-bit timer as well as

standard communication interface such as SPI, I2C, USART and 4x28-segment LCD. The

4x 28-segment LCD is available on the medium density value line STM8L05xxx.

The STM8L05xxx family operates from 1.8 V to 3.6 V and is available in the

temperature range.

The modular design of the peripheral set allows the same peripherals to be found in different

ST microcontroller families including 32-bit families. This makes any transition to a different

family very easy, and simplified even more by the use of a common set of development

tools.

All value line STM8L ultra low power products are based on the same architecture with the

same memory mapping and a coherent pinout.

-40 to +85 °C

Doc ID 023331 Rev 1 9/102

Description STM8L052C6

2.1 Device overview

Table 1. Medium density value line STM8L05xxx low power device features and

peripheral counts

Features STM8L052C6

Flash (Kbytes) 32

Data EEPROM (bytes) 256

RAM (Kbytes) 2

LCD 4x28

Basic

(8-bit)

Timers

General purpose

Advanced control

(16-bit)

SPI 1 Communication interfaces

I2C 1

USART 1

GPIOs 41

12-bit synchronized ADC (number of channels)

(1)

(25)

RTC, window watchdog, independent watchdog,

Others

16-MHz and 38-kHz internal RC,

1- to 16-MHz and 32-kHz external oscillator

CPU frequency 16 MHz

Operating voltage 1.8 V to 3.6 V

Operating temperature -40 to +85 °C

Package LQFP48

1. The number of GPIOs given in this table includes the NRST/PA1 pin but the application can use the NRST/PA1 pin as general purpose output only (PA1).

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STM8L052C6 Description

2.2 Ultra low power continuum

The ultra low power value line STM8L05xxx and STM8L15xxx are fully pin-to-pin, software and feature compatible. Besides the full compatibility within the STM8L family, the devices are part of STMicroelectronics microcontrollers ultra low power strategy which also includes STM8L101xx and STM32L15xxx. The STM8L and STM32L families allow a continuum of performance, peripherals, system architecture, and features.

They are all based on STMicroelectronics 0.13 µm ultra-low leakage process.

Note: 1 The STM8L05xxx is pin-to-pin compatible with STM8L101xx devices.

2 The STM32L family is pin-to-pin compatible with the general purpose STM32F family.

Please refer to STM32L15x documentation for more information on these devices.

Performance

All families incorporate highly energy-efficient cores with both Harvard architecture and pipelined execution: advanced STM8 core for STM8L families and ARM Cortex™-M3 core for STM32L family. In addition specific care for the design architecture has been taken to optimize the mA/DMIPS and mA/MHz ratios.

This allows the ultra low power performance to range from 5 up to 33.3 DMIPs.

Shared peripherals

STM8L05x, STM8L15x and STM32L15xx share identical peripherals which ensure a very easy migration from one family to another:

● Analog peripheral: ADC1

● Digital peripherals: RTC and some communication interfaces

Common system strategy

To offer flexibility and optimize performance, the STM8L and STM32L devices use a common architecture:

● Same power supply range from 1.8 to 3.6 V

● Architecture optimized to reach ultra-low consumption both in low power modes and

Run mode

● Fast startup strategy from low power modes

● Flexible system clock

● Ultra-safe reset: same reset strategy for both STM8L and STM32L including power-on

reset, power-down reset, brownout reset and programmable voltage detector

Features

ST ultra low power continuum also lies in feature compatibility:

● More than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm

● Memory density ranging from 4 to 128 Kbytes

Doc ID 023331 Rev 1 11/102

Functional overview STM8L052C6

16 MHz internal RC

Clock

Clocks

Address, control and data buses

Debug module

SPI1

32 Kbytes

Interrupt controller

2 Kbytes RAM

to core and peripherals

IWDG

(38 kHz clock)

(SWIM)

Port A

Port B

Port C

I²C1

USART1

Power

VOLT. REG.

Port F

1-16 MHz oscillator

32 kHz oscillator

38 kHz internal RC

LCD driver

4x28

WWDG

STM8 Core

controller

and

CSS

256 bytes

Port D

Port E

Beeper

RTC

memoryprogram

data EEPROM

DD18

DD1

=1.8 V

SS1

SWIM

SCL, SDA,

MOSI, MISO,

SCK, NSS

RX, TX, CK

ADC1_INx

DDA

SSA

SMB

DDA/VSSA

12-bit ADC1

REF+

REF-

3.6 V

NRST

PA[7:0]

PB[7:0]

PC[7:0]

PD[7:0]

PE[7:0]

PF0

BEEP

ALARM, CALIB

SEGx, COMx

POR/PDR

OSC_IN,

OSC_OUT

OSC32_IN,

OSC32_OUT

BOR

PVD

PVD_IN

RESET

DMA1

8-bit Timer 4

16-bit Timer 3

16-bit Timer 2

16-bit Timer 1

(4 channels)

2 channels

3 channels

LCD

= 2.5 V

3.6 V

LCD booster

Internal reference

voltage

VREFINT out

Infrared interface

IR_TIM

3 Functional overview

Figure 1. Medium density value line STM8L05xxx device block diagram

1. Legend:

12/102 Doc ID 023331 Rev 1

ADC: Analog-to-digital converter BOR: Brownout reset DMA: Direct memory access I²C: Inter-integrated circuit multimaster interface LCD: Liquid crystal display POR/PDR: Power on reset / power down reset RTC: Real-time clock SPI: Serial peripheral interface SWIM: Single wire interface module USART: Universal synchronous asynchronous receiver transmitter WWDG: Window watchdog IWDG: independent watchdog

STM8L052C6 Functional overview

3.1 Low power modes

The medium density value line STM8L05xxx devices support five low power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

● Wait mode: The CPU clock is stopped, but selected peripherals keep running. An

internal or external interrupt, event or a Reset can be used to exit the microcontroller from Wait mode (WFE or WFI mode).

● Low power run mode: The CPU and the selected peripherals are running. Execution

is done from RAM with a low speed oscillator (LSI or LSE). Flash memory and data EEPROM are stopped and the voltage regulator is configured in ultra low power mode. The microcontroller enters Low power run mode by software and can exit from this mode by software or by a reset. All interrupts must be masked. They cannot be used to exit the microcontroller from this mode.

● Low power wait mode: This mode is entered when executing a Wait for event in Low

power run mode. It is similar to Low power run mode except that the CPU clock is stopped. The wakeup from this mode is triggered by a Reset or by an internal or external event (peripheral event generated by the timers, serial interfaces, DMA controller (DMA1) and I/O ports). When the wakeup is triggered by an event, the system goes back to Low power run mode. All interrupts must be masked. They cannot be used to exit the microcontroller from this mode.

● Active-halt mode: CPU and peripheral clocks are stopped, except RTC. The wakeup

can be triggered by RTC interrupts, external interrupts or reset.

● Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.

The RAM content is preserved. The wakeup is triggered by an external interrupt or reset. A few peripherals have also a wakeup from Halt capability. Switching off the internal reference voltage reduces power consumption. Through software configuration it is also possible to wake up the device without waiting for the internal reference voltage wakeup time to have a fast wakeup time of 5 µs.

Doc ID 023331 Rev 1 13/102

Functional overview STM8L052C6

3.2 Central processing unit STM8

3.2.1 Advanced STM8 Core

The 8-bit STM8 core is designed for code efficiency and performance with an Harvard architecture and a 3-stage pipeline.

It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing, and 80 instructions.

Architecture and registers

● Harvard architecture

● 3-stage pipeline

● 32-bit wide program memory bus - single cycle fetching most instructions

● X and Y 16-bit index registers - enabling indexed addressing modes with or without

offset and read-modify-write type data manipulations

● 8-bit accumulator

● 24-bit program counter - 16-Mbyte linear memory space

● 16-bit stack pointer - access to a 64-Kbyte level stack

● 8-bit condition code register - 7 condition flags for the result of the last instruction

Addressing

● 20 addressing modes

● Indexed indirect addressing mode for lookup tables located anywhere in the address

space

● Stack pointer relative addressing mode for local variables and parameter passing

Instruction set

● 80 instructions with 2-byte average instruction size

● Standard data movement and logic/arithmetic functions

● 8-bit by 8-bit multiplication

● 16-bit by 8-bit and 16-bit by 16-bit division

● Bit manipulation

● Data transfer between stack and accumulator (push/pop) with direct stack access

● Data transfer using the X and Y registers or direct memory-to-memory transfers

3.2.2 Interrupt controller

The medium density value line STM8L05xxx devices feature a nested vectored interrupt controller:

● Nested interrupts with 3 software priority levels

● 32 interrupt vectors with hardware priority

● Up to 40 external interrupt sources on 11 vectors

● Trap and reset interrupts

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STM8L052C6 Functional overview

3.3 Reset and supply management

3.3.1 Power supply scheme

The device requires a 1.8 V to 3.6 V operating supply voltage (VDD). The external power supply pins must be connected as follows:

● V

3.3.2 Power supply supervisor

The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset (PDR), coupled with a brownout reset (BOR) circuitry . At power-on, BOR is always active, and ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable BOR permanently.

SS1

; V

= 1.8 to 3.6 V: external power supply for I/Os and for the internal regulator.

DD1

Provided externally through V

SSA ; VDDA

SSA

SS2

connected to V

REF+

externally through V

= 1.8 to 3.6 V: external power supplies for analog peripherals. V

must be connected to V

; V

= 1.8 to 3.6 V: external power supplies for I/Os. V

; V

DD2

REF-

and V

DD1

SS1

(for ADC1): external reference voltage for ADC1. Must be provided

and V

REF+

pins, the corresponding ground pin is V

DD1

and V

, respectively.

SS1

DD2

, respectively.

pin.

REF-

and V

SS1

must be

SS2

DDA

and

Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To reduce the power consumption in Halt mode, it is possible to automatically switch off the internal reference voltage (and consequently the BOR) in Halt mode. The device remains under reset when V

for any external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the V

DD/VDDA

power supply and compares it to the V levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An interrupt can be generated when V V

DD/VDDA

is higher than the V a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

3.3.3 Voltage regulator

The medium density value line STM8L05xxx embeds an internal voltage regulator for generating the 1.8 V power supply for the core and peripherals.

This regulator has two different modes:

● Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event

(WFE) modes

● Low power voltage regulator mode (LPVR) for Halt, Active-halt, Low power run and Low

power wait modes

When entering Halt or Active-halt modes, the system automatically switches from the MVR to the LPVR in order to reduce current consumption.

is below a specified threshold, V

threshold. This PVD offers 7 different

PVD

DD/VDDA

threshold. The interrupt service routine can then generate

PVD

drops below the V

POR/PDR

PVD

or V

, without the need

BOR

threshold and/or when

Doc ID 023331 Rev 1 15/102

Functional overview STM8L052C6

3.4 Clock management

The clock controller distributes the system clock (SYSCLK) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness.

Features

● Clock prescaler: To get the best compromise between speed and current

consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.

● Safe clock switching: Clock sources can be changed safely on the fly in run mode

through a configuration register.

● Clock management: To reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

● System clock sources: 4 different clock sources can be used to drive the system

clock:

– 1-16 MHz High speed external crystal (HSE)

– 16 MHz High speed internal RC oscillator (HSI)

– 32.768 kHz Low speed external crystal (LSE)

– 38 kHz Low speed internal RC (LSI)

● RTC and LCD clock sources: The above four sources can be chosen to clock the

RTC and the LCD, whatever the system clock.

● Startup clock: After reset, the microcontroller restarts by default with an internal

2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.

● Clock security system (CSS): This feature can be enabled by software. If a HSE clock

failure occurs, the system clock is automatically switched to HSI.

● Configurable main clock output (CCO): This outputs an external clock for use by the

application.

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STM8L052C6 Functional overview

HSE OSC

1-16 MHz

HSI RC

16 MHz

LSI RC 38 kH z

LSE OSC

32 768 k

HSI

LSI

RTC

prescaler

/1;2;4;8;16;32;64

PCLK

to peripherals

RTCCLK/2

to LCD

to IWDG

SYSCLK

HSE

(1)

(2)

LSI LSE

OSC_OUT

OSC32_OUT

OSC_IN

OSC32_IN

clock output

CCO

prescaler

/1;2;4;8;16;32;64

HSI LSI HSE LSE

CCO

to core and

memory

SYSCLK Presc aler

/1;2;4;8;16;32;64;128

IWDGCLK

RTCSEL[3:0]

LSE

(2)

CLKBEEPSEL[1:0]

to BEEP

BEEPCLK

CSS

configurable

/ 2

Peripheral Clock enable (15 bits)

to RTC

RTCCLK

clock enable (1 bit)

LCDCLK

to LCD

SYSCLK

Halt

clock enable (1 bit)

LCD peripheral

RTCCLK

LCD peripheral

(1)

(2)

Figure 2. Medium density value line STM8L05xxx clock tree diagram

1. The HSE clock source can be either an external crystal/ceramic resonator or an external source (HSE

bypass). Refer to Section HSE clock in the STM8L15x and STM8L16x reference manual (RM0031).

2. The LSE clock source can be either an external crystal/ceramic resonator or a external source (LSE

bypass). Refer to Section LSE clock in the STM8L15x and STM8L16x reference manual (RM0031).

3.5 Low power real-time clock

The real-time clock (RTC) is an independent binary coded decimal (BCD) timer/counter.

Six byte locations contain the second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day months are made automatically.

It provides a programmable alarm and programmable periodic interrupts with wakeup from Halt capability.

● Periodic wakeup time using the 32.768 kHz LSE with the lowest resolution (of 61 µs) is

from min. 122 µs to max. 3.9 s. With a different resolution, the wakeup time can reach 36 hours.

● Periodic alarms based on the calendar can also be generated from every second to

every year.

Doc ID 023331 Rev 1 17/102

Functional overview STM8L052C6

3.6 LCD (Liquid crystal display)

The LCD is only available on STM8L052xx devices.

● The liquid crystal display drives up to 4 common terminals and up to 28 segment

terminals to drive up to 112 pixels. Internal step-up converter to guarantee contrast control whatever V

● Static 1/2, 1/3, 1/4 duty supported.

● Static 1/2, 1/3, bias supported.

● Phase inversion to reduce power consumption and EMI.

● Up to 4 pixels which can be programmed to blink.

● The LCD controller can operate in Halt mode.

Note: Unnecessary segments and common pins can be used as general I/O pins.

3.7 Memories

The medium density value line STM8L05xxx devices have the following main features:

● 2 Kbytes of RAM

● The non-volatile memory is divided into three arrays:

– 32 Kbytes of medium density embedded Flash program memory

– 256 bytes of data EEPROM

–Option bytes

The EEPROM embeds the error correction code (ECC) feature. It supports the read-whilewrite (RWW): it is possible to execute the code from the program matrix while programming/erasing the data matrix.

The option byte protects part of the Flash program memory from write and readout piracy.

3.8 DMA

A 4-channel direct memory access controller (DMA1) offers a memory-to-memory and peripherals-from/to-memory transfer capability. The 4 channels are shared between the following IPs with DMA capability: ADC1, I2C1, SPI1, USART1and the four timers.

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STM8L052C6 Functional overview

3.9 Analog-to-digital converter

● 12-bit analog-to-digital converter (ADC1) with 25 channels (including 1 fast channel)

and internal reference voltage

● Conversion time down to 1 µs with f

● Programmable resolution

● Programmable sampling time

● Single and continuous mode of conversion

● Scan capability: automatic conversion performed on a selected group of analog inputs

● Analog watchdog

● Triggered by timer

SYSCLK

= 16 MHz

Note: ADC1 can be served by DMA1.

3.10 System configuration controller and routing interface

The system configuration controller provides the capability to remap some alternate functions on different I/O ports. TIM4 and ADC1 DMA channels can also be remapped.

The highly flexible routing interface allows application software to control the routing of different I/Os to the TIM1 timer input captures. It also controls the routing of internal analog signals to ADC1 and the internal reference voltage V

REFINT

3.11 Timers

The medium density value line STM8L05xxx devices contain one advanced control timer (TIM1), two 16-bit general purpose timers (TIM2 and TIM3) and one 8-bit basic timer (TIM4).

All the timers can be served by DMA1.

Ta bl e 2 compares the features of the advanced control, general-purpose and basic timers.

Table 2. Timer feature comparison

Timer

TIM1

TIM2

TIM3

TIM4 8-bit up

Counter

resolution

16-bit up/down

Counter

type

Prescaler factor

Any integer

from 1 to 65536

Any power of 2

from 1 to 128

Any power of 2

from 1 to 32768

DMA1

request

generation

Ye s

Capture/compare

channels

3 + 1 3

Complementary

outputs

None

Doc ID 023331 Rev 1 19/102

Functional overview STM8L052C6

3.11.1 TIM1 - 16-bit advanced control timer

This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver.

● 16-bit up, down and up/down autoreload counter with 16-bit prescaler

● 3 independent capture/compare channels (CAPCOM) configurable as input capture,

output compare, PWM generation (edge and center aligned mode) and single pulse mode output

● 1 additional capture/compare channel which is not connected to an external I/O

● Synchronization module to control the timer with external signals

● Break input to force timer outputs into a defined state

● 3 complementary outputs with adjustable dead time

● Encoder mode

● Interrupt capability on various events (capture, compare, overflow, break, trigger)

3.11.2 16-bit general purpose timers

● 16-bit autoreload (AR) up/down-counter

● 7-bit prescaler adjustable to fixed power of 2 ratios (1…128)

● 2 individually configurable capture/compare channels

● PWM mode

● Interrupt capability on various events (capture, compare, overflow, break, trigger)

● Synchronization with other timers or external signals (external clock, reset, trigger and

enable)

3.11.3 8-bit basic timer

The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. It can be used for timebase generation with interrupt generation on timer overflow.

3.12 Watchdog timers

The watchdog system is based on two independent timers providing maximum security to the applications.

3.12.1 Window watchdog timer

The window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence.

3.12.2 Independent watchdog timer

The independent watchdog peripheral (IWDG) can be used to resolve processor malfunctions due to hardware or software failures.

It is clocked by the internal LSI RC clock source, and thus stays active even in case of a CPU clock failure.

20/102 Doc ID 023331 Rev 1

STM8L052C6 Functional overview

3.13 Beeper

The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz.

3.14 Communication interfaces

3.14.1 SPI

The serial peripheral interface (SPI1) provides half/ full duplex synchronous serial communication with external devices.

● Maximum speed: 8 Mbit/s (f

● Full duplex synchronous transfers

● Simplex synchronous transfers on 2 lines with a possible bidirectional data line

● Master or slave operation - selectable by hardware or software

● Hardware CRC calculation

● Slave/master selection input pin

SYSCLK

Note: SPI1 can be served by the DMA1 Controller.

/2) both for master and slave

3.14.2 I²C

The I2C bus interface (I2C1) provides multi-master capability, and controls all I²C busspecific sequencing, protocol, arbitration and timing.

● Master, slave and multi-master capability

● Standard mode up to 100 kHz and fast speed modes up to 400 kHz

● 7-bit and 10-bit addressing modes

● SMBus 2.0 and PMBus support

● Hardware CRC calculation

Note: I

C1 can be served by the DMA1 Controller.

3.14.3 USART

The USART interface (USART1) allows full duplex, asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format. It offers a very wide range of baud rates.

● 1 Mbit/s full duplex SCI

● SPI1 emulation

● High precision baud rate generator

● Smartcard emulation

● IrDA SIR encoder decoder

● Single wire half duplex mode

Note: USART1 can be served by the DMA1 Controller.

Doc ID 023331 Rev 1 21/102

Functional overview STM8L052C6

3.15 Infrared (IR) interface

The medium density value line STM8L05xxx devices contain an infrared interface which can be used with an IR LED for remote control functions. Two timer output compare channels are used to generate the infrared remote control signals.

3.16 Development support

Development tools

Development tools for the STM8 microcontrollers include:

● The STice emulation system offering tracing and code profiling

● The STVD high-level language debugger including C compiler, assembler and

integrated development environment

● The STVP Flash programming software

The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools.

Single wire data interface (SWIM) and debug module

The debug module with its single wire data interface (SWIM) permits non-intrusive real-time in-circuit debugging and fast memory programming.

The Single wire interface is used for direct access to the debugging module and memory programming. The interface can be activated in all device operation modes.

The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, CPU operation can also be monitored in realtime by means of shadow registers.

Bootloader

A bootloader is available to reprogram the Flash memory using the USART1 interface. The reference document for the bootloader is UM0560: STM8 bootloader user manual.

The bootloader is used to download application software into the device memories, including RAM, program and data memory, using standard serial interfaces. It is a complementary solution to programming via the SWIM debugging interface.

22/102 Doc ID 023331 Rev 1

STM8L052C6 Pin description

44 43 42 41 4 0 39 38 3 7

35 34 33 32 31 30 29 28 27 26 25

13 1 4 15 16 17 18 19 20 21 22

1 2 3 4 5 6 7 8 9 10 11

48 47 46 45

PA5

SS1/VSSA/VREF-

NRST/PA1

PA2 PA3 PA4

PA6

VLCD

PE0

PE1

PD1

PD2

PD3

PB0

PE3

PD0

PE5

PE4

PA7

DD1

DDA

REF+

PE2

PB1

PB2

PC0

PC1

DD2VSS2

PC2

PC3

PC4

PC5

PC6

PC7

PE6

PE7

PB3

PB4

PB5

PB6

PB7

PF0

PD4

PD5

PD6

PD7

PA 0

4 Pin description

Figure 3. STM8L052C6 48-pin LQFP48 package pinout (with LCD)

Doc ID 023331 Rev 1 23/102

Pin description STM8L052C6

Table 3. Legend/abbreviation for Table 4

Typ e I= input, O = output, S = power supply

FT Five-volt tolerant

Level

Port and control configuration

Reset state

Table 4. Medium density value line STM8L05xxx pin description

TT 3.6 V tolerant

Output HS = high sink/source (20 mA)

Input float = floating, wpu = weak pull-up

Output T = true open drain, OD = open drain, PP = push pull

Bold X (pin state after reset release). Unless otherwise specified, the pin state is the same during the reset phase (i.e. “under reset”) and after internal reset release (i.e. at reset state).

number

LQFP48

2 NRST/PA1

PA2/OSC_IN/

[USART1_TX] [SPI1_MISO]

PA3/OSC_OUT/[USART1_

RX]

(8)

/[SPI1_MOSI]

PA4/TIM2_BKIN/

LCD_COM0/ADC1_IN2

PA5/TIM3_BKIN/

LCD_COM1/ADC1_IN1

PA 6/ [ADC1_TRIG]/

LCD_COM2/ADC1_IN0

8 PA7/LCD_SEG0

(4)

PB0

/TIM2_CH1/

LCD_SEG10/ADC1_IN18

PB1/TIM3_CH1/

LCD_SEG11/ ADC1_IN17

PB2/ TIM2_CH2/

LCD_SEG12/ ADC1_IN16

Pin name

(1)

(8)

(3)

(8)

Input Output

Type

I/O level

wpu

floating

Default alternate function

(after reset)

Main function

Ext. interrupt

High sink/source

I/O X HS X Reset PA 1

HSE oscillator input /

I/O X X X HS X X Port A2

[USART1 transmit] / [SPI1 master in- slave out]

HSE oscillator output /

I/O X X X HS X X Port A3

[USART1 receive]/ [SPI1 master out/slave in]/

I/O TT

(2)

XXXHSXXPort A4

(2)

XXXHSXXPort A5

Timer 2 - break input / LCD COM 0 / ADC1 input 2

Timer 3 - break input / LCD_COM 1 / ADC1 input 1

[ADC1 - trigger] / LCD_COM2 /

I/O TT

(2)

XXXHSXXPort A6

ADC1 input 0

I/O FT X X X HS X X Port A7 LCD segment 0

I/O TT

(2)X(4)X(4)

(2)

XXXHSXXPort B1

(2)

XXXHSXXPort B2

XHSX XPort B0

Timer 2 - channel 1 / LCD segment 10 / ADC1_IN18

Timer 3 - channel 1 / LCD segment 11 / ADC1_IN17

Timer 2 - channel 2 / LCD segment 12 / ADC1_IN16

24/102 Doc ID 023331 Rev 1

STM8L052C6 Pin description

Table 4. Medium density value line STM8L05xxx pin description (continued)

number

LQFP48

37 PC0

38 PC1

Input Output

Pin name

Typ e

I/O level

floating

PB3/TIM2_ETR/ LCD_SEG13/

I/O TT

(2)

XXXHSXXPort B3

ADC1_IN15

(4)

PB4

/[SPI1_NSS]

LCD_SEG14/

(8)

I/O TT

(2)X(4)X(4)

ADC1_IN14

PB5/[SPI1_SCK] LCD_SEG15/

(8)

I/O TT

(2)

XXXHSXXPort B5

ADC1_IN13

(8)

PB6/[SPI1_MOSI] LCD_SEG16/

I/O TT

(2)

XXXHSXXPort B6

ADC1_IN12

PB7/[SPI1_MISO] LCD_SEG17/

(8)

I/O TT

(2)

XXXHSXXPort B7

ADC1_IN11

(3)

/I2C1_SDA I/O FT X X T

(3)

/I2C1_SCL I/O FT X X T

PC2/USART1_RX/ LCD_SEG22/ADC1_IN6/

I/O TT

(2)

XXXHSXXPort C2

VREFINT

wpu

Ext. interrupt

High sink/source

XHSX XPort B4

(5)

Default alternate function

(after reset)

Main function

Timer 2 - external trigger / LCD segment 13 /ADC1_IN15

[SPI1 master/slave select] / LCD segment 14 / ADC1_IN14

[SPI1 clock] / LCD segment 15 / ADC1_IN13

[SPI1 master out/slave in]/ LCD segment 16 / ADC1_IN12

[SPI1 master in- slave out]

/LCD segment 17 / ADC1_IN11

Port C0 I2C1 data

Port C1 I2C1 clock

USART1 receive / LCD segment 22 / ADC1_IN6 /Internal voltage reference output

PC3/USART1_TX/

LCD_SEG23/ ADC1_IN5

PC4/USART1_CK/ I2C1_SMB/CCO/

LCD_SEG24/ ADC1_IN4

PC5/OSC32_IN

/[SPI1_NSS]

[USART1_TX]

PC6/OSC32_OUT/

[SPI1_SCK] [USART1_RX]

PC7/LCD_SEG25/

ADC1_IN3

(8)

USART1 transmit / LCD segment 23 /

I/O TT

(2)

XXXHSXXPort C3

ADC1_IN5

USART1 synchronous clock / I2C1_SMB / Configurable clock output /

I/O TT

(2)

XXXHSXXPort C4

LCD segment 24/ ADC1_IN4

LSE oscillator input / [SPI1

I/O X X X HS X X Port C5

master/slave select] / [USART1 transmit]

LSE oscillator output /

I/O X X X HS X X Port C6

[SPI1 clock] / [USART1 receive]

I/O TT

(2)

XXXHSXXPort C7

LCD segment 25 /ADC1_IN3

Doc ID 023331 Rev 1 25/102

Pin description STM8L052C6

Table 4. Medium density value line STM8L05xxx pin description (continued)

number

LQFP48

Pin name

PD0/TIM3_CH2/

[ADC1_TRIG]

(8)

LCD_SEG7/ADC1_IN22/

PD1/TIM3_ETR/ LCD_COM3/ ADC1_IN21

PD2/TIM1_CH1 /LCD_SEG8/ ADC1_IN20

PD3/ TIM1_ETR/ LCD_SEG9/ADC1_IN19

PD4/TIM1_CH2 /LCD_SEG18/ ADC1_IN10

Typ e

I/O TT

Input Output

I/O level

wpu

floating

Ext. interrupt

High sink/source

(2)

XXXHSXXPort D0

(2)

XXXHSXXPort D1

(2)

XXXHSXXPort D2

(2)

XXXHSXXPort D3

(2)

XXXHSXXPort D4

Main function

Default alternate function

(after reset)

Timer 3 - channel 2 / [ADC1_Trigger] / LCD segment 7 / ADC1_IN22

Timer 3 - external trigger / LCD_COM3 / ADC1_IN21

Timer 1 - channel 1 / LCD segment 8 / ADC1_IN20

Timer 1 - externaltrigger / LCD segment 9 / ADC1_IN19

Timer 1 - channel 2 / LCD segment 18 / ADC1_IN10

PD5/TIM1_CH3

/LCD_SEG19/

I/O TT

ADC1_IN9

PD6/TIM1_BKIN /LCD_SEG20/

ADC1_IN8/RTC_CALIB/

I/O TT

/VREFINT

PD7/TIM1_CH1N /LCD_SEG21/

ADC1_IN7/RTC_ALARM/V

I/O TT

REFINT

14 PE0

(3)

/LCD_SEG1 I/O FT X X X HS X X Port E0 LCD segment 1

PE1/TIM1_CH2N/ LCD_SEG2

PE2/TIM1_CH3N/ LCD_SEG3

I/O TT

17 PE3/LCD_SEG4 I/O TT

18 PE4/LCD_SEG5 I/O TT

PE5/LCD_SEG6/

ADC1_IN23

PE6/LCD_SEG26/

PVD_IN

I/O TT

(2)

XXXHSXXPort D5

Timer 1 - channel 3 / LCD segment 19 / ADC1_IN9

Timer 1 - break input / LCD

(2)

XXXHSXXPort D6

segment 20 / ADC1_IN8 / RTC calibration / Internal voltage reference output

Timer 1 - inverted channel

(2)

XXXHSXXPort D7

1/ LCD segment 21 / ADC1_IN7 / RTC alarm / Internal voltage reference output

(2)

XXXHSXXPort E1

(2)

XXXHSXXPort E2

(2)

XXXHSXXPort E3 LCD segment 4

(2)

XXXHSXXPort E4 LCD segment 5

(2)

XXXHSXXPort E5

(2)

XXXHSXXPort E6 LCD segment 26/PVD_IN

Timer 1 - inverted channel 2 / LCD segment 2

Timer 1 - inverted channel 3 / LCD segment 3

LCD segment 6 / ADC1_IN23

26/102 Doc ID 023331 Rev 1

STM8L052C6 Pin description

Table 4. Medium density value line STM8L05xxx pin description (continued)

number

LQFP48

Pin name

Typ e

Input Output

I/O level

wpu

floating

Main function

Default alternate function

(after reset)

Ext. interrupt

High sink/source

PE7/LCD_SEG27

32 PF0/ADC1_IN24 I/O X X X HS X X Por t F0

I/O TT

(2)

XXXHSXXPort E7 LCD segment 27

ADC1_IN24

13 VLCD S LCD booster external capacitor

13 Reserved Reserved. Must be tied to V

10 V

11 V

12 V

39 V

40 V

DDA

REF+

SS1/VSSA/VREF-

DD2

SS2

(6)

PA 0

/[USART1_CK]

SWIM/BEEP/IR_TIM

(8)

(7)

S Digital power supply

S Analog supply voltage

S ADC1 positive voltage reference

I/O ground / Analog ground voltage / ADC1 negative voltage reference

S IOs supply voltage

S IOs ground voltage

[USART1 synchronous

I/O X X

(6)

XXPort A0

(7)

(8)

clock]

output /Beep output

/ SWIM input and

/ Infrared Timer output

1. At power-up, the PA1/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA1), it can be configured only as output open-drain or push-pull, not as a general purpose input. Refer to Section Configuring NRST/PA1 pin as general purpose output in the STM8L15x and STM8L16x reference manual (RM0031).

2. In the 3.6 V tolerant I/Os, protection diode to V

3. In the 5 V tolerant I/Os, protection diode to V

4. A pull-up is applied to PB0 and PB4 during the reset phase. These two pins are input floating after reset release.

5. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to V not implemented).

6. The PA0 pin is in input pull-up during the reset phase and after reset release.

7. High Sink LED driver capability available on PA0.

8. [ ] Alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not aduplication of the function).

is not implemented.

are

Note: The slope control of all GPIO pins, except true open drain pins, can be programmed. By

default, the slope control is limited to 2 MHz.

Doc ID 023331 Rev 1 27/102

Pin description STM8L052C6

4.1 System configuration options

As shown in Table 4: Medium density value line STM8L05xxx pin description, some alternate functions can be remapped on different I/O ports by programming one of the two remapping registers described in the “ Routing interface (RI) and system configuration controller” section in the STM8L15x and STM8L16x reference manual (RM0031).

28/102 Doc ID 023331 Rev 1

STM8L052C6 Memory and register map

GPIO and peripheral registers

0x00 0000

Reserved

Medium density

(32 Kbytes)

Reset and interrupt vectors

0x00 1000

0x00 10FF

RAM

0x00 07FF

(2 Kbytes)

(1)

(513 bytes)

(1)

0x00 1100

Data EEPROM

0x00 4800

0x00 48FF

0x00 4900

0x00 7FFF

0x00 8000

0x00 FFFF

0x00 0800

0x00 0FFF

0x00 47FF

0x00 7EFF

0x00 8080

0x00 807F

0x00 7F00

Reserved

including

Stack

(256 bytes)

Option bytes

0x00 4FFF 0x00 5000

0x00 57FF 0x00 5800

Reserved

0x00 5FFF

Boot ROM

0x00 6000

0x00 67FF

(2 Kbytes)

0x00 6800

Reserved

CPU/SWIM/Debug/ITC

Registers

0x00 5000

GPIO Ports

0x00 5050

Flash

0x00 50C0

ITC-EXTI

0x00 50D3

RST

0x00 50E0

CLK

0x00 50F3

WWDG

0x00 5210

IWDG

0x00 5230

BEEP

0x00 5250

RTC

0x00 5280

SPI1

0x00 52B0

I2C1

0x00 52E0

USART1

TIM2

TIM3

TIM1

TIM4

IRTIM

ADC1

0x00 5070

DMA1

SYSCFG

LCD

0x00 509E

0x00 50A0

0x00 50B0

0x00 5140

0x00 5200

0x00 52FF

0x00 5340

0x00 5380

0x00 5400

0x00 5430

0x00 5440

Flash program memory

WFE

0x00 50A6

0x00 50B2

PWR

Reserved

5 Memory and register map

5.1 Memory mapping

The memory map is shown in Figure 4.

Figure 4. Memory map

1. Table 5 lists the boundary addresses for each memory size. The top of the stack is at the RAM end address.

2. Refer to Table 7 for an overview of hardware register mapping, to Table 6 for details on I/O port hardware registers, and to Table 8 for information on CPU/SWIM/debug module controller registers.

Doc ID 023331 Rev 1 29/102

Memory and register map STM8L052C6

Table 5. Flash and RAM boundary addresses

Memory area Size Start address End address

RAM 2 Kbytes 0x00 0000 0x00 07FF

Flash program memory 32 Kbytes 0x00 8000 0x00 FFFF

5.2 Register map

Table 6. I/O port hardware register map

0x00 5000

0x00 5001 PA_IDR Port A input pin value register 0xXX

0x00 5002 PA_DDR Port A data direction register 0x00

0x00 5003 PA_CR1 Port A control register 1 0x01

0x00 5004 PA_CR2 Port A control register 2 0x00

0x00 5005

0x00 5006 PB_IDR Port B input pin value register 0xXX

0x00 5007 PB_DDR Port B data direction register 0x00

0x00 5008 PB_CR1 Port B control register 1 0x00

Address Block Register label Register name

PA_ODR Port A data output latch register 0x00

Por t A

PB_ODR Port B data output latch register 0x00

Por t B

Reset

status

0x00 5009 PB_CR2 Port B control register 2 0x00

0x00 500A

PC_ODR Port C data output latch register 0x00

0x00 500B PC_IDR Port C input pin value register 0xXX

0x00 500C PC_DDR Port C data direction register 0x00

Por t C

0x00 500D PC_CR1 Port C control register 1 0x00

0x00 500E PC_CR2 Port C control register 2 0x00

0x00 500F

PD_ODR Port D data output latch register 0x00

0x00 5010 PD_IDR Port D input pin value register 0xXX

0x00 5011 PD_DDR Port D data direction register 0x00

Por t D

0x00 5012 PD_CR1 Port D control register 1 0x00

0x00 5013 PD_CR2 Port D control register 2 0x00

0x00 5014

PE_ODR Port E data output latch register 0x00

0x00 5015 PE_IDR Port E input pin value register 0xXX

0x00 5016 PE_DDR Port E data direction register 0x00

Por t E

0x00 5017 PE_CR1 Port E control register 1 0x00

0x00 5018 PE_CR2 Port E control register 2 0x00

30/102 Doc ID 023331 Rev 1

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