ST STM8L052C6 User Manual

STM8L052C6

LQFP48

Value Line, 8-bit ultralow power MCU, 32-KB Flash,

256-byte data EEPROM, RTC, LCD, timers, USART, I2C, SPI, ADC

Datasheet − production data

Features

■ Operating conditions

– Operating power supply: 1.8 V to 3.6 V
– Temperature range: -40 °C to 85 °C

■ Low power features

– 5 low power modes: Wait, Low power run

(5.1 µA), Low power wait (3 µA), Active-halt

with full RTC (1.3 µA), Halt (350 nA)
– Consumption: 195 µA/MHz + 440 µA
– Ultra-low leakage per I/0: 50 nA
– Fast wakeup from Halt: 4.7 µs

■ Advanced STM8 core

– Harvard architecture and 3-stage pipeline
– Max freq. 16 MHz, 16 CISC MIPS peak
– Up to 40 external interrupt sources

■ Reset and supply management

– Low power, ultra-safe BOR reset with 5

selectable thresholds
– Ultra low power POR/PDR
– Programmable voltage detector (PVD)

■ Clock management

– 32 kHz and 1 to 16 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC
– Internal 38 kHz low consumption RC
– Clock security system

■ Low power RTC

– BCD calendar with alarm interrupt
– Auto-wakeup from Halt w/ periodic interrupt

■ LCD: up to 4x28 segments w/ step-up

converter

■ Memories

– 32 KB Flash program memory and

256 bytes data EEPROM with ECC, RWW
– Flexible write and read protection modes
– 2 Kbytes of RAM

■ DMA

– 4 channels supporting ADC, SPI, I2C,

USART, timers

– 1 channel for memory-to-memory

■ 12-bit ADC up to 1 Msps/25 channels

– Internal reference voltage

■ Timers

– Two 16-bit timers with 2 channels (used as

IC, OC, PWM), quadrature encoder

– One 16-bit advanced control timer with 3

channels, supporting motor control
– One 8-bit timer with 7-bit prescaler
– 2 watchdogs: 1 Window, 1 Independent
– Beeper timer with 1, 2 or 4 kHz frequencies

■ Communication interfaces

– Synchronous serial interface (SPI)

2

–Fast I

C 400 kHz SMBus and PMBus

– USART (ISO 7816 interface and IrDA)

■ Up to 41 I/Os, all mappable on interrupt vectors

■ Development support

– Fast on-chip programming and non-

intrusive debugging with SWIM
– Bootloader using USART

June 2012 Doc ID 023331 Rev 1 1/102

This is information on a product in full production.

www.st.com

1

Contents STM8L052C6

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2 Ultra low power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2.1 Advanced STM8 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2.2 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.5 Low power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.6 LCD (Liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.7 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.8 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.9 Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.10 System configuration controller and routing interface . . . . . . . . . . . . . . . 19

3.11 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.11.1 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.11.2 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.11.3 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.12 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.12.1 Window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.12.2 Independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.13 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.14 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.14.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.14.2 I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2/102 Doc ID 023331 Rev 1

STM8L052C6 Contents

3.14.3 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.15 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.16 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.1 System configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

8.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

8.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

8.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

8.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 56

8.3.3 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

8.3.4 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

8.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

8.3.6 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

8.3.7 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

8.3.8 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

8.3.9 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

8.3.10 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

8.3.11 12-bit ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

8.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

8.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

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Contents STM8L052C6

9 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

9.1 ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

9.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

9.2.1 48-pin low profile quad flat 7x7mm package (LQFP48) . . . . . . . . . . . . . 98

10 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

4/102 Doc ID 023331 Rev 1

STM8L052C6 List of tables

List of tables

Table 1. Medium density value line STM8L05xxx low power device features and

peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 2. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 3. Legend/abbreviation for Table 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 4. Medium density value line STM8L05xxx pin description . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 5. Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 6. I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 7. General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 8. CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 9. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 10. Option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 11. Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 12. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 13. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 14. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 15. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 16. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 17. Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 18. Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 19. Total current consumption and timing in Low power run mode at VDD = 1.8 V to

3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 20. Total current consumption in Low power wait mode at VDD = 1.8 V to 3.6 V . . . . . . . . . . 63

Table 21. Total current consumption and timing in Active-halt mode at VDD = 1.8 V to 3.6 V. . . . . . 64

Table 22. Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal. . 65

Table 23. Total current consumption and timing in Halt mode at VDD = 1.8 to 3.6 V . . . . . . . . . . . . 65

Table 24. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 25. Current consumption under external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 26. HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 27. LSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 28. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 29. LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 30. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 31. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 32. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 33. Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 34. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 35. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 36. Output driving current (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 37. Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 38. Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 77

Table 39. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 40. SPI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 41. I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 42. LCD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 43. Reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 44. ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 45. ADC1 accuracy with VDDA = 3.3 V to 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 46. ADC1 accuracy with VDDA = 2.4 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

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List of tables STM8L052C6

Table 47. ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 48. R

max for f

AIN

= 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

ADC

Table 49. EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 50. EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 51. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 52. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 53. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 54. LQFP48 48-pin low profile quad flat package, mechanical data. . . . . . . . . . . . . . . . . . . . . 98

Table 55. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

6/102 Doc ID 023331 Rev 1

STM8L052C6 List of figures

List of figures

Figure 1. Medium density value line STM8L05xxx device block diagram . . . . . . . . . . . . . . . . . . . . 12

Figure 2. Medium density value line STM8L05xxx clock tree diagram . . . . . . . . . . . . . . . . . . . . . . 17

Figure 3. STM8L052C6 48-pin LQFP48 package pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 4. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 5. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 6. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 7. POR/BOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 8. Typ. IDD(RUN) vs. VDD, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 9. Typ. IDD(Wait) vs. VDD, fCPU = 16 MHz 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 10. Typ. IDD(LPR) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 11. Typ. IDD(LPW) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 12. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 13. LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 14. Typical HSI frequency vs V

Figure 15. Typical LSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 16. Typical VIL and VIH vs VDD (high sink I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 17. Typical VIL and VIH vs VDD (true open drain I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 18. Typical pull-up resistance R
Figure 19. Typical pull-up current I

Figure 20. Typ. VOL @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 21. Typ. VOL @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 22. Typ. VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 23. Typ. VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 24. Typ. VDD - VOH @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 25. Typ. VDD - VOH @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 26. Typical NRST pull-up resistance R
Figure 27. Typical NRST pull-up current I

Figure 28. Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 29. SPI1 timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 30. SPI1 timing diagram - slave mode and CPHA=1
Figure 31. SPI1 timing diagram - master mode

Figure 32. Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 33. ADC1 accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 34. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 35. Maximum dynamic current consumption on V

conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 36. Power supply and reference decoupling (V

Figure 37. Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . . 93

Figure 38. LQFP48 48-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 39. LQFP48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 40. Medium density value line STM8L05xxx ordering information scheme . . . . . . . . . . . . . . 100

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

DD

vs VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

PU

vs VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

pu

vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

PU

vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

pu

(1)

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

REF+

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

supply pin during ADC

REF+

not connected to V

). . . . . . . . . . . . . . 93

DDA

Doc ID 023331 Rev 1 7/102

Introduction STM8L052C6

1 Introduction

This document describes the features, pinout, mechanical data and ordering information of

the medium density value line STM8L052C6 microcontroller with 32-Kbyte Flash memory

density. For further details on the whole STMicroelectronics medium density family please

refer to Section 2.2: Ultra low power continuum.

For detailed information on device operation and registers, refer to the reference manual

(RM0031).

For information on to the Flash program memory and data EEPROM, refer to the

programming manual (PM0054).

For information on the debug module and SWIM (single wire interface module), refer to the

STM8 SWIM communication protocol and debug module user manual (UM0470).

For information on the STM8 core, refer to the STM8 CPU programming manual (PM0044).

Medium density value line devices provide the following benefits:

● Integrated system

– 32 Kbytes of medium density embedded Flash program memory
– 256 bytes of data EEPROM
– 2 Kbytes of RAM
– Internal high speed and low-power low speed RC
– Embedded reset

● Ultra low power consumption

– 195 µA/MHZ + 440 µA (consumption)
– 0.9 µA with LSI in Active-halt mode
– Clock gated system and optimized power management
– Capability to execute from RAM for Low power wait mode and low power run mode

● Advanced features

– Up to 16 MIPS at 16 MHz CPU clock frequency
– Direct memory access (DMA) for memory-to-memory or peripheral-to-memory

access

● Short development cycles

– Application scalability across a common family product architecture with

compatible pinout, memory map and modular peripherals

– Wide choice of development tools

Refer to Table 1: Medium density value line STM8L05xxx low power device features and

peripheral counts and Section 3: Functional overview for an overview of the complete range

of peripherals proposed in this family.

Figure 1 shows the block diagram of the medium density value line STM8L05xxx family.

8/102 Doc ID 023331 Rev 1

STM8L052C6 Description

2 Description

The medium density value line STM8L05xxx devices are members of the STM8L ultra low

power 8-bit family.

The value line STM8L05xxx ultra low power family features the enhanced STM8 CPU core

providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the

advantages of a CISC architecture with improved code density, a 24-bit linear addressing

space and an optimized architecture for low power operations.

The family includes an integrated debug module with a hardware interface (SWIM) which

allows non-intrusive In-application debugging and ultra-fast Flash programming.

Medium density value line STM8L05xxx microcontrollers feature embedded data EEPROM

and low-power, low-voltage, single-supply program Flash memory.

All devices offer 12-bit ADC, real-time clock, 16-bit timers, one 8-bit timer as well as

standard communication interface such as SPI, I2C, USART and 4x28-segment LCD. The

4x 28-segment LCD is available on the medium density value line STM8L05xxx.

The STM8L05xxx family operates from 1.8 V to 3.6 V and is available in the

temperature range.

The modular design of the peripheral set allows the same peripherals to be found in different

ST microcontroller families including 32-bit families. This makes any transition to a different

family very easy, and simplified even more by the use of a common set of development

tools.

All value line STM8L ultra low power products are based on the same architecture with the

same memory mapping and a coherent pinout.

-40 to +85 °C

Doc ID 023331 Rev 1 9/102

Description STM8L052C6

2.1 Device overview

Table 1. Medium density value line STM8L05xxx low power device features and

peripheral counts

Features STM8L052C6

Flash (Kbytes) 32

Data EEPROM (bytes) 256

RAM (Kbytes) 2

LCD 4x28

Basic

1

(8-bit)

Timers

General purpose

Advanced control

2

(16-bit)

1

(16-bit)

SPI 1
Communication
interfaces

I2C 1

USART 1

GPIOs 41

12-bit synchronized ADC
(number of channels)

(1)

1

(25)

RTC, window watchdog, independent watchdog,

Others

16-MHz and 38-kHz internal RC,

1- to 16-MHz and 32-kHz external oscillator

CPU frequency 16 MHz

Operating voltage 1.8 V to 3.6 V

Operating temperature -40 to +85 °C

Package LQFP48

1. The number of GPIOs given in this table includes the NRST/PA1 pin but the application can use the
NRST/PA1 pin as general purpose output only (PA1).

10/102 Doc ID 023331 Rev 1

STM8L052C6 Description

2.2 Ultra low power continuum

The ultra low power value line STM8L05xxx and STM8L15xxx are fully pin-to-pin, software
and feature compatible. Besides the full compatibility within the STM8L family, the devices
are part of STMicroelectronics microcontrollers ultra low power strategy which also includes
STM8L101xx and STM32L15xxx. The STM8L and STM32L families allow a continuum of
performance, peripherals, system architecture, and features.

They are all based on STMicroelectronics 0.13 µm ultra-low leakage process.

Note: 1 The STM8L05xxx is pin-to-pin compatible with STM8L101xx devices.

2 The STM32L family is pin-to-pin compatible with the general purpose STM32F family.

Please refer to STM32L15x documentation for more information on these devices.

Performance

All families incorporate highly energy-efficient cores with both Harvard architecture and
pipelined execution: advanced STM8 core for STM8L families and ARM Cortex™-M3 core
for STM32L family. In addition specific care for the design architecture has been taken to
optimize the mA/DMIPS and mA/MHz ratios.

This allows the ultra low power performance to range from 5 up to 33.3 DMIPs.

Shared peripherals

STM8L05x, STM8L15x and STM32L15xx share identical peripherals which ensure a very
easy migration from one family to another:

● Analog peripheral: ADC1

● Digital peripherals: RTC and some communication interfaces

Common system strategy

To offer flexibility and optimize performance, the STM8L and STM32L devices use a
common architecture:

● Same power supply range from 1.8 to 3.6 V

● Architecture optimized to reach ultra-low consumption both in low power modes and

Run mode

● Fast startup strategy from low power modes

● Flexible system clock

● Ultra-safe reset: same reset strategy for both STM8L and STM32L including power-on

reset, power-down reset, brownout reset and programmable voltage detector

Features

ST ultra low power continuum also lies in feature compatibility:

● More than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm

● Memory density ranging from 4 to 128 Kbytes

Doc ID 023331 Rev 1 11/102

Functional overview STM8L052C6

16 MHz internal RC

Clock

Clocks

Address, control and data buses

Debug module

SPI1

32 Kbytes

Interrupt controller

2 Kbytes RAM

to core and
peripherals

IWDG

(38 kHz clock)

(SWIM)

Port A

Port B

Port C

I²C1

USART1

Power

VOLT. REG.

Port F

1-16 MHz oscillator

32 kHz oscillator

38 kHz internal RC

LCD driver

4x28

WWDG

STM8 Core

controller

and

CSS

256 bytes

Port D

Port E

Beeper

RTC

memoryprogram

data EEPROM

@V

DD

V

DD18

V

DD1

=1.8 V

V

SS1

SWIM

SCL, SDA,

MOSI, MISO,

SCK, NSS

RX, TX, CK

ADC1_INx

V

DDA

V

SSA

SMB

@V

DDA/VSSA

12-bit ADC1

V

REF+

V

REF-

3.6 V

NRST

PA[7:0]

PB[7:0]

PC[7:0]

PD[7:0]

PE[7:0]

PF0

BEEP

ALARM, CALIB

SEGx, COMx

POR/PDR

OSC_IN,

OSC_OUT

OSC32_IN,

OSC32_OUT

to

BOR

PVD

PVD_IN

RESET

DMA1

8-bit Timer 4

16-bit Timer 3

16-bit Timer 2

16-bit Timer 1

(4 channels)

2 channels

2 channels

3 channels

V

LCD

= 2.5 V

3.6 V

to

LCD booster

Internal reference

voltage

VREFINT out

Infrared interface

IR_TIM

3 Functional overview

Figure 1. Medium density value line STM8L05xxx device block diagram

1. Legend:

12/102 Doc ID 023331 Rev 1

ADC: Analog-to-digital converter
BOR: Brownout reset
DMA: Direct memory access
I²C: Inter-integrated circuit multimaster interface
LCD: Liquid crystal display
POR/PDR: Power on reset / power down reset
RTC: Real-time clock
SPI: Serial peripheral interface
SWIM: Single wire interface module
USART: Universal synchronous asynchronous receiver transmitter
WWDG: Window watchdog
IWDG: independent watchdog

STM8L052C6 Functional overview

3.1 Low power modes

The medium density value line STM8L05xxx devices support five low power modes to
achieve the best compromise between low power consumption, short startup time and
available wakeup sources:

● Wait mode: The CPU clock is stopped, but selected peripherals keep running. An

internal or external interrupt, event or a Reset can be used to exit the microcontroller
from Wait mode (WFE or WFI mode).

● Low power run mode: The CPU and the selected peripherals are running. Execution

is done from RAM with a low speed oscillator (LSI or LSE). Flash memory and data
EEPROM are stopped and the voltage regulator is configured in ultra low power mode.
The microcontroller enters Low power run mode by software and can exit from this
mode by software or by a reset.
All interrupts must be masked. They cannot be used to exit the microcontroller from this
mode.

● Low power wait mode: This mode is entered when executing a Wait for event in Low

power run mode. It is similar to Low power run mode except that the CPU clock is
stopped. The wakeup from this mode is triggered by a Reset or by an internal or
external event (peripheral event generated by the timers, serial interfaces, DMA
controller (DMA1) and I/O ports). When the wakeup is triggered by an event, the
system goes back to Low power run mode.
All interrupts must be masked. They cannot be used to exit the microcontroller from this
mode.

● Active-halt mode: CPU and peripheral clocks are stopped, except RTC. The wakeup

can be triggered by RTC interrupts, external interrupts or reset.

● Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.

The RAM content is preserved. The wakeup is triggered by an external interrupt or
reset. A few peripherals have also a wakeup from Halt capability. Switching off the
internal reference voltage reduces power consumption. Through software configuration
it is also possible to wake up the device without waiting for the internal reference
voltage wakeup time to have a fast wakeup time of 5 µs.

Doc ID 023331 Rev 1 13/102

Functional overview STM8L052C6

3.2 Central processing unit STM8

3.2.1 Advanced STM8 Core

The 8-bit STM8 core is designed for code efficiency and performance with an Harvard
architecture and a 3-stage pipeline.

It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing, and 80 instructions.

Architecture and registers

● Harvard architecture

● 3-stage pipeline

● 32-bit wide program memory bus - single cycle fetching most instructions

● X and Y 16-bit index registers - enabling indexed addressing modes with or without

offset and read-modify-write type data manipulations

● 8-bit accumulator

● 24-bit program counter - 16-Mbyte linear memory space

● 16-bit stack pointer - access to a 64-Kbyte level stack

● 8-bit condition code register - 7 condition flags for the result of the last instruction

Addressing

● 20 addressing modes

● Indexed indirect addressing mode for lookup tables located anywhere in the address

space

● Stack pointer relative addressing mode for local variables and parameter passing

Instruction set

● 80 instructions with 2-byte average instruction size

● Standard data movement and logic/arithmetic functions

● 8-bit by 8-bit multiplication

● 16-bit by 8-bit and 16-bit by 16-bit division

● Bit manipulation

● Data transfer between stack and accumulator (push/pop) with direct stack access

● Data transfer using the X and Y registers or direct memory-to-memory transfers

3.2.2 Interrupt controller

The medium density value line STM8L05xxx devices feature a nested vectored interrupt
controller:

● Nested interrupts with 3 software priority levels

● 32 interrupt vectors with hardware priority

● Up to 40 external interrupt sources on 11 vectors

● Trap and reset interrupts

14/102 Doc ID 023331 Rev 1

STM8L052C6 Functional overview

3.3 Reset and supply management

3.3.1 Power supply scheme

The device requires a 1.8 V to 3.6 V operating supply voltage (VDD). The external power
supply pins must be connected as follows:

● V

● V

● V

● V

3.3.2 Power supply supervisor

The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR), coupled with a brownout reset (BOR) circuitry . At power-on, BOR is always active,
and ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached,
the option byte loading process starts, either to confirm or modify default thresholds, or to
disable BOR permanently.

SS1

; V

= 1.8 to 3.6 V: external power supply for I/Os and for the internal regulator.

DD1

Provided externally through V

SSA ; VDDA

V

SSA

SS2

connected to V

REF+

externally through V

= 1.8 to 3.6 V: external power supplies for analog peripherals. V

must be connected to V

; V

= 1.8 to 3.6 V: external power supplies for I/Os. V

; V

DD2

REF-

and V

DD1

SS1

(for ADC1): external reference voltage for ADC1. Must be provided

and V

REF+

pins, the corresponding ground pin is V

DD1

DD1

and V

, respectively.

SS1

DD2

, respectively.

pin.

REF-

and V

SS1

must be

SS2

.

DDA

and

Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Halt mode, it is possible to automatically switch off the
internal reference voltage (and consequently the BOR) in Halt mode. The device remains
under reset when V

DD

for any external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the
V

DD/VDDA

power supply and compares it to the V
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when V
V

DD/VDDA

is higher than the V
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

3.3.3 Voltage regulator

The medium density value line STM8L05xxx embeds an internal voltage regulator for
generating the 1.8 V power supply for the core and peripherals.

This regulator has two different modes:

● Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event

(WFE) modes

● Low power voltage regulator mode (LPVR) for Halt, Active-halt, Low power run and Low

power wait modes

When entering Halt or Active-halt modes, the system automatically switches from the MVR
to the LPVR in order to reduce current consumption.

is below a specified threshold, V

threshold. This PVD offers 7 different

PVD

DD/VDDA

threshold. The interrupt service routine can then generate

PVD

drops below the V

POR/PDR

PVD

or V

, without the need

BOR

threshold and/or when

Doc ID 023331 Rev 1 15/102

Functional overview STM8L052C6

3.4 Clock management

The clock controller distributes the system clock (SYSCLK) coming from different oscillators
to the core and the peripherals. It also manages clock gating for low power modes and
ensures clock robustness.

Features

● Clock prescaler: To get the best compromise between speed and current

consumption the clock frequency to the CPU and peripherals can be adjusted by a
programmable prescaler.

● Safe clock switching: Clock sources can be changed safely on the fly in run mode

through a configuration register.

● Clock management: To reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

● System clock sources: 4 different clock sources can be used to drive the system

clock:

– 1-16 MHz High speed external crystal (HSE)

– 16 MHz High speed internal RC oscillator (HSI)

– 32.768 kHz Low speed external crystal (LSE)

– 38 kHz Low speed internal RC (LSI)

● RTC and LCD clock sources: The above four sources can be chosen to clock the

RTC and the LCD, whatever the system clock.

● Startup clock: After reset, the microcontroller restarts by default with an internal

2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the
application program as soon as the code execution starts.

● Clock security system (CSS): This feature can be enabled by software. If a HSE clock

failure occurs, the system clock is automatically switched to HSI.

● Configurable main clock output (CCO): This outputs an external clock for use by the

application.

16/102 Doc ID 023331 Rev 1

STM8L052C6 Functional overview

HSE OSC

1-16 MHz

HSI RC

16 MHz

LSI RC
38 kH z

LSE OSC

32 768 k

H

z

HSI

LSI

RTC

prescaler

/1;2;4;8;16;32;64

PCLK

to peripherals

RTCCLK/2

to LCD

to IWDG

SYSCLK

HSE

(1)

(2)

LSI
LSE

OSC_OUT

OSC32_OUT

OSC_IN

OSC32_IN

clock output

CCO

prescaler

/1;2;4;8;16;32;64

HSI
LSI
HSE
LSE

CCO

to core and

memory

SYSCLK
Presc aler

/1;2;4;8;16;32;64;128

IWDGCLK

RTCSEL[3:0]

LSE

(2)

CLKBEEPSEL[1:0]

to BEEP

BEEPCLK

CSS

configurable

.

/ 2

Peripheral
Clock enable (15 bits)

to RTC

RTCCLK

clock enable (1 bit)

LCDCLK

to LCD

SYSCLK

Halt

clock enable (1 bit)

LCD peripheral

RTCCLK

LCD peripheral

(1)

(2)

Figure 2. Medium density value line STM8L05xxx clock tree diagram

1. The HSE clock source can be either an external crystal/ceramic resonator or an external source (HSE

bypass). Refer to Section HSE clock in the STM8L15x and STM8L16x reference manual (RM0031).

2. The LSE clock source can be either an external crystal/ceramic resonator or a external source (LSE

bypass). Refer to Section LSE clock in the STM8L15x and STM8L16x reference manual (RM0031).

3.5 Low power real-time clock

The real-time clock (RTC) is an independent binary coded decimal (BCD) timer/counter.

Six byte locations contain the second, minute, hour (12/24 hour), week day, date, month,
year, in BCD (binary coded decimal) format. Correction for 28, 29 (leap year), 30, and 31
day months are made automatically.

It provides a programmable alarm and programmable periodic interrupts with wakeup from
Halt capability.

● Periodic wakeup time using the 32.768 kHz LSE with the lowest resolution (of 61 µs) is

from min. 122 µs to max. 3.9 s. With a different resolution, the wakeup time can reach
36 hours.

● Periodic alarms based on the calendar can also be generated from every second to

every year.

Doc ID 023331 Rev 1 17/102

Functional overview STM8L052C6

3.6 LCD (Liquid crystal display)

The LCD is only available on STM8L052xx devices.

● The liquid crystal display drives up to 4 common terminals and up to 28 segment

terminals to drive up to 112 pixels. Internal step-up converter to guarantee contrast
control whatever V

● Static 1/2, 1/3, 1/4 duty supported.

● Static 1/2, 1/3, bias supported.

● Phase inversion to reduce power consumption and EMI.

● Up to 4 pixels which can be programmed to blink.

● The LCD controller can operate in Halt mode.

DD

.

Note: Unnecessary segments and common pins can be used as general I/O pins.

3.7 Memories

The medium density value line STM8L05xxx devices have the following main features:

● 2 Kbytes of RAM

● The non-volatile memory is divided into three arrays:

– 32 Kbytes of medium density embedded Flash program memory

– 256 bytes of data EEPROM

–Option bytes

The EEPROM embeds the error correction code (ECC) feature. It supports the read-while­write (RWW): it is possible to execute the code from the program matrix while
programming/erasing the data matrix.

The option byte protects part of the Flash program memory from write and readout piracy.

3.8 DMA

A 4-channel direct memory access controller (DMA1) offers a memory-to-memory and
peripherals-from/to-memory transfer capability. The 4 channels are shared between the
following IPs with DMA capability: ADC1, I2C1, SPI1, USART1and the four timers.

18/102 Doc ID 023331 Rev 1

STM8L052C6 Functional overview

3.9 Analog-to-digital converter

● 12-bit analog-to-digital converter (ADC1) with 25 channels (including 1 fast channel)

and internal reference voltage

● Conversion time down to 1 µs with f

● Programmable resolution

● Programmable sampling time

● Single and continuous mode of conversion

● Scan capability: automatic conversion performed on a selected group of analog inputs

● Analog watchdog

● Triggered by timer

SYSCLK

= 16 MHz

Note: ADC1 can be served by DMA1.

3.10 System configuration controller and routing interface

The system configuration controller provides the capability to remap some alternate
functions on different I/O ports. TIM4 and ADC1 DMA channels can also be remapped.

The highly flexible routing interface allows application software to control the routing of
different I/Os to the TIM1 timer input captures. It also controls the routing of internal analog
signals to ADC1 and the internal reference voltage V

REFINT

.

3.11 Timers

The medium density value line STM8L05xxx devices contain one advanced control timer
(TIM1), two 16-bit general purpose timers (TIM2 and TIM3) and one 8-bit basic timer
(TIM4).

All the timers can be served by DMA1.

Ta bl e 2 compares the features of the advanced control, general-purpose and basic timers.

Table 2. Timer feature comparison

Timer

TIM1

TIM2

TIM3

TIM4 8-bit up

Counter

resolution

16-bit up/down

Counter

type

Prescaler factor

Any integer

from 1 to 65536

Any power of 2

from 1 to 128

Any power of 2

from 1 to 32768

DMA1

request

generation

Ye s

Capture/compare

channels

3 + 1 3

2

0

Complementary

outputs

None

Doc ID 023331 Rev 1 19/102

Functional overview STM8L052C6

3.11.1 TIM1 - 16-bit advanced control timer

This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver.

● 16-bit up, down and up/down autoreload counter with 16-bit prescaler

● 3 independent capture/compare channels (CAPCOM) configurable as input capture,

output compare, PWM generation (edge and center aligned mode) and single pulse
mode output

● 1 additional capture/compare channel which is not connected to an external I/O

● Synchronization module to control the timer with external signals

● Break input to force timer outputs into a defined state

● 3 complementary outputs with adjustable dead time

● Encoder mode

● Interrupt capability on various events (capture, compare, overflow, break, trigger)

3.11.2 16-bit general purpose timers

● 16-bit autoreload (AR) up/down-counter

● 7-bit prescaler adjustable to fixed power of 2 ratios (1…128)

● 2 individually configurable capture/compare channels

● PWM mode

● Interrupt capability on various events (capture, compare, overflow, break, trigger)

● Synchronization with other timers or external signals (external clock, reset, trigger and

enable)

3.11.3 8-bit basic timer

The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable
prescaler. It can be used for timebase generation with interrupt generation on timer overflow.

3.12 Watchdog timers

The watchdog system is based on two independent timers providing maximum security to
the applications.

3.12.1 Window watchdog timer

The window watchdog (WWDG) is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.

3.12.2 Independent watchdog timer

The independent watchdog peripheral (IWDG) can be used to resolve processor
malfunctions due to hardware or software failures.

It is clocked by the internal LSI RC clock source, and thus stays active even in case of a
CPU clock failure.

20/102 Doc ID 023331 Rev 1

STM8L052C6 Functional overview

3.13 Beeper

The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.

3.14 Communication interfaces

3.14.1 SPI

The serial peripheral interface (SPI1) provides half/ full duplex synchronous serial
communication with external devices.

● Maximum speed: 8 Mbit/s (f

● Full duplex synchronous transfers

● Simplex synchronous transfers on 2 lines with a possible bidirectional data line

● Master or slave operation - selectable by hardware or software

● Hardware CRC calculation

● Slave/master selection input pin

SYSCLK

Note: SPI1 can be served by the DMA1 Controller.

/2) both for master and slave

3.14.2 I²C

The I2C bus interface (I2C1) provides multi-master capability, and controls all I²C bus­specific sequencing, protocol, arbitration and timing.

● Master, slave and multi-master capability

● Standard mode up to 100 kHz and fast speed modes up to 400 kHz

● 7-bit and 10-bit addressing modes

● SMBus 2.0 and PMBus support

● Hardware CRC calculation

Note: I

2

C1 can be served by the DMA1 Controller.

3.14.3 USART

The USART interface (USART1) allows full duplex, asynchronous communications with
external devices requiring an industry standard NRZ asynchronous serial data format. It
offers a very wide range of baud rates.

● 1 Mbit/s full duplex SCI

● SPI1 emulation

● High precision baud rate generator

● Smartcard emulation

● IrDA SIR encoder decoder

● Single wire half duplex mode

Note: USART1 can be served by the DMA1 Controller.

Doc ID 023331 Rev 1 21/102

Functional overview STM8L052C6

3.15 Infrared (IR) interface

The medium density value line STM8L05xxx devices contain an infrared interface which can
be used with an IR LED for remote control functions. Two timer output compare channels
are used to generate the infrared remote control signals.

3.16 Development support

Development tools

Development tools for the STM8 microcontrollers include:

● The STice emulation system offering tracing and code profiling

● The STVD high-level language debugger including C compiler, assembler and

integrated development environment

● The STVP Flash programming software

The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit
debugging/programming tools.

Single wire data interface (SWIM) and debug module

The debug module with its single wire data interface (SWIM) permits non-intrusive real-time
in-circuit debugging and fast memory programming.

The Single wire interface is used for direct access to the debugging module and memory
programming. The interface can be activated in all device operation modes.

The non-intrusive debugging module features a performance close to a full-featured
emulator. Beside memory and peripherals, CPU operation can also be monitored in real­time by means of shadow registers.

Bootloader

A bootloader is available to reprogram the Flash memory using the USART1 interface. The
reference document for the bootloader is UM0560: STM8 bootloader user manual.

The bootloader is used to download application software into the device memories,
including RAM, program and data memory, using standard serial interfaces. It is a
complementary solution to programming via the SWIM debugging interface.

22/102 Doc ID 023331 Rev 1

STM8L052C6 Pin description

44 43 42 41 4 0 39 38 3 7

36

35
34
33
32
31
30
29
28
27
26
25

24

23

12

13 1 4 15 16 17 18 19 20 21 22

1
2
3
4
5
6
7
8
9
10
11

48 47 46 45

PA5

V

SS1/VSSA/VREF-

NRST/PA1

PA2
PA3
PA4

PA6

VLCD

PE0

PE1

PD1

PD2

PD3

PB0

PE3

PD0

PE5

PE4

PA7

V

DD1

V

DDA

V

REF+

PE2

PB1

PB2

PC0

PC1

V

DD2VSS2

PC2

PC3

PC4

PC5

PC6

PC7

PE6

PE7

PB3

PB4

PB5

PB6

PB7

PF0

PD4

PD5

PD6

PD7

PA 0

4 Pin description

Figure 3. STM8L052C6 48-pin LQFP48 package pinout (with LCD)

Doc ID 023331 Rev 1 23/102

Pin description STM8L052C6

Table 3. Legend/abbreviation for Table 4

Typ e I= input, O = output, S = power supply

FT Five-volt tolerant

Level

Port and control
configuration

Reset state

Table 4. Medium density value line STM8L05xxx pin description

TT 3.6 V tolerant

Output HS = high sink/source (20 mA)

Input float = floating, wpu = weak pull-up

Output T = true open drain, OD = open drain, PP = push pull

Bold X (pin state after reset release).
Unless otherwise specified, the pin state is the same during the reset phase (i.e.
“under reset”) and after internal reset release (i.e. at reset state).

Pin

number

LQFP48

2 NRST/PA1

PA2/OSC_IN/

3

[USART1_TX]
[SPI1_MISO]

PA3/OSC_OUT/[USART1_

4

RX]

(8)

/[SPI1_MOSI]

PA4/TIM2_BKIN/

5

LCD_COM0/ADC1_IN2

PA5/TIM3_BKIN/

6

LCD_COM1/ADC1_IN1

PA 6/ [ADC1_TRIG]/

7

LCD_COM2/ADC1_IN0

8 PA7/LCD_SEG0

(4)

PB0

24

/TIM2_CH1/

LCD_SEG10/ADC1_IN18

PB1/TIM3_CH1/

25

LCD_SEG11/
ADC1_IN17

PB2/ TIM2_CH2/

26

LCD_SEG12/
ADC1_IN16

Pin name

(1)

(8)

/

(8)

(3)

(8)

Input Output

Type

I/O level

wpu

floating

OD

PP

Default alternate function

(after reset)

Main function

Ext. interrupt

High sink/source

I/O X HS X Reset PA 1

HSE oscillator input /

I/O X X X HS X X Port A2

[USART1 transmit] / [SPI1
master in- slave out]

HSE oscillator output /

I/O X X X HS X X Port A3

[USART1 receive]/ [SPI1
master out/slave in]/

I/O TT

I/O TT

(2)

XXXHSXXPort A4

(2)

XXXHSXXPort A5

Timer 2 - break input /
LCD COM 0 / ADC1 input 2

Timer 3 - break input /
LCD_COM 1 / ADC1 input
1

[ADC1 - trigger] /
LCD_COM2 /

I/O TT

(2)

XXXHSXXPort A6

ADC1 input 0

I/O FT X X X HS X X Port A7 LCD segment 0

I/O TT

I/O TT

I/O TT

(2)X(4)X(4)

(2)

XXXHSXXPort B1

(2)

XXXHSXXPort B2

XHSX XPort B0

Timer 2 - channel 1 / LCD
segment 10 / ADC1_IN18

Timer 3 - channel 1 / LCD
segment 11 / ADC1_IN17

Timer 2 - channel 2 / LCD
segment 12 / ADC1_IN16

24/102 Doc ID 023331 Rev 1

STM8L052C6 Pin description

Table 4. Medium density value line STM8L05xxx pin description (continued)

Pin

number

LQFP48

27

28

29

30

31

37 PC0

38 PC1

41

Input Output

Pin name

Typ e

I/O level

floating

PB3/TIM2_ETR/
LCD_SEG13/

I/O TT

(2)

XXXHSXXPort B3

ADC1_IN15

(4)

PB4

/[SPI1_NSS]

LCD_SEG14/

(8)

/

I/O TT

(2)X(4)X(4)

ADC1_IN14

PB5/[SPI1_SCK]
LCD_SEG15/

(8)

/

I/O TT

(2)

XXXHSXXPort B5

ADC1_IN13

(8)

PB6/[SPI1_MOSI]
LCD_SEG16/

/

I/O TT

(2)

XXXHSXXPort B6

ADC1_IN12

PB7/[SPI1_MISO]
LCD_SEG17/

(8)

/

I/O TT

(2)

XXXHSXXPort B7

ADC1_IN11

(3)

/I2C1_SDA I/O FT X X T

(3)

/I2C1_SCL I/O FT X X T

PC2/USART1_RX/
LCD_SEG22/ADC1_IN6/

I/O TT

(2)

XXXHSXXPort C2

VREFINT

PP

wpu

OD

Ext. interrupt

High sink/source

XHSX XPort B4

(5)

(5)

Default alternate function

(after reset)

Main function

Timer 2 - external trigger /
LCD segment 13
/ADC1_IN15

[SPI1 master/slave select] /
LCD segment 14 /
ADC1_IN14

[SPI1 clock] / LCD segment
15 / ADC1_IN13

[SPI1 master out/slave in]/
LCD segment 16 /
ADC1_IN12

[SPI1 master in- slave out]

/LCD segment 17 /
ADC1_IN11

Port C0 I2C1 data

Port C1 I2C1 clock

USART1 receive /
LCD segment 22 /
ADC1_IN6 /Internal voltage
reference output

PC3/USART1_TX/

42

LCD_SEG23/
ADC1_IN5

PC4/USART1_CK/
I2C1_SMB/CCO/

43

LCD_SEG24/
ADC1_IN4

PC5/OSC32_IN

44

/[SPI1_NSS]

[USART1_TX]

PC6/OSC32_OUT/

45

[SPI1_SCK]
[USART1_RX]

PC7/LCD_SEG25/

46

ADC1_IN3

(8)

(8)

(8)

/

(8)

USART1 transmit /
LCD segment 23 /

I/O TT

(2)

XXXHSXXPort C3

ADC1_IN5

USART1 synchronous
clock / I2C1_SMB /
Configurable clock output /

I/O TT

(2)

XXXHSXXPort C4

LCD segment 24/
ADC1_IN4

LSE oscillator input / [SPI1

/

I/O X X X HS X X Port C5

master/slave select] /
[USART1 transmit]

LSE oscillator output /

I/O X X X HS X X Port C6

[SPI1 clock] / [USART1
receive]

I/O TT

(2)

XXXHSXXPort C7

LCD segment 25
/ADC1_IN3

Doc ID 023331 Rev 1 25/102

Pin description STM8L052C6

Table 4. Medium density value line STM8L05xxx pin description (continued)

Pin

number

LQFP48

20

21

22

23

33

Pin name

PD0/TIM3_CH2/

[ADC1_TRIG]

(8)

/

LCD_SEG7/ADC1_IN22/

PD1/TIM3_ETR/
LCD_COM3/
ADC1_IN21

PD2/TIM1_CH1
/LCD_SEG8/
ADC1_IN20

PD3/ TIM1_ETR/
LCD_SEG9/ADC1_IN19

PD4/TIM1_CH2
/LCD_SEG18/
ADC1_IN10

Typ e

I/O TT

I/O TT

I/O TT

I/O TT

I/O TT

Input Output

I/O level

wpu

floating

OD

Ext. interrupt

High sink/source

(2)

XXXHSXXPort D0

(2)

XXXHSXXPort D1

(2)

XXXHSXXPort D2

(2)

XXXHSXXPort D3

(2)

XXXHSXXPort D4

PP

Main function

Default alternate function

(after reset)

Timer 3 - channel 2 /
[ADC1_Trigger] / LCD
segment 7 / ADC1_IN22

Timer 3 - external trigger /
LCD_COM3 / ADC1_IN21

Timer 1 - channel 1 / LCD
segment 8 / ADC1_IN20

Timer 1 - externaltrigger /
LCD segment 9 /
ADC1_IN19

Timer 1 - channel 2 / LCD
segment 18 / ADC1_IN10

PD5/TIM1_CH3

34

/LCD_SEG19/

I/O TT

ADC1_IN9

PD6/TIM1_BKIN
/LCD_SEG20/

35

ADC1_IN8/RTC_CALIB/

I/O TT

/VREFINT

PD7/TIM1_CH1N
/LCD_SEG21/

36

ADC1_IN7/RTC_ALARM/V

I/O TT

REFINT

14 PE0

15

16

(3)

/LCD_SEG1 I/O FT X X X HS X X Port E0 LCD segment 1

PE1/TIM1_CH2N/
LCD_SEG2

PE2/TIM1_CH3N/
LCD_SEG3

I/O TT

I/O TT

17 PE3/LCD_SEG4 I/O TT

18 PE4/LCD_SEG5 I/O TT

PE5/LCD_SEG6/

19

ADC1_IN23

PE6/LCD_SEG26/

47

PVD_IN

I/O TT

I/O TT

(2)

XXXHSXXPort D5

Timer 1 - channel 3 / LCD
segment 19 / ADC1_IN9

Timer 1 - break input / LCD

(2)

XXXHSXXPort D6

segment 20 / ADC1_IN8 /
RTC calibration / Internal
voltage reference output

Timer 1 - inverted channel

(2)

XXXHSXXPort D7

1/ LCD segment 21 /
ADC1_IN7 / RTC alarm /
Internal voltage reference
output

(2)

XXXHSXXPort E1

(2)

XXXHSXXPort E2

(2)

XXXHSXXPort E3 LCD segment 4

(2)

XXXHSXXPort E4 LCD segment 5

(2)

XXXHSXXPort E5

(2)

XXXHSXXPort E6 LCD segment 26/PVD_IN

Timer 1 - inverted channel
2 / LCD segment 2

Timer 1 - inverted channel
3 / LCD segment 3

LCD segment 6 /
ADC1_IN23

26/102 Doc ID 023331 Rev 1

STM8L052C6 Pin description

Table 4. Medium density value line STM8L05xxx pin description (continued)

Pin

number

LQFP48

Pin name

Typ e

Input Output

I/O level

wpu

floating

OD

PP

Main function

Default alternate function

(after reset)

Ext. interrupt

High sink/source

PE7/LCD_SEG27

48

32 PF0/ADC1_IN24 I/O X X X HS X X Por t F0

I/O TT

(2)

XXXHSXXPort E7 LCD segment 27

ADC1_IN24

13 VLCD S LCD booster external capacitor

13 Reserved Reserved. Must be tied to V

10 V

11 V

12 V

39 V

40 V

DD

DDA

REF+

9V

SS1/VSSA/VREF-

DD2

SS2

(6)

PA 0

1

/[USART1_CK]

SWIM/BEEP/IR_TIM

(8)

(7)

S Digital power supply

S Analog supply voltage

S ADC1 positive voltage reference

S

I/O ground / Analog ground voltage /
ADC1 negative voltage reference

S IOs supply voltage

S IOs ground voltage

[USART1 synchronous

/

I/O X X

(6)

HS

X

XXPort A0

(7)

(8)

clock]

output /Beep output

/ SWIM input and

/ Infrared Timer output

DD

1. At power-up, the PA1/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA1), it can be
configured only as output open-drain or push-pull, not as a general purpose input. Refer to Section Configuring NRST/PA1
pin as general purpose output in the STM8L15x and STM8L16x reference manual (RM0031).

2. In the 3.6 V tolerant I/Os, protection diode to V

3. In the 5 V tolerant I/Os, protection diode to V

4. A pull-up is applied to PB0 and PB4 during the reset phase. These two pins are input floating after reset release.

5. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to V
not implemented).

6. The PA0 pin is in input pull-up during the reset phase and after reset release.

7. High Sink LED driver capability available on PA0.

8. [ ] Alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not
aduplication of the function).

is not implemented.

DD

is not implemented.

DD

DD

are

Note: The slope control of all GPIO pins, except true open drain pins, can be programmed. By

default, the slope control is limited to 2 MHz.

Doc ID 023331 Rev 1 27/102

Pin description STM8L052C6

4.1 System configuration options

As shown in Table 4: Medium density value line STM8L05xxx pin description, some
alternate functions can be remapped on different I/O ports by programming one of the two
remapping registers described in the “ Routing interface (RI) and system configuration
controller” section in the STM8L15x and STM8L16x reference manual (RM0031).

28/102 Doc ID 023331 Rev 1

STM8L052C6 Memory and register map

GPIO and peripheral registers

0x00 0000

Reserved

Medium density

(32 Kbytes)

Reset and interrupt vectors

0x00 1000

0x00 10FF

RAM

0x00 07FF

(2 Kbytes)

(1)

(513 bytes)

(1)

0x00 1100

Data EEPROM

0x00 4800

0x00 48FF

0x00 4900

0x00 7FFF

0x00 8000

0x00 FFFF

0x00 0800

0x00 0FFF

0x00 47FF

0x00 7EFF

0x00 8080

0x00 807F

0x00 7F00

Reserved

including

Stack

(256 bytes)

Option bytes

0x00 4FFF
0x00 5000

0x00 57FF
0x00 5800

Reserved

0x00 5FFF

Boot ROM

0x00 6000

0x00 67FF

(2 Kbytes)

0x00 6800

Reserved

CPU/SWIM/Debug/ITC

Registers

0x00 5000

GPIO Ports

0x00 5050

Flash

0x00 50C0

ITC-EXTI

0x00 50D3

RST

0x00 50E0

CLK

0x00 50F3

WWDG

0x00 5210

IWDG

0x00 5230

BEEP

0x00 5250

RTC

0x00 5280

SPI1

0x00 52B0

I2C1

0x00 52E0

USART1

TIM2

TIM3

TIM1

TIM4

IRTIM

ADC1

0x00 5070

DMA1

SYSCFG

LCD

RI

0x00 509E

0x00 50A0

0x00 50B0

0x00 5140

0x00 5200

0x00 52FF

0x00 5340

0x00 5380

0x00 5400

0x00 5430

0x00 5440

Flash program memory

WFE

0x00 50A6

0x00 50B2

PWR

Reserved

Reserved

Reserved

5 Memory and register map

5.1 Memory mapping

The memory map is shown in Figure 4.

Figure 4. Memory map

1. Table 5 lists the boundary addresses for each memory size. The top of the stack is at the RAM end
address.

2. Refer to Table 7 for an overview of hardware register mapping, to Table 6 for details on I/O port hardware
registers, and to Table 8 for information on CPU/SWIM/debug module controller registers.

Doc ID 023331 Rev 1 29/102

Memory and register map STM8L052C6

Table 5. Flash and RAM boundary addresses

Memory area Size Start address End address

RAM 2 Kbytes 0x00 0000 0x00 07FF

Flash program memory 32 Kbytes 0x00 8000 0x00 FFFF

5.2 Register map

Table 6. I/O port hardware register map

0x00 5000

0x00 5001 PA_IDR Port A input pin value register 0xXX

0x00 5002 PA_DDR Port A data direction register 0x00

0x00 5003 PA_CR1 Port A control register 1 0x01

0x00 5004 PA_CR2 Port A control register 2 0x00

0x00 5005

0x00 5006 PB_IDR Port B input pin value register 0xXX

0x00 5007 PB_DDR Port B data direction register 0x00

0x00 5008 PB_CR1 Port B control register 1 0x00

Address Block Register label Register name

PA_ODR Port A data output latch register 0x00

Por t A

PB_ODR Port B data output latch register 0x00

Por t B

Reset

status

0x00 5009 PB_CR2 Port B control register 2 0x00

0x00 500A

PC_ODR Port C data output latch register 0x00

0x00 500B PC_IDR Port C input pin value register 0xXX

0x00 500C PC_DDR Port C data direction register 0x00

Por t C

0x00 500D PC_CR1 Port C control register 1 0x00

0x00 500E PC_CR2 Port C control register 2 0x00

0x00 500F

PD_ODR Port D data output latch register 0x00

0x00 5010 PD_IDR Port D input pin value register 0xXX

0x00 5011 PD_DDR Port D data direction register 0x00

Por t D

0x00 5012 PD_CR1 Port D control register 1 0x00

0x00 5013 PD_CR2 Port D control register 2 0x00

0x00 5014

PE_ODR Port E data output latch register 0x00

0x00 5015 PE_IDR Port E input pin value register 0xXX

0x00 5016 PE_DDR Port E data direction register 0x00

Por t E

0x00 5017 PE_CR1 Port E control register 1 0x00

0x00 5018 PE_CR2 Port E control register 2 0x00

30/102 Doc ID 023331 Rev 1

STM8L052C6 Memory and register map

Table 6. I/O port hardware register map (continued)

Address Block Register label Register name

0x00 5019

PF_ODR Port F data output latch register 0x00

0x00 501A PF_IDR Port F input pin value register 0xXX

0x00 501B PF_DDR Port F data direction register 0x00

Por t F

0x00 501C PF_CR1 Port F control register 1 0x00

0x00 501D PF_CR2 Port F control register 2 0x00

Table 7. General hardware register map

Address Block Register label Register name

0x00 501E to

0x00 5049

0x00 5050

FLASH_CR1 Flash control register 1 0x00

Reserved area (44 bytes)

0x00 5051 FLASH_CR2 Flash control register 2 0x00

0x00 5052 FLASH _PUKR

Flash

Flash program memory unprotection key

register

0x00 5053 FLASH _DUKR Data EEPROM unprotection key register 0x00

0x00 5054 FLASH _IAPSR

0x00 5055 to

0x00 506F

Flash in-application programming status

register

Reserved area (27 bytes)

Reset

status

Reset

status

0x00

0x00

Doc ID 023331 Rev 1 31/102

Memory and register map STM8L052C6

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 5070

0x00 5071 DMA1_GIR1 DMA1 global interrupt register 1 0x00

0x00 5072 to

0x00 5074

0x00 5075 DMA1_C0CR DMA1 channel 0 configuration register 0x00

0x00 5076 DMA1_C0SPR DMA1 channel 0 status & priority register 0x00

0x00 5077 DMA1_C0NDTR

0x00 5078 DMA1_C0PARH

0x00 5079 DMA1_C0PARL

0x00 507A Reserved area (1 byte)

0x00 507B DMA1_C0M0ARH

0x00 507C DMA1_C0M0ARL

0x00 507D
0x00 507E

DMA1

DMA1_GCSR

DMA1 global configuration & status

register

Reserved area (3 bytes)

DMA1 number of data to transfer register

(channel 0)

DMA1 peripheral address high register

(channel 0)

DMA1 peripheral address low register

(channel 0)

DMA1 memory 0 address high register

(channel 0)

DMA1 memory 0 address low register

(channel 0)

Reserved area (2 bytes)

Reset

status

0xFC

0x00

0x52

0x00

0x00

0x00

0x00 507F DMA1_C1CR DMA1 channel 1 configuration register 0x00

0x00 5080 DMA1_C1SPR DMA1 channel 1 status & priority register 0x00

0x00 5081 DMA1_C1NDTR

0x00 5082 DMA1_C1PARH

0x00 5083 DMA1_C1PARL

DMA1 number of data to transfer register

(channel 1)

DMA1 peripheral address high register

(channel 1)

DMA1 peripheral address low register

(channel 1)

0x00

0x52

0x00

32/102 Doc ID 023331 Rev 1

STM8L052C6 Memory and register map

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 5084

0x00 5085 DMA1_C1M0ARH

0x00 5086 DMA1_C1M0ARL

0x00 5087
0x00 5088

0x00 5089 DMA1_C2CR DMA1 channel 2 configuration register 0x00

0x00 508A DMA1_C2SPR DMA1 channel 2 status & priority register 0x00

0x00 508B DMA1_C2NDTR

0x00 508C DMA1_C2PARH

0x00 508D DMA1_C2PARL

0x00 508E Reserved area (1 byte)

0x00 508F DMA1_C2M0ARH

DMA1

0x00 5090 DMA1_C2M0ARL

Reserved area (1 byte)

DMA1 memory 0 address high register

(channel 1)

DMA1 memory 0 address low register

(channel 1)

Reserved area (2 bytes)

DMA1 number of data to transfer register

(channel 2)

DMA1 peripheral address high register

(channel 2)

DMA1 peripheral address low register

(channel 2)

DMA1 memory 0 address high register

(channel 2)

DMA1 memory 0 address low register

(channel 2)

Reset

status

0x00

0x00

0x00

0x52

0x00

0x00

0x00

0x00 5091
0x00 5092

0x00 5093 DMA1_C3CR DMA1 channel 3 configuration register 0x00

0x00 5094 DMA1_C3SPR DMA1 channel 3 status & priority register 0x00

0x00 5095 DMA1_C3NDTR

0x00 5096

0x00 5097

0x00 5098 Reserved area (1 byte)

0x00 5099 DMA1_C3M0ARH

0x00 509A DMA1_C3M0ARL

0x00 509B to

0x00 509D

0x00 509E SYSCFG_RMPCR1 Remapping register 1 0x00

0x00 509F SYSCFG_RMPCR2 Remapping register 2 0x00

DMA1_C3PARH_

C3M1ARH

DMA1_C3PARL_

C3M1ARL

Reserved area (2 bytes)

DMA1 number of data to transfer register

(channel 3)

DMA1 peripheral address high register

(channel 3)

DMA1 peripheral address low register

(channel 3)

DMA1 memory 0 address high register

(channel 3)

DMA1 memory 0 address low register

(channel 3)

Reserved area (3 bytes)

0x00

0x40

0x00

0x00

0x00

Doc ID 023331 Rev 1 33/102

Memory and register map STM8L052C6

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 50A0

0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00

0x00 50A2 EXTI_CR3 External interrupt control register 3 0x00

ITC - EXTI

0x00 50A3 EXTI_SR1 External interrupt status register 1 0x00

0x00 50A4 EXTI_SR2 External interrupt status register 2 0x00

0x00 50A5 EXTI_CONF1 External interrupt port select register 1 0x00

0x00 50A6

0x00 50A7 WFE_CR2 WFE control register 2 0x00

WFE

0x00 50A8 WFE_CR3 WFE control register 3 0x00

0x00 50AC to

0x00 50AF

0x00 50B0

RST

0x00 50B1 RST_SR Reset status register 0x01

0x00 50B2

PWR

0x00 50B3 PWR_CSR2 Power control and status register 2 0x00

0x00 50B4 to

0x00 50BF

EXTI_CR1 External interrupt control register 1 0x00

WFE_CR1 WFE control register 1 0x00

Reserved area (4 bytes)

RST_CR Reset control register 0x00

PWR_CSR1 Power control and status register 1 0x00

Reserved area (12 bytes)

Reset

status

0x00 50C0

0x00 50C1 CLK_CRTCR Clock RTC register 0x00

0x00 50C2 CLK_ICKR Internal clock control register 0x11

0x00 50C3 CLK_PCKENR1 Peripheral clock gating register 1 0x00

0x00 50C4 CLK_PCKENR2 Peripheral clock gating register 2 0x80

0x00 50C5 CLK_CCOR Configurable clock control register 0x00

0x00 50C6 CLK_ECKR External clock control register 0x00

0x00 50C7 CLK_SCSR System clock status register 0x01

0x00 50C8 CLK_SWR System clock switch register 0x01

0x00 50C9 CLK_SWCR Clock switch control register 0bxxxx0000

0x00 50CA CLK_CSSR Clock security system register 0x00

0x00 50CB CLK_CBEEPR Clock BEEP register 0x00

0x00 50CC CLK_HSICALR HSI calibration register 0xxx

0x00 50CD CLK_HSITRIMR HSI clock calibration trimming register 0x00

0x00 50CE CLK_HSIUNLCKR HSI unlock register 0x00

0x00 50CF CLK_REGCSR Main regulator control status register 0bxx11100x

0x00 50D0 to

0x00 50D2

CLK

CLK_DIVR Clock master divider register 0x03

Reserved area (3 bytes)

34/102 Doc ID 023331 Rev 1

STM8L052C6 Memory and register map

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 50D3

0x00 50D4 WWDG_WR WWDR window register 0x7F

0x00 50D5 to

00 50DF

0x00 50E0

0x00 50E1 IWDG_PR IWDG prescaler register 0x00

0x00 50E2 IWDG_RLR IWDG reload register 0xFF

0x00 50E3 to

0x00 50EF

0x00 50F0

0x00 50F1
0x00 50F2

0x00 50F3 BEEP_CSR2 BEEP control/status register 2 0x1F

0x00 50F4 to

0x00 513F

WWDG

IWDG

BEEP

WWDG_CR WWDG control register 0x7F

Reserved area (11 bytes)

IWDG_KR IWDG key register 0xXX

Reserved area (13 bytes)

BEEP_CSR1 BEEP control/status register 1 0x00

Reserved area (2 bytes)

Reserved area (76 bytes)

Reset

status

Doc ID 023331 Rev 1 35/102

Memory and register map STM8L052C6

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 5140

RTC_TR1 Time register 1 0x00

Reset

status

0x00 5141 RTC_TR2 Time register 2 0x00

0x00 5142 RTC_TR3 Time register 3 0x00

0x00 5143 Reserved area (1 byte)

0x00 5144 RTC_DR1 Date register 1 0x01

0x00 5145 RTC_DR2 Date register 2 0x21

0x00 5146 RTC_DR3 Date register 3 0x00

0x00 5147 Reserved area (1 byte)

0x00 5148 RTC_CR1 Control register 1 0x00

0x00 5149 RTC_CR2 Control register 2 0x00

0x00 514A RTC_CR3 Control register 3 0x00

0x00 514B Reserved area (1 byte)

0x00 514C RTC_ISR1 Initialization and status register 1 0x00

0x00 514D RTC_ISR2 Initialization and Status register 2 0x00

0x00 514E
0x00 514F

0x00 5150 RTC_SPRERH

0x00 5151 RTC_SPRERL

RTC

0x00 5152 RTC_APRER

(1)

(1)

(1)

Reserved area (2 bytes)

Synchronous prescaler register high 0x00

Synchronous prescaler register low 0xFF

Asynchronous prescaler register 0x7F

0x00 5153 Reserved area (1 byte)

0x00 5154 RTC_WUTRH

0x00 5155 RTC_WUTRL

0x00 5156 to

0x00 5158

(1)

(1)

Wakeup timer register high 0xFF

Wakeup timer register low 0xFF

Reserved area (3 bytes)

0x00 5159 RTC_WPR Write protection register 0x00

0x00 515A
0x00 515B

Reserved area (2 bytes)

0x00 515C RTC_ALRMAR1 Alarm A register 1 0x00

0x00 515D RTC_ALRMAR2 Alarm A register 2 0x00

(1)

(1)

(1)

(1)

(1)

0x00 515E RTC_ALRMAR3 Alarm A register 3 0x00

0x00 515F RTC_ALRMAR4 Alarm A register 4 0x00

0x00 5160 to

0x00 51FF

Reserved area (160 bytes)

36/102 Doc ID 023331 Rev 1

STM8L052C6 Memory and register map

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 5200

0x00 5201 SPI1_CR2 SPI1 control register 2 0x00

0x00 5202 SPI1_ICR SPI1 interrupt control register 0x00

0x00 5203 SPI1_SR SPI1 status register 0x02

SPI1

0x00 5204 SPI1_DR SPI1 data register 0x00

0x00 5205 SPI1_CRCPR SPI1 CRC polynomial register 0x07

0x00 5206 SPI1_RXCRCR SPI1 Rx CRC register 0x00

0x00 5207 SPI1_TXCRCR SPI1 Tx CRC register 0x00

0x00 5208 to

0x00 520F

0x00 5210

0x00 5211 I2C1_CR2 I2C1 control register 2 0x00

0x00 5212 I2C1_FREQR I2C1 frequency register 0x00

0x00 5213 I2C1_OARL I2C1 own address register low 0x00

0x00 5214 I2C1_OARH I2C1 own address register high 0x00

0x00 5215 Reserved (1 byte)

0x00 5216 I2C1_DR I2C1 data register 0x00

SPI1_CR1 SPI1 control register 1 0x00

Reserved area (8 bytes)

I2C1_CR1 I2C1 control register 1 0x00

Reset

status

0x00 5217 I2C1_SR1 I2C1 status register 1 0x00

0x00 5218 I2C1_SR2 I2C1 status register 2 0x00

0x00 5219 I2C1_SR3 I2C1 status register 3 0x0x

0x00 521A I2C1_ITR I2C1 interrupt control register 0x00

0x00 521B I2C1_CCRL I2C1 clock control register low 0x00

0x00 521C I2C1_CCRH I2C1 clock control register high 0x00

0x00 521D I2C1_TRISER I2C1 TRISE register 0x02

0x00 521E I2C1_PECR I2C1 packet error checking register 0x00

0x00 521F to

0x00 522F

I2C1

Reserved area (17 bytes)

Doc ID 023331 Rev 1 37/102

Memory and register map STM8L052C6

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 5230

0x00 5231 USART1_DR USART1 data register undefined

0x00 5232 USART1_BRR1 USART1 baud rate register 1 0x00

0x00 5233 USART1_BRR2 USART1 baud rate register 2 0x00

0x00 5234 USART1_CR1 USART1 control register 1 0x00

0x00 5235 USART1_CR2 USART1 control register 2 0x00

0x00 5236 USART1_CR3 USART1 control register 3 0x00

0x00 5237 USART1_CR4 USART1 control register 4 0x00

0x00 5238 USART1_CR5 USART1 control register 5 0x00

0x00 5239 USART1_GTR USART1 guard time register 0x00

0x00 523A USART1_PSCR USART1 prescaler register 0x00

0x00 523B to

0x00 524F

USART1

USART1_SR USART1 status register 0xC0

Reserved area (21 bytes)

Reset

status

38/102 Doc ID 023331 Rev 1

STM8L052C6 Memory and register map

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 5250

0x00 5251 TIM2_CR2 TIM2 control register 2 0x00

0x00 5252 TIM2_SMCR TIM2 Slave mode control register 0x00

0x00 5253 TIM2_ETR TIM2 external trigger register 0x00

0x00 5254 TIM2_DER TIM2 DMA1 request enable register 0x00

0x00 5255 TIM2_IER TIM2 interrupt enable register 0x00

0x00 5256 TIM2_SR1 TIM2 status register 1 0x00

0x00 5257 TIM2_SR2 TIM2 status register 2 0x00

0x00 5258 TIM2_EGR TIM2 event generation register 0x00

0x00 5259 TIM2_CCMR1 TIM2 capture/compare mode register 1 0x00

0x00 525A TIM2_CCMR2 TIM2 capture/compare mode register 2 0x00

0x00 525B TIM2_CCER1 TIM2 capture/compare enable register 1 0x00

0x00 525C TIM2_CNTRH TIM2 counter high 0x00

0x00 525D TIM2_CNTRL TIM2 counter low 0x00

0x00 525E TIM2_PSCR TIM2 prescaler register 0x00

0x00 525F TIM2_ARRH TIM2 auto-reload register high 0xFF

0x00 5260 TIM2_ARRL TIM2 auto-reload register low 0xFF

TIM2

TIM2_CR1 TIM2 control register 1 0x00

Reset

status

0x00 5261 TIM2_CCR1H TIM2 capture/compare register 1 high 0x00

0x00 5262 TIM2_CCR1L TIM2 capture/compare register 1 low 0x00

0x00 5263 TIM2_CCR2H TIM2 capture/compare register 2 high 0x00

0x00 5264 TIM2_CCR2L TIM2 capture/compare register 2 low 0x00

0x00 5265 TIM2_BKR TIM2 break register 0x00

0x00 5266 TIM2_OISR TIM2 output idle state register 0x00

0x00 5267 to

0x00 527F

Reserved area (25 bytes)

Doc ID 023331 Rev 1 39/102

Memory and register map STM8L052C6

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 5280

0x00 5281 TIM3_CR2 TIM3 control register 2 0x00

0x00 5282 TIM3_SMCR TIM3 Slave mode control register 0x00

0x00 5283 TIM3_ETR TIM3 external trigger register 0x00

0x00 5284 TIM3_DER TIM3 DMA1 request enable register 0x00

0x00 5285 TIM3_IER TIM3 interrupt enable register 0x00

0x00 5286 TIM3_SR1 TIM3 status register 1 0x00

0x00 5287 TIM3_SR2 TIM3 status register 2 0x00

0x00 5288 TIM3_EGR TIM3 event generation register 0x00

0x00 5289 TIM3_CCMR1 TIM3 Capture/Compare mode register 1 0x00

0x00 528A TIM3_CCMR2 TIM3 Capture/Compare mode register 2 0x00

0x00 528B TIM3_CCER1 TIM3 Capture/Compare enable register 1 0x00

0x00 528C TIM3_CNTRH TIM3 counter high 0x00

0x00 528D TIM3_CNTRL TIM3 counter low 0x00

0x00 528E TIM3_PSCR TIM3 prescaler register 0x00

0x00 528F TIM3_ARRH TIM3 Auto-reload register high 0xFF

0x00 5290 TIM3_ARRL TIM3 Auto-reload register low 0xFF

TIM3

TIM3_CR1 TIM3 control register 1 0x00

Reset

status

0x00 5291 TIM3_CCR1H TIM3 Capture/Compare register 1 high 0x00

0x00 5292 TIM3_CCR1L TIM3 Capture/Compare register 1 low 0x00

0x00 5293 TIM3_CCR2H TIM3 Capture/Compare register 2 high 0x00

0x00 5294 TIM3_CCR2L TIM3 Capture/Compare register 2 low 0x00

0x00 5295 TIM3_BKR TIM3 break register 0x00

0x00 5296 TIM3_OISR TIM3 output idle state register 0x00

0x00 5297 to

0x00 52AF

Reserved area (25 bytes)

40/102 Doc ID 023331 Rev 1

STM8L052C6 Memory and register map

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 52B0

0x00 52B1 TIM1_CR2 TIM1 control register 2 0x00

0x00 52B2 TIM1_SMCR TIM1 Slave mode control register 0x00

0x00 52B3 TIM1_ETR TIM1 external trigger register 0x00

0x00 52B4 TIM1_DER TIM1 DMA1 request enable register 0x00

0x00 52B5 TIM1_IER TIM1 Interrupt enable register 0x00

0x00 52B6 TIM1_SR1 TIM1 status register 1 0x00

0x00 52B7 TIM1_SR2 TIM1 status register 2 0x00

0x00 52B8 TIM1_EGR TIM1 event generation register 0x00

0x00 52B9 TIM1_CCMR1 TIM1 Capture/Compare mode register 1 0x00

0x00 52BA TIM1_CCMR2 TIM1 Capture/Compare mode register 2 0x00

0x00 52BB TIM1_CCMR3 TIM1 Capture/Compare mode register 3 0x00

0x00 52BC TIM1_CCMR4 TIM1 Capture/Compare mode register 4 0x00

0x00 52BD TIM1_CCER1 TIM1 Capture/Compare enable register 1 0x00

0x00 52BE TIM1_CCER2 TIM1 Capture/Compare enable register 2 0x00

0x00 52BF TIM1_CNTRH TIM1 counter high 0x00

0x00 52C0 TIM1_CNTRL TIM1 counter low 0x00

TIM1

0x00 52C1 TIM1_PSCRH TIM1 prescaler register high 0x00

0x00 52C2 TIM1_PSCRL TIM1 prescaler register low 0x00

0x00 52C3 TIM1_ARRH TIM1 Auto-reload register high 0xFF

TIM1_CR1 TIM1 control register 1 0x00

Reset

status

0x00 52C4 TIM1_ARRL TIM1 Auto-reload register low 0xFF

0x00 52C5 TIM1_RCR TIM1 Repetition counter register 0x00

0x00 52C6 TIM1_CCR1H TIM1 Capture/Compare register 1 high 0x00

0x00 52C7 TIM1_CCR1L TIM1 Capture/Compare register 1 low 0x00

0x00 52C8 TIM1_CCR2H TIM1 Capture/Compare register 2 high 0x00

0x00 52C9 TIM1_CCR2L TIM1 Capture/Compare register 2 low 0x00

0x00 52CA TIM1_CCR3H TIM1 Capture/Compare register 3 high 0x00

0x00 52CB TIM1_CCR3L TIM1 Capture/Compare register 3 low 0x00

0x00 52CC TIM1_CCR4H TIM1 Capture/Compare register 4 high 0x00

0x00 52CD TIM1_CCR4L TIM1 Capture/Compare register 4 low 0x00

0x00 52CE TIM1_BKR TIM1 break register 0x00

0x00 52CF TIM1_DTR TIM1 dead-time register 0x00

0x00 52D0 TIM1_OISR TIM1 output idle state register 0x00

0x00 52D1 TIM1_DCR1 DMA1 control register 1 0x00

Doc ID 023331 Rev 1 41/102

Memory and register map STM8L052C6

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 52D2

TIM1

0x00 52D3 TIM1_DMA1R TIM1 DMA1 address for burst mode 0x00

0x00 52D4 to

0x00 52DF

0x00 52E0

0x00 52E1 TIM4_CR2 TIM4 control register 2 0x00

0x00 52E2 TIM4_SMCR TIM4 Slave mode control register 0x00

0x00 52E3 TIM4_DER TIM4 DMA1 request enable register 0x00

0x00 52E4 TIM4_IER TIM4 Interrupt enable register 0x00

TIM4

0x00 52E5 TIM4_SR1 TIM4 status register 1 0x00

0x00 52E6 TIM4_EGR TIM4 Event generation register 0x00

0x00 52E7 TIM4_CNTR TIM4 counter 0x00

0x00 52E8 TIM4_PSCR TIM4 prescaler register 0x00

0x00 52E9 TIM4_ARR TIM4 Auto-reload register 0x00

0x00 52EA to

0x00 52FE

0x00 52FF IRTIM IR_CR Infrared control register 0x00

TIM1_DCR2 TIM1 DMA1 control register 2 0x00

Reserved area (12 bytes)

TIM4_CR1 TIM4 control register 1 0x00

Reserved area (21 bytes)

Reset

status

0x00 5300 to

0x00 533F

Reserved area (64 bytes)

42/102 Doc ID 023331 Rev 1

STM8L052C6 Memory and register map

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 5340

0x00 5341 ADC1_CR2 ADC1 configuration register 2 0x00

0x00 5342 ADC1_CR3 ADC1 configuration register 3 0x1F

0x00 5343 ADC1_SR ADC1 status register 0x00

0x00 5344 ADC1_DRH ADC1 data register high 0x00

0x00 5345 ADC1_DRL ADC1 data register low 0x00

0x00 5346 ADC1_HTRH ADC1 high threshold register high 0x0F

0x00 5347 ADC1_HTRL ADC1 high threshold register low 0xFF

0x00 5348 ADC1_LTRH ADC1 low threshold register high 0x00

ADC1

0x00 5349 ADC1_LTRL ADC1 low threshold register low 0x00

0x00 534A ADC1_SQR1 ADC1 channel sequence 1 register 0x00

0x00 534B ADC1_SQR2 ADC1 channel sequence 2 register 0x00

0x00 534C ADC1_SQR3 ADC1 channel sequence 3 register 0x00

0x00 534D ADC1_SQR4 ADC1 channel sequence 4 register 0x00

0x00 534E ADC1_TRIGR1 ADC1 trigger disable 1 0x00

0x00 534F ADC1_TRIGR2 ADC1 trigger disable 2 0x00

0x00 5350 ADC1_TRIGR3 ADC1 trigger disable 3 0x00

ADC1_CR1 ADC1 configuration register 1 0x00

Reset

status

0x00 5351 ADC1_TRIGR4 ADC1 trigger disable 4 0x00

0x00 5352 to

0x00 53FF

0x00 5400

0x00 5401 LCD_CR2 LCD control register 2 0x00

0x00 5402 LCD_CR3 LCD control register 3 0x00

0x00 5403 LCD_FRQ LCD frequency selection register 0x00

LCD

0x00 5404 LCD_PM0 LCD Port mask register 0 0x00

0x00 5405 LCD_PM1 LCD Port mask register 1 0x00

0x00 5406 LCD_PM2 LCD Port mask register 2 0x00

0x00 5407 Reserved area

LCD_CR1 LCD control register 1 0x00

Reserved area (174 bytes)

Doc ID 023331 Rev 1 43/102

Memory and register map STM8L052C6

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 5408 to

0x00 540B

0x00 540C LCD_RAM0 LCD display memory 0 0x00

0x00 540D LCD_RAM1 LCD display memory 1 0x00

0x00 540E LCD_RAM2 LCD display memory 2 0x00

0x00 540F LCD_RAM3 LCD display memory 3 0x00

0x00 5410 LCD_RAM4 LCD display memory 4 0x00

0x00 5411 LCD_RAM5 LCD display memory 5 0x00

0x00 5412 LCD_RAM6 LCD display memory 6 0x00

0x00 5413 LCD_RAM7 LCD display memory 7 0x00

0x00 5414 LCD_RAM8 LCD display memory 8 0x00

0x00 5415 LCD_RAM9 LCD display memory 9 0x00

0x00 5416 LCD_RAM10 LCD display memory 10 0x00

0x00 5417 LCD_RAM11 LCD display memory 11 0x00

0x00 5418 LCD_RAM12 LCD display memory 12 0x00

0x00 5419 LCD_RAM13 LCD display memory 13 0x00

0x00 541A to

0x00 542F

LCD

Reserved area (4 bytes)

Reserved area (22 bytes)

Reset

status

44/102 Doc ID 023331 Rev 1

STM8L052C6 Memory and register map

Table 7. General hardware register map (continued)

Address Block Register label Register name

0x00 5430

Reserved area (1 byte) 0x00

0x00 5431 RI_ICR1 Timer input capture routing register 1 0x00

0x00 5432 RI_ICR2 Timer input capture routing register 2 0x00

0x00 5433 RI_IOIR1 I/O input register 1 undefined

0x00 5434 RI_IOIR2 I/O input register 2 undefined

0x00 5435 RI_IOIR3 I/O input register 3 undefined

0x00 5436 RI_IOCMR1 I/O control mode register 1 0x00

0x00 5437 RI_IOCMR2 I/O control mode register 2 0x00

RI

0x00 5438 RI_IOCMR3 I/O control mode register 3 0x00

0x00 5439 RI_IOSR1 I/O switch register 1 0x00

0x00 543A RI_IOSR2 I/O switch register 2 0x00

0x00 543B RI_IOSR3 I/O switch register 3 0x00

0x00 543C RI_IOGCR I/O group control register 0x3F

0x00 543D RI_ASCR1 Analog switch register 1 0x00

0x00 543E RI_ASCR2 Analog switch register 2 0x00

0x00 543F RI_RCR Resistor control register 1 0x00

0x00 5440 to

0x00 5444

1. These registers are not impacted by a system reset. They are reset at power-on.

Reserved area (5 bytes)

Reset

status

Table 8. CPU/SWIM/debug module/interrupt controller registers

Address Block Register Label Register Name

0x00 7F00

A Accumulator 0x00

0x00 7F01 PCE Program counter extended 0x00

0x00 7F02 PCH Program counter high 0x00

0x00 7F03 PCL Program counter low 0x00

0x00 7F04 XH X index register high 0x00

(1)

0x00 7F05 XL X index register low 0x00

CPU

0x00 7F06 YH Y index register high 0x00

0x00 7F07 YL Y index register low 0x00

0x00 7F08 SPH Stack pointer high 0x03

0x00 7F09 SPL Stack pointer low 0xFF

0x00 7F0A CCR Condition code register 0x28

Doc ID 023331 Rev 1 45/102

Reset

Status

Memory and register map STM8L052C6

Table 8. CPU/SWIM/debug module/interrupt controller registers (continued)

Address Block Register Label Register Name

0x00 7F0B to

0x00 7F5F

0x00 7F60 CFG_GCR Global configuration register 0x00

0x00 7F70

0x00 7F71 ITC_SPR2 Interrupt Software priority register 2 0xFF

0x00 7F72 ITC_SPR3 Interrupt Software priority register 3 0xFF

0x00 7F73 ITC_SPR4 Interrupt Software priority register 4 0xFF

0x00 7F74 ITC_SPR5 Interrupt Software priority register 5 0xFF

0x00 7F75 ITC_SPR6 Interrupt Software priority register 6 0xFF

0x00 7F76 ITC_SPR7 Interrupt Software priority register 7 0xFF

0x00 7F77 ITC_SPR8 Interrupt Software priority register 8 0xFF

0x00 7F78 to

0x00 7F79

0x00 7F80 SWIM SWIM_CSR SWIM control status register 0x00

0x00 7F81 to

0x00 7F8F

0x00 7F90

CPU

ITC_SPR1 Interrupt Software priority register 1 0xFF

ITC-SPR

DM_BK1RE DM breakpoint 1 register extended byte 0xFF

Reserved area (85 bytes)

Reserved area (2 bytes)

Reserved area (15 bytes)

Reset

Status

0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF

0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF

0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte 0xFF

0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF

0x00 7F95 DM_BK2RL DM breakpoint 2 register low byte 0xFF

0x00 7F96 DM_CR1 DM Debug module control register 1 0x00

0x00 7F97 DM_CR2 DM Debug module control register 2 0x00

0x00 7F98 DM_CSR1 DM Debug module control/status register 1 0x10

0x00 7F99 DM_CSR2 DM Debug module control/status register 2 0x00

0x00 7F9A DM_ENFCTR DM enable function register 0xFF

0x00 7F9B to

0x00 7F9F

1. Accessible by debug module only

DM

Reserved area (5 bytes)

46/102 Doc ID 023331 Rev 1

STM8L052C6 Interrupt vector mapping

6 Interrupt vector mapping

Table 9. Interrupt mapping

IRQ

No.

Source

block

Description

Wakeup

from Halt

mode

Wakeup

from

Active-

halt mode

Wakeup

from Wait

(WFI

mode)

Wakeup

from Wait

(WFE

(1)

mode)

Vector

address

RESET Reset Yes Yes Yes Yes 0x00 8000

TRAP Software interrupt - - - - 0x00 8004

0 Reserved 0x00 8008

FLASH end of programing/

1 FLASH

write attempted to

- - Yes Yes 0x00 800C

protected page interrupt

DMA1 channels 0/1 half

2 DMA1 0/1

transaction/transaction

- - Yes Yes 0x00 8010

complete interrupt

DMA1 channels 2/3 half

3 DMA1 2/3

transaction/transaction

- - Yes Yes 0x00 8014

complete interrupt

4RTC

EXTI E/F/

5

PVD

(2)

RTC alarm A/
wakeup

External interrupt port E/F
PVD interrupt

Yes Yes Yes Yes 0x00 8018

Yes Yes Yes Yes 0x00 801C

6 EXTIB/G External interrupt port B/G Yes Yes Yes Yes 0x00 8020

7 EXTID/H External interrupt port D/H Yes Yes Yes Yes 0x00 8024

8 EXTI0 External interrupt 0 Yes Yes Yes Yes 0x00 8028

9 EXTI1 External interrupt 1 Yes Yes Yes Yes 0x00 802C

10 EXTI2 External interrupt 2 Yes Yes Yes Yes 0x00 8030

11 EXTI3 External interrupt 3 Yes Yes Yes Yes 0x00 8034

12 EXTI4 External interrupt 4 Yes Yes Yes Yes 0x00 8038

13 EXTI5 External interrupt 5 Yes Yes Yes Yes 0x00 803C

14 EXTI6 External interrupt 6 Yes Yes Yes Yes 0x00 8040

15 EXTI7 External interrupt 7 Yes Yes Yes Yes 0x00 8044

16 LCD LCD interrupt - - Yes Yes 0x00 8048

CLK system clock switch/

17 CLK/TIM1

CSS interrupt/

- - Yes Yes 0x00 804C

TIM 1 break

ACD1 end of conversion/

18 ADC1

analog watchdog/

Yes Yes Yes Yes 0x00 8050

overrun interrupt

Doc ID 023331 Rev 1 47/102

Interrupt vector mapping STM8L052C6

Table 9. Interrupt mapping (continued)

IRQ

No.

Source

block

Description

Wakeup

from Halt

mode

Wakeup

from

Active-

halt mode

Wakeup

from Wait

(WFI

mode)

Wakeup

from Wait

(WFE

(1)

mode)

Vector

address

TIM2 update/overflow/

19 TIM2

trigger/break

- - Yes Yes 0x00 8054

interrupt

20 TIM2

21 TIM3

22 TIM3

23 TIM1

TIM2capture/
compare interrupt

TIM3 update/overflow/
trigger/break interrupt

TIM3 capture/compare
interrupt

Update /overflow/trigger/
COM

- - Yes Yes 0x00 8058

- - Yes Yes 0x00 805C

- - Yes Yes 0x00 8060

- - - Yes 0x00 8064

24 TIM1 Capture/compare - - - Yes 0x00 8068

25 TIM4

TIM4 update/overflow/
trigger interrupt

- - Yes Yes 0x00 806C

SPI1 TX buffer empty/

26 SPI1

RX buffer not empty/

Yes Yes Yes Yes 0x00 8070

error/wakeup interrupt

USART1transmit data

27 USART1

register empty/
transmission complete

- - Yes Yes 0x00 8074

interrupt

USART1 received data

28 USART1

ready/overrun error/
idle line detected/parity

- - Yes Yes 0x00 8078

error/global error interrupt

2

29 I

1. The Low power wait mode is entered when executing a WFE instruction in Low power run mode. In WFE mode, the
interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes back to WFE mode.
When the interrupt is configured as a wakeup event, the CPU wakes up and resumes processing.

2. The interrupt from PVD is logically OR-ed with Port E and F interrupts. Register EXTI_CONF allows to select between Port
E and Port F interrupt (see External interrupt port select register (EXTI_CONF) in the RM0031).

3. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address.

C1 I2C1 interrupt

(3)

Yes Yes Yes Yes 0x00 807C

48/102 Doc ID 023331 Rev 1

STM8L052C6 Option bytes

7 Option bytes

Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated memory block.

All option bytes can be modified in ICP mode (with SWIM) by accessing the EEPROM
address. See Tab le 1 0 for details on option byte addresses.

The option bytes can also be modified ‘on the fly’ by the application in IAP mode, except for
the ROP and UBC values which can only be taken into account when they are modified in
ICP mode (with the SWIM).

Refer to the STM8Lxx Flash programming manual (PM0054) and STM8 SWIM and Debug
Manual (UM0470) for information on SWIM programming procedures.

Table 10. Option byte addresses

Option

Addr. Option name

Read-out

0x00 4800

0x00 4802

0x00 4807 Reserved 0x00

0x00 4808

0x00 4809

0x00 480A

0x00 480B Bootloader

0x00 480C 0x00

protection

(ROP)

UBC (User

Boot code size)

Independent

watchdog

option

Number of

stabilization

clock cycles for

HSE and LSE

oscillators

Brownout reset

(BOR)

option bytes

(OPTBL)

byte

No.

OPT0 ROP[7:0] 0xAA

OPT1 UBC[7:0] 0x00

OPT3

[3:0]

OPT4 Reserved LSECNT[1:0] HSECNT[1:0] 0x00

OPT5

[3:0]

OPTBL

[15:0]

76543210

Reserved

Reserved BOR_TH

Option bits Factory

default
setting

WWDG

_HALT

OPTBL[15:0]

WWDG

_HW

IWDG

_HALT

IWDG

_HW

BOR_

ON

0x00

0x01

0x00

Doc ID 023331 Rev 1 49/102

Option bytes STM8L052C6

Table 11. Option byte description

Option

byte

No.

ROP[7:0] Memory readout protection (ROP)

OPT0

0xAA: Disable readout protection (write access via SWIM protocol)
Refer to Readout protection section in the STM8L05x/15x and STM8L16x reference manual

(RM0031).

UBC[7:0] Size of the user boot code area

0x00: no UBC
0x01: the UBC contains only the interrupt vectors.

OPT1

0x02: Page 0 and 1 reserved for the UBC and read/write protected. Page 0 contains only the interrupt
vectors.
0x03 - Page 0 to 2 reserved for UBC, memory write-protected
0xFF - Page 0 to 254 reserved for UBC, memory write-protected
Refer to User boot code section in the STM8L05x/15x and STM8L16x reference manual (RM0031).

OPT2 Reserved

IWDG_HW: Independent watchdog

0: Independent watchdog activated by software
1: Independent watchdog activated by hardware

IWDG_HALT: Independent window watchdog off on Halt/Active-halt

0: Independent watchdog continues running in Halt/Active-halt mode
1: Independent watchdog stopped in Halt/Active-halt mode

OPT3

WWDG_HW: Window watchdog

0: Window watchdog activated by software
1: Window watchdog activated by hardware

Option description

OPT4

WWDG_HALT: Window window watchdog reset on Halt/Active-halt

0: Window watchdog stopped in Halt mode
1: Window watchdog generates a reset when MCU enters Halt mode

HSECNT: Number of HSE oscillator stabilization clock cycles

0x00 - 1 clock cycle
0x01 - 16 clock cycles
0x10 - 512 clock cycles
0x11 - 4096 clock cycles

LSECNT: Number of LSE oscillator stabilization clock cycles

0x00 - 1 clock cycle
0x01 - 16 clock cycles
0x10 - 512 clock cycles
0x11 - 4096 clock cycles

Refer to Table 29: LSE oscillator characteristics on page 69.

50/102 Doc ID 023331 Rev 1

STM8L052C6 Option bytes

Table 11. Option byte description (continued)

Option

byte

No.

OPT5

OPTBL

Option description

BOR_ON:

0: Brownout reset off
1: Brownout reset on

BOR_TH[3:1]: Brownout reset thresholds. Refer to Ta b le 20 for details on the thresholds according to
the value of BOR_TH bits.

OPTBL[15:0]:
This option is checked by the boot ROM code after reset. Depending on
content of addresses 00 480B, 00 480C and 0x8000 (reset vector) the
CPU jumps to the bootloader or to the reset vector.
Refer to the UM0560 bootloader user manual for more details.

Doc ID 023331 Rev 1 51/102

Electrical parameters STM8L052C6

50 pF

STM8L PIN

8 Electrical parameters

8.1 Parameter conditions

Unless otherwise specified, all voltages are referred to VSS.

8.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T
the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics
is indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).

8.1.2 Typical values

= 25 °C and TA = TA max (given by

A

Unless otherwise specified, typical data is based on TA = 25 °C, V
design guidelines and is not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated

8.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

8.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 5.

Figure 5. Pin loading conditions

(mean±2Σ).

= 3 V. It is given only as

DD

52/102 Doc ID 023331 Rev 1

STM8L052C6 Electrical parameters

V

IN

STM8L PIN

8.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 6.

Figure 6. Pin input voltage

8.2 Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.

Table 12. Voltage characteristics

Symbol Ratings Min Max Unit

- V

V

DD

SS

External supply voltage (including V
and V

DD2

(1)

)

Input voltage on true open-drain pins
(PC0 and PC1)

(2)

V

IN

Input voltage on five-volt tolerant (FT)
pins (PA7 and PE0)

Input voltage on 3.6 V tolerant (TT) pins V

Input voltage on any other pin V

DDA

- 0.3 4.0 V

V

- 0.3 VDD + 4.0

SS

- 0.3 V

V

SS

- 0.3 4.0

SS

- 0.3 4.0

SS

DD

+ 4.0

see Absolute maximum

V

ESD

Electrostatic discharge voltage

ratings (electrical sensitivity)

on page 95

1. All power (V
external power supply.

2. VIN maximum must always be respected. Refer to Table 13. for maximum allowed injected current values.

DD1

, V

DD2

, V

) and ground (V

DDA

SS1

, V

SS2

, V

) pins must always be connected to the

SSA

V

Doc ID 023331 Rev 1 53/102

Electrical parameters STM8L052C6

Table 13. Current characteristics

Symbol Ratings Max. Unit

I

VDD

I

VSS

Total current into V

Total current out of V

power line (source) 80

DD

ground line (sink) 80

SS

Output current sunk by IR_TIM pin (with high sink LED driver
capability)

I

IO

Output current sunk by any other I/O and control pin 25

Output current sourced by any I/Os and control pin - 25

Injected current on true open-drain pins (PC0 and PC1)

(1)

Injected current on five-volt tolerant (FT) pins (PA7 and PE0)

I

INJ(PIN)

Injected current on 3.6 V tolerant (TT) pins

Injected current on any other pin

ΣI

INJ(PIN)

1. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. I
never be exceeded. Refer to Table 12. for maximum allowed input voltage values.

2. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. I
never be exceeded. Refer to Table 12. for maximum allowed input voltage values.

3. When several inputs are submitted to a current injection, the maximum ΣI
positive and negative injected currents (instantaneous values).

Table 14. Thermal characteristics

Total injected current (sum of all I/O and control pins)

(2)

(1)

(3)

is the absolute sum of the

INJ(PIN)

(1)

- 5 / +0

- 5 / +0

- 5 / +0

- 5 / +5

± 25

80

INJ(PIN)

INJ(PIN)

mA

must

must

Symbol Ratings Value Unit

T

STG

T

Storage temperature range -65 to +150

Maximum junction temperature 150

J

° C

54/102 Doc ID 023331 Rev 1

STM8L052C6 Electrical parameters

8.3 Operating conditions

Subject to general operating conditions for VDD and TA.

8.3.1 General operating conditions

Table 15. General operating conditions

Symbol Parameter Conditions Min. Max. Unit

System clock

f

SYSCLK

1. f

2. To calculate P

3. T

(1)

frequency

V

DD

V

DDA

(2)

P

D

T

A

T

J

SYSCLK

characteristics” table.

Jmax

Standard operating
voltage

Analog operating
voltage

Power dissipation at

= 85 °C

T

A

Temperature range 1.8 V ≤ V

Junction temperature
range

= f

CPU

), use the formula P

Dmax(TA

is given by the test limit. Above this value, the product behavior is not guaranteed.

Dmax

1.8 V ≤ V

Must be at the same

potential as V

-40 °C ≤ T

=(T

-TA)/ΘJA with T

Jmax

< 3.6 V 0 16 MHz

DD

DD

LQFP48 288 mW

< 3.6 V -40 85 °C

DD

< 85 °C -40 105

A

Jmax

1.8 3.6 V

1.8 3.6 V

in this table and Θ

in “Thermal

JA

(3)

°C

Doc ID 023331 Rev 1 55/102

Electrical parameters STM8L052C6

8.3.2 Embedded reset and power control block characteristics

Table 16. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min

t

VDD

t

TEMP

V

PDR

V

BOR0

V

BOR1

V

BOR2

V

BOR3

V

BOR4

VDD rise time rate

VDD fall time rate

Reset release delay

BOR detector
enabled

BOR detector
enabled

rising

V

DD

0

20

Power-down reset threshold Falling edge 1.30

Brown-out reset threshold 0
(BOR_TH[2:0]=000)

Brown-out reset threshold 1
(BOR_TH[2:0]=001)

Brown-out reset threshold 2
(BOR_TH[2:0]=010)

Brown-out reset threshold 3
(BOR_TH[2:0]=011)

Brown-out reset threshold 4
(BOR_TH[2:0]=100)

Falling edge 1.67 1.70 1.74

Rising edge 1.69 1.75 1.80

Falling edge 1.87 1.93 1.97

Rising edge 1.96 2.04 2.07

Falling edge 2.22 2.3 2.35

Rising edge 2.31 2.41 2.44

Falling edge 2.45 2.55 2.60

Rising edge 2.54 2.66 2.7

Falling edge 2.68 2.80 2.85

Rising edge 2.78 2.90 2.95

(1)

(1)

(2)

Typ

3ms

1.50 1.65 V

Max Unit

(1)

∞

µs/V

(1)

∞

V

V

PVD0

PVD threshold 0

Rising edge 1.88 1.94 1.99

Falling edge 1.98 2.04 2.09

Falling edge 1.80 1.84 1.88

V

PVD1

PVD threshold 1

Rising edge 2.08 2.14 2.18

Falling edge 2.2 2.24 2.28

V

PVD2

PVD threshold 2

Rising edge 2.28 2.34 2.38

Falling edge 2.39 2.44 2.48

V

PVD3

PVD threshold 3

Rising edge 2.47 2.54 2.58

Falling edge 2.57 2.64 2.69

V

PVD4

PVD threshold 4

Rising edge 2.68 2.74 2.79

Falling edge 2.77 2.83 2.88

V

PVD5

PVD threshold 5

Rising edge 2.87 2.94 2.99

Falling edge 2.97 3.05 3.09

V

PVD6

1. Data guaranteed by design, not tested in production.

2. Data based on characterization results, not tested in production.

PVD threshold 6

Rising edge 3.08 3.15 3.20

V

56/102 Doc ID 023331 Rev 1

STM8L052C6 Electrical parameters

1.8 V

Vdd

Internal NRST

VBOR0

BOR threshold

BOR Threshold_0

PDR Threshold

with

BOR

without

BOR

Time

with

BOR

Safe Reset

Reset

at power up

BOR activated by user for

power down detection

Vdd

Vdd

Operating power supply

3.6 V

without BOR = Batte ry lif e exten sion

VPDR

Safe Reset release

BOR always active

Figure 7. POR/BOR thresholds

8.3.3 Supply current characteristics

Total current consumption

The MCU is placed under the following conditions:

● All I/O pins in input mode with a static value at V

● All peripherals are disabled except if explicitly mentioned.

In the following table, data is based on characterization results, unless otherwise specified.

Subject to general operating conditions for V

DD

and TA.

or VSS (no load)

DD

Doc ID 023331 Rev 1 57/102

Electrical parameters STM8L052C6

Table 17. Total current consumption in Run mode

Symbol

I

DD(RUN)

Para

meter

Supply
current
in run

(2)

mode

All
peripherals
OFF,
code
executed
from RAM,

from 1.8

V

DD

V to

3.6 V

Conditions

HSI RC osc.

(16 MHz)

HSE external
clock

(f

CPU=fHSE

LSI RC osc.
(typ. 38 kHz)

(3)

(1)

f

= 125 kHz

CPU

f

= 1 MHz

CPU

= 4 MHz

f

CPU

f

= 8 MHz

CPU

f

= 16 MHz

CPU

f

= 125 kHz

CPU

f

= 1 MHz

CPU

f

= 4 MHz

CPU

(4)

)

= 8 MHz

f

CPU

f

= 16 MHz

CPU

f

= f

CPU

LSI

LSE external

= f

clock

f

CPU

LSE

(32.768 kHz)

f

= 125 kHz

CPU

f

= 1 MHz

CPU

I

DD(RUN)

Supply
current
in Run
mode

All
peripherals
OFF, code
executed
from Flash,

from

V

DD

1.8 V to 3.6 V

HSI RC

(6)

osc.

HSE external
clock

(f

CPU=fHSE

)

LSI RC osc.

(4)

= 4 MHz

f

CPU

= 8 MHz

f

CPU

f

= 16 MHz

CPU

f

= 125 kHz

CPU

f

= 1 MHz

CPU

f

= 4 MHz

CPU

f

= 8 MHz

CPU

= 16 MHz

f

CPU

= f

f

CPU

LSI

LSE ext. clock
(32.768

(7)

kHz)

1. All peripherals OFF, VDD from 1.8 V to 3.6 V, HSI internal RC osc. , f

2. CPU executing typical data processing

3. The run from RAM consumption can be approximated with the linear formula:
IDD(run_from_RAM) = Freq * 90 µA/MHz + 380 µA

f

CPU

= f

LSE

CPU=fSYSCLK

Max

Typ

55 °C

85 °C

0.39 0.47 0.49

0.48 0.56 0.58

0.75 0.84 0.86

1.10 1.20 1.25

1.85 1.93 2.12

0.05 0.06 0.09

0.18 0.19 0.20

0.55 0.62 0.64

0.99 1.20 1.21

1.90 2.22 2.23

0.040 0.045 0.046

0.035 0.040 0.048

0.43 0.55 0.56

0.60 0.77 0.80

1.11 1.34 1.37

1.90 2.20 2.23

3.8 4.60 4.75

0.30 0.36 0.39

0.40 0.50 0.52

1.15 1.31 1.40

2.17 2.33 2.44

4.0 4.46 4.52

0.110 0.123 0.130

0.100 0.101 0.104

Unit

(5)

mA

(5)

(5)

mA

58/102 Doc ID 023331 Rev 1

STM8L052C6 Electrical parameters

1.50

1.75

2.00

2.25

2.50

2.75

3.00

1.8 2.1 2.6 3.1 3.6
V

DD

[V]

IDD(RUN)HSI [mA]

-40°C
25°C
85°C

ai18213V2

4. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE
consumption
(I

) must be added. Refer to Table 28.

DD HSE

5. Tested in production.

6. The run from Flash consumption can be approximated with the linear formula:

(run_from_Flash) = Freq * 195 µA/MHz + 440 µA

I

DD

7. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE
consumption

) must be added. Refer to Table 29.

(I

DD LSE

Figure 8. Typ. I

1. Typical current consumption measured with code executed from RAM

DD(RUN)

vs. VDD,f

= 16MHz

CPU

Doc ID 023331 Rev 1 59/102

Electrical parameters STM8L052C6

In the following table, data is based on characterization results, unless otherwise specified.

Table 18. Total current consumption in Wait mode

Max

(4)

=HSE)

(1)

= 125 kHz

f

CPU

f

= 1 MHz

CPU

= 4 MHz

f

CPU

f

= 8 MHz

CPU

f

= 16 MHz

CPU

f

= 125 kHz

CPU

f

= 1 MHz

CPU

f

= 4 MHz

CPU

(4)

)

f

CPU

f

CPU

f

CPU

f

CPU

f

CPU

f

CPU

f

CPU

f

CPU

f

CPU

f

CPU

f

CPU

f

CPU

f

CPU

f

CPU

f

CPU

f

CPU

= 8 MHz

= 16 MHz

= f

LSI

= f

LSE

= 125 kHz

= 1 MHz

= 4 MHz

= 8 MHz

= 16 MHz

= 125 kHz

= 1 MHz

= 4 MHz

= 8 MHz

= 16 MHz

= f

LSI

= f

LSE

Typ

55°C

°C

85

(2)

0.33 0.39 0.41

0.35 0.41 0.44

0.42 0.51 0.52

0.52 0.57 0.58

0.68 0.76 0.79

0.032 0.056 0.068

0.078 0.121 0.144

0.218 0.26 0.30

0.40 0.52 0.57

0.760 1.01 1.05

0.035 0.044 0.046

0.032 0.036 0.038

0.38 0.48 0.49

0.41 0.49 0.51

0.50 0.57 0.58

0.60 0.66 0.68

0.79 0.84 0.86

0.06 0.08 0.09

0.10 0.17 0.18

0.24 0.36 0.39

0.50 0.58 0.61

1.00 1.08 1.14

0.055 0.058 0.065

0.051 0.056 0.060

Unit

mA

mA

Symbol Parameter

Supply

I

DD(Wait)

current in
Wait mode

Supply

I

DD(Wait)

current in
Wait

mode

CPU not
clocked,
all peripherals
OFF,
code executed
from RAM
with Flash in

(3)

mode

I

DDQ

from

V

DD

1.8 V to 3.6 V

CPU not
clocked,
all peripherals
OFF,
code executed
from Flash,

from

V

DD

1.8 V to 3.6 V

Conditions

HSI

HSE external
clock

(f

CPU=fHSE

,

LSI

(5)

LSE
external clock
(32.768
kHz)

HSI

HSE
external clock
(f

CPU

LSI

(5)

LSE
external clock
(32.768 kHz)

1. All peripherals OFF, VDD from 1.8 V to 3.6 V, HSI internal RC osc. , f

2. For temperature range 6.

3. Flash is configured in I

mode in Wait mode by setting the EPM or WAITM bit in the Flash_CR1 register.

DDQ

60/102 Doc ID 023331 Rev 1

CPU

= f

SYSCLK

STM8L052C6 Electrical parameters

500

550

600

650

700

750

800

850

900

950

1000

1.8 2.1 2.6 3.1 3.6
V

DD

[V]

IDD(WAIT)HSI

[μA]

-40°C
25°C
85°C

ai18214V2

4. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE
consumption
(I

) must be added. Refer to Table 28.

DD HSE

5. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE
consumption

) must be added. Refer to Table 29.

(I

DD HSE

Figure 9. Typ. I

1. Typical current consumption measured with code executed from Flash memory.

DD(Wait)

vs. VDD,f

CPU

=16MHz

1)

Doc ID 023331 Rev 1 61/102

Electrical parameters STM8L052C6

In the following table, data is based on characterization results, unless otherwise specified.

Table 19. Total current consumption and timing in Low power run mode at V

= 1.8 V to

DD

3.6 V

Symbol Parameter

Conditions

all peripherals OFF

LSI RC osc.
(at 38 kHz)

with TIM2 active

I

DD(LPR)

Supply current in Low
power run mode

all peripherals OFF

(3)

LSE

external
clock
(32.768 kHz)

with TIM2 active

1. No floating I/Os

2. Timer 2 clock enabled and counter running

3. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption
) must be added. Refer to Table 29

(I

DD LSE

(1)

(2)

(2)

Typ Ma x Unit

= -40 °C

T

A

to 25 °C

T

= 55 °C 5.7 6

A

= 85 °C 6.8 7.5

T

A

T

= -40 °C

A

to 25 °C

T

= 55 °C 6.0 6.3

A

= 85 °C 7.2 7.8

T

A

TA = -40 °C
to 25 °C

T

= 55 °C 5.67 6.1

A

= 85 °C 5.85 6.3

T

A

TA = -40 °C
to 25 °C

T

= 55 °C 6.10 6.4

A

= 85 °C 6.30 7

T

A

5.1 5.4

5.4 5.7

5.25 5.6

5.59 6

μA

Figure 10. Typ. I

[μA]

DD(LPR)LSI

I

DD(LPR)

vs. V

18

16

14

12

10

8

6

4

2

0

1. 8 2.1 2.6 3.1 3.6

(LSI clock source)

DD

V

DD

62/102 Doc ID 023331 Rev 1

[V]

–40° C

25° C

85° C

ai18216V2

STM8L052C6 Electrical parameters

0.00

2.00

4.00

6.00

8.00

10.00

12.00

14.00

16.00

1.8 2.1 2.6

3.1 3.6

V

DD

[V]

I

DD(LPW )LSI

[µA]

-40°C

25°C

85°C

ai18217V2

In the following table, data is based on characterization results, unless otherwise specified.

Table 20. Total current consumption in Low power wait mode at V

Symbol Parameter

Conditions

(1)

= 1.8V to 3.6V

DD

Typ Max Uni t

I

DD(LPW)

Supply current in
Low power wait mode

LSI RC osc.
(at 38 kHz)

LSE external

(3)

clock
(32.768 kHz)

all peripherals OFF

with TIM2 active

(2)

all peripherals OFF

with TIM2 active

(2)

TA = -40 °C to 25 °C

T

= 55 °C 3.3 3.6

A

= 85 °C 4.4 5

T

A

= -40 °C to 25 °C

T

A

T

= 55 °C 3.7 4

A

= 85 °C 4.8 5.4

T

A

T

= -40 °C to 25 °C

A

T

= 55 °C 2.42 2.82

A

= 85 °C 3.10 3.71

T

A

TA = -40 °C to 25 °C

= 55 °C 2.50 2.81

T

A

= 85 °C 3.16 3.82

T

A

33.3

3.4 3.7

2.35 2.7

2.46 2.75

1. No floating I/Os.

2. Timer 2 clock enabled and counter is running.

3. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption
) must be added. Refer to Table 29.

(I

DD LSE

Figure 11. Typ. I

DD(LPW)

vs. V

(LSI clock source)

DD

μA

Doc ID 023331 Rev 1 63/102

Electrical parameters STM8L052C6

In the following table, data is based on characterization results, unless otherwise specified.

Table 21. Total current consumption and timing in Active-halt mode at V

Symbol Parameter

Conditions

(1)

= 1.8 V to 3.6 V

DD

Typ Max Unit

I

DD(AH)

I

DD(AH)

Supply current in
Active-halt mode

Supply current in
Active-halt mode

Supply current during

I

DD(WUFAH)

wakeup time from
Active-halt mode
(using HSI)

Wakeup time from

(8)(9)

t

WU_HSI(AH)

Active-halt mode to
Run mode (using HSI)

Wakeup time from

(9)

(8)

Active-halt mode to
Run mode (using LSI)

t

WU_LSI(AH)

1. No floating I/O, unless otherwise specified.

2. RTC enabled. Clock source = LSI

3. RTC enabled, LCD enabled with external V

LSI RC

(at 38 kHz)

LSE external
clock
(32.768 kHz)

(6)

LCD OFF

(2)

LCD ON
(static duty/
external

(3)

)

V

LCD

LCD ON
(1/4 duty/
external

(4)

)

V

LCD

LCD ON
(1/4 duty/
internal

(5)

V

)

LCD

LCD OFF

(7)

LCD ON
(static duty/
external

(3)

V

)

LCD

LCD ON
(1/4 duty/
external

(4)

)

V

LCD

LCD ON
(1/4 duty/
internal

(5)

V

)

LCD

TA = -40 °C to 25 °C

T

= 55 °C 1.2 3

A

= 85 °C 1.5 3.4

T

A

TA = -40 °C to 25 °C

T

= 55 °C 1.5 3.3

A

= 85 °C 1.9 4.3

T

A

TA = -40 °C to 25 °C

T

= 55 °C 1.95 4.4

A

= 85 °C 2.4 5.4

T

A

TA = -40 °C to 25 °C

= 55 °C 4.15 9.3

T

A

= 85 °C 4.5 10.2

T

A

TA = -40 °C to 25 °C

T

= 55 °C 0.62 1.4

A

= 85 °C 0.88 2.1

T

A

TA = -40 °C to 25 °C

= 55 °C 0.95 2.2

T

A

= 85 °C 1.3 3.2

T

A

TA = -40 °C to 25 °C

T

= 55 °C 1.6 3.8

A

= 85 °C 1.8 4.2

T

A

TA = -40 °C to 25 °C

= 55 °C 3.7 8.3

T

A

= 85 °C 3.9 9.2

T

A

0.9 2.1

1.4 3.1

1.9 4.3

3.9 8.75

0.5 1.2

0.85 1.9

1.5 2.5

3.4 7.6

2.4 mA

4.7 7 μs

150 μs

= 3 V, static duty, division ratio = 256, all pixels active, no LCD connected.

LCD

μA

μA

64/102 Doc ID 023331 Rev 1

STM8L052C6 Electrical parameters

4. RTC enabled, LCD enabled with external V

5. LCD enabled with internal LCD booster V

connected.

6. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption

7. RTC enabled. Clock source = LSE.

8. Wakeup time until start of interrupt vector fetch.

9. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register.

Table 22. Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal

) must be added. Refer to Table 29.

(I

DD LSE

The first word of interrupt routine is fetched 4 CPU cycles after t

Symbol Parameter Condition

, 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected.

LCD

= 3 V , 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD

LCD

.

WU

(1)

Typ Unit

LSE 1.15

V

= 1.8 V

I

DD(AH)

(2)

Supply current in Active-halt
mode

V

DD

DD

= 3 V

(3)

LSE/32

LSE 1.30

(3)

LSE/32

1.05

µA

1.20

LSE 1.45

V

= 3.6 V

DD

1. No floating I/O, unless otherwise specified.

2. Based on measurements on bench with 32.768 kHz external crystal oscillator.

3. RTC clock is LSE divided by 32.

LSE/32

(3)

1.35

In the following table, data is based on characterization results, unless otherwise specified.

Table 23. Total current consumption and timing in Halt mode at V

t

WU_HSI(Halt)

t

WU_LSI(Halt)

1. TA = -40 to 85 °C, no floating I/O, unless otherwise specified.

2. Tested in production.

3. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register.

4. Wakeup time until start of interrupt vector fetch.

The first word of interrupt routine is fetched 4 CPU cycles after t

Symbol Parameter Condition

TA = -40 °C to 25 °C 350

TA = 85 °C 1160

I

DD(Halt)

Supply current in Halt mode
(Ultra-low-power ULP bit =1 in

PWR_CSR2 register)

the

Supply current during wakeup

I

DD(WUHalt)

time from Halt mode (using
HSI)

(3)(4)

Wakeup time from Halt to Run
mode (using HSI)

(3)(4)

Wakeup time from Halt mode
to Run mode (using LSI)

.

WU

(1)

= 1.8 to 3.6 V

DD

Typ Max Unit

1400

2800

2.4 mA

4.7 7 µs

150 µs

(2)

nATA = 55 °C 580 2000

(2)

Doc ID 023331 Rev 1 65/102

Electrical parameters STM8L052C6

Current consumption of on-chip peripherals

Table 24. Peripheral current consumption

Symbol Parameter

I

DD(TIM1)

I

DD(TIM2)

I

DD(TIM3)

I

DD(TIM4)

I

DD(USART1)

I

DD(SPI1)

I

DD(I2C1)

I

DD(DMA1)

I

DD(WWDG)

I

DD(ALL)

I

DD(ADC1)

I

DD(PVD/BOR)

I

DD(BOR)

TIM1 supply current

TIM2 supply current

TIM3 supply current

TIM4 timer supply current

USART1 supply current

SPI1 supply current

I2C1 supply current

DMA1 supply current

WWDG supply current

Peripherals ON

ADC1 supply current

Power voltage detector and brownout Reset unit supply current

(5)

Brownout Reset unit supply current

(1)

(1)

(1)

(1)

(2)

(2)

(2)

(2)

(2)

(3)

(4)

(5)

including LSI supply

I

DD(IDWDG)

Independent watchdog supply current

current

excluding LSI
supply current

1. Data based on a differential IDD measurement between all peripherals OFF and a timer counter running at 16 MHz. The

CPU is in Wait mode in both cases. No IC/OC programmed, no I/O pins toggling. Not tested in production.

2. Data based on a differential I

the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pins
toggling. Not tested in production.

3. Peripherals listed above the I

4. Data based on a differential I

5. Including supply current of internal reference voltage.

measurement between the on-chip peripheral in reset configuration and not clocked and

DD

parameter ON: TIM1, TIM2, TIM3, TIM4, USART1, SPI1, I2C1, DMA1, WWDG.

DD(ALL)

measurement between ADC in reset configuration and continuous ADC conversion.

DD

Typ.

= 3.0 V

V

DD

13

8

8

3

6

3

5

3

2

44 µA/MHz

1500

2.6

2.4

0.45

0.05

Unit

µA/MHz

µA

Table 25. Current consumption under external reset

Symbol Parameter Conditions Typ Unit

V

= 1.8 V 48

I

DD(RST)

1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset.

Supply current under

external reset

(1)

All pins are externally
tied to V

DD

DD

= 3 V 76

DD

= 3.6 V 91

V

DD

66/102 Doc ID 023331 Rev 1

µAV

STM8L052C6 Electrical parameters

8.3.4 Clock and timing characteristics

HSE external clock (HSEBYP = 1 in CLK_ECKCR)

Subject to general operating conditions for VDD and TA.

Table 26. HSE external clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

f

HSE_ext

V

HSEH

V

HSEL

C

in(HSE)

I

LEAK_HSE

1. Data guaranteed by Design, not tested in production.

External clock source

frequency

(1)

OSC_IN input pin high level
voltage

OSC_IN input pin low level
voltage

OSC_IN input

capacitance

(1)

OSC_IN input leakage
current

116MHz

0.7 x V

V

SS

DD

V

0.3 x V

2.6 pF

V

< V

IN

< V

DD

SS

LSE external clock (LSEBYP=1 in CLK_ECKCR)

Subject to general operating conditions for VDD and TA.

LSEL

in(LSE)

(2)

(2)

External clock source frequency

(1)

OSC32_IN input pin high level voltage 0.7 x V

OSC32_IN input pin low level voltage V

OSC32_IN input capacitance

(1)

SS

32.768 kHz

DD

0.3 x V

0.6 pF

V

DD

OSC32_IN input leakage current ±1 µA

Table 27. LSE external clock characteristics

Symbol Parameter Min Typ Max Unit

f

LSE_ext

V

LSEH

V

C

I

LEAK_LSE

1. Data guaranteed by Design, not tested in production.

2. Data based on characterization results, not tested in production.

DD

V

DD

±1 µA

V

DD

Doc ID 023331 Rev 1 67/102

Electrical parameters STM8L052C6

OSC_OUT

OSC_IN

f

HSE

to core

C

L1

C

L2

R

F

STM8

Resonator

Consumption

control

g

m

R

m

C

m

L

m

C

O

Resonator

g

mcrit

2 Π× f

HSE

×()

2

Rm× 2Co C+()

2

=

HSE crystal/ceramic resonator oscillator

The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).

Table 28. HSE oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

f

HSE

R

C

I

DD(HSE)

g

t

SU(HSE)

1. C=

2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small R

Refer to crystal manufacturer for more details

High speed external oscillator
frequency

Feedback resistor 200 kΩ

F

(1)

Recommended load capacitance

(2)

C = 20 pF,

f

= 16 MHz

HSE oscillator power consumption

OSC

C = 10 pF,

=16 MHz

f

OSC

Oscillator transconductance 3.5

m

(4)

Startup time VDD is stabilized 1 ms

C

=

C

is approximately equivalent to 2 x crystal C

L1

L2

LOAD

.

116MHz

20 pF

2.5 (startup)

0.7 (stabilized)

2.5 (startup)

0.46 (stabilized)

(3)

3. Data guaranteed by Design. Not tested in production.

4. t

is the startup time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation. This

SU(HSE)

value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

Figure 12. HSE oscillator circuit diagram

value.

m

(3)

mA

(3)

mA/V

HSE oscillator critical g

Rm: Motional resistance (see crystal specification), Lm: Motional inductance (see crystal specification),

: Motional capacitance (see crystal specification), Co: Shunt capacitance (see crystal specification),

C

m

=C: Grounded external capacitance

C

L1=CL2

>> g

g

m

mcrit

68/102 Doc ID 023331 Rev 1

formula

m

STM8L052C6 Electrical parameters

OSC_OUT

OSC_IN

f

LSE

C

L1

C

L2

R

F

STM8

Resonator

Consumption

control

g

m

R

m

C

m

L

m

C

O

Resonator

LSE crystal/ceramic resonator oscillator

The LSE clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).

Table 29. LSE oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

f

LSE

R

C

I

DD(LSE)

g

t

SU(LSE)

1. C=

2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with a small R

Refer to crystal manufacturer for more details.

Low speed external oscillator
frequency

Feedback resistor ΔV = 200 mV 1.2 MΩ

F

(1)

Recommended load capacitance

(2)

32.768 kHz

8pF

1.4

V

= 1.8 V 450

LSE oscillator power consumption

Oscillator transconductance 3

m

(4)

Startup time VDD is stabilized 1 s

C

=

C

is approximately equivalent to 2 x crystal C

L1

L2

DD

= 3 V 600

DD

= 3.6 V 750

V

DD

.

LOAD

(3)

(3)

3. Data guaranteed by Design. Not tested in production.

4. t

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation.

SU(LSE)

This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

Figure 13. LSE oscillator circuit diagram

value.

m

µA

nAV

µA/V

Doc ID 023331 Rev 1 69/102

Electrical parameters STM8L052C6

13.0

13.5

14.0

14.5

15.0

15.5

16.0

16.5

17.0

17.5

18.0

1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6

V

DD

[V]

HSI

frequency

[MHz]

-40°C
25°C
85°C

ai18218V2

Internal clock sources

Subject to general operating conditions for VDD, and TA.

High speed internal RC oscillator (HSI)

In the following table, data is based on characterization results, not tested in production,
unless otherwise specified.

Table 30. HSI oscillator characteristics

Symbol Parameter

Conditions

(1)

Min Typ Max Unit

f

HSI

ACC

TRIM

t

su(HSI)

I

DD(HSI)

1. VDD = 3.0 V, TA = -40 to 85 °C unless otherwise specified.

2. Tested in production.

3. The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16

(0x00, 0x10, 0x20, 0x30...0xE0). Refer to the AN3101 “STM8L15x internal RC oscillator calibration” application note for
more details.

4. Guaranteed by design, not tested in production.

Frequency VDD = 3.0 V 16 MHz

Accuracy of HSI
oscillator (factory

HSI

calibrated)

HSI user trimming
step

(3)

VDD = 3.0 V, TA = 25 °C -1

1.8 V ≤ V

-40 °C ≤ TA ≤ 85 °C

Trimming code ≠ multiple of 16 0.4 0.7 %

Trimming code = multiple of 16 ± 1.5 %

HSI oscillator setup
time (wakeup time)

HSI oscillator power
consumption

Figure 14. Typical HSI frequency vs V

≤ 3.6 V,

DD

DD

(2)

-5 5 %

3.7 6

100 140

(2)

1

(4)

(4)

%

µs

µA

70/102 Doc ID 023331 Rev 1

STM8L052C6 Electrical parameters

25

27

29

31

33

35

37

39

41

43

45

1.8 2.1 2.6 3.1 3.6

V

DD

[V]

LSI

frequency

[kHz]

-40°C
25°C
85°C

ai18219V2

Low speed internal RC oscillator (LSI)

In the following table, data is based on characterization results, not tested in production.

Table 31. LSI oscillator characteristics

Symbol

Parameter

(1)

Conditions

(1)

Min Typ Max Unit

f

t

su(LSI)

I

DD(LSI)

1. VDD = 1.8 V to 3.6 V, TA = -40 to 85 °C unless otherwise specified.

2. Guaranteed by design, not tested in production.

3. This is a deviation for an individual part, once the initial frequency has been measured.

Figure 15. Typical LSI frequency vs. V

Frequency 26 38 56 kHz

LSI

LSI oscillator wakeup time 200

LSI oscillator frequency

(3)

drift

0 °C ≤ TA ≤ 85 °C -12 11 %

DD

(2)

µs

Doc ID 023331 Rev 1 71/102

Electrical parameters STM8L052C6

8.3.5 Memory characteristics

TA = -40 to 85 °C unless otherwise specified.

Table 32. RAM and hardware registers

Symbol Parameter Conditions Min Typ Max Unit

V

RM

1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware
registers (only in Halt mode). Guaranteed by characterization, not tested in production.

Data retention mode

Flash memory

Table 33. Flash program and data EEPROM memory

(1)

Halt mode (or Reset) 1.8 V

Symbol Parameter Conditions Min Typ

V

Operating voltage

DD

(all modes, read/write/erase)

f

SYSCLK

= 16 MHz 1.8 3.6 V

Programming time for 1 or 64 bytes (block)
erase/write cycles (on programmed byte)

t

prog

Programming time for 1 to 64 bytes (block)
write cycles (on erased byte)

T

=+25 °C, VDD = 3.0 V

I

Programming/ erasing consumption

prog

Data retention (program memory) after 100
erase/write cycles at TA= –40 to +85 °C

(2)

t

RET

Data retention (data memory) after 100000
erase/write cycles at T

= –40 to +85 °C

A

Erase/write cycles (program memory)

(3)

N

RW

Erase/write cycles

1. Data based on characterization results, not tested in production.

2. Conforming to JEDEC JESD22a117

3. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation
addresses a single byte.

4. Data based on characterization performed on the whole data memory.

(data memory)

A

=+25 °C, VDD = 1.8 V

T

A

T

= +85 °C 30

RET

= +85 °C 30

T

RET

TA = –40 to +85 °C

100

100

(1)

(1)

(1)

(1)

(4)

Max

(1)

6ms

3ms

0.7 mA

years

cycles

kcycles

Unit

8.3.6 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above V
in order to give an indication of the robustness of the microcontroller in cases when
abnormal injection accidentally happens, susceptibility tests are performed on a sample
basis during device characterization.

72/102 Doc ID 023331 Rev 1

(for standard pins) should be avoided during normal product operation. However,

DD

STM8L052C6 Electrical parameters

Functional susceptibilty to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into the
I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error, out of spec current
injection on adjacent pins or other functional failure (for example reset, oscillator frequency
deviation, LCD levels, etc.).

The test results are given in the following table.

Table 34. I/O current injection susceptibility

Functional susceptibility

Symbol Description

Negative
injection

Positive

injection

Unit

Injected current on true open-drain pins (PC0 and
PC1)

I

INJ

Injected current on all five-volt tolerant (FT) pins -5 +0

Injected current on all 3.6 V tolerant (TT) pins -5 +0

Injected current on any other pin -5 +5

8.3.7 I/O port pin characteristics

General characteristics

Subject to general operating conditions for VDD and TA unless otherwise specified. All
unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or
an external pull-up or pull-down resistor.

-5 +0

mA

Doc ID 023331 Rev 1 73/102

Electrical parameters STM8L052C6

Table 35. I/O static characteristics

Symbol Parameter

Input voltage on true open-drain
pins (PC0 and PC1)

Input voltage on five-volt
tolerant (FT) pins (PA7 and

V

Input low level voltage

IL

(2)

PE0)

Input voltage on 3.6 V tolerant
(TT) pins

Input voltage on any other pin

Input voltage on true open-drain
pins (PC0 and PC1)
with VDD < 2 V

Input voltage on true open-drain
pins (PC0 and PC1)
with V

Input voltage on five-volt
tolerant (FT) pins (PA7 and
PE0)

V

Input high level voltage

IH

(2)

with V

Input voltage on five-volt
tolerant (FT) pins (PA7 and
PE0)
with VDD ≥ 2 V

Conditions

≥ 2 V

DD

< 2 V

DD

(1)

Min

Typ

VSS-0.3 0.3 x V

-0.3 0.3 x V

V

SS

VSS-0.3 0.3 x V

V

-0.3 0.3 x V

SS

0.70 x V

0.70 x V

DD

DD

Max Unit

DD

DD

V

DD

DD

5.2

5.5

5.2
V

5.5

Input voltage on 3.6 V tolerant
(TT) pins

Input voltage on any other pin

V

Schmitt trigger voltage

hys

hysteresis

(3)

I/Os 200

True open drain I/Os 200

V

≤ VIN≤ V

SS

DD

High sink I/Os

V

≤ VIN≤ V

I

Input leakage current

lkg

(4)

SS

True open drain I/Os

V

≤ VIN≤ V

SS

DD

DD

PA0 with high sink LED driver

0.70 x V

DD

--50

- - 200

- - 200

capability

R

C

1. VDD = 3.0 V, TA = -40 to 85 °C unless otherwise specified.

2. Data based on characterization results, not tested in production.

3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

4. The max. value may be exceeded if negative current is injected on adjacent pins.

5. Not tested in production.

Weak pull-up equivalent

PU

resistor

I/O pin capacitance 5 pF

IO

(2)(6)

V

IN=VSS

30 45 60 kΩ

3.6

VDD+0.3

mV

(5)

(5)

nA

(5)

74/102 Doc ID 023331 Rev 1

STM8L052C6 Electrical parameters

0

0.5

1

1.5

2

2.5

3

1.8 2.1 2.6 3.1 3.6
V

DD

[V]

V

IL

and

V

IH

[V]

-40°C
25°C
85°C

ai18220V2

0

0.5

1

1.5

2

2.5

3

1.8 2.1 2.6 3.1 3.6

V

DD

[V]

V

IL

and V

IH

[V]

-40°C
25°C
85°C

ai18221V2

6. RPU pull-up equivalent resistor based on a resistive transistor(corresponding I

Figure 19).

Figure 16. Typical VIL and V

Figure 17. Typical V

and V

IL

vs VDD (high sink I/Os)

IH

vs VDD (true open drain I/Os)

IH

current characteristics described in

PU

Doc ID 023331 Rev 1 75/102

Electrical parameters STM8L052C6

30

35

40

45

50

55

60

1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

V

DD

[V]

Pull-Up resistance [k

Ω

]

-40°C
25°C
85°C

ai18222V2

0

20

40

60

80

100

120

1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6
V

DD

[V]

Pull-Up current [μA]

-40°C
25°C
85°C

ai18223V2

Figure 18. Typical pull-up resistance RPU vs VDD with VIN=V

Figure 19. Typical pull-up current Ipu vs VDD with VIN=V

SS

SS

76/102 Doc ID 023331 Rev 1

STM8L052C6 Electrical parameters

Output driving current

Subject to general operating conditions for V

Table 36. Output driving current (high sink ports)

I/O

Symbol Parameter Conditions Min Max Unit

Type

(1)

V

High sink

V

OH

1. The IIO current sunk must always respect the absolute maximum rating specified in Table 13 and the sum
of I

(I/O ports and control pins) must not exceed I

IO

2. The IIO current sourced must always respect the absolute maximum rating specified in Table 13 and the
sum of I

IO

Output low level voltage for an I/O pin

OL

(2)

Output high level voltage for an I/O pin

(I/O ports and control pins) must not exceed I

and TA unless otherwise specified.

DD

= +2 mA,

I

IO

= 3.0 V

V

DD

= +2 mA,

I

IO

= 1.8 V

V

DD

= +10 mA,

I

IO

= 3.0 V

V

DD

= -2 mA,

I

VSS

.

VDD

.

IO

= 3.0 V

V

DD

= -1 mA,

I

IO

= 1.8 V

V

DD

I

= -10 mA,

IO

V

= 3.0 V

DD

VDD-0.45

V

-0.45

DD

V

-0.7 V

DD

0.45 V

0.45 V

0.7 V

V

V

Table 37. Output driving current (true open drain ports)

I/O

Symbol Parameter Conditions Min Max Unit

Type

= +3 mA,

I

IO

V

= 3.0 V

(1)

V

Output low level voltage for an I/O pin

OL

Open drain

1. The IIO current sunk must always respect the absolute maximum rating specified in Table 13 and the sum
of I

(I/O ports and control pins) must not exceed I

IO

VSS

.

DD

I

= +1 mA,

IO

V

DD

= 1.8 V

0.45

0.45

Table 38. Output driving current (PA0 with high sink LED driver capability)

I/O

Symbol Parameter Conditions Min Max Unit

Type

= +20 mA,

I

(1)

V

IR

1. The IIO current sunk must always respect the absolute maximum rating specified in Table 13 and the sum
of IIO (I/O ports and control pins) must not exceed I

Output low level voltage for an I/O pin

OL

VSS

.

V

IO

DD

= 2.0 V

0.45 V

V

Doc ID 023331 Rev 1 77/102

Electrical parameters STM8L052C6

0

0.25

0.5

0.75

1

02468101214161820

I

OL

[mA]

V

OL

[V]

-40°C

25°C

85°C

ai18226V2

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0123456 78

I

OL

[mA]

V

OL

[V]

-40°C

25°C

85°C

ai18227V2

ai18228V2

0

0.1

0.2

0.3

0.4

0.5

01234567

I

OL

[mA]

V

OL

[V]

-40°C

25°C

85°C

0

0.1

0.2

0.3

0.4

0.5

01234567

I

OL

[mA]

V

OL

[V]

-40°C

25°C

85°C

BJ7

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

0 2 4 6 8 101214161820

I

OH

[mA]

V

DD

- V

OH

[V]

-40°C

25°C

85°C

ai12830V2

0

0.1

0.2

0.3

0.4

0.5

012345 67

I

OH

[mA]

V

DD

- V

OH

[V]

-40°C

25°C

85°C

BJ7

Figure 20. Typ. VOL @ VDD = 3.0 V (high sink

ports)

Figure 22. Typ. VOL @ VDD = 3.0 V (true open

drain ports)

Figure 21. Typ. VOL @ VDD = 1.8 V (high sink

ports)

Figure 23. Typ. VOL @ VDD = 1.8 V (true open

drain ports)

Figure 24. Typ. V

DD - VOH

sink ports)

78/102 Doc ID 023331 Rev 1

@ VDD = 3.0 V (high

Figure 25. Typ. V

sink ports)

DD - VOH

@ VDD = 1.8 V (high

STM8L052C6 Electrical parameters

30

35

40

45

50

55

60

1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
V

DD

[V]

Pull-up

resistance

[k

Ω

]

-40°C
25°C
85°C

ai18224V2

NRST pin

Subject to general operating conditions for VDD and TA unless otherwise specified.

Table 39. NRST

Symbol Parameter Conditions Min

pin characteristics

Typ

Max Unit

V

IL(NRST)

V

IH(NRST)

NRST input low level voltage

NRST input high level voltage

(1)

(1)

IOL = 2 mA
for 2.7 V ≤ V
V

(3)

(3)

(1)

I

= 1.5 mA

OL

for V

DD

V

OL(NRST)

V

HYST

R

PU(NRST)

V

F(NRST)

V

NF(NRST)

1. Data based on characterization results, not tested in production.

2. 200 mV min.

3. Data guaranteed by design, not tested in production.

NRST output low level voltage

NRST input hysteresis

(3)

NRST pull-up equivalent resistor

(1)

NRST input filtered pulse

NRST input not filtered pulse

Figure 26. Typical NRST pull-up resistance RPU vs VDD

DD

< 2.7 V

≤ 3.6

V

1.4

SS

0.8

V

DD

0.4

10%V

DD

(2)

30 45 60 kΩ

50

300

V

mV

ns

Doc ID 023331 Rev 1 79/102

Electrical parameters STM8L052C6

ai18225V2

0

20

40

60

80

100

120

1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6

V

DD

[V]

Pull-U

p current [ μA]

-40°C

25°C

85

°C

EXTERNAL

RESET

CIRCUIT

STM8

Filter

R

PU

V

DD

INTERNAL RESET

NRST

0.1 µF

(Optional)

Figure 27. Typical NRST pull-up current Ipu vs VDD

The reset network shown in Figure 28 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below the V

IL(NRST)

max. level specified

in Ta bl e 3 9 . Otherwise the reset is not taken into account internally.

For power consumption sensitive applications, the external reset capacitor value can be
reduced to limit the charge/discharge current. If the NRST signal is used to reset the
external circuitry, attention must be paid to the charge/discharge time of the external
capacitor to fulfill the external devices reset timing conditions. The minimum recommended
capacity is 10 nF.

Figure 28. Recommended NRST pin configuration

80/102 Doc ID 023331 Rev 1

STM8L052C6 Electrical parameters

8.3.8 Communication interfaces

SPI1 - Serial peripheral interface

Unless otherwise specified, the parameters given in Ta bl e 4 0 are derived from tests
performed under ambient temperature, f
conditions summarized in Section 8.3.1. Refer to I/O port characteristics for more details on
the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Table 40. SPI1 characteristics

Symbol Parameter Conditions

SYSCLK

frequency and VDD supply voltage

(1)

Min Max Unit

f

SCK

1/t

c(SCK)

t

r(SCK)

t

f(SCK)

t

su(NSS)

t

h(NSS)

t

w(SCKH)

t

w(SCKL)

t

su(MI)

t

su(SI)

t

h(MI)

t

h(SI)

t

a(SO)

t

dis(SO)

t

v(SO)

t

v(MO)

t

h(SO)

t

h(MO)

(2)

(2)

(2)

(2)

(2)

(2)

(2)

(2)(3)

(2)(4)

(2)

(2)

(2)

(2)

SPI1 clock frequency

Master mode 0 8

Slave mode 0 8

SPI1 clock rise and fall
time

NSS setup time Slave mode 4 x 1/f

Capacitive load: C = 30 pF - 30 ns

SYSCLK

NSS hold time Slave mode 80 -

(2)

SCK high and low time

Master mode,

MASTER

= 8 MHz, f

f

SCK

= 4 MHz

105 145

Master mode 30 -

Data input setup time

Slave mode 3 -

Master mode 15 -

Data input hold time

Slave mode 0 -

Data output access time Slave mode - 3x 1/f

Data output disable time Slave mode 30 -

Data output valid time Slave mode (after enable edge) - 60

Data output valid time

Master mode (after enable
edge)

-20

Slave mode (after enable edge) 15 -

Data output hold time

Master mode (after enable
edge)

1-

MHz

-

SYSCLK

1. Parameters are given by selecting 10 MHz I/O output frequency.

2. Values based on design simulation and/or characterization results, and not tested in production.

3. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data.

4. Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in Hi-Z.

Doc ID 023331 Rev 1 81/102

Electrical parameters STM8L052C6

ai14134

SCK Input

CPHA=0

MOSI

INPUT

MISO

OUT PUT

CPHA=0

MS B O U T

MSB IN

BI T6 O UT

LSB IN

LSB OUT

CPOL=0

CPOL=1

BIT1 IN

NSS input

t

SU(NSS)

t

c(SCK)

t

h(NSS)

t

a(SO)

t

w(SCKH)

t

w(SCKL)

t

v(SO)

t

h(SO)

t

r(SCK)

t

f(SCK)

t

dis(SO)

t

su(SI)

t

h(SI)

ai14135

SCK Input

CPHA=1

MOSI

INPUT

MISO

OUT PUT

CPHA=1

MS B O U T

MSB IN

BI T6 O UT

LSB IN

LSB OUT

CPOL=0

CPOL=1

BIT1 IN

t

SU(NSS)

t

c(SCK)

t

h(NSS)

t

a(SO)

t

w(SCKH)

t

w(SCKL)

t

v(SO)

t

h(SO)

t

r(SCK)

t

f(SCK)

t

dis(SO)

t

su(SI)

t

h(SI)

NSS input

Figure 29. SPI1 timing diagram - slave mode and CPHA=0

Figure 30. SPI1 timing diagram - slave mode and CPHA=1

1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

DD

DD

.

(1)

82/102 Doc ID 023331 Rev 1

STM8L052C6 Electrical parameters

ai14136

SCK output

CPHA=0

MOSI

OUTUT

MISO

INP U T

CPHA=0

MSBIN

M SB OUT

BIT6 IN

LSB OUT

LSB IN

CPOL=0

CPOL=1

B I T1 OUT

NSS input

t

c(SCK)

t

w(SCKH)

t

w(SCKL)

t

r(SCK)

t

f(SCK)

t

h(MI)

High

SCK output

CPHA=1

CPHA=1

CPOL=0

CPOL=1

t

su(MI)

t

v(MO)

t

h(MO)

Figure 31. SPI1 timing diagram - master mode

(1)

1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

DD

DD

.

Doc ID 023331 Rev 1 83/102

Electrical parameters STM8L052C6

I2C - Inter IC control interface

Subject to general operating conditions for V

The STM8L I

2

C interface (I2C1) meets the requirements of the Standard I2C communication

DD

, f

SYSCLK

, and TA unless otherwise specified.

protocol described in the following table with the restriction mentioned below:

Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SDA and SCL).

Table 41. I2C characteristics

Symbol Parameter

t

w(SCLL)

t

w(SCLH)

t

su(SDA)

t

h(SDA)

t

r(SDA)

t

r(SCL)

t

f(SDA)

t

f(SCL)

t

h(STA)

t

su(STA)

t

su(STO)

t

w(STO:STA)

C

1. f

SYSCLK

Data based on standard I

2.

SCL clock low time 4.7 1.3

SCL clock high time 4.0 0.6

SDA setup time 250 100

SDA data hold time 0 0 900

SDA and SCL rise time 1000 300

SDA and SCL fall time 300 300

START condition hold time 4.0 0.6

Repeated START condition setup
time

STOP condition setup time 4.0 0.6 μs

STOP to START condition time (bus
free)

Capacitive load for each bus line 400 400 pF

b

must be at least equal to 8 MHz to achieve max fast I2C speed (400 kHz).

2

C protocol requirement, not tested in production.

Standard mode

I2C

(2)

Min

Max

(2)

Fast mode I

(2)

Min

4.7 0.6

4.7 1.3 μs

2C(1)

Max

(2)

Unit

μs

ns

μs

Note: For speeds around 200 kHz, the achieved speed can have a± 5% tolerance

For other speed ranges, the achieved speed can have a± 2% tolerance
The above variations depend on the accuracy of the external components used.

84/102 Doc ID 023331 Rev 1

STM8L052C6 Electrical parameters

REPEATED START

START

STOP

START

t

f(SDA)

t

r(SDA)

t

su(SDA)th(SDA)

t

f(SCL)

t

r(SCL)

t

w(SCLL)

t

w(SCLH)

t

h(STA)

t

su(STO)

t

su(STA)tw(STO:STA)

SDA

SCL

4.7kΩ
SDA

STM8L

SCL

V

DD

100Ω

100Ω

V

DD

4.7kΩ

I2CBUS

2

Figure 32.

Typical application with I

C bus and timing diagram

1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x V

1)

DD

Doc ID 023331 Rev 1 85/102

Electrical parameters STM8L052C6

8.3.9 LCD controller

In the following table, data is guaranteed by design. Not tested in production.

Table 42. LCD characteristics

Symbol Parameter Min Typ Max. Unit

V

LCD

V

LCD0

V

LCD1

V

LCD2

V

LCD3

V

LCD4

V

LCD5

V

LCD6

V

LCD7

C

EXT

I

DD

(2)

R

HN

(3)

R

LN

V

33

V

23

V

12

V

13

V

0

1. LCD enabled with 3 V internal booster (LCD_CR1 = 0x08), 1/4 duty, 1/3 bias, division ratio= 64, all pixels
active, no LCD connected.

2. RHN is the total high value resistive network.

3. RLN is the total low value resistive network.

High value resistive network (low drive) 6.6 MΩ

Low value resistive network (high drive) 360 kΩ

Segment/Common higher level voltage V

Segment/Common lowest level voltage 0 V

LCD external voltage 3.6 V

LCD internal reference voltage 0 2.6 V

LCD internal reference voltage 1 2.7 V

LCD internal reference voltage 2 2.8 V

LCD internal reference voltage 3 2.9 V

LCD internal reference voltage 4 3.0 V

LCD internal reference voltage 5 3.1 V

LCD internal reference voltage 6 3.2 V

LCD internal reference voltage 7 3.3 V

V

external capacitance 0.1 2 µF

LCD

Supply current

Supply current

Segment/Common 2/3 level voltage 2/3V

Segment/Common 1/2 level voltage 1/2V

Segment/Common 1/3 level voltage 1/3V

(1)

at VDD = 1.8 V

(1)

at VDD = 3 V 3 µA

3µA

LCDx

LCDx

LCDx

LCDx

V

V

V

V

VLCD external capacitor

The application can achieve a stabilized LCD reference voltage by connecting an external
capacitor C

86/102 Doc ID 023331 Rev 1

EXT

to the V

LCD

pin. C

is specified in Ta bl e 4 2 .

EXT

STM8L052C6 Electrical parameters

8.3.10 Embedded reference voltage

In the following table, data is based on characterization results, not tested in production,
unless otherwise specified.

Table 43. Reference voltage characteristics

Symbol Parameter Conditions Min Typ Max. Unit

I

REFINT

T

S_VREFINT

I

BUF

V

REFINT out

I

LPBUF

I

REFOUT

C

REFOUT

t

VREFINT

t

BUFEN

ACC

STAB

(1)(2)

(2)

(2)

(2)

(2)

VREFINT

VREFINT

Internal reference voltage
consumption

ADC sampling time when reading
the internal reference voltage

Internal reference voltage buffer
consumption (used for ADC)

Reference voltage output 1.202

Internal reference voltage low
power buffer consumption

Buffer output current

(4)

1.4 µA

510µs

13.5 25 µA

(3)

1.224 1.242

730 1200 nA

(3)

1µA

Reference voltage output load 50 pF

Internal reference voltage startup
time

Internal reference voltage buffer
startup time once enabled

Accuracy of V

REFINT

VREFINT_Factory_CONV byte

Stability of V

REFINT

(1)

stored in the

over

(5)

temperature

Stability of V

REFINT

over

temperature

-40 °C ≤ TA ≤
85 °C

0 °C ≤ TA ≤ 50

°C

23ms

10 µs

± 5 mV

20 50 ppm/°C

20 ppm/°C

V

STAB

VREFINT

1. Defined when ADC output reaches its final value ±1/2LSB

2. Data guaranteed by Design. Not tested in production.

3. Tested in production at V

4. To guaranty less than 1%

5. Measured at V

Stability of V
hours

= 3 V ±10 mV.

DD

V

REFOUT

= 3 V ±10 mV. This value takes into account VDD accuracy and ADC conversion accuracy.

DD

REFINT

deviation.

after 1000

Doc ID 023331 Rev 1 87/102

TBD ppm

Electrical parameters STM8L052C6

8.3.11 12-bit ADC1 characteristics

In the following table, data is guaranteed by design, not tested in production.

Table 44. ADC1 characteristics

Symbol Parameter Conditions Min Typ Max Unit

V

DDA

V

REF+

V

REF-

I

VDDA

I

VREF+

V

AIN

T

R

AIN

C

ADC

f

ADC

f

CONV

Analog supply voltage 1.8 3.6 V

Reference supply
voltage

Lower reference voltage

Current on the VDDA
input pin

2.4 V ≤ V

1.8 V ≤ V

≤ 3.6 V

DDA

≤ 2.4 V V

DDA

2.4

V

DDA

DDA

V

SSA

1000 1450 µA

700

Current on the VREF+
input pin

400

(peak)

450

(average)

Conversion voltage
range

Temperature range -40 85 °C

A

External resistance on
V

AIN

Internal sample and
hold capacitor

ADC sampling clock
frequency

on PF0 fast channel

on all other channels

on PF0 fast channel

on all other channels

2.4 V≤ V

DDA

≤ 3.6 V

without zooming

1.8 V≤ V

DDA

≤ 2.4 V

with zooming

V

on PF0 fast

AIN

channel

(2)

0

V

REF+

50

16 pF

0.320 16 MHz

0.320 8 MHz

(4)(5)

1

12-bit conversion rate

V

on all other

AIN

channels

760

(1)

(3)

(4)(5)

(1)

V

V

V

µA

µA

kΩ

MHz

kHz

f

TRIG

t

LAT

External trigger
frequency

External trigger latency 3.5 1/f

88/102 Doc ID 023331 Rev 1

t

conv

1/f

ADC

SYSCLK

STM8L052C6 Electrical parameters

Table 44. ADC1 characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

V

on PF0 fast

t

S

t

conv

t

WKUP

t

IDLE

t

VREFINT

Sampling time

12-bit conversion time

Wakeup time from OFF
state

Time before a new

(6)

conversion

Internal reference
voltage startup time

AIN

channel

< 2.4 V

V

DDA

on PF0 fast

V

AIN

channel

2.4 V ≤ V

on slow channels

V

AIN

V

DDA

V

on slow channels

AIN

2.4 V ≤ V

≤ 3.6 V

DDA

< 2.4 V

≤ 3.6 V

DDA

16 MHz 1

= +25 °C 1

T

A

T

= +70 °C 20

A

0.43

0.22

0.86

0.41

(4)(5)

(4)(5)

(4)(5)

(4)(5)

12 + t

(4)

S

µs

µs

µs

µs

1/f

ADC

µs

3µs

(7)

(7)

refer to

Ta bl e 4 3

s

ms

ms

1. The current consumption through V

- one constant (max 300 µA)

- one variable (max 400 µA), only during sampling time + 2 first conversion pulses.
So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 µA at
1Msps

2. V

3. Guaranteed by design, not tested in production.

4. Minimum sampling and conversion time is reached for maximum Rext = 0.5 kΩ.

5. Value obtained for continuous conversion on fast channel.

6. The time between 2 conversions, or between ADC ON and the first conversion must be lower than t

7. The t

REF-

or V

IDLE

must be tied to ground.

DDA

maximum value is ∞ on the “Z” revision code of the device.

is composed of two parameters:

REF

IDLE.

Doc ID 023331 Rev 1 89/102

Electrical parameters STM8L052C6

In the following three tables, data is guaranteed by characterization result, not tested in
production.

Table 45. ADC1 accuracy with V

Symbol Parameter Conditions Typ Max Unit

DNL Differential non linearity

INL Integral non linearity

TUE Total unadjusted error

Offset Offset error

Gain Gain error

= 3.3 V to 2.5 V

DDA

= 16 MHz 1 1.6

f

ADC

f

= 8 MHz 1 1.6

ADC

= 4 MHz 1 1.5

f

ADC

= 16 MHz 1.2 2

f

ADC

f

= 8 MHz 1.2 1.8

ADC

= 4 MHz 1.2 1.7

f

ADC

= 16 MHz 2.2 3.0

f

ADC

f

= 8 MHz 1.8 2.5

ADC

= 4 MHz 1.8 2.3

f

ADC

f

= 16 MHz 1.5 2

ADC

= 8 MHz 1 1.5

f

ADC

= 4 MHz 0.7 1.2

f

ADC

f

= 16 MHz

ADC

= 8 MHz

ADC

= 4 MHz

f

ADC

LSB

LSB

11.5f

Table 46. ADC1 accuracy with V

Symbol Parameter Typ Max Unit

DNL Differential non linearity 1 2 LSB

INL

TUE

Integral non linearity

Total unadjusted error

Offset Offset error 1 2 LSB

Gain Gain error 1.5 3 LSB

Table 47. ADC1 accuracy with V

Symbol Parameter Typ Max Unit

DNL Differential non linearity 1 2 LSB

INL

TUE

Integral non linearity

Total unadjusted error

Offset Offset error 2 3 LSB

Gain Gain error 2 3 LSB

= 2.4 V to 3.6 V

DDA

= V

DDA

REF+

= 1.8 V to 2.4 V

1.7 3 LSB

24LSB

23LSB

35LSB

90/102 Doc ID 023331 Rev 1

STM8L052C6 Electrical parameters

E

O

E

G

1LSB

IDEAL

(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line

E

T

=Total Unadjusted Error: maximum deviation

between the actual and the ideal transfer curves.

E

O

=Offset Error: deviation between the first actual

transition and the first ideal one.

E

G

=Gain Error: deviation between the last ideal

transition and the last actual one.

E

D

=Differential Linearity Error: maximum deviation

between actual steps and the ideal one.

E

L

=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.

4095

4094

4093

5

4

3

2

1

0

7

6

1234567

4093 4094 4095 4096

(1)

(2)

E

T

E

D

E

L

(3)

V

DDA

V

SSA

ai14395b

V

REF+

4096

(or depending on package)]

V

DDA

4096

[1LSB

IDEAL =

ai17090e

STM8L05xxx

V

DD

AINx

IL±50 nA

0.6 V

V

T

R

AIN

(1)

C

parasitic

V

AIN

0.6 V

V

T

R

ADC

C

ADC

(1)

12-bit

converter

Sample and hold ADC
converter

Figure 33. ADC1 accuracy characteristics

Figure 34. Typical connection diagram using the ADC

1. Refer to Ta b le 4 4 for the values of R

2. C

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

parasitic

pad capacitance (roughly 7 pF). A high C
this, f

should be reduced.

ADC

and C

AIN

Doc ID 023331 Rev 1 91/102

.

ADC

value will downgrade conversion accuracy. To remedy

parasitic

Electrical parameters STM8L052C6

ADC clock

Sampling (n cycles)

Conversion (12 cycles)

I

ref+

300µA

700µA

Figure 35. Maximum dynamic current consumption on V

supply pin during ADC

REF+

conversion

Table 48. R

Ts

(cycles)

AIN

Ts

(µs)

max for f

2.4 V < V

= 16 MHz

ADC

Slow channels Fast channels

< 3.6 V 1.8 V < V

DDA

4 0.25 Not allowed Not allowed 0.7 Not allowed

(1)

R

max (kohm)

AIN

< 2.4 V 2.4 V < V

DDA

< 3.3 V 1.8 V < V

DDA

DDA

< 2.4 V

9 0.5625 0.8 Not allowed 2.0 1.0

16 1 2.0 0.8 4.0 3.0

24 1.5 3.0 1.8 6.0 4.5

48 3 6.8 4.0 15.0 10.0

96 6 15.0 10.0 30.0 20.0

192 12 32.0 25.0 50.0 40.0

384 24 50.0 50.0 50.0 50.0

1. Guaranteed by design, not tested in production.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 36 or Figure 37,
depending on whether V

is connected to V

REF+

or not. Good quality ceramic 10 nF

DDA

capacitors should be used. They should be placed as close as possible to the chip.

92/102 Doc ID 023331 Rev 1

STM8L052C6 Electrical parameters

V

REF+

S

STM8L

V

DDA

V

SSA/VREF-

1 μF // 10 nF

F

1 μF // 10 nF

Supply

External

reference

ai17031b

V

REF+/VDDA

STM8L

1 μF // 10 nF

V

REF–/VSSA

ai17032b

Supply

Figure 36. Power supply and reference decoupling (V

// 10 n

Figure 37. Power supply and reference decoupling (V

not connected to V

REF+

TM8L

connected to V

REF+

DDA

DDA

)

)

Doc ID 023331 Rev 1 93/102

Electrical parameters STM8L052C6

8.3.12 EMC characteristics

Susceptibility tests are performed on a sample basis during product characterization.

Functional EMS (electromagnetic susceptibility)

Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).

● ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device

until a functional disturbance occurs. This test conforms with the IEC 61000 standard.

● FTB: A burst of fast transient voltage (positive and negative) is applied to V

through a 100 pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 61000 standard.

A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.

and VSS

DD

Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.

To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).

Table 49. EMS data

Symbol Parameter Conditions

V

= 3.3 V, TA = +25 °C,

DD

= 16 MHz,

f

CPU

conforms to IEC 61000

= 3.3 V, TA = +25 °C,

V

DD

= 16 MHz,

f

CPU

conforms to IEC 61000

V

FESD

V

EFTB

Voltage limits to be applied on
any I/O pin to induce a functional
disturbance

Fast transient voltage burst limits
to be applied through 100 pF on

and V

V

DD

functional disturbance

pins to induce a

SS

Using HSI

Using HSE 2B

Level/

Class

3B

4A

Electromagnetic interference (EMI)

Based on a simple application running on the product (toggling 2 LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm IEC61967-2 which specifies the board and the loading of each pin.

94/102 Doc ID 023331 Rev 1

STM8L052C6 Electrical parameters

Table 50. EMI data

Symbol Parameter Conditions

S

EMI

1. Not tested in production.

Peak level

(1)

V

DD

TA = +25 °C,
LQFP32
conforming to
IEC61967-2

= 3.6 V,

Monitored

frequency band

Max vs.

Unit

16 MHz

0.1 MHz to 30 MHz -3

dBμV30 MHz to 130 MHz 9

130 MHz to 1 GHz 4

SAE EMI Level 2 -

Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models
can be simulated: human body model and charge device model. This test conforms to the
JESD22-A114A/A115A standard.

Table 51. ESD absolute maximum ratings

Symbol Ratings Conditions

V

ESD(HBM)

V

ESD(CDM)

1. Data based on characterization results, not tested in production.

Electrostatic discharge voltage
(human body model)

Electrostatic discharge voltage
(charge device model)

= +25 °C

T

A

Maximum

(1)

value

2000

500

Static latch-up

● LU: 3 complementary static tests are required on 6 parts to assess the latch-up

performance. A supply overvoltage (applied to each power supply pin) and a current
injection (applied to each input, output and configurable I/O pin) are performed on each
sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,
refer to the application note AN1181.

Table 52. Electrical sensitivities

Symbol Parameter Class

LU Static latch-up class II

Unit

V

Doc ID 023331 Rev 1 95/102

Electrical parameters STM8L052C6

8.4 Thermal characteristics

The maximum chip junction temperature (T

) must never exceed the values given in

Jmax

Table 15: General operating conditions on page 55.

The maximum chip-junction temperature, T

, in degree Celsius, may be calculated using

Jmax

the following equation:

T

Jmax

= T

Amax

+ (P

Dmax

x ΘJA)

Where:

● T

● Θ

● P

● P

is the maximum ambient temperature in °C

Amax

is the package junction-to-ambient thermal resistance in °C/W

JA

is the sum of P

Dmax

is the product of I

INTmax

INTmax

DD

and P

I/Omax (PDmax

= P

INTmax

+ P

and VDD, expressed in Watts. This is the maximum chip

I/Omax

)

internal power.

● P

represents the maximum power dissipation on output pins

I/Omax

Where:
P

I/Omax =

taking into account the actual V

Σ (VOL*IOL) + Σ((VDD-VOH)*I OH),

and VOH/IOH of the I/Os at low and high level in

OL/IOL

the application.

Table 53. Thermal characteristics

Symbol Parameter Value Unit

Θ

JA

Thermal resistance junction-ambient
LQFP 48- 7 x 7 mm

(1)

65 °C/W

1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection
environment.

96/102 Doc ID 023331 Rev 1

STM8L052C6 Package characteristics

9 Package characteristics

9.1 ECOPACK

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

Doc ID 023331 Rev 1 97/102

Package characteristics STM8L052C6

5B_ME

L

A1 K

L1

D

"

"

ccc

$

D

D1

D3

E3

E1 E

24

25

36

37

b

48

1

Pin 1
identification

12

13

9.2 Package mechanical data

9.2.1 48-pin low profile quad flat 7x7mm package (LQFP48)

Figure 38. LQFP48 48-pin low profile quad flat package outline

1. Drawing is not to scale.

Table 54. LQFP48 48-pin low profile quad flat package, mechanical data

mm inches

(1)

Dim.

Min Typ Max Min Typ Max

A 1.6 0.063

A1 0.05 0.15 0.002 0.0059

A2 1.35 1.4 1.45 0.0531 0.0551 0.0571

b 0.17 0.22 0.27 0.0067 0.0087 0.0106

c 0.09 0.2 0.0035 0.0079

D 8.8 9 9.2 0.3465 0.3543 0.3622

D1 6.8 7 7.2 0.2677 0.2756 0.2835

D3 5.5 0.2165

E 8.8 9 9.2 0.3465 0.3543 0.3622

E1 6.8 7 7.2 0.2677 0.2756 0.2835

E3 5.5 0.2165

e 0.5 0.0197

L 0.45 0.6 0.75 0.0177 0.0236 0.0295

L1 1 0.0394

k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°

ccc 0.08 0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

98/102 Doc ID 023331 Rev 1

STM8L052C6 Package characteristics

9.70

5.80

7.30

12

24

0.20

7.30

1

37

36

1.20

5.80

9.70

0.30

25

1.20

0.50

5B_FP

1348

Figure 39. LQFP48 recommended footprint

1. Dimensions are in millimeters.

Doc ID 023331 Rev 1 99/102

Device ordering information STM8L052C6

STM8 L 052 C 6 T 6

Product class

STM8 microcontroller

Pin count

C = 48 pins

Example:

Sub-family type

052 = Ultra-low-power with LCD

Family type

L = Low power

Temperature range

6 = - 40 °C to 85 °C

Program memory size

6 = 32 Kbytes

Package

T = LQFP

10 Device ordering information

Figure 40. Medium density value line STM8L05xxx ordering information scheme

1. For a list of available options (e.g. memory size, package) and orderable part numbers

or for further information on any aspect of this device, please contact the ST sales
office nearest to you

100/102 Doc ID 023331 Rev 1