MAC
– 128-Kbyte Flash, 8-Kbyte RAM memory
– AES128 encryption accelerator
– Flexible ADC, SPI/UART/TWI serial
communications, and general-purpose
timers
– 24 highly configurable GPIOs with Schmitt
trigger inputs
■ Industry-leading ARM® Cortex™-M3
processor
– Leading 32-bit processing performance
– Highly efficient Thumb®-2 instruction set
– Operation at 6, 12 or 24 MHz
– Flexible nested vectored interrupt controller
■ Low power consumption, advanced
management
– RX Current (w/ CPU): 27 mA
– TX Current (w/ CPU, +3 dBm TX): 31 mA
– Low deep sleep current, with retained RAM
and GPIO: 400 nA/800 nA with/without
sleep timer
– Low-frequency internal RC oscillator for
low-power sleep timing
– High-frequency internal RC oscillator for
fast (100 µs) processor start-up from sleep
■ Exceptional RF performance
– Normal mode link budget up to 102 dB;
configurable up to 107 dB
– -99 dBm normal RX sensitivity;
configurable to -100 dBm (1% PER, 20
byte packet)
– +3 dB normal mode output power;
configurable up to +7 dBm
– Robust WiFi and Bluetooth coexistence
STM32W108HB
STM32W108CB
Data brief
■ Innovative network and processor debug
– Non-intrusive hardware packet trace
– Serial wire/JTAG interface
– Standard ARM debug capabilities: Flash
patch & breakpoint; data watchpoint &
trace; instrumentation trace macrocell
■ Application flexibility
– Single voltage operation: 2.1-3.6 V with
internal 1.8 V and 1.25 V regulators
– Optional 32.768 kHz crystal for higher timer
accuracy
– Low external component count with single
24 MHz crystal
– Support for external power amplifier
– Small 7x7 mm 48-pin QFN package or
6x6 mm 40-pin QFN package
Applications
■ Smart energy
■ Building automation and control
■ Home automation and control
■ Security and monitoring
■ ZigBee® Pro wireless sensor networking
■ RF4CE products and remote controls
■ 6LoWPAN and custom protocols
Table 1.Device summary
FeatureSTM32W108HBSTM32W108CB
Package40-pin QFN48-pin QFN
August 2009Doc ID 15851 Rev 11/20
For further information contact your local STMicroelectronics sales office.
www.st.com
20
DescriptionSTM32W108CB, STM32W108HB
1 Description
The STM32W is a fully integrated System-on-Chip that integrates a 2.4 GHz, IEEE
802.15.4-compliant transceiver, 32-bit ARM® Cortex™-M3 microprocessor, Flash and RAM
memory, and peripherals of use to designers of ZigBee-based systems.
The transceiver utilizes an efficient architecture that exceeds the dynamic range
requirements imposed by the IEEE 802.15.4-2003 standard by over 15 dB. The integrated
receive channel filtering allows for robust co-existence with other communication standards
in the 2.4 GHz spectrum, such as IEEE 802.11 and Bluetooth. The integrated regulator,
VCO, loop filter, and power amplifier keep the external component count low. An optional
high performance radio mode (boost mode) is software-selectable to boost dynamic range.
The integrated 32-bit ARM® Cortex™-M3 microprocessor is highly optimized for high
performance, low power consumption, and efficient memory utilization. Including an
integrated MPU, it supports two different modes of operation: System mode and Application
mode. The networking stack software runs in System mode with full access to all areas of
the chip. Application code runs in Application mode with limited access to the STM32W
resources; this allows for the scheduling of events by the application developer while
preventing modification of restricted areas of memory and registers. This architecture
results in increased stability and reliability of deployed solutions.
The STM32W has 128 Kbytes of embedded Flash memory and 8 Kbytes of integrated RAM
for data and program storage. The STM32W HAL software employs an effective wearleveling algorithm that optimizes the lifetime of the embedded Flash.
To maintain the strict timing requirements imposed by the ZigBee and IEEE 802.15.4-2003
standards, the STM32W integrates a number of MAC functions into the hardware. The MAC
hardware handles automatic ACK transmission and reception, automatic backoff delay, and
clear channel assessment for transmission, as well as automatic filtering of received
packets. A packet trace interface is also integrated with the MAC, allowing complete, nonintrusive capture of all packets to and from the STM32W.
The STM32W offers a number of advanced power management features that enable long
battery life. A high-frequency internal RC oscillator allows the processor core to begin code
execution quickly upon waking. Various deep sleep modes are available with less than 1 µA
power consumption while retaining RAM contents. To support user-defined applications, onchip peripherals include UART, SPI, TWI, ADC and general-purpose timers, as well as up to
24 GPIOs. Additionally, an integrated voltage regulator, power-on-reset circuit, and sleep
timer are available.
1.1 Development tools
Finally, the STM32W utilizes standard Serial Wire and JTAG interfaces for powerful software
debugging and programming of the ARM Cortex-M3 core. The STM32W integrates the
standard ARM system debug components: Flash Patch and Breakpoint (FPB), Data
Watchpoint and Trace (DWT), and Instrumentation Trace Macrocell (DWT).
Unless otherwise specified, all voltages are referenced to VSS.
2.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3Σ).
2.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
2V≤ V
tested.
≤ 3.6 V voltage range). They are given only as design guidelines and are not
DD
= 25 °C and TA = TAmax (given by
A
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated
2.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
2.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 2.
2.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 3.
Figure 2.Pin loading conditionsFigure 3.Pin input voltage
Stresses above the absolute maximum ratings listed in Table 2: Voltage characteristics,
Table 3: Current characteristics, and Table 4: Thermal characteristics may cause permanent
damage to the device. These are stress ratings only and functional operation of the device
at these conditions is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Table 2.Voltage characteristics
RatingsMin.Max.Unit
Regulator input voltage (VDD_PADS)-0.3+3.6V
Analog, Memory and Core voltage (VDD_24MHZ, VDD_VCO,
VDD_RF, VDD_IF, VDD_PADSA, VDD_MEM, VDD_PRE,
VDD_SYNTH, VDD_CORE)
Voltage on RF_P,N; RF_TX_ALT_P,N-0.3+3.6V
-0.3+2.0V
RF Input Power (for max level for correct packet reception see
Table 11: Receive characteristics) RX signal into a lossless balun
Voltage on any GPIO (PA[7:0], PB[7:0], PC[7:0]), SWCLK, nRESET,
VREG_OUT
-0.3
Voltage on BIAS_R, OSCA, OSCB-0.3
Table 3.Current characteristics
+15dBm
VDD_PADS
+0.3
VDD_PADSA
+0.3
SymbolRatings Max.Unit
I
VDD
I
VSS
Total current into VDD/V
Total current out of V
power lines (source)150
DDA
ground lines (sink)150
SS
Output current sunk by any I/O and control pin25
I
IO
Output current source by any I/Os and control pin− 25
Injected current on NRST pin± 5
I
INJ(PIN)
Injected current on HSE OSC_IN and LSE OSC_IN pins± 5
Injected current on any other pin± 5
ΣI
INJ(PIN)
Table 4.Thermal characteristics
Total injected current (sum of all I/O and control pins)± 25
Analog and memory input voltage
(VDD_24MHZ, VDD_VCO, VDD_RF,
–
VDD_IF, VDD_PADSA, VDD_MEM,
VDD_PRE, VDD_SYNTH)
–Core input voltage (VDD_CORE)1.181.251.32V
–Operating temperature range-40+85°C
f
HCLK
PCLK1
f
PCLK2
V
Internal AHB clock frequency0 72
Internal APB1 clock frequency0 36
Internal APB2 clock frequency0 72
Standard operating voltage23.6V
DD
Analog operating voltage
V
DDA
(ADC not used)
Analog operating voltage
Must be the same
potential as V
DD
(ADC used)
1.71.81.9V
MHzf
23.6
V
2.43.6
V
Backup operating voltage1.83.6V
BAT
Maximum power
Ambient temperature for 6 suffix
version
dissipation
Low power
dissipation
TA
Maximum power
Ambient temperature for 7 suffix
version
dissipation
Low power
dissipation
6 suffix version–40 105
J Junction temperature range
T
7 suffix version–40 125
2.3.2 Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
–40 85
°C
–40 105
–40 105
°C
–40 125
°C
6/20Doc ID 15851 Rev 1
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