ST STM1831 User Manual

Features

■ Voltage monitored on separate sense

input V

■

Factory-trimmed voltage thresholds in 100 mV
increments from 1.6 V to 5.7 V

■ ±2% voltage threshold accuracy

■ Operating voltage 1.6 V to 6.0 V

■ Open drain output

■ Low supply current of 0.8 µA (typ.)

■ Time delay programmable by external

capacitor

■ Power supply transient immunity

■ Available in SOT23-5 package

■ Operating temperature –40 to 85 °C

SEN

STM1831

Voltage detector with sense input

and external delay capacitor

SOT23-5

Applications

■ Microprocessor reset circuitry

■ Charge voltage monitors

■ Memory battery backup switch circuits

■ Power failure detection circuits

November 2010 Doc ID 18180 Rev 1 1/24

www.st.com

1

Contents STM1831

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2/24 Doc ID 18180 Rev 1

STM1831 List of tables

List of tables

Table 1. Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 3. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 4. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 5. SOT23-5 - 5-lead small outline transistor package mechanical data . . . . . . . . . . . . . . . . . 21

Table 6. STM1831 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 7. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Doc ID 18180 Rev 1 3/24

List of figures STM1831

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. SOT23-5 pin connections (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Application hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5. Timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 6. Supply current vs. sense voltage, V
Figure 7. Supply current vs. input voltage, V
Figure 8. Detect voltage vs. ambient temperature, V
Figure 9. Detect voltage vs. supply voltage, V
Figure 10. Hysteresis voltage vs. ambient temperature, V
Figure 11. C

pin sink current vs. supply voltage, V

D

Figure 12. Output voltage vs. sense voltage, V

on RST

is 100 kΩ, CD pin open . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 13. Output voltage vs. supply voltage, V

on RST

is 100 kΩ, CD pin open . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 14. Output current vs. supply voltage, V
Figure 15. Relative delay resistance vs. ambient temperature, V
Figure 16. Release delay time vs. delay capacitance, T
Figure 17. Detect delay time vs. delay capacitance, T
Figure 18. RST

Figure 19. RST

output leakage current vs. ambient temperature,

V

CC

= V

SEN

= V

= 6.0 V, CD pin open . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

OUT

output leakage current vs. output voltage, VCC = V

T

= 85 °C, CD pin open . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

A

Figure 20. Sense current vs. supply voltage, V
Figure 21. Sense current vs. ambient temperature, V

Figure 22. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 23. SOT23-5 - 5-lead small outline transistor package mechanical drawing . . . . . . . . . . . . . . 21

= 3.0 V, V

CC

= 1.9 V (RST asserted) . . . . . . . . . . . . . . . . . . . . . . 9

SEN

DET

= 2.4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

DET

= 0 V, VCD = 0.5 V . . . . . . . . . . . . . . . . . . . . 11

SEN

= 2.4 V, TA = 25 °C, external pull-up resistor

DET

= VCC, external pull-up resistor

SEN

= 0 V, V

SEN

= 25 °C. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

A

= 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

A

= 1.9 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

SEN

CC

= V

= 2.0 V . . . . . . . . . . . . . . . . . . . . . . . 9

DET

= 2.4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

= 2.4 V . . . . . . . . . . . . . . . . . . . . . . . . 11

DET

= 0.5 V. . . . . . . . . . . . . . . . . . . . . . . 13

RST

SEN

= 5 V, V

CC

SEN

= 6.0 V,

= 6 V, VCD = 0 V . . 13

SEN

= 5 V . . . . . . . . . . . . . . . . . . . . . . . . 16

4/24 Doc ID 18180 Rev 1

STM1831 Description

1 Description

The STM1831 is a voltage detector with very low current consumption. It monitors a voltage
on a separate input pin (V
down to 0 V. In addition, the delay of the output can be adjusted by an external capacitor.

Figure 1. Logic diagram

.

Table 1. Pin descriptions

Pin Type Name Function

), which is fully functional even if the monitored voltage goes

SEN

V

CC

V

SEN

C

STM1831

D

V

SS

RST

AM00700

1 Output open drain RST

2Power V

3Power V

4 Input V

5I/O C

Active-low reset output

Ground

SS

Supply voltage

CC

Sense voltage

SEN

Delay capacitor

D

Figure 2. SOT23-5 pin connections (top view)

RST

V

SS

V

CC

1

2

34

5

C

V

D

SEN

AM00852

Doc ID 18180 Rev 1 5/24

Description STM1831

1.1 Pin descriptions

See Figure 1 and Ta bl e 1 for a brief overview of the signals available on this device.

Power supply (VCC)

This pin is used to provide power to the device. A 0.1 µF decoupling ceramic capacitor is
recommended to be connected between the V
device as possible.

and VSS pins, as close to the STM1831

CC

Sense voltage input (V

Input voltage on this pin is monitored. When it drops below the threshold (V
output (RST
from V

) is asserted. If VCC is close to 0 V, internal logic disconnects the voltage divider

input in order to minimize I

SEN

SEN

)

), reset

DET

current (see Figure 3 and Figure 20).

SEN

Reset output (RST)

Reset output is asserted when the voltage on the V
(V

).

DET

The STM1831 has an open drain, active-low output which sinks current when the output is
asserted. Connect a pull-up resistor from RST

to any supply voltage up to 6 V (see

Figure 4). Select a resistor value large enough to register a logic low, and small enough to

register a logic high, while all of the input current and leakage paths connected to the reset
output line are being supplied. A 10 kΩ pull-up is sufficient in most applications.

The advantages of open drain output include the ability to connect more open drain outputs
in parallel (wired OR connections) as well as connecting the output to a power supply
voltage other than V

CC

.

input pin drops below the threshold

SEN

Delay capacitor (CD)

Capacitor CD determines the delay (tCD) between reset deassertion and the moment when
V

voltage exceeds the V

SEN

Any external leakage due to poor quality timing capacitors or excessive humidity may cause
a significant leakage current which extends the t
tracks between the C

pin and its respective timing capacitor should be as short as

D

possible, properly covered with solder mask and isolated from other tracks (especially V
by as great a distance as possible. Low-leakage timing capacitors (ceramic or film capacitor)
should be used.

threshold (see Figure 5 with calculations for more details).

DET

timing. To minimize this effect, the PCB

CD

SS

)

Leave C

6/24 Doc ID 18180 Rev 1

pin open if unused (i.e. tCD = 0 ms).

D

STM1831 Description

Figure 3. Block diagram

V

CC

V

SEN

Logic

R

1

R

2

R

3

C

D

Figure 4. Application hookup

Monitored

voltage

C

D

RST

R

CD

V

REF

V

SS

AM00853

V

SEN

V

CC

(1)

R

STM1831

C

D

V

RST

SS

1. External pull-up resistor is needed for open drain RST output. A 10 kΩ is sufficient in most applications.

Doc ID 18180 Rev 1 7/24

AM00699

Operation STM1831

2 Operation

The STM1831 voltage detector monitors system voltages from 1.6 V to 5.7 V in 100 mV
increments, has a voltage hysteresis (V
capacitor C

.

D

The STM1831 asserts a reset output (RST
(V

). The reset output stays asserted until VCC goes above the detect voltage with

DET

hysteresis (V

DET

+ V

). If the external capacitor is connected to the CD pin, the reset

HYS

output deassertion is adequately delayed (see Figure 5 with calculations below for more
details). Leave the C

pin open if unused (i.e. tCD = 0 ms).

D

Figure 5. Timing waveforms

V

SEN

V

DET

C

D

) and an output delay programmable by external

HYS

) whenever VCC goes below the detect voltage

V

+ V

DET

V

HYST

TCD

RST

t

t

t

The t

detect delay time

DET

release delay time (measured when external capacitor CD is disconnected)

REL

delay by external capacitor CD.

CD

delay can be calculated based on Equation 1:

CD

Equation 1

and considering R

Equation 2

t

DET

t

CD

= 2 MΩ (typ.) and V

CD

t

CD

R–

CDCD

TCD

1.39 106CD×× sF,()≅

t

+ t

REL

CD

V

TCD

⎛⎞

In 1

××=

--------------–

⎝⎠

V

CC

= 1.5 V (typ.) at VCC = 3.0 V:

AM00854

8/24 Doc ID 18180 Rev 1