40-volt, 3-amp, quad power half bridge
Features
Multipower BCD technology
Low input/output pulse width distortion
200 mΩ R
stage
CMOS-compatible logic inputs
Thermal protection
Thermal warning output
Undervoltage protection
Short-circuit protection
Description
The STA515W is a monolithic quad half-bridge
stage in Multipower BCD Technology. The device
can be used as a dual bridge or reconfigured, by
connecting pin CONFIG to pins VDD, as a single
bridge with double-current capability.
The device is designed, particularly, to be the
output stage of a stereo all-digital high-efficiency
amplifier. It is capable of delivering 10 W x
Table 1. Device summary
complementary DMOS output
dsON
STA515W
PowerSSO36 package
with exposed pad down
4 channels into 4-Ω loads with 10% THD at
V
= 18 V in single-ended configuration.
CC
It can also deliver 20 W + 20 W into 8-Ω loads
with 10% THD at V
or, in single parallel BTL configuration, 40 W into
a 8-Ω load with 10% THD at V
The input pins have a threshold proportional to
the voltage on pin VL.
The STA515W comes in a 36-pin PowerSSO
package with exposed pad down (EPD).
= 18 V in BTL configuration
CC
= 26 V.
CC
Order code Ambient temp. range Package Packaging
STA515W 0 to 70 °C PowerSSO36 EPD Tube
STA515W13TR 0 to 70 °C PowerSSO36 EPD Tape and reel
April 2010 Doc ID 11079 Rev 2 1/14
www.st.com
14
Introduction STA515W
1 Introduction
Figure 1. STA515W circuit for quad single-ended amplifiers
+3.3V
TH_WARN
C58
100nF
VCC1A
29
IN1A
IN1A
23
VL
24
CONFIG
25
PWRDNPWR_DN
R57
R59
100nF
C60
C58
100nF
10K
C53
IN1B
IN2A
IN2B
FAULT
TRISTATE
THWARN
IN1B
VDD
VDD
VSS
VSS
VCCSIG
VCCSIG
IN2A
GNDREG
GNDCLEAN
IN2B
GNDSUB
10K
100nF
27
26
28
30
21
22
33
34
35
36
31
20
19
32
1
PROTECTION
&
LOGIC
REGULATORS
M3
M2
M5
M4
M17
M15
M16
M14
15
17
16
14
12
11
10
13
7
8
9
6
4
3
2
5
D03AU1474bc
OUT1A
OUT1A
GND1A
VCC1B
OUT1B
OUT1B
GND1B
VCC2A
OUT2A
OUT2A
GND2A
VCC2B
OUT2B
OUT2B
GND2B
C81
100nF
C82
100nF
C83
100nF
C84
100nF
R61
5K
C31 820µF
C91
1µF
R62
5K
R63
C32 820µF
5K
C92
1µF
R64
5K
R65
C33 820µF
5K
C93
1µF
R66
5K
R67
C34 820µF
5K
C94
1µF
R68
5K
1µF
L11 22µH
C71
R41
100nF
20
C41
330pF
C51
C61
1µF
100nF
C42
330pF
C43
330pF
C52
C62
1µF
100nF
C44
330pF
R51
6
L12 22µH
C72
R42
100nF
20
R52
6
1µF
L13 22µH
C73
R43
100nF
20
R53
6
L14 22µH
C74
R44
100nF
20
R54
6
+V
CC
C21
2200µF
4Ω
4Ω
4Ω
4Ω
2/14 Doc ID 11079 Rev 2
STA515W Pin description
2 Pin description
Figure 2. Pin out
VCCSIG
VCCSIG
VSS
VSS
IN2B
IN2A
IN1B
IN1A
THWARN
FAU LT
TRISTATE
PWRDN
CONFIG
VL
VDD
VDD
GNDREG
GNDCLEAN
Table 2. Pin list
GNDSUB
OUT2B
OUT2B
VCC2B
GND2B
GND2A
VCC2A
OUT2A
OUT2A
OUT1B
OUT1B
VCC1B
GND1B
GND1A
VCC1A
OUT1A
OUT1A
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
STA515W
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
Pin Name Type Description
1 GNDSUB PWR Substrate ground
2, 3 OUT2B O Output half bridge 2B
4 VCC2B PWR Positive supply
5 GND2B PWR Negative supply
6 GND2A PWR Negative supply
7 VCC2A PWR Positive supply
8, 9 OUT2A O Output half bridge 2A
10, 11 OUT1B O Output half bridge 1B
12 VCC1B PWR Positive supply
13 GND1B PWR Negative supply
14 GND1A PWR Negative supply
15 VCC1A PWR Positive supply
16, 17 OUT1A O Output half bridge 1A
18 N.C. - No internal connection
19 GNDCLEAN PWR Logical ground
20 GNDREG PWR Ground for regulator V
DD
21, 22 VDD PWR 5-V regulator referred to ground
23 VL PWR High logical state setting voltage, V
Doc ID 11079 Rev 2 3/14
L
Pin description STA515W
Table 2. Pin list
Pin Name Type Description
Configuration pin:
24 CONFIG I
25 PWRDN I
26 TRISTATE I
27 FAULT O
28 THWARN O
29 IN1A I Input of half bridge 1A
30 IN1B I Input of half bridge 1B
0: normal operation
1: bridges in parallel, see Parallel-output and high-current
operation on page 9
Stand-by pin:
0: low-power mode
1: normal operation
Hi-Z pin:
0: all power amplifier outputs in high-impedance state
1: normal operation
Fault pin advisor (open-drain device, needs pull-up resistor):
0: fault detected (short circuit or thermal, for example)
1: normal operation
Thermal-warning advisor (open-drain device, needs pull-up
resistor):
o
0: temperature of the IC >130
C
1: normal operation
31 IN2A I Input of half bridge 2A
32 IN2B I Input of half bridge 2B
33, 34 VSS PWR 5-V regulator referred to +V
35, 36 VCCSIG PWR Signal positive supply
CC
4/14 Doc ID 11079 Rev 2
STA515W Electrical characteristics
3 Electrical characteristics
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
V
CC
V
max
T
op
P
tot
T
stg
Table 4. Recommended operating conditions
DC supply voltage (Pins 4, 7, 12, 15) 40 V
Maximum voltage on pins 23 to 32 5.5 V
Operating temperature range 0 to 70 °C
Power dissipation (Tcase = 70 °C) 21 W
, TjStorage and junction temperature -40 to 150 °C
Symbol Parameter Min Typ Max Unit
V
CC
V
L
T
amb
Table 5. Thermal data
DC supply voltage (Pins 4, 7, 12, 15) 10 - 36 V
Input logic reference 2.7 3.3 5.0 V
Ambient temperature 0 - 70 °C
Symbol Parameter Min Typ Max Unit
T
T
T
t
hSD
warn
j-case
jSD
Thermal resistance junction to case (thermal pad) - - 1.5 °C/W
Thermal shut-down junction temperature - 150 - °C
Thermal warning temperature - 130 - °C
Thermal shut-down hysteresis - 25 - °C
Unless otherwise stated, the test conditions for Ta bl e 6 below are VL = 3.3 V, VCC = 30 V,
R
=8Ω, fSW = 384 kHz and T
L
Table 6. Electrical characteristics
Symbol Parameter Test conditions Min Typ Max Unit
R
I
g
g
dsON
dss
N
P
Power P-channel/N-channel
MOSFET R
dsON
Power P-channel/N-channel
leakage Idss
Power P-channel R
matching
Power N-channel R
matching
Dt_s Low current dead time (static) see Figure 3 - 1020ns
= 25 °C
amb
= 1 A - 200 270 mΩ
I
dd
V
= 35 V --50µA
CC
dsON
dsON
= 1 A 95--%
I
dd
= 1 A 95--%
I
dd
Doc ID 11079 Rev 2 5/14
Electrical characteristics STA515W
Table 6. Electrical characteristics (continued)
Symbol Parameter Test conditions Min Typ Max Unit
Dt_d
t
d ON
t
d OFF
t
r
t
f
V
CC
V
IN-Low
V
IN-High
I
IN-H
I
IN-L
I
PWRDN-H
V
Low
High current dead time
(dynamic)
L = 22 µH, C = 470 nF
= 8 Ω, Idd = 3.0 A
R
L
see Figure 4
--50ns
Turn-on delay time Resistive load - - 100 ns
Turn-off delay time Resistive load - - 100 ns
Rise time
Fall time
Resistive load
see Figure 3
Resistive load
see Figure 3
--25ns
--25ns
Supply operating voltage - 10 - 36 V
Half-bridge input, low level
voltage
Half-bridge input, high level
voltage
-
-
High level input current VIN = V
-
VL / 2 +
300 mV
L
-1-µA
-
-
V
/ 2
L
300 mV
-
V
V
Low level input current VIN = 0.3 V - 1 - µA
High level PWRDN pin input
current
V
= 3.3 V - 35 - µA
L
Low logical state voltage
(pins PWRDN, TRISTATE)
VL = 3.3V --0.8V
(seeTa bl e 7 )
V
High
I
VCC-
PWRDN
I
FAULT
I
VCC-HiZ
I
VCC
I
OCP
V
UVP
t
pw_min
High logical state voltage
(pins PWRDN, TRISTATE)
VL = 3.3 V 1.7 - - V
(seeTa bl e 7 )
Supply current from VCC in
power down
V
= 0 V --3mA
PWRDN
Output current on pins
FAULT, THWARN with fault
= 3.3V -1-mA
V
pin
condition
Supply current from VCC in
3-state
V
TRISTATE
= 0 V - 22 - mA
Input pulse width
Supply current from VCC in
operation (both channels
switching)
= 50% duty,
switching frequency
= 384 kHz,
-50-mA
no LC filters
Overcurrent protection
threshold Isc (short circuit
- 36- A
current limit)
Undervoltage protection
threshold
--7-V
Output minimum pulse width No load 70 - 150 ns
6/14 Doc ID 11079 Rev 2
STA515W Electrical characteristics
Table 7. Threshold switching voltage variation with voltage on pin VL
Voltage on pin VL, V
L
V
max V
LOW
min Unit
HIGH
2.7 0.7 1.5 V
3.3 0.8 1.7 V
5.0 0.85 1.85 V
Table 8. Logic truth table
Pin
TRISTATE
Inputs as per Figure 4 Transistors as per Figure 4
Output mode
INxA INxB Q1 Q2 Q3 Q4
0 x x Off Off Off Off Hi Z
100OffOffOnOnDump
101OffOnOnOffNegative
110OnOffOffOnPositive
111OnOnOffOffNot used
Test circuits
Figure 3. Test circuit
OUTxY
Vcc
Low current dead time = MAX(DTr,DTf)
Duty cycle = 50%
INxY
gnd
+Vcc
OUTxY
R 8Ω
DTfDTr
+
-
(3/4)Vcc
(1/2)Vcc
(1/4)Vcc
t
vdc = Vcc/2
D03AU1458
Figure 4. Current dead time test circuit
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+V
CC
Duty cycle=A Duty cycle=B
DTin(A)
INA
Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure
Q1
Q3
OUTA
Iout=4.5A
DTout(A)
C69
470nF
Rload=8Ω
C71 470nF
DTout(B) DTin(B)
L68 22µL67 22µ
Iout=4.5A
C70
470nF
Q2
OUTB
Q4
INB
D03AU1517
Doc ID 11079 Rev 2 7/14
Applications information STA515W
4 Applications information
The STA515W is a dual channel H-bridge that can deliver 20 W per channel into 8 Ω with
10% THD at V
The STA515W converts both DDX and binary-logic-controlled PWM signals into audio
power at the load. It includes a logic interface, integrated bridge drivers, high efficiency
MOSFET outputs and thermal and short-circuit protection circuitry.
In DDX mode, two logic-level signals per channel are used to control the high-speed
MOSFET switches which drive the speaker load in a bridge configuration, according to the
damped ternary modulation operation.
In binary mode, both full-bridge and half-bridge modes are supported.
The STA515W includes overcurrent and thermal protection as well as an undervoltage
lockout with automatic recovery. A thermal warning status is also provided.
Figure 5. Block diagram for DDX or binary modes
= 18 V with high efficiency.
CC
INL[1,2]
INR[1,2]
VL
PWRDN
TRISTATE
FAU LT
THWARN
Logic
interface
and
decode
Protection
circuit
Regulators
Left
H-bridge
Right
H-bridge
Figure 6. Block diagram for binary half-bridge mode
INL[1,2]
INR[1,2]
VL
PWRDN
TRISTATE
FAU LT
THWARN
Logic
interface
and
decode
Protection
circuit
Regulators
Left A
bridge
Left B
bridge
Right A
bridge
Right B
bridge
OUTPL
OUTNL
OUTPR
OUTNR
OUTPL
OUTNL
OUTPR
OUTNR
Logic interface and decode
The STA515W power outputs are controlled using one or two logic-level timing signals. In
order to provide a proper logic interface, pin VL must operate at the same voltage as the
DDX control logic supply.
8/14 Doc ID 11079 Rev 2
STA515W Applications information
Protection circuits
The STA515W includes protection circuitry for overcurrent and thermal overload conditions.
A thermal warning pin (THWARN) is activated low (open-drain MOSFET) when the IC
temperature exceeds 130 °C, which is in advance of the thermal shutdown protection. When
a fault condition is detected an internal fault signal acts to immediately disable the output
power MOSFETs, placing both H-bridges in the high-impedance state. At the same time an
open-drain MOSFET connected to pin FAULT is switched on.
There are two possible modes subsequent to activating a fault:
z Shutdown mode:
with pins FAULT (with pull-up resistor) and TRISTATE independent, an activated fault
disables the device, signalling low at pin FAULT.
The device may subsequently be reset to normal operation by toggling pin TRISTATE
from high to low and back to high using an external logic signal.
z Automatic recovery mode:
This is shown in the applications circuit in Figure 7 and Figure 7 on page 10.
Pins FAULT and TRISTATE are shorted together and connected to a time constant
circuit comprising R59 and C58.
An activated fault forces a reset on pin TRISTATE causing normal operation to resume
following a delay determined by the time constant of the circuit.
If the fault condition is still present, the circuit operation continues, repeating until the
fault condition is removed.
An increase in the time constant of the circuit produces a longer recovery interval.
Care must be taken in the overall system design so as not to exceed the protection
thresholds under normal operation.
Power outputs
The STA515W power and output pins are duplicated to provide a low-impedance path for
the device bridged outputs. All duplicated power, ground and output pins must be connected
for proper operation.
Pins PWRDN or TRISTATE should be used to set all MOSFETS to the high-impedance
state during power-up and until the logic power supply, VL, has settled.
Parallel-output and high-current operation
When using DDX mode, the STA515W outputs can be connected in parallel to increase the
output current capability. In this configuration the device can provide 40 W into 8 Ω.
This mode of operation is enabled with pin CONFIG connected to VDD. The inputs must be
combined to give INLA = INLB and INRA = INRB, then the corresponding outputs can be
shorted together to give OUTLA = OUTLB and OUTRA = OUTRB.
Output filter
A passive 2nd-order filter is used on the STA515W power outputs to reconstruct an analog
audio signal. The system performance can be significantly affected by the output filter
design and choice of passive components.
Filter designs for 4-Ω and 8-Ω loads are shown in the applications circuits of Figure 1 on
page 2 for the half-bridge mode, and Figure 7 and Figure 8 on page 10 for the full bridge.
Doc ID 11079 Rev 2 9/14
Applications information STA515W
Applications circuits
Figure 7 below shows a typical full-bridge circuit for supplying 20 W + 20 W into 8-Ω
speakers with 10% THD at V
Figure 7. Typical stereo full-bridge configuration for 20 + 20 W
IN1A
+3.3V
TH_WARN
C58
100nF
IN1A
R57
R59
10K
10K
C58
100nF
IN1B
C53
100nF
C60
100nF
IN2A
GNDCLEAN
IN2B
CONFIG
PWRDNPWR_DN
FAULT
TRISTATE
THWARN
IN1B
VDD
VDD
VCCSIG
VCCSIG
IN2A
GNDREG
IN2B
GNDSUB
VSS
VSS
29
VL
23
24
25
27
26
28
30
21
22
33
34
35
36
31
20
19
32
1
CC
PROTECTION
&
LOGIC
REGULATORS
= 18 V.
M3
M2
M5
M4
M17
M15
M16
M14
VCC1A
15
C30
1µF
17
OUT1A
16
OUT1A
14
GND1A
12
VCC1B
OUT1B
OUT1B
GND1B
VCC2A
OUT2A
OUT2A
GND2A
VCC2B
OUT2B
OUT2B
GND2B
C32
220nF
C31
220nF
C31
220nF
11
10
13
7
8
9
6
4
3
2
5
L18 22µH
C52
330pF
R63
20
L19 22µH
L113 22µH
C109
330pF
R104
20
L112 22µH
D00AU1148Bbc
C20
100nF
R98
R100
C21
100nF
C110
100nF
R103
R102
C111
100nF
6
6
6
6
470nF
C101
100nF
C107
100nF
470nF
C106
100nF
C23
C108
C99
100nF
+V
CC
C55
1000µF
8Ω
8Ω
Figure 8 below shows a single-BTL configuration capable of supplying 40 W into a 4-Ω load
at 10% THD with V
= 19 V. This result was obtained with peak power for <1 s using the
CC
STA308+STA515W+STA50X demo board. A PWM modulator as driver is required.
Figure 8. Typical single-BTL configuration for 40 W
V
+3.3V
TH_WARN
10K
nPWR_DN
IN1A
IN1B
100nF
100nF
X7R
100nF
L
23 N.C.
GNDCLEAN
10K
100nF
X7R
100nF
X7R
Add.
GNDREG
CONFIG
THWARN
PWRDN
FAULT
TRISTATE
VCCSIG
VCCSIG
GNDSUB
VDD
VDD
IN1A
IN1B
IN2A
IN2B
VSS
VSS
19
20
21
22
24
28
25
27
26
29
30
31
32
33
34
35
36
1
18
17
OUT1A
16
OUT1A
11
OUT1B
10
OUT1B
OUT2A
9
OUT2A
8
OUT2B
3
OUT2B
2
VCC1A
15
VCC1B
12
VCC2A
7
VCC2B
4
GND1A
14
GND1B
13
GND2A
6
GND2B
5
10µH
22Ω
1/2W
330pF
10µH
1µF
X7R
220nF
1µF
X7R
220nF
D04AU1545bc
3.3
1/2W
3.3
1/2W
100nF
FILM
100nF
FILM
2200µF
63V
220nF
X7R
220nF
X7R
Vcc
Vcc
680nF
FILM
4Ω
10/14 Doc ID 11079 Rev 2
STA515W Package mechanical data
5 Package mechanical data
The STA515W comes in a 36-pin PowerSSO package with exposed pad down (EPD).
Figure 9 below shows the package outline and Ta bl e 9 gives the dimensions.
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
Table 9. PowerSSO36 EPD dimensions
Symbol
A 2.15 - 2.47 0.085 - 0.097
A2 2.15 - 2.40 0.085 - 0.094
a1 0.00 - 0.10 0.000 - 0.004
b 0.18 - 0.36 0.007 - 0.014
c 0.23 - 0.32 0.009 - 0.013
D 10.10 - 10.50 0.398 - 0.413
E 7.40 - 7.60 0.291 - 0.299
e - 0.5 - - 0.020 -
e3 - 8.5 - - 0.335 -
F - 2.3 - - 0.091 -
G- - 0.10 - - 0.004
H 10.10 - 10.50 0.398 - 0.413
h- - 0.40 - - 0.016
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
Dimensions in mm Dimensions in inches
Min Typ Max Min Typ Max
k 0 - 8 degrees 0 - 8 degrees
L 0.60 - 1.00 0.024 - 0.039
M - 4.30 - - 0.169 -
N - - 10 degrees - - 10 degrees
O - 1.20 - - 0.047 -
Q - 0.80 - - 0.031 -
S - 2.90 - - 0.114 -
T - 3.65 - - 0.144 -
U - 1.00 - - 0.039 -
X 4.10 - 4.70 0.161 - 0.185
Y 6.50 - 7.10 0.256 - 0.280
Doc ID 11079 Rev 2 11/14
12/14 Doc ID 11079 Rev 2
Figure 9. PowerSSO36 EPD outline drawing
h x 45°
Package mechanical data STA515W
STA515W Revision history
6 Revision history
Table 10. Document revision history
Date Revision Changes
Nov-2004 1 Initial release.
Added order code STA515W13TR
Modified Figure 1 on page 2
Reconstructed pin list in Table 2 on page 3 with information from
27-Apr-2010 2
former table 3 Functional pin status
Updated Vlow and Vhigh spec in Table 6 on page 5
Modified Figure 3 and Figure 4 on page 7
Updated applications circuits in Figure 7 and Figure 8 on page 10
Doc ID 11079 Rev 2 13/14
STA515W
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14/14 Doc ID 11079 Rev 2
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