ST STA381BW User Manual

STA381BW

2.1-channel high-efficiency digital audio system

Features

■ Wide-range supply voltage

– 4.5 V to 26 V (operating range)
– 30 V (absolute maximum rating)

2

■ I

C control with selectable device address

■ Embedded full IC protection

– Manufacturing short-circuit protection (out

vs. gnd, out vs. vcc, out vs. out)
– Thermal protection
– Overcurrent protection
– Undervoltage protection

■ 1 Vrms stereo analog input

2

■ I

S interface, sampling rate 32 kHz ~ 192 kHz,
with internal sampling frequency converter for
fixed processing frequency

■ Three output power stage configurations

– 2.0 mode, L/R full bridges
– 2.1 mode, L/R two half-bridges, subwoofer

full bridge

– 2.1 mode, L/R full bridges, PWM output for

external subwoofer amplifier

■ Driving load capabilities

– 2 x 20 W into 8 Ω ternary modulation
– 2 x 9 W into 4 Ω + 1 x 20 W into 8 Ω

■ FFX

■ Fixed output PWM frequency at any input

■ Embedded RMS meter for measuring real-time

■ Two analog outputs

■ New fully programmable noise-gating function

TM

100 dB dynamic range

sampling frequency

loudness

– Selectable headphone / line out driver with

adjustable gain via external resistors

–New F3X

TM

analog output

Sound Terminal

Datasheet − production data

VQFN48 (7 x 7 mm)

■ Headphone

– Embedded negative charge pump
– Full capless output configuration
– Driving load capabilities: 40 mW into 32 Ω

■ Line out

– 2 Vrms line output capability

■ Up to 12 user-programmable biquads with

noise-shaping technology

■ Direct access to coefficients through I

shadowing mechanism

■ Fixed (88.2 kHz / 96 kHz) internal processing

sampling rate

■ Two independent DRCs configurable as a

dual-band anticlipper or independent
limiters/compressors (B

■ Digital gain/att +48 dB to -80 dB with

2

DRC)

0.125 dB/step resolution

■ Independent (fade-in, fade-out) soft volume

update with programmable rate 48 ~ 1.5 dB/ms

■ Bass/treble tones control

■ Audio presets: 15 crossover filters,

5 anticlipping modes, nighttime listening mode

■ STSpeakerSafe

–Pre

- and post-processing DC blocking filters

TM

protection circuitry

– Checksum engine for filter coefficients
– PWM fault self-diagnosis

■ STCompressor

Table 1. Device summary

Order code Package Packing

STA381BW VQFN48 Tray

TM

dual-band DRC

2

C

®

STA381BWTR VQFN48 Tape and Reel

August 2012 Doc ID 018835 Rev 7 1/171

This is information on a product in full production.

www.st.com

1

Contents STA381BW

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.1 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.4 Electrical specifications for the digital section . . . . . . . . . . . . . . . . . . . . . 22

3.5 Electrical specifications for the power section . . . . . . . . . . . . . . . . . . . . . 23

3.6 Electrical specifications for the analog section . . . . . . . . . . . . . . . . . . . . . 24

4 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1 Processing data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2 Input oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.3 STCompressorTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.3.1 STC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.3.2 Band splitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.3.3 Level meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.3.4 Mapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.3.5 Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.3.6 Dynamic attack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.3.7 Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.3.8 Stereo link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.3.9 Programming of coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.3.10 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5I

2

C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.1.1 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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STA381BW Contents

5.1.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.1.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.1.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.3.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.3.2 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.4 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.4.1 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.4.2 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.4.3 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.4.4 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.4.5 Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.4.6 Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6 Register description: New Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6.1 CLK register (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.2 STATUS register (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.3 RESET register (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.4 Soft volume register (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.5 MVOL register (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.6 FINEVOL register (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.7 CH1VOL register (addr 0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.8 CH2VOL register (addr 0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.9 POST scaler register (addr 0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.10 OPER register (addr 0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.11 FUNCT register (addr 0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.11.1 Dual-band DRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.12 HPCFG register (addr 0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.13 Configuration register A (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.13.1 Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.13.2 Interpolation ratio selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.13.3 Fault-detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.14 Configuration register B (addr 0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6.14.1 Serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

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Contents STA381BW

6.14.2 Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.14.3 Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6.14.4 Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6.15 Configuration register C (addr 0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6.15.1 FFX compensating pulse size register . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6.16 Configuration register D (addr 0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6.16.1 DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6.16.2 Post-scale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6.16.3 Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6.16.4 Zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.16.5 Submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.17 Configuration register E (addr 0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.17.1 Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.17.2 AM mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.17.3 PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

6.17.4 Zero-crossing enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

6.18 Configuration register F (addr 0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

6.18.1 Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

6.18.2 Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . 65

6.18.3 LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.18.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.18.5 External amplifier power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.19 Volume control registers (addr 0x17 - 0x1B) . . . . . . . . . . . . . . . . . . . . . . 66

6.19.1 Mute/line output configuration register (addr 0x17) . . . . . . . . . . . . . . . . 66

6.19.2 Channel 3 / line output volume (addr 0x1B) . . . . . . . . . . . . . . . . . . . . . . 68

6.20 Audio preset registers (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.20.1 AM interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.20.2 Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.21 Channel configuration registers (addr 0x1F - 0x21) . . . . . . . . . . . . . . . . . 70

6.21.1 Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.21.2 EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.21.3 Volume bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.21.4 Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.21.5 Limiter select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.21.6 Output mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.22 Tone control register (addr 0x22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

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STA381BW Contents

6.22.1 Tone control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.23 Dynamic control registers (addr 0x23 - 0x26 / addr 0x43 - 0x46) . . . . . . 73

6.23.1 Limiter 1 attack/release rate (L1AR addr 0x23) . . . . . . . . . . . . . . . . . . . 73

6.23.2 Limiter 1 attack/release threshold (L1ATRT addr 0x24) . . . . . . . . . . . . . 73

6.23.3 Limiter 2 attack/release rate ( L2AR addr 0x25) . . . . . . . . . . . . . . . . . . 73

6.23.4 Limiter 2 attack/release threshold ( L2 ATRT addr 0x26) . . . . . . . . . . . . 73

6.23.5 Limiter 1 extended attack threshold (addr 0x43) . . . . . . . . . . . . . . . . . . 77

6.23.6 Limiter 1 extended release threshold (addr 0x44) . . . . . . . . . . . . . . . . . 77

6.23.7 Limiter 2 extended attack threshold (addr 0x45) . . . . . . . . . . . . . . . . . . 78

6.23.8 Limiter 2 extended release threshold (addr 0x46) . . . . . . . . . . . . . . . . . 78

6.24 User-defined coefficient control registers (addr 0x27 - 0x37) . . . . . . . . . . 78

6.24.1 Coefficient address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

6.24.2 Coefficient b1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 78

6.24.3 Coefficient b1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

6.24.4 Coefficient b1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

6.24.5 Coefficient b2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.24.6 Coefficient b2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.24.7 Coefficient b2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.24.8 Coefficient a1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.24.9 Coefficient a1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.24.10 Coefficient a1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.24.11 Coefficient a2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.24.12 Coefficient a2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6.24.13 Coefficient a2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6.24.14 Coefficient b0 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6.24.15 Coefficient b0 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6.24.16 Coefficient b0 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6.24.17 Coefficient write/read control register . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6.24.18 User-defined EQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

6.24.19 Pre-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

6.24.20 Post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

6.25 Fault-detect recovery constant registers (addr 0x3C - 0x3D) . . . . . . . . . . 85

6.26 Extended configuration register (addr 0x47) . . . . . . . . . . . . . . . . . . . . . . 85

6.26.1 Extended post-scale range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6.26.2 Extended attack rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6.26.3 Extended biquad selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

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Contents STA381BW

6.27 PLL configuration registers

(address 0x52; 0x53; 0x54; 0x55; 0x56; 0x57) . . . . . . . . . . . . . . . . . . . . 87

6.28 Short-circuit protection mode registers SHOK (address 0x58) . . . . . . . . 89

6.29 Extended coefficient range up to -4...4 (address 0x5A) . . . . . . . . . . . . . . 90

6.30 Miscellaneous registers (address 0x5C, 0x5D) . . . . . . . . . . . . . . . . . . . . 91

6.30.1 Rate power-down enable (RPDNEN) bit . . . . . . . . . . . . . . . . . . . . . . . . 91

6.30.2 Bridge immediately off (BRIDGOFF) bit (address 0x4B, bit D5) . . . . . . 91

6.30.3 Channel PWM enable (CPWMEN) bit . . . . . . . . . . . . . . . . . . . . . . . . . . 92

6.30.4 External amplifier hardware pin enabler (LPDP, LPD LPDE) bits . . . . . 92

6.30.5 Power-down delay selector (PNDLSL[2:0]) bits . . . . . . . . . . . . . . . . . . . 92

6.30.6 Short-circuit check enable bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

6.31 Bad PWM detection registers (address 0x5E, 0x5F, 0x60) . . . . . . . . . . . 93

6.32 Enhanced zero-detect mute and input level measurement

(address 0x61-0x65, 0x3F, 0x40, 0x6F) . . . . . . . . . . . . . . . . . . . . . . . . . . 94

6.33 Headphone/Line out configuration register (address 0x66) . . . . . . . . . . . 96

6.34 F3XCFG (address 0x69; 0x6A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

6.35 STCompressorTM configuration register (address 0x6B; 0x6C) . . . . . . . 98

6.36 Charge pump synchronization (address 0x70) . . . . . . . . . . . . . . . . . . . . . 98

6.37 Coefficient RAM CRC protection (address 0x71-0x7D) . . . . . . . . . . . . . . 99

6.38 MISC4 (address 0x7E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

7 Register description: Sound Terminal compatibility . . . . . . . . . . . . . 103

7.1 Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

7.1.1 Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

7.1.2 Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

7.1.3 Fault-detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

7.2 Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

7.2.1 Serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

7.2.2 Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

7.2.3 Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

7.2.4 Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

7.2.5 Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

7.3 Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

7.3.1 FFX compensating pulse size register . . . . . . . . . . . . . . . . . . . . . . . . . 112

7.4 Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

7.4.1 DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

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7.4.2 Post-scale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

7.4.3 Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

7.4.4 Zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

7.4.5 Submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

7.5 Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

7.5.1 Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

7.5.2 AM mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

7.5.3 PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

7.5.4 Zero-crossing enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

7.5.5 Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

7.6 Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

7.6.1 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

7.6.2 Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

7.6.3 Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . 121

7.6.4 LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

7.6.5 IC power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

7.6.6 External amplifier power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

7.7 Volume control registers (addr 0x06 - 0x0A) . . . . . . . . . . . . . . . . . . . . . 122

7.7.1 Mute/line output configuration register . . . . . . . . . . . . . . . . . . . . . . . . . 122

7.7.2 Master volume register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

7.7.3 Channel 1 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

7.7.4 Channel 2 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

7.7.5 Channel 3 / line output volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

7.8 Audio preset registers (addr 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

7.8.1 Audio preset register (addr 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

7.8.2 AM interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . 125

7.8.3 Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

7.9 Channel configuration registers (addr 0x0E - 0x10) . . . . . . . . . . . . . . . . 126

7.9.1 Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

7.9.2 EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

7.9.3 Volume bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

7.9.4 Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

7.9.5 Limiter select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

7.9.6 Output mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

7.10 Tone control register (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

7.10.1 Tone control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

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7.11 Dynamic control registers (addr 0x12 - 0x15) . . . . . . . . . . . . . . . . . . . . 129

7.11.1 Limiter 1 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

7.11.2 Limiter 1 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

7.11.3 Limiter 2 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

7.11.4 Limiter 2 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

7.11.5 Limiter 1 extended attack threshold (addr 0x32) . . . . . . . . . . . . . . . . . 133

7.11.6 Limiter 1 extended release threshold (addr 0x33) . . . . . . . . . . . . . . . . 133

7.11.7 Limiter 2 extended attack threshold (addr 0x34 . . . . . . . . . . . . . . . . . ) 134

7.11.8 Limiter 2 extended release threshold (addr 0x35) . . . . . . . . . . . . . . . . 134

7.12 User-defined coefficient control registers (addr 0x16 - 0x26) . . . . . . . . . 134

7.12.1 Coefficient address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

7.12.2 Coefficient b1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . 134

7.12.3 Coefficient b1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . 134

7.12.4 Coefficient b1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

7.12.5 Coefficient b2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . 135

7.12.6 Coefficient b2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . 135

7.12.7 Coefficient b2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

7.12.8 Coefficient a1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . 135

7.12.9 Coefficient a1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . 135

7.12.10 Coefficient a1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

7.12.11 Coefficient a2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . 135

7.12.12 Coefficient a2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . 136

7.12.13 Coefficient a2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

7.12.14 Coefficient b0 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . 136

7.12.15 Coefficient b0 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . 136

7.12.16 Coefficient b0 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

7.12.17 Coefficient write/read control register . . . . . . . . . . . . . . . . . . . . . . . . . 136

7.12.18 User-defined EQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

7.12.19 Pre-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

7.12.20 Post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

7.13 Fault-detect recovery constant registers (addr 0x2B - 0x2C) . . . . . . . . . 141

7.14 Device status register (addr 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

7.15 EQ coefficients configuration register (addr 0x31) . . . . . . . . . . . . . . . . . 141

7.16 Extended configuration register (addr 0x36) . . . . . . . . . . . . . . . . . . . . . 142

7.16.1 Dual-band DRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

7.16.2 Extended post-scale range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

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7.16.3 Extended attack rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

7.16.4 Extended BIQUAD selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

7.17 EQ soft volume configuration registers (addr 0x37 - 0x38) . . . . . . . . . . 145

7.18 Extra volume resolution configuration registers (address 0x3F; 0x40) . . 146

7.19 PLL configuration registers

(address 0x41; 0x42; 0x43; 0x44; 0x45; 0X46) . . . . . . . . . . . . . . . . . . . 147

7.20 Short-circuit protection mode registers SHOK (address 0x47) . . . . . . . 149

7.21 Extended coefficient range up to -4...4 (address 0x49, 0x4A) . . . . . . . . 151

7.22 Miscellaneous registers (address 0x4B, 0x4C) . . . . . . . . . . . . . . . . . . . 151

7.22.1 Rate power-down enable (RPDNEN) bit (address 0x4B, bit D7) . . . . . 151

7.22.2 Bridge immediately off (BRIDGOFF) bit (address 0x4B, bit D5) . . . . . 152

7.22.3 Channel PWM enable (CPWMEN) bit (address 0x4B, bit D2) . . . . . . . 152

7.22.4 External amplifier hardware pin enabler (LPDP, LPD LPDE) bits

(address 0x4C, bit D7, D6, D5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

7.22.5 Power-down delay selector (PNDLSL[2:0]) bits

(address 0x4C, bit D4, D3, D2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

7.22.6 Short-circuit check enable bit (address 0x4C, bit D0) . . . . . . . . . . . . . 153

7.23 Bad PWM detection registers (address 0x4D, 0x4E, 0x4F) . . . . . . . . . . 154

7.24 Enhanced zero-detect mute and input level measurement

(address 0x50-0x54, 0x2E, 0x2F and 0x5E) . . . . . . . . . . . . . . . . . . . . . 155

7.25 Headphone/Line out configuration register (address 0x55) . . . . . . . . . . 157

7.26 F3XCFG (address 0x58; 0x59) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

7.27 STCompressorTM configuration register (address 0x5A; 0x5B) . . . . . . 159

7.28 Charge pump synchronization (address 0x5F) . . . . . . . . . . . . . . . . . . . 160

7.29 Coefficient RAM CRC protection (address 0x60-0x6C) . . . . . . . . . . . . . 161

7.30 MISC3 (address 0x6E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

7.31 MISC4 (address 0x7E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

8 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

8.1 Application schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

8.2 Headphone and 2 Vrms line out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

8.3 Typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

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List of tables STA381BW

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 5. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 6. Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 7. Electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 8. Electrical specifications for the analog section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 9. Coefficients extended-range configuration 0x74h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 10. Compressor ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 11. Conversion example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 12. STC coefficients memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 13. STC band splitter filters memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 14. Default register map table: NEW MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 15. CLK register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 16. STATUS register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 17. RESET register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 18. Soft volume register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 19. Master volume register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 20. Fine volume register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 21. Channel 1 volume register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 22. Channel 2 volume register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 23. OPER register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 24. OPER configuration selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 25. FUNCT register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 26. HPCFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 27. Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 28. Input sampling rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 29. Internal interpolation ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 30. IR bit settings as a function of the input sampling rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 31. Fault-detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 32. Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 33. Support serial audio input formats for MSB-first (SAIFB = 0) . . . . . . . . . . . . . . . . . . . . . . . 60

Table 34. Supported serial audio input formats for LSB-first (SAIFB = 1) . . . . . . . . . . . . . . . . . . . . . 61

Table 35. Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 36. Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 37. FFX compensating pulse size bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 38. Compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 39. DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 40. Post-scale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 41. Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 42. Zero-detect mute enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 43. Submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 44. Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 45. AM mode enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 46. PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 47. Zero-crossing enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 48. Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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Table 49. Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 50. LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 51. IC power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 52. External amplifier power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 53. Line output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 54. Mute configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 55. Channel 3 volume as a function of CH3VOL[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 56. AM interference frequency switching bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 57. Audio preset AM switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 58. Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 59. Bass management crossover frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 60. Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 61. EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 62. Volume bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 63. Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 64. Channel limiter mapping as a function of C3LS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 65. Channel output mapping as a function of C3OM bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 66. Tone control boost/cut as a function of BTC and TTC bits . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 67. Limiter attack rate as a function of LxA bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 68. Limiter release rate as a function of LxR bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 69. Limiter attack threshold as a function of LxAT bits (AC mode) . . . . . . . . . . . . . . . . . . . . . . 76

Table 70. Limiter release threshold as a function of LxRT bits (AC mode). . . . . . . . . . . . . . . . . . . . . 76

Table 71. Limiter attack threshold as a function of LxAT bits (DRC mode) . . . . . . . . . . . . . . . . . . . . 77

Table 72. Limiter release threshold as a function of LxRT bits (DRC mode) . . . . . . . . . . . . . . . . . . . 77

Table 73. RAM block for biquads, mixing, scaling and bass management. . . . . . . . . . . . . . . . . . . . . 84

Table 74. Extended post-scale range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 75. Extended attack rate, limiter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 76. Extended attack rate, limiter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 77. Extended biquad selector, biquad 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 78. Extended biquad selector, biquad 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 79. Extended biquad selector, biquad 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 80. PLL factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 81. PLL register 0x54 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 82. PLL register 0x55 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 83. PLL register 0x56 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 84. PLL register 0x57 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 85. Coefficients extended range configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 86. External amplifier enabler configuration bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 87. PNDLSL bits configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 88. Zero-detect threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 90. Manual threshold register 0x3F, 0x40 and 0x6F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 89. Zero-detect hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 91. Headphone/Line out configuration bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 92. F3X configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 93. F3X configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 94. Register STCCFG0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 95. STCCFG0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 96. Register STCCFG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 97. STCCFG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 98. Charge pump sync configuration bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 99. Misc register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 100. I

2

C registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

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List of tables STA381BW

Table 101. Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 102. Input sampling rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 103. Internal interpolation ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 104. IR bit settings as a function of the input sampling rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 105. Fault-detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 106. Serial audio input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 107. Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 108. Support serial audio input formats for MSB-first (SAIFB = 0) . . . . . . . . . . . . . . . . . . . . . . 109

Table 109. Supported serial audio input formats for LSB-first (SAIFB = 1) . . . . . . . . . . . . . . . . . . . . 110

Table 110. Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 111. Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 112. FFX compensating pulse size bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 113. Compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 114. DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 115. Post-scale link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 116. Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 117. Zero-detect mute enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 118. Submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 119. Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 120. AM mode enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 121. PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 122. Zero-crossing enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 123. Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 124. Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 125. Output configuration engine selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 126. Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 127. Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 128. LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 129. IC power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 130. External amplifier power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 131. Line output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 132. Mute configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 133. Master volume offset as a function of MVOL[7:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 134. Channel volume as a function of CxVOL[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 135. AM interference frequency switching bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 136. Audio preset AM switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 137. Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 138. Bass management crossover frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 139. Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 140. EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 141. Volume bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 142. Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 143. Channel limiter mapping as a function of CxLS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 144. Channel output mapping as a function of CxOM bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 145. Tone control boost/cut as a function of BTC and TTC bits . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 146. Limiter attack rate as a function of LxA bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 147. Limiter release rate as a function of LxR bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 148. Limiter attack threshold as a function of LxAT bits (AC mode) . . . . . . . . . . . . . . . . . . . . . 132

Table 149. Limiter release threshold as a function of LxRT bits (AC mode). . . . . . . . . . . . . . . . . . . . 132

Table 150. Limiter attack threshold as a function of LxAT bits (DRC mode) . . . . . . . . . . . . . . . . . . . 133

Table 151. Limiter release threshold as a function of LxRT bits (DRC mode) . . . . . . . . . . . . . . . . . . 133

Table 152. RAM block for biquads, mixing, scaling and bass management. . . . . . . . . . . . . . . . . . . . 140

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Table 153. Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Table 154. Extended post-scale range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Table 155. Extended attack rate, limiter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 156. Extended attack rate, limiter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 157. Extended biquad selector, biquad 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 158. Extended biquad selector, biquad 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 159. Extended biquad selector, biquad 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 160. Soft volume update enable, increase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Table 161. Soft volume update enable, decrease . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Table 162. Volume fine-tuning steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Table 163. Extra volume resolution enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Table 164. PLL factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Table 165. PLL register 0x43 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Table 166. PLL register 0x44 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Table 167. PLL register 0x45 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Table 168. PLL register 0x46 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Table 169. Coefficients extended range configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 170. External amplifier enabler configuration bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 171. PNDLSL bits configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 172. Zero-detect threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Table 173. Zero-detect hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Table 174. Manual threshold register 0x2E, 0x2F and 0x5E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Table 175. Headphone/Line out configuration bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Table 176. F3X configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Table 177. F3X configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Table 178. STCompressorTM configuration bits1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Table 179. STCompressorTM configuration bits 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Table 180. Charge pump sync configuration bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Table 181. Misc register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 182. MISC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 183. VQFN48 (7 x 7 x 0.9 mm) package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Table 184. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

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List of figures STA381BW

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 2. Pin connections VQFN48 (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 3. Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 4. Processing path, first part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 5. Processing path, second part: 2.1 output with individually configurable anticlipper/DRCs. 26
Figure 6. Processing path, second part: 2.0 output with B
Figure 7. Processing path, second part: 2.1 output configuration with STCompressor
Figure 8. STCompressor

Figure 9. Band splitter with 4th order filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 10. STCompressor
Figure 11. STCompressor

TM

block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

TM

behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

TM

behavior as a limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 12. Offset effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 13. Stereo link block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 14. Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 15. Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 16. OPER = 00 (default value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 17. OPER = 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 18. OPER = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 19. OPER = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 20. Output mapping scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 21. 2.0 channels (OPER = 00) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 22. 2.1 channels (OPER = 11) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 23. 2.1 channels (OPER = 10) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 24. B

2

DRC scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 25. Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 26. Short-circuit detection timing diagram (no short detected) . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 27. Alternate function for INTLINE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 28. Coefficients direct access single-write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 29. Coefficients direct access multiple-write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 30. Coefficients direct access single-read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 31. OCFG = 00 (default value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 32. OCFG = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 33. OCFG = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 34. OCFG = 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 35. Output mapping scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 36. 2.0 channels (OCFG = 00) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 37. 2.1 channels (OCFG = 01) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 38. 2.1 channels (OCFG = 10) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 39. Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 40. B

2

DRC scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Figure 41. Extra resolution volume scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Figure 42. Short-circuit detection timing diagram (no short detected) . . . . . . . . . . . . . . . . . . . . . . . . 150

Figure 43. Alternate function for INTLINE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Figure 44. External audio source to line/headphone out application scheme . . . . . . . . . . . . . . . . . . 164

Figure 45. F3X (from SAI) source to line/headphone out application scheme. . . . . . . . . . . . . . . . . . 165

Figure 46. F3X auxiliary analog output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Figure 47. Headphone and line out block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Figure 48. Output configuration for stereo BTL mode in filterlight configuration . . . . . . . . . . . . . . . . 167

2

DRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

TM

. . . . . . . . . 27

14/171 Doc ID 018835 Rev 7

STA381BW List of figures

Figure 49. VQFN48 (7 x 7 x 0.9 mm) package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Doc ID 018835 Rev 7 15/171

Description STA381BW

1 Description

The STA381BW is an integrated solution embedding digital audio processing, digital
amplification, FFX
the Sound Terminal

TM

power output stage, headphone and 2 Vrms line outputs. It is part of

®

family and provides full digital audio streaming from the source to the

speaker, offering cost effectiveness, low power dissipation and sound enrichment.

The STA381BW input section consists of a flexible digital input serial audio interface,
feeding the digital processing unit, and an analog 1 Vrms input for a seamless connection
with pure analog sources. The serial audio data input interface supports many formats,
including the popular IIS format.

The STA381BW is based on an FFX
technology from STMicroelectronics. FFX

TM

(Fully Flexible Amplification) processor, proprietary

TM

is the evolution of the ST ternary technology:
the advanced processor is available for ternary, binary, binary differential and phase shift
PWM modulation. The STA381BW embeds the ternary, binary and binary differential
implementations, a subset of the full capability of the FFX

TM

processor.

The STA381BW power section consists of four independent half-bridges. These can be
configured via digital control to operate in different modes. A 2.1-channel setup can be
implemented with two half-bridges (L/R) together with a single full-bridge (subwoofer).
Alternatively, the 2.0-channel setup can be done with two full-bridges. When using this
configuration, an external amplifier for the SW channel can also be driven through the PWM
output. The STA381BW is able to deliver 2 x 20 W (ternary) into an 8 Ω load at 18 V or
2 x 9 W (binary) into a 4 Ω load, plus 1 x 20 W (ternary) into an 8 Ω load at 18 V.

The STA381BW also provides a capless headphone out (with embedded negative charge
pump), able to deliver up to 40 mW into a 32 Ω load or, alternatively, can be configured as a
2 Vrms line output.

The STA381BW digital processing unit includes up to 12 programmable biquads (EQs),
allowing perfect sound equalization and offering advanced noise-shaping techniques.
Moreover, the coefficient range ensures a great variety of filter shapes (low/high-pass,
low/high shelf, peak, notch, band-pass). The equalization engine is fully compatible with the
ST speaker compensation technology embedded into the APWorkbench suite. A state-of­the-art multi-band DRC, STCompressor
protection with full audio quality preservation against sudden sound peaks. Moreover,
STSpeakerSafe

TM

technology offers reliable speaker protection under any condition. The

TM

equalizes the system to provide active speaker

master clock can be from stable BICKI (64xfs, 50% duty cycle) or external XTI.

16/171 Doc ID 018835 Rev 7

STA381BW Description

1.1 Block diagram

Figure 1. Block diagram

Doc ID 018835 Rev 7 17/171

Pin connections STA381BW

2 Pin connections

2.1 Connection diagram

Figure 2. Pin connections VQFN48 (top view)

SDI

VDDDIG2

GNDDIG2

48

47

TESTMODESASCL

46

45

44

SDA

43

INTLINE

42

PWDN

41

RESET

40

LRCKI

BICKI

39

38

37

VCC_REG

VSS_REG

OUT2B

GND2

VCC2

OUT2A

OUT1B

VCC1

GND1

OUT1A

VDD_REG

GND_REG

1

2

3

4

5

6

7

8

9

10

11

12

13

14

F3XL

F3X_FILT

STA 381BW

15

16

17

F3XR

LINEINL

LINEINR

18

19

LINEHPOUT_L

LINEHPOUT_R

20

GNDA

21

22

VDD3V3

SOFTMUTE

23

CPVSS

24

CPM

36

MCLK

AGNDPLL

35

VREGFILT

34

33

TWARN/FFX4A

32

EAPD/FFX4B

FFX3B

31

30

FFX3A

29

GNDDIG1

28

VDDDIG1

27

VDD3V3CHP

26

CPP

25

GNDPSUB

18/171 Doc ID 018835 Rev 7

STA381BW Pin connections

2.2 Pin description

Table 2. Pin list

VQFN 48-pin Name Type Description

1 VCC_REG POWER VCC reg

2 VSS_REG POWER Vss reg, VCC_REG-3.3 V

3 OUT2B OUTPUT Half-bridge 2B output

4 GND2 POWER Half-bridge 2A and 2B ground

5 VCC2 POWER Half-bridge 2A and 2B supply

6 OUT2A OUTPUT Half-bridge 2A output

7 OUT1B OUTPUT Half-bridge 1B output

8 VCC1 POWER Half-bridge 1A and 1B supply

9 GND1 POWER Half-bridge 1A and 1B ground

10 OUT1A OUTPUT Half-bridge 1A output

11 VDD_REG POWER VDD reg 3.3 V

12 GND_REG POWER DC reg ground

13 F3X_FILT POWER F3X reference voltage

14 F3XL OUTPUT F3X analog out left channel

15 F3XR OUTPUT F3X analog out right channel

16 LINEINL INPUT Line in left channel

17 LINEINR INPUT Line in right channel

18 LINEHPOUT_L OUTPUT Headphone/line driver left channel

19 LINEHPOUT_R OUTPUT Headphone/line driver right channel

20 GNDA POWER Headphone/line driver power ground

21 SOFTMUTE INPUT Soft mute

22 VDD3V3 POWER +3 V LDO power supply

23 CPVSS POWER -3.3 V charge pump pin

24 CPM FILTER CHP Cfly negative

25 GNDPSUB POWER Charge pump ground

26 CPP FILTER CHP Cfly positive

27 VDD3V3CHP POWER Charge pump power supply

28 VDDDIG1 POWER I/O ring power supply

29 GNDDIG1 POWER Digital core ground

30 FFX3A OUTPUT Digital PWM line out

31 FFX3B OUTPUT Digital PWM line out

Doc ID 018835 Rev 7 19/171

Pin connections STA381BW

Table 2. Pin list (continued)

VQFN 48-pin Name Type Description

32 EAPD/FFX4B OUTPUT Digital PWM line out

33 TWARN/FFX4A OUTPUT Digital PWM line out

34 VREGFILT POWER Digital VDD from core

35 AGNDPLL POWER PLL analog ground

36 MCLK INPUT PLL input clock

37 BICKI INPUT IIS serial clock

38 LRCKI INPUT IIS left/right clock

39 SDI INPUT IIS serial data input

40 RESET INPUT Reset

Device power-down

41 PWDN INPUT

0 = power-down
1 = normal operation

42 INTLINE OUTPUT Fault interrupt

43 SDA I/O IIC serial data

44 SCL INPUT IIC serial clock

45 SA INPUT IIC select address (pull-down)

46 TEST_MODE INPUT

This pin must be connected to
ground (pull-down)

47 GNDDIG2 POWER Digital I/O ground

48 VDDDIG2 POWER Digital core LDO supply

20/171 Doc ID 018835 Rev 7

STA381BW Electrical specifications

3 Electrical specifications

3.1 Absolute maximum ratings

Table 3. Absolute maximum ratings

Symbol Parameter Min Typ Max Unit

Vcc Power supply voltage (VCCxA, VCCxB) -0.3 30 V

VDD_DIG Digital supply voltage -0.3 4 V

VDD3V3
VDD3V3CHP

Top Operating junction temperature 0 150 °C

Tstg Storage temperature -40 150 °C

R

Line

R

Hp

R

Btl

Charge pump and analog path LDO supply -0.3 4 V

Load impedance - line driver mode 1 kΩ

Load impedance - headphone driver mode 16 Ω

Load impedance - power output-BTL mode 5 Ω

Warning: Stresses beyond those listed in Table 3 above may cause

permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any
other conditions beyond those indicated under
“Recommended operating conditions” are not implied.
Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability. In the real
application, power supplies with nominal values rated within
the recommended operating conditions may rise beyond the
maximum operating conditions for a short time when no or
very low current is sunk (amplifier in mute state). In this case
the reliability of the device is guaranteed, provided that the
absolute maximum ratings are not exceeded.

3.2 Thermal data

Table 4. Thermal data

Symbol Parameter Min Typ Max Unit

Rth j-case Thermal resistance junction-case (thermal pad) 1.5 °C/W

Tth-sdj Thermal shutdown junction temperature 150 °C

Tth-w Thermal warning temperature 130 °C

Tth-sdh Thermal shutdown hysteresis 20 °C

Doc ID 018835 Rev 7 21/171

Electrical specifications STA381BW

3.3 Recommended operating conditions

Table 5. Recommended operating conditions

Symbol Parameter Min Typ Max Unit

Vcc Power supply voltage (VCCxA, VCCxB) 4.5 26 V

VDD_DIG Digital supply voltage 2.7 3.3 3.6 V

VDD3V3
VDD3V3CHP

Tamb Ambient temperature 0 70 °C

R

Line

R

Hp

R

Btl

Charge pump and analog path LDO supply 2.7 3.3 3.6 V

Load impedance - line driver mode 5 10 kΩ

Load impedance - headphone driver mode 16 32 Ω

Load impedance - power output-BTL mode 5 8 Ω

3.4 Electrical specifications for the digital section

The specifications given in this section are valid for the operating conditions:
VDD_DIG = 3.3 V, T

(shou

Table 6. Electrical specifications - digital section

amb

= 25 °C.

Symbol Parameter Conditions Min Typ Max Unit

Low level input current without

I

il

pull-up/down device

I

V

V

V

V

R

High level input current without

ih

pull-up/down device

Low level input voltage 0.8 V

il

High level input voltage 2.0 V

ih

Low level output voltage Iol = 2 mA 0.15 V

ol

High level output voltage Ioh = 2 mA

oh

Pull-up/down resistance 50 kΩ

pu

Vi = 0 V 0.5 µA

Vi = VDD_DIG
= 3.3 V

VDD_DIG

-0.15

0.1 µA

V

22/171 Doc ID 018835 Rev 7

STA381BW Electrical specifications

3.5 Electrical specifications for the power section

The specifications given in this section are valid for the operating conditions: VCC=24V,
f=1kHz, f

Table 7. Electrical specifications - power section

Symbol Parameter Conditions Min Typ Max Unit

Po

R

dsON

gP Power Pchannel R

gN Power Nchannel R

Idss Power Pchannel/Nchannel leakage 10 µA

I

LDT

t

r

t

f

Output power BTL Digital limited

Output power SE R

Power Pchannel/Nchannel MOSFET ld = 1.5 A 120 mΩ

Low current dead time (static) Resistive load

Rise time Resistive load

Fall time Resistive load

Supply current from Vcc in power-down PWRDN = 0 0.1 1 µA

= 384 kHz, T

sw

= 4 Ω Digital limited

L

matching ld = 1.5 A 95 %

dsON

matching ld = 1.5 A 95 %

dsON

= 25° C and RL = 8 Ω, unless otherwise specified.

amb

(1)

(1)

(1)

(2)

(2)

(2)

20

5

WOutput power SE Digital limited

9

815ns

10 18 ns

10 18 ns

I

vcc

Supply current from Vcc in operation

PCM Input signal = -60 dBfs,
Switching frequency = 384 kHz,

52 60 mA

No LC filters

Ilim Overcurrent limit 4 5 6.5 A

UVL Undervoltage protection 3.5 4.3 V

V

t

Overvoltage protection 28.25 V

OV

Output minimum pulse width No load 20 30 60 ns

min

DR Dynamic range 100 dB

Signal-to-noise ratio, ternary mode A-weighted 100 dB

SNR

Signal-to-noise ratio, binary mode A-weighted 90 dB

THD+N Total harmonic distortion + noise

FFX stereo mode, Po = 1 W,
f=1kHz

0.2 %

FFX stereo mode,

X

TA LK

Crosstalk

<5 kHz, one channel driven at

1 W and other channel

80 dB

measured

η Peak efficiency, FFX mode Po = 2 x 20 W into 8 Ω 90 %

1. The related THD can be defined through appropriate DRC settings (see section: 4.3: STCompressorTM)

2. Refer to Figure 3: Test circuit.

Doc ID 018835 Rev 7 23/171

Electrical specifications STA381BW

Figure 3. Test circuit

3.6 Electrical specifications for the analog section

The specifications given in this section are valid for the operating conditions: VCC = 24 V

f=1kHz, T

Table 8. Electrical specifications for the analog section

Symbol Parameter Conditions Min Typ Max Unit

Vout Output voltage for line out G

Pout Output voltage for HP out THD+N = 10%, G

DR Dynamic range for line out

X-Talk Channel separation for line out V

PSRR Power supply rejection ratio

Line input resistance 30

R

in

THD+N Total harmonic distortion + noise

1. Refer to 8.2: Headphone and 2 Vrms line out, Figure 47: Headphone and line out block diagram, Rin = R1

= 25 °C, VDD3V3 = 3.3 V, R

amb

= 2.5, THD < 1%, Rload = 5 kΩ 1.9 2.1 Vrms

v

Vout = 2 V
Vin = 0.8 mV (-60 dBFs)

= 2 Vrms, Gv = 2.5 75 dB

out

HP mode, P

Line out mode, V

HP mode, V

Line out mode, V

= 5 kΩ, R

Line

= 2.5, Rload = 32 Ω 40 mW

v

, Fin = 200 Hz,

RMS

= 15 mW 70 dB

0

= 2 Vrms 70

Out

= 200 mV

out

Out

RMS

= 0.2 Vrms, Gv = 2.5 0.03 %

= 32 Ω, unless otherwise specified.

Hp

100 dB

(1)

, Gv = 2.5 0.03 %

kΩ

24/171 Doc ID 018835 Rev 7

STA381BW Device overview

4 Device overview

The mentioned hyperlink in this section relates to the default New Map Section 6: Register

description: New Map.

4.1 Processing data path

The whole STA381BW processing chain is composed of two consecutive sections. In the
first one dual-channel processing is implemented (Figure 4) and then each channel is fed
into the post-mixing block allowing to generate either a third channel (typically used in 2.1
output configurations together with crossover filters) or to have the channels processed by
the dual-band DRC block (2.0 output configuration with crossover filters used to define the
cutoff frequency of the two bands).

The first section begins with a 2x oversampling FIR filter allowing 2*Fs audio processing.
Then a selectable high-pass filter removes the DC level (enabled if HFB = 0). The channel 1
and 2 processing chain can include up to 8 filters, depending on the selected configuration
(bits BQL, BQ5, BQ6, BQ7 and XO[3:0]). By default, 4 independent filters per channel are
enabled, plus the pre-configured Bass and Treble controls (BQL=0, BQ5=0, BQ6=0,
BQ7=0).

The STA381BW offers the possibility to share the filter coefficients between the two
processing channels. When this option is set (BQL=1), filters from the 1st to the 4th have the
same coeffcients set. Under these conditions, filters from the 5th to 7th can be used as
custom filters as well (provided the relevant BQx bits are set). Once again filter coefficients
are shared between the two processing channels.

Moreover the common 8th filter, from the subsequent processing section, can be available
on both channels (provided the pre-defined crossover frequencies are not used, XO[3:0]=0,
and the dual-band DRC is not used).

Figure 4. Processing path, first part

Sampl i ng Fr equency = 2 xFs

Tone Control

Tone Control

Treble

Or

Biquad#7

Treble

Or

Biquad#7

L

R

I2S Input
Interface

X2Ov er-

-sampl ing
FIR

Sampling Frequency = Fs

X2Ov er-

-sampl ing
FIR

Sampl i ng Fr equency = 2 xFs

Pre-

-scale

Pre-

-scale

Hi-Pas s

Filter

Hi-Pas s

Filter

Biquad#1Biquad#2Biquad#3Biquad

Userd Defi ned Fil ters

Biquad#1Biquad#2Biquad#3Biquad

Userd Defi ned Fil ters

#4

#4

De-emph

Or

Biquad#5

De-emph

Or

Biqua

d#5

Bass

Or

Biquad#6

Bass

Or

Biquad#6

Doc ID 018835 Rev 7 25/171

Device overview STA381BW

The second processing stage embeds a mixing block, a biquadratic/crossover filter, a DRC
stage, the volume control, a DC cut filter and a post scaler. Depending on the device
settings, the following configuration and features are available:

● 2.1 output with individually configurable anticlipper/DRCs (Figure 5): two individually

configurable DRC/anticlippers are available while the eighth biquadratic filter, jointly
with the mixer block, can be used to perform LFE. This configuration and features
ensure the backward compatibility with previous Sound Terminal

®

products.

Figure 5. Processing path, second part: 2.1 output with individually configurable

anticlipper/DRCs

L

C1Mx1

+

R

C1Mx2

C2Mx1

+

C2Mx2

C3Mx1

+

C3Mx2

Us er-Defined

Mix Coef ficients

Channel ½

Biquad#8

--------------

Hi-pass XO

Filter

Channel ½

Biquad#8

--------------

Hi-pass XO

Filter

Channel 3

Biquad#8

-- -- -- ---- ----

Low- pass XO

filter

Crossover Frequency

Determined by XO Setting

(User D efined If

XO=0000)

Channel 1

Vol ume

Channel 2

Vol ume

Channel 3

Vol ume

Anti -clipper

/

DRC

Anti -clipper

/

DRC

Anti- clipper

/

DRC

DC Cut

Filter

DC Cut

Filter

DC Cut

Filter

Pos t Scale

Pos t Scale

Pos t Scale

26/171 Doc ID 018835 Rev 7

STA381BW Device overview

● 2.0 output with B

2

DRC (Figure 6): the mixer and the eighth biquadratic filter are used to
divide the channel into two sub-bands, then each sub-band is independently processed
by a DRC block. The two bands are then re-composed and fed to the following
processing blocks. The crossover frequency is user-selectable. This configuration and
features ensure the backward compatibility with the previous Sound Terminal
products. For further information please refer to Chapter 6.11.1: Dual-band DRC.

DRC 2

DRC 1

DRC 1

DRC 2

2

DRC

+

DC Cut

Filter

DC Cut

Filter

Post Scale

Post Scale

TM

. When

Figure 6. Processing path, second part: 2.0 output with B

Channel 3

Vol ume

L

R

● 2.1 output with STCompressor

C1Mx1

+

C1Mx2

C2Mx1

+

C2Mx2

C3Mx1

+

C3Mx2

User-Def ined

Mix Coef fici ents

B2DRC

Hi-p ass XO

filter

B2DRC

Hi-p ass XO

filter

Crossover Frequency

Determined by XO Setting

(User Defi ned I f

XO=000 0)

TM

- Channel 1
++

+

-

Vol ume

Channel 2

Vol ume

Channel 3

Vol ume

(Figure 7): the STA381BW embeds the latest, state­of-the-art multi-band dynamic, range compressor, called STCompressor
using this configuration, up to 10 biquad filters are available for dedicated processing.
Please refer to Section 4.3: STCompressorTM for further information about this feature.

®

Figure 7. Processing path, second part: 2.1 output configuration with

STCompressor

L

R

TM

C1Mx1

+

C1Mx2

C2Mx1

+

C2Mx2

C3Mx1

+

C3Mx2

User-Defined

Mix Coefficients

Channel ½

Biquad#8

--------------

Hi-p ass XO

Filter

Channel ½

Biquad#8

--------------

Hi-p ass XO

Filter

Channel 3

Biquad#8

--------------

Low-p ass XO

filter

Crossover Frequency

Determined by XO Sett ing

(User Defin ed If

XO=0000)

STCompressor

STCompressor

Vol ume

And

Limit er

Vol ume

And

Limit er

Vol ume

And

Limit er

DC Cut

Filter

DC Cut

Filter

DC Cut

Filter

Post Scale

Post Scale

Post Scale

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Device overview STA381BW

4.2 Input oversampling

Figure 4 shows the input oversampling block in front of the main processing. When 32 kHz

Fs is used, the default x2 oversampling ratio can be increased to a x3.

Activating this feature, it is possible to have a 384 kHz PWM switching frequency (instead of
the default 256 kHz) when 32 kHz Fs is used.

When bit 0 of register PLLCFG1 is set to one, the feature is activated so that the PLL ratio is
modified to generate 49.152 MHz internal clock and the audio data path (after the input
oversampling block) is running at 96 kHz.

It is not recommended to use the x3 oversampling feature when Fs > 32 kHz because of the
PLL maximum frequency constraint.

4.3 STCompressor

The STCompressorTM (STC from now on) is a stereo, dual-band Dynamic Range Control
(DRC) and its main purpose is to provide optimum output power level control for speaker
protection, preserving as much as possible the original audio quality of the signal.

Two m ai n I
data flow control bits, these registers also allow enabling the checksum engine to protect the
STC filters from erroneous coefficients downloads, thus improving the final application
circuitry and safety of the speakers.

2

C registers control the STC behavior: STCCFG0 and STCCFG1. On top of the

TM

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STA381BW Device overview

4.3.1 STC block diagram

Figure 8. STCompressorTM block diagram

DRC 0

Offs et

Band 0

In put

Ch 0

In put

Ch 1

Band

Sp li tter

Band

Sp li tter

(Low freqs)

Band 1

(High freqs)

Band 0

(Low freqs)

Band 1

(High freqs)

Level

Meter

Level

Meter

Level
Meter

Level
Meter

Mapper Attenuator

DRC 1

Mapper

DRC 2

Mapper

DRC 3

Mapper

Attenuato r

Offs et

Offs et

Attenua to r

Attenua to r

X

Ou tp ut

Ch 0

+

X

X

Ou tp ut

Ch 1

+

X

Offs et

The STC takes as input 2 channels and every channel is processed independently (i.e. an
independent DRC for each band of each channel) following the steps listed below
(Figure 8):

1. Splits the input signal into 2 bands (band splitter)

2. Measures the level of the signal (level meter)

3. Computes the attenuation (mapper)

4. Applies the attenuation and offset (attenuator)

The band splitter settings are common to both the processing channels while the settings of
the remaining blocks can be independently set for each band of each processing channel.

Caution: All the settings explained hereafter apply only to the behavior of the STCompressor

the settings concerning other device operating configurations (see Chapter 4.1: Processing

data path) please refer to the appropriate paragraphs and registers.

4.3.2 Band splitter

The band splitter block is used to divide the signal into 2 sub-bands (typically low- and high­frequency bands). This is done through two 2
thus allowing to have up to a 4

th

order filter per band. This feature guarantees a totally flat
band recombination (see Figure 9). Using different filtering orders, indeed, causes a non­negligible gain around the filter’s cutoff frequency, endangering the overall audio fidelity and,
eventually, also the safety of the speaker. The sub-band recombination can be enabled or
disabled.

nd

order biquads (IIR filters) for each band,

TM

. For

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Device overview STA381BW

The band splitter filter coefficients have a user-selectable range [-1, 1), [-2, 2) and [-4, 4).
The RAM coefficient 0x7 is responsible for these settings according to Tab l e 9 . The range
default value is [-4, 4).

Table 9. Coefficients extended-range configuration 0x74h

CEXT_Bx[1] CEXT_Bx[0] Range

00

01

10

1 1 Reserved

[-1;1)

[-2;2)

[-4;4)

Please refer to Section 6.24: User-defined coefficient control registers (addr 0x27 - 0x37)
and to Ta bl e 1 3 for further details.

Figure 9. Band splitter with 4

Band Splitter

Inp ut

Ch x

BQ 0

th

order filtering

BQ 1

Band 0

…

Output

Ch x

+=

BQ 0

BQ 1

Band 1

…

4.3.3 Level meter

The level meter block measures the input signal level (in dB). Two kinds of measures are
performed: peak and RMS. The mapper configuration and the input signal automatically
determine which measurement to take into account.

4.3.4 Mapper

The mapper block computes the appropriate attenuation value (expressed in dB) to be
applied to the signal, basing its calculations on the level meter output value, on the
compressor threshold and on the limiter threshold.The attenuation value is then passed to
the attenuator block.

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STA381BW Device overview

The STC reacts differently depending on these three parameters (Figure 10):

● level meter output value < compressor threshold < limiter threshold: under these

circumstances the signal level is small enough to not require any type of
limiting/compressing action. The signal remains unchanged.

● compressor threshold < level meter output value < limiter threshold: under these

circumstances the signal level is compressed to a ratio determined by the compressor
rate.

● compressor threshold < limiter threshold < level meter output value: under these

circumstances the signal level exceeds the limiter threshold which represents the
maximum output power allowed. The signal is limited to avoid unpredictable effects and
damages.

The compressor threshold, the limiter threshold and the compressor rate are all user­selectable parameters. The compressor threshold range of value is [-48, 0] dB with a

0.25 dB step. The limiter threshold range of values is [-24, +12] dB with a 0.25 dB step. The
compressor ratio range of value is [0, 15], the meaning of these values is specified in

Ta bl e 1 0 . For further details please refer to Ta b l e 1 2 . Either setting the compressor rate to

1:1 or setting the compressor threshold greater than the limiter threshold makes the STC
behave as a pure limiter (Figure 11).

Figure 10. STCompressor

[dB]

L.T.

C.T.

OUTPUT

TM

behavior

C.R.

C.T. L.T. L.T. comp

INPUT

Linear Zone

Compression Zone

Limiting Zone

[dB]

Doc ID 018835 Rev 7 31/171

Device overview STA381BW

Figure 11. STCompressorTM behavior as a limiter

Linear Zone

[dB]

L.T.

Limiting Zone

OUTPUT

Table 10. Compressor ratio

Compressor ratio Ratio value

01:1

1 1:1.25

21:1.5

3 1:1.75

41:2

51:2.5

61:3

71:3.5

81:4

91:4.5

10 1:5

11 1:5.5

12 1.6

L.T.

INPUT

[dB]

13 1:7

14 1:8

15 1:16

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STA381BW Device overview

4.3.5 Attenuator

The attenuation is characterized by two different phases: attack and release.

Given an input signal above the limiter threshold, during the attack phase the STC
decreases the gain in order to reach the output level determined by the mapper. In this
process the key parameter is the attack rate (dB/ms) which determines how fast the STC
reacts according to the following equation:

AttackTime

where:

● Output Signal Level is the attenuated signal coming from the attenuator block itself and

used as feedback

● Mapper Level is the target signal level to be reached

The attack rate is user-selectable and its range is [0, +16] dB/ms with a 0.25 dB/ms step.

Given an input signal moving below the limiter threshold, during the release phase the STC
increases the gain in order to return the original input signal dynamic. In this process the key
parameter is the release rate (dB/ms) which determines how fast the STC releases the
attenuation on the input signal according to the following equation:

ReleaseTime

OutputSignalLevel MapperLevel–

-------------------------------------------------------------------------------------------------- -=

OutputSignalLevel MapperLevel–

-------------------------------------------------------------------------------------------------- -=

AttackRate

ReleaseRate

The release rate is user-selectable and its range is [0.0078, 1) dB/ms with a 0.0039 dB/ms
step.

4.3.6 Dynamic attack

Due to its dynamic, the input signal may exceed the limiter threshold by a variable amount of
decibels. In such different situations it might be useful to be able to tune the attack rate to
make the STC react slower or faster depending on the context. The attack rate value, set by
the user, can be dynamically varied through the dynamic attack rate (DAR). It is a parameter
(expressed in ms/dB) acting as a weighted coefficient, multiplying the difference between
the attenuator output signal and the mapper target level. The dynamic attack rate affects the
user-programmed attack rate according to the following equations:

DynamicAttackTime OutputSignalLevel MapperLevel–()DAR×=

AttackTime

The DAR is user-definable and its range of values is [0, +1) ms/dB, (Ta bl e 1 2 ) with a

0.0039 ms/dB step. The DAR is the same for all 4 sub-bands.

OutputSignalLevel MapperLevel–

-------------------------------------------------------------------------------------------------- - DynamicAttackTime+=

AttackRate⇒

AttackRate

OutputSignalLevel MapperLevel–

-------------------------------------------------------------------------------------------------- -=

AttackTime DynamicAttackTime–

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Device overview STA381BW

4.3.7 Offset

The offset is a user-selectable gain or volume control. When using the STC it is advised to
use the offset to tune the output volume instead of the regular volume controls. The offset is
located before the attenuator block, ensuring that the output power limit (limiter threshold) is
never exceeded (Figure 12). On the other side, the traditional volume control is located after
the STC attenuator, thus a wrong setting of this control could nullify the STC effect.

Each sub-band has its own and independent offset. Its range is [0, +48] dB with a 0.25 dB
step (Ta bl e 1 2 ).

Figure 12. Offset effect

4.3.8 Stereo link

The stereo link feature allows applying the same attenuation to the corresponding band of
each channel (i.e. band 0 left channel and band 0 right or band 1 left channel and band 1
right channel). This should help to prevent image shifting that could occur when individually
compressing each channel and causing a volume mismatch between left and right.

When the stereo link is active, the proper attenuation for each band is independently
computed, then the highest one for each band is applied (Figure 13).

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STA381BW Device overview

Figure 13. Stereo link block diagram

Ch 0 – Band 0

From mapper

Ch 0 – Band 0

From mapper
Ch 0 – Band 1

Ch 0 – Band 1

Ch 1 – Band 0

From mapper
Ch 1 – Band 0

From mapper
Ch 1 – Band 1

Ch 1 – Band 1

Attenuator

Attenuator

Attenuator

Attenuator

4.3.9 Programming of coefficients

The coefficients are expressed in different value ranges and in decimal notation (refer to the
previous paragraphs). In order to be programmed they must be converted into a
[-1, +1) range and in hexadecimal notation (Tab le 1 1). This can be achieved with the
following procedure:

● if CoeffDecValue>0

Atte nuator

Max

Atte nuation

Band 0

Atte nuator

Atte nuator

Max

Atte nuation

Band 1

Atte nuator

X

+

Output

Ch 0

X

X

+

Output

Ch 1

X

CoeffI2CValue rnd CoeffDecValue 26⁄()223×()=

● if CoeffDecValue<0

24

CoeffI2CValue 2

rnd CoeffDecValue 26⁄()223×()–=

where CoeffI2CValue is the final decimal value to be converted into hexadecimal notation
while CoeffDecValue is the coefficient value (in decimal notation) to start from.

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Device overview STA381BW

Table 11. Conversion example

Original value (dec) I2C value (hex)

+48.00 0x600000

+24.00 0x300000

+16.00 0x200000

+12.00 0x180000

+06.00 0x0C0000

+02.00 0x040000

+01.00 0x020000

-01.00 0xFE0000

-02.00 0xFC0000

-06.00 0xF40000

-12.00 0xE80000

-24.00 0xD00000

-48.00 0xA00000

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STA381BW Device overview

4.3.10 Memory map

All the control parameters listed in the previous paragraphs are stored in the internal device
memory. Please refer to Ta bl e 1 2 and Tab le 1 3 for a complete list of their addresses.

For the programming procedure please refer to Section 6.24: User-defined coefficient

control registers (addr 0x27 - 0x37). Be aware that the read-all operation is not available for

the STC coefficients memory.

Table 12. STC coefficients memory map

Function Address Parameter Range Precision Unit Default

0x54 RR: release rate [0.0078,1) 0.0039 dB/ms 0x200000

dB/ms 0x200000

Band 0

0x55 AR: attack rate [0,16]

0x56 LT: limiter threshold [-24, +12] 0.25 dB 0x000000

DRC 0

0x57 CR: compressor ratio [0,15] 1 index 0x000000

0x58 CT: compressor threshold [-48, 0] 0.25 dB 0x000000

0.25

CH0

CH1

Band 1

Band 0

Band 1

OFFSET

0x59 RR: release rate [0.0078,1) 0.0039 dB/ms 0x200000

05A AR: attack rate [0,16]

0x5B LT: limiter threshold [-24, +12] 0.25 dB 0x000000

DRC 1

0x5C CR: compressor ratio [0,15] 1 index 0x000000

0x5D CT: compressor threshold [-48, 0] 0.25 dB 0x000000

0x5E RR: release rate [0.0078,1) 0.0039 dB/ms 0x200000

0x5F AR: attack rate [0,16]

0x60 LT: limiter threshold [-24, +12] 0.25 dB 0x000000

DRC 2

0x61 CR: compressor ratio [0,15] 1 index 0x000000

0x62 CT: compressor threshold [-48, 0] 0.25 dB 0x000000

0x63 RR: release rate [0.0078,1) 0.0039 dB/ms 0x200000

0x64 AR: attack rate [0,16]

0x65 LT: limiter threshold [-24, +12] 0.25 dB 0x000000

DRC 3

0x66 CR: compressor ratio [0,15] 1 index 0x000000

0x67 CT: compressor threshold [-48, 0] 0.25 dB 0x000000

0X68 OFS0: offset DRC 0 [0, +48] 0.25 dB 0x000000

0X69 OFS1: offset DRC 1 [0, +48] 0.25 dB 0x000000

0X6A OFS2: offset DRC 2 [0, +48] 0.25 dB 0x000000

0X6B OFS3: offset DRC 3 [0, +48] 0.25 dB 0x000000

0.25

0.25

0.25

dB/ms 0x200000

dB/ms 0x200000

dB/ms 0x200000

Dynamic attack rate 0x71 DAR: dynamic attack rate [0, 1) 0.0039 ms/dB 0x000000

CRC expected 0x72

CRC computed 0x73

Biquads CTRL 0x74

Band splitter filter
coefficients range

Doc ID 018835 Rev 7 37/171

0x0000AA

Device overview STA381BW

Table 13. STC band splitter filters memory map

Function Address Coefficient Range Default

0x40 B1/2 [-1, 1), [-2, 2), [-4, 4) 0x000000

0x41 B2 [-1, 1), [-2, 2), [-4, 4) 0x000000

0x42 -A1/2 [-1, 1), [-2, 2), [-4, 4) 0x000000

BQ0

0x43 -A2 [-1, 1), [-2, 2), [-4, 4) 0x000000

0x44 B0/2 [-1, 1), [-2, 2), [-4, 4) 0x100000

Band 0

Band 1

0x45 B1/2 [-1, 1), [-2, 2), [-4, 4) 0x000000

0x46 B2 [-1, 1), [-2, 2), [-4, 4) 0x000000

0x47 -A1/2 [-1, 1), [-2, 2), [-4, 4) 0x000000

BQ1

0x48 -A2 [-1, 1), [-2, 2), [-4, 4) 0x000000

0x49 B0/2 [-1, 1), [-2, 2), [-4, 4) 0x100000

0x4A B1/2 [-1, 1), [-2, 2), [-4, 4) 0x000000

0x4B B2 [-1, 1), [-2, 2), [-4, 4) 0x000000

0x4C -A1/2 [-1, 1), [-2, 2), [-4, 4) 0x000000

BQ0

0x4D -A2 [-1, 1), [-2, 2), [-4, 4) 0x000000

0x4E B0/2 [-1, 1), [-2, 2), [-4, 4) 0x100000

0x4F B1/2 [-1, 1), [-2, 2), [-4, 4) 0x000000

0x50 B2 [-1, 1), [-2, 2), [-4, 4) 0x000000

0x51 -A1/2 [-1, 1), [-2, 2), [-4, 4) 0x000000

BQ1

0x52 -A2 [-1, 1), [-2, 2), [-4, 4) 0x000000

0x53 B0/2 [-1, 1), [-2, 2), [-4, 4) 0x100000

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STA381BW I2C bus specification

5 I2C bus specification

The STA381BW supports the I2C protocol via the input ports SCL and SDA_IN (master to
slave) and the output port SDA_OUT (slave to master). This protocol defines any device that
sends data on to the bus as a transmitter and any device that reads the data as a receiver.
The device that controls the data transfer is known as the master and the other as the slave.
The master always starts the transfer and provides the serial clock for synchronization. The
STA381BW is always a slave device in all of its communications. It supports up to
400 kb/sec rate (fast-mode bit rate). The STA381BW I
interface works properly only in the case that the master clock generated by the PLL has a
frequency 10 times higher compared to the frequency of the applied SCL signal.

5.1 Communication protocol

5.1.1 Data transition or change

Data changes on the SDA line must only occur when the SCL clock is low. An SDA transition
while the clock is high is used to identify a START or STOP condition.

2

C is a slave-only interface. The I2C

5.1.2 Start condition

START is identified by a high-to-low transition of the data bus SDA signal while the clock
signal SCL is stable in the high state. A START condition must precede any command for
data transfer.

5.1.3 Stop condition

STOP is identified by a low-to-high transition of the data bus SDA signal while the clock
signal SCL is stable in the high state. A STOP condition terminates communication between
the STA381BW and the bus master.

5.1.4 Data input

During the data input the STA381BW samples the SDA signal on the rising edge of clock
SCL. For correct device operation, the SDA signal must be stable during the rising edge of
the clock and the data can change only when the SCL line is low.

5.2 Device addressing

To start communication between the master and the STA381BW, the master must initiate
with a start condition. Following this, the master sends to the SDA line 8 bits (MSB first)
corresponding to the device select address and read or write mode.

The seven most significant bits are the device address identifiers, corresponding to the I
bus definition. In the STA381BW the I
the SA port configuration, 0x38 when SA = 0, and 0x3A when SA = 1.

2

C interface has two device addresses depending on

2

C

The eighth bit (LSB) identifies read or write operation RW, this bit is set to 1 for read mode
and to 0 for write mode. After a START condition the STA381BW identifies on the bus the
device address and if a match is found, it acknowledges the identification on SDA bus during

Doc ID 018835 Rev 7 39/171

I2C bus specification STA381BW

the 9th bit time. The byte following the device identification byte is the internal space
address.

5.3 Write operation

Following the START condition, the master sends a device select code with the RW bit set
to 0. The STA381BW acknowledges this and then waits for the byte of the internal address.
After receiving the internal byte address the STA381BW again responds with an
acknowledgement.

5.3.1 Byte write

In the byte write mode the master sends one data byte which is acknowledged by the
STA381BW. The master then terminates the transfer by generating a STOP condition.

5.3.2 Multi-byte write

The multi-byte write mode can start from any internal address. The master generating a
STOP condition terminates the transfer.

5.4 Read operation

5.4.1 Current address byte read

Following the START condition, the master sends a device select code with the RW bit set
to 1. The STA381BW acknowledges this and then responds by sending one byte of data.
The master then terminates the transfer by generating a STOP condition.

5.4.2 Current address multi-byte read

The multi-byte read modes can start from any internal address. Sequential data bytes are
read from sequential addresses within the STA381BW. The master acknowledges each
data byte read and then generates a STOP condition, terminating the transfer.

5.4.3 Random address byte read

Following the START condition, the master sends a device select code with the RW bit set
to 0. The STA381BW acknowledges this and then the master writes the internal address
byte. After receiving the internal byte address, the STA381BW again responds with an
acknowledgement. The master then initiates another START condition and sends the device
select code with the RW bit set to 1. The STA381BW acknowledges this and then responds
by sending one byte of data. The master then terminates the transfer by generating a STOP
condition.

5.4.4 Random address multi-byte read

The multi-byte read mode can start from any internal address. Sequential data bytes are
read from sequential addresses within the STA381BW. The master acknowledges each
data byte read and then generates a STOP condition, terminating the transfer.

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STA381BW I2C bus specification

5.4.5 Write mode sequence

Figure 14. Write mode sequence

BYTE

BYTE

WRITE

WRITE

MULTIBYTE

MULTIBYTE

WRITE

WRITE

DEV-ADDR

DEV-ADDR

START RW

START RW

DEV-ADDR

DEV-ADDR

START

START

ACK

ACK

SUB-ADDR

SUB-ADDR

ACK

ACK

SUB-ADDR

SUB-ADDR

RW

RW

ACK

ACK

ACK

ACK

DATA IN

DATA IN

DATA IN

DATA IN

ACK

ACK

ACK

ACK

STOP

STOP

DATA IN

DATA IN

ACK

ACK

STOP

STOP

5.4.6 Read mode sequence

Figure 15. Read mode sequence

CURRENT

CURRENT
ADDRESS

ADDRESS

READ

READ

RANDOM

RANDOM

ADDRESS

ADDRESS

READ

READ

SEQUENTIAL

SEQUENTIAL

CURRENT

CURRENT

READ

READ

SEQUENTIAL

SEQUENTIAL

RANDOM

RANDOM

READ

READ

DEV-ADDR

DEV-ADDR

START RW

START RW

DEV-ADDR

DEV-ADDR

START

START

START

START

START RW

START RW

DEV-ADDR

DEV-ADDR

DEV-ADDR

DEV-ADDR

HIGH

HIGH

RW=

RW=

ACK

ACK

ACK

ACK

RW

RW

ACK

ACK

ACK

ACK

DATA

DATA

SUB-ADDR

SUB-ADDR

DATA

DATA

SUB-ADDR

SUB-ADDR

NO ACK

NO ACK

ACK

ACK

ACK

ACK

ACK

ACK

STOP

STOP

DATA

DATA

DEV-ADDR

DEV-ADDR

DEV-ADDR

DEV-ADDR

ACK

ACK

WRTRATS

WRTRATS

ACK

ACK

ACK

ACK

WRTRATS

WRTRATS

DATA

DATA

DATA

DATA

DATA

DATA

NO ACK

NO ACK

NO ACK

NO ACK

ACK

ACK

STOP

STOP

STOP

STOP

ACK NO ACK

ACK NO ACK

DATA

DATA

DATA

DATA

STOP

STOP

Doc ID 018835 Rev 7 41/171

Register description: New Map STA381BW

6 Register description: New Map

Mapping of two registers is available on the STA381BW, the selection is done by setting
register 0x7E bit D7. By default, 0x7E is set to 1 and refers to a map that is not compatible
with previous Sound Terminal devices. This register’s mapping is also called “New Map”.

To keep compatibility with previous Sound Terminal devices, 0x7E bit D7 must be set to 0
after device turn-on and after any reset (via SW or via external pin). Please refer to

Section 7: Register description: Sound Terminal compatibility for all the information about

device compatibility.

Missing addresses are to be considered as reserved.

Table 14. Default register map table: NEW MAP

Addr Name D7 D6 D5 D4 D3 D2 D1 D0

0x00 CLK CLK_CFG[3:0] I2S

0x01 STATUS FAULT DRCCRC EQCRC BADPWM I2SERR PLLUL

0x02 RESET SRESET

0x03 SVOL SVOL[1:0]

0x04 MVOL MVOL[7:0]

0x05 FINEVOL FINE[1:0]

0x06 CH1VOL CH1VOL[7:0]

0x07 CH2VOL CH2VOL[7:0]

0x08 POST POST[7:0]

0x09 OPER OPER[1:0]

0x0A FUNCT CRC APEQ PEQ AMDRC MDRCE DRC

0x10 HPCFG MUTE

0x11 CONFA FDRB IR1 IR0 MCS2 MCS1 MCS0

0x12 CONFB C2IM C1IM DSCKE SAIFB SAI3 SAI2 SAI1 SAI0

0x13 CONFC CSZ3 CSZ2 CSZ1 CSZ0

0x14 CONFD SME ZDE BQL PSL DSPB

0x15 CONFE ZCE PWMS AME NSBW

0x16 CONFF EAPD PWDN LDTE BCLE IDE

0x17 MUTELOC LOC1 LOC0 C3M C2M C1M MMUTE

0x1B CH3VOL CH3VOL[7:0]

0x1D AUTO XO3 XO2 XO1 XO0 AMAM2 AMAM1 AMAM0 AMAME

0x1F C1CFG C1BO C1VBP C1EQBP C1TCB

0x20 C2CFG C2BO C2VBP C2EQBP C2TCB

0x21 C3CFG C3OM1 C3OM0 C3LS1 C3LS0 C3BO C3VBP

0x22 TONE TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0

0x23 L1AR L1A3 L1A2 L1A1 L1A0 L1R3 L1R2 L1R1 L1R0

0x24 L1ATRT L1AT3 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 L1RT0

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STA381BW Register description: New Map

Table 14. Default register map table: NEW MAP (continued)

Addr Name D7 D6 D5 D4 D3 D2 D1 D0

0x25 L2AR L2A3 L2A2 L2A1 L2A0 L2R3 L2R2 L2R1 L2R0

0x26 L2ATRT L2AT3 L2AT2 L2AT1 L2AT0 L2RT3 L2RT2 L2RT1 L2RT0

0x27 CFADDR CFA5 CFA4 CFA3 CFA2 CFA1 CFA0

0x28 B1CF1 C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16

0x29 B1CF2 C1B15 C1B14 C1B13 C1B12 C1B11 C1B10 C1B9 C1B8

0x2A B1CF3 C1B7 C1B6 C1B5 C1B4 C1B3 C1B2 C1B1 C1B0

0x2B B2CF1 C2B23 C2B22 C2B21 C2B20 C2B19 C2B18 C2B17 C2B16

0x2C B2CF2 C2B15 C2B14 C2B13 C2B12 C2B11 C2B10 C2B9 C2B8

0x2D B2CF3 C2B7 C2B6 C2B5 C2B4 C2B3 C2B2 C2B1 C2B0

0x2E A1CF1 C3B23 C3B22 C3B21 C3B20 C3B19 C3B18 C3B17 C3B16

0x2F A1CF2 C3B15 C3B14 C3B13 C3B12 C3B11 C3B10 C3B9 C3B8

0x30 A1CF3 C3B7 C3B6 C3B5 C3B4 C3B3 C3B2 C3B1 C3B0

0x31 A2CF1 C4B23 C4B22 C4B21 C4B20 C4B19 C4B18 C4B17 C4B16

0x32 A2CF2 C4B15 C4B14 C4B13 C4B12 C4B11 C4B10 C4B9 C4B8

0x33 A2CF3 C4B7 C4B6 C4B5 C4B4 C4B3 C4B2 C4B1 C4B0

0x34 B0CF1 C5B23 C5B22 C5B21 C5B20 C5B19 C5B18 C5B17 C5B16

0x35 B0CF2 C5B15 C5B14 C5B13 C5B12 C5B11 C5B10 C5B9 C5B8

0x36 B0CF3 C5B7 C5B6 C5B5 C5B4 C5B3 C5B2 C5B1 C5B0

0x37 CFUD RA R1 WA W1

0x3C FDRC1 FDRC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10 FDRC9 FDRC8

0x3D FDRC2 FDRC7 FDRC6 FDRC5 FDRC4 FDRC3 FDRC2 FDRC1 FDRC0

0x3F MTH2

0x40 MTH1 MTH[15:8]

0x43 EATH1 EATHEN1 EATH1[6:0]

0x44 ERTH1 ERTHEN1 ERTH1[6:0]

0x45 EATH2 EATHEN2 EATH2[6:0]

0x46 ERTH2 ERTHEN2 ERTH2[6:0]

0x47 CONFX PS48DB XAR1 XAR2 BQ5 BQ6 BQ7

0x52 PLLFRAC1 PLL_FRAC[15:8]

0x53 PLLFRAC2 PLL_FRAC[7:0]

0x54

0x55

0x56

0x57

0x58

0x5A

PLLDIV

PLLCFG0

PLLCFG1

PLLSTATE

SHOK

CXT41

PLL_DITH[1:0] PLL_NDIV[5:0]

PLL_DPD PLL_FCT PLL_STB

PLL_DIRP PLL_PWD PLL_BYP OSC_PD

CEXT_B4[1:0] CEXT_B3[1:0] CEXT_B2[1:0] CEXT_B1[1:0]

PLL_

STBBYP

MTH[21:16]

PLL_IDIV[3:0]

BOOST32K

BYPSTATE PDSTATE OSCOK LOWCK

GNDSH VCCSH OUTSH

Doc ID 018835 Rev 7 43/171

Register description: New Map STA381BW

Table 14. Default register map table: NEW MAP (continued)

Addr Name D7 D6 D5 D4 D3 D2 D1 D0

0x5B

0x5C

0x5D

0x5E BPTH BPTH[5:0]

0x60

0x61

0x62

0x63

0x64

0x65

0x66

0x69

0x6A

0x6B

0x6C

0x6F

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

CXT75

MISC1

MISC2

RPDNEN

LPDP LPD LPDE PNDLSL[2:0] SHEN

BPTIM

ZCCFG0

WTHH WTHL FINETH HSEL[1:0] ZMTH[2:0]

ZCCFG1

ZCCFG2

ZCCFG3

ZCCFG4

HPCFG

F3XCFG1

F3XCFG2

HPLN CPFEN CPOK ABFAULT DCROK

F3XLNK

F3X_FAULT

STCCFG0

STCCFG1

MTH0 MTH[7:0]

CHPSINC

BQCHKE0 BQ_CKE[7:0]

BQCHKE1 BQ_CKE[15:8]

BQCHKE2 BQ_CKE[23:16]

XCCHKE0 XC_CKE[7:0]

XCCHKE1 XC_CKE[15:8]

XCCHKE2 XC_CKE[23:16]

BQCHKR0 BQ_CKR[7:0]

BQCHKR1 BQ_CKR[15:8]

BQCHKR2 BQ_CKR[23:16]

XCCHKR0 XC_CKR[7:0]

XCCHKR1 XC_CKR[15:8]

XCCHKR2 XC_CKR[23:16]

CHKCTRL XCAUTO BCAUTO

MISC4

SMAP WRA CH12

CEXT_B7[1:0] CEXT_B6[1:0] CEXT_B5[1:0]

BRIDGOFF

BPTIM[7:0]

RMS_CH0[7:0]

RMS_CH0[15:8]

RMS_CH1[7:0]

RMS_CH1[15:8]

CHPI INITCNT[3:0] CHPRD

CPWMEN

F3X_SM_SLOPE[2:0] F3X_MUTE F3X_ENA

NP_

CRCRES

STC_LNK

44/171 Doc ID 018835 Rev 7

STA381BW Register description: New Map

6.1 CLK register (addr 0x00)

D7 D6 D5 D4 D3 D2 D1 D0

CLK_CFG[3:0] Reserved Reserved Reserved I2S

00000000

Table 15. CLK register

Bit R/W RST Name Description

7R/W 0

6R/W 0

CLK_CFG[3:0]

5R/W 0

4R/W 0

0R/W 0 I2S

6.2 STATUS register (addr 0x01)

D7 D6 D5 D4 D3 D2 D1 D0

FAULT DRCCRC EQCRC BADPWM Reserved Reserved I2SERR PLLUL

NA NA NA NA NA NA NA NA

Table 16. STATUS register

Bit R/W RST Name Description

7R FAULT

6 R DRCCRC

(1)

0000: 44.1/48 kHz BITCLK = 64 Fs
0001: 32 kHz BITCLK = 64 Fs
0010: 96 kHz BITCLK = 64 Fs
0011: 48/44.1/32 kHz MCK = 256 Fs
others: clock configuration depends on IR/MCS bits

2

‘0’ = SAI configured in I

S mode

‘1’ = SAI configuration depends on CONFB register
status

‘0’ = the power bridge is in fault condition
‘1’ = the power bridge is in normal condition

‘0’ = normal operation
‘1’ = CRC error on DRC BIQUADS

5 R EQCRC

4R BADPWM

‘0’ = normal operation
‘1’ = CRC error on BIQUADS

‘0’ = normal operation
‘1’ = PWM outputs are invalid

‘0’ = normal operation

1 R I2SERR

‘1’ = SAI interface error detected (see Section 6.14:

Configuration register B (addr 0x12))

0 R PLLUL

1. Fault status is set to 1 once the power bridge goes to tri-state mode.

‘0’ = PLL is locked
‘1’ = PLL is not locked

Doc ID 018835 Rev 7 45/171

Register description: New Map STA381BW

6.3 RESET register (addr 0x02)

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Reserved Reserved Reserved Reserved Reserved Reserved SRESET

00000000

Table 17. RESET register

Bit R/W RST Name Description

0 R/W 0 SRESET

‘0’: normal operation
‘1’: reset the device

After SRESET is written, the last IC acknowledge is skipped and the EAPD bit (reg 0x16 bit
D7) is set to 1 instead of the 0 default value obtained after hardware reset.

6.4 Soft volume register (addr 0x03)

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Reserved Reserved Reserved Reserved Reserved SVOL[1:0]

00000001

Table 18. Soft volume register

Bit R/W RST Name Description

1R/W

SVOL[1:0]

0R/W

00: 30 ms
01: 100 ms (default)
10: 100 ms
11: Soft-mute disabled

Values are specified for fs = 48 kHz, 96 kHz or 192 kHz.

46/171 Doc ID 018835 Rev 7

STA381BW Register description: New Map

6.5 MVOL register (addr 0x04)

D7 D6 D5 D4 D3 D2 D1 D0

MVOL[7:0]

00000000

Table 19. Master volume register

Bit R/W RST Name Description

7R/W 0

6R/W 0

5R/W 0

4R/W 0

MVOL[7:0]

3R/W 0

2R/W 0

1R/W 0

0R/W 0

0x00: Hard mute (immediate switchoff)
0x01: Mute
0x02: Mute (PWM on)
0x03: Mute (PWM on)
others: volume = [(MVOL-255)/2] dB

(1)

1. If the volume is below -60 dB, the level will be approximated to 1 dB step.

6.6 FINEVOL register (addr 0x05)

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Reserved Reserved Reserved Reserved Reserved FINE[1:0]

00000000

Table 20. Fine volume register

Bit R/W RST Name Description

1R/W

FINE[1:0]

0R/W

00 = 0 dB
01 = -0.125 dB
10 = -0.25 dB
11 = -0.375 dB

Doc ID 018835 Rev 7 47/171

Register description: New Map STA381BW

6.7 CH1VOL register (addr 0x06)

D7 D6 D5 D4 D3 D2 D1 D0

CH1VOL[7:0]

10011111

Table 21. Channel 1 volume register

Bit R/W RST Name Description

7R/W 1

6R/W 0

5R/W 0

4R/W 1

CH1VOL[7:0]

3R/W 1

2R/W 1

1R/W 1

0R/W 1

1. If the volume is below -60 dB, the level will be approximated to 1 dB step.

0x00: mute
others: volume = [(CH1VOL-159)/2] dB

(1)

6.8 CH2VOL register (addr 0x07)

D7 D6 D5 D4 D3 D2 D1 D0

CH2VOL[7:0]

10011111

Table 22. Channel 2 volume register

Bit R/W RST Name Description

7R/W 1

6R/W 0

5R/W 0

4R/W 1

CH2VOL[7:0]

3R/W 1

2R/W 1

1R/W 1

0R/W 1

1. If the volume is below -60 dB, the level will be approximated to 1 dB step.

0x00: mute
others: volume = [(CH2VOL-159)/2] dB

(1)

48/171 Doc ID 018835 Rev 7

STA381BW Register description: New Map

6.9 POST scaler register (addr 0x08)

D7 D6 D5 D4 D3 D2 D1 D0

POST[7:0]

10000000

Post scaler is set to POST/128 for both CH1 and CH2.

6.10 OPER register (addr 0x09)

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Reserved Reserved Reserved Reserved Reserved OPER[1:0]

00000000

Table 23. OPER register

Bit R/W RST Name Description

1R/W 0

OPER[1:0] output configuration modes

0R/W 0

Table 24. OPER configuration selection

OPER[1:0] Output configuration PBTL enable

2-channel (full-bridge) power, 2-channel data-out:
1A/1B → 1A/1B

00

2A/2B → 2A/2B
LineOut1 → 3A/3B

No

LineOut2 → 4A/4B
Line out configuration determined by LOC register

2-channel (full-bridge) power, 1-channel FFX:
1A/1B → 1A/1B

11

2A/2B → 2A/2B

Ye s
3A/3B → 3A/3B
EAPDEXT and TWARNEXT Active

2(half-bridge).1(full-bridge) on-board power:
1A → 1A Binary 0°

10

2A → 1B Binary 90°
3A/3B → 2A/2B Binary 45°

No

1A/B → 3A/B Binary 0°
2A/B → 4A/B Binary 90°

01

1 channel mono-parallel:
3A → 1A/1B w/ C3BO 45°
3B → 2A/2B w/ C3BO 45°
1A/1B → 3A/3B
2A/2B → 4A/4B
CH3 downmixed on all the PWM channels.

Doc ID 018835 Rev 7 49/171

No

Register description: New Map STA381BW

Figure 16. OPER = 00 (default value)

OUT1A

OUT1A

Half

Half

Bridge

Bridge

Channel 1

LPF

LPF

LPF

LPF

Channel 1

Channel 2

Channel 2

LineOut1

LineOut1

LineOut2

LineOut2

Half

Half

Bridge

Bridge

Half

Half

Bridge

Bridge

Half

Half

Bridge

Bridge

OUT1B

OUT1B

OUT2A

OUT2A

OUT2B

OUT2B

OUT3A

OUT3A

OUT3B

OUT3B

OUT4A

OUT4A

OUT4B

OUT4B

Figure 17. OPER = 11

Half

Half

Bridge

Bridge

OUT1A

OUT1A

Channel 1

Channel 1

Figure 18. OPER = 10

Bridge

Bridge

Bridge

Bridge

Bridge

Bridge

Half

Half

Bridge

Bridge

Half

Half

Bridge

Bridge

Half

Half

Bridge

Bridge

Half

Half

Bridge

Bridge

Half

Half

Half

Half

Half

Half

OUT1A

OUT1A

OUT1B

OUT1B

OUT2A

OUT2A

OUT2B

OUT2B

OUT3A

OUT3A

OUT3B

OUT3B

EAPD

EAPD

OUT1B

OUT1B

OUT2A

OUT2A

OUT2B

OUT2B

Power

Power
Device

Device

Channel 3

Channel 3

Channel 1

Channel 1

Channel 2

Channel 2

Channel 2

Channel 2

Channel 3

Channel 3

50/171 Doc ID 018835 Rev 7

STA381BW Register description: New Map

Figure 19. OPER = 01

OUT1A

OUT1A

Half

Half

Bridge

Bridge

OUT1B

OUT2B

OUT2B

OUT3A

OUT3A

OUT3B

OUT3B

OUT4A

OUT4A

OUT4B

OUT4B

OUT1B

OUT2A

OUT2A

Channel 1

Channel 1

Channel 2

Channel 2

Channel 3

Channel 3

Half

Half

Bridge

Bridge

Half

Half

Bridge

Bridge

Half

Half

Bridge

Bridge

The STA381BW can be configured to support different output configurations. For each PWM
output channel, a PWM slot is defined. A PWM slot is always 1 / (8 * fs) seconds length. The
PWM slot defines the maximum extension for the PWM rising and falling edge, that is, the
rising edge as well as the falling edge cannot range outside the PWM slot boundaries.

Figure 20. Output mapping scheme

FFX1A

FFX1A

FFX1A

FFX1A

FFX1A

FFX1A

FFX1 B

FFX1 B

FFX1 B

FFX1 B

FFX1 B

FFX1 B

FFX2 A

FFX2 A

FFX2 A

FFX2 A

FFX2 A

FFX2 A

FFX

FFX

FFX

FFX

FFX

FFX

2B

2B

2B

2B

2B

FFX ™

FFX ™

FFX ™

FFX ™

FFX ™

FFX

mo

mo

mo

mo

mo

mo

dulator

dulator

dulator

dulator

dulator

dulator

TM

2B

FFX3 A

FFX3 A

FFX3 A

FFX3 A

FFX3 A

FFX3 A

FFX3B

FFX3B

FFX3B

FFX3B

FFX3B

FFX3B

FFX4 A

FFX4 A

FFX4 A

FFX4 A

FFX4 A

FFX4 A

FFX 4B

FFX 4B

FFX 4B

FFX 4B

FFX 4B

REMAP

REMAP

REMAP

REMAP

REMAP

REMAP

OUT1A

OUT1A

OUT1A

OUT1A

OUT1A

OUT1A

OUT1B

OUT1B

OUT1B

OUT1B

OUT1B

OUT1B

OUT2A

OUT2A

OUT2A

OUT2A

OUT2A

OUT2A

OUT2B

OUT2B

OUT2B

OUT2B

OUT2B

OUT2B

OUT3A

OUT3A

OUT3A

OUT3A

OUT3A

OUT3B

OUT3B

OUT3B

OUT3B

OUT3B

OUT4A

OUT4A

OUT4A

OUT4A

OUT4A

OUT4B

OUT4B

OUT4B

OUT4B

OUT4B

Power

Power

Power

Power

Power

Power

Bridg

Bridg

Bridg

Bridg

Bridg

Bridg

OUT1A

OUT1A

OUT1A

OUT1A

OUT1A

OUT1A

OUT1B

OUT1B

OUT1B

OUT1B

OUT1B

OUT1B

e

e

e

e

e

e

OUT2A

OUT2A

OUT2A

OUT2A

OUT2A

OUT2A

OUT2

OUT2

OUT2

OUT2

OUT2

OUT2

B

B

B

B

B

B

Doc ID 018835 Rev 7 51/171

Register description: New Map STA381BW

For each configuration the PWM signals from the digital driver are mapped in different ways
to the power stage.

2.0 channels, two full-bridges (OPER = 00)

● FFX1A -> OUT1A

● FFX1B -> OUT1B

● FFX2A -> OUT2A

● FFX2B -> OUT2B

● FFX3A -> OUT3A

● FFX3B -> OUT3B

● FFX4A -> OUT4A

● FFX4B -> OUT4B

● FFX1A/1B configured as ternary

● FFX2A/2B configured as ternary

● FFX3A/3B configured as line out ternary

● FFX4A/4B configured as line out ternary

On channel 3 line out (LOC bits = 00, reg 0x17 bit D7,D6) the same data as channel 1
processing is sent. On channel 4 line out (LOC bits = 00) the same data as channel 2
processing is sent. In this configuration, neither volume control nor EQ has any effect on
channels 3 and 4.

In this configuration the PWM slot phase is the following as shown in Figure 21.

Figure 21. 2.0 channels (OPER = 00) PWM slots

OUT1A

OUT1A

OUT1B

OUT1B

OUT2A

OUT2A

OUT2B

OUT2B

OUT3A

OUT3A

OUT3B

OUT3B

OUT4A

OUT4A

OUT4B

OUT4B

52/171 Doc ID 018835 Rev 7

STA381BW Register description: New Map

2.1 channels, two half-bridges + one full-bridge (OPER = 11)

● FFX1A -> OUT1A

● FFX2A -> OUT1B

● FFX3A -> OUT2A

● FFX3B -> OUT2B

● FFX1A -> OUT3A

● FFX1B -> OUT3B

● FFX2A -> OUT4A

● FFX2B -> OUT4B

● FFX1A/1B configured as binary

● FFX2A/2B configured as binary

● FFX3A/3B configured as binary

● FFX4A/4B is not used

In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT3/OUT4
channels, channel 1 and channel 2 PWM are replicated.

In this configuration the PWM slot phase is the following as shown in Figure 22.

Figure 22. 2.1 channels (OPER = 11) PWM slots

OUT1A

OUT1A

OUT1A

OUT1A

OUT1A

OUT1A

OUT1B

OUT1B

OUT1B

OUT1B

OUT1B

OUT1B

OUT2A

OUT2A

OUT2A

OUT2A

OUT2A

OUT2A

OUT2B

OUT2B

OUT2B

OUT2B

OUT2B

OUT2B

OUT3A

OUT3A

OUT3A

OUT3A

OUT3A

OUT3A

OUT3B

OUT3B

OUT3B

OUT3B

OUT3B

OUT3B

OUT4A

OUT4A

OUT4A

OUT4A

OUT4A

OUT4B

OUT4B

OUT4B

OUT4B

OUT4B

Doc ID 018835 Rev 7 53/171

Register description: New Map STA381BW

2.1 channels, two full-bridges + one external full-bridge (OPER = 10)

● FFX1A -> OUT1A

● FFX1B -> OUT1B

● FFX2A -> OUT2A

● FFX2B -> OUT2B

● FFX3A -> OUT3A

● FFX3B -> OUT3B

● EAPD -> OUT4A

● TWARN -> OUT4B

● FFX1A/1B configured as ternary

● FFX2A/2B configured as ternary

● FFX3A/3B configured as ternary

● FFX4A/4B is not used

In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT4 channel the
external bridge control signals are muxed.

In this configuration the PWM slot phase is the following as shown in Figure 23.

Figure 23. 2.1 channels (OPER = 10) PWM slots

OUT1A

OUT1A

OUT1A

OUT1A

OUT1B

OUT1B

OUT1B

OUT1B

OUT2A

OUT2A

OUT2A

OUT2A

OUT2B

OUT2B

OUT2B

OUT2B

OUT3A

OUT3A

OUT3A

OUT3A

OUT3B

OUT3B

OUT3B

OUT3B

54/171 Doc ID 018835 Rev 7

STA381BW Register description: New Map

6.11 FUNCT register (addr 0x0A)

D7 D6 D5 D4 D3 D2 D1 D0

Reserved CRC APEQ PEQ Reserved AMDRC MDRCE DRC

00100000

Table 25. FUNCT register

Bit R/W RST Name Description

6R/W 0 CRC

5 R/W 1 APEQ

4 R/W 0 PEQ

2 R/W 0 AMDRC

1 R/W 0 MDRCE

0R/W 0 DRC

6.11.1 Dual-band DRC

The STA381BW device provides a dual-band DRC (B2DRC) on the left and right channels
data path, as depicted in Figure 24. Dual-band DRC is activated by setting MDRCE = 1.

Figure 24. B

2

DRC scheme

‘0’: disable CRC computation and comparison
‘1’: enable CRC computation and comparison

‘0’: extended BQ disabled, 8th biquadratic filter disabled
‘1’: extended BQ enabled, 8th biquadratic filter enabled

‘0’: Normal operation
‘1’: PEQ disabled, disables all biquadratic filters

‘0’: STCompressor bypassed
‘1’: STCompressor enabled

‘0’: MDRCE bypassed
‘1’: MDRCE enabled

‘0’: DRC disabled
‘1’: DRC enabled

Channel 3

Vo lume

DRC 2

B2DRC

L

R

Hi-p ass XO

fil ter

B2DRC

Hi-p ass XO

fil ter

- Channel 1
++

+

-

Vol ume

Channel 2

Vo lume

Channel 3

Vol ume

DRC 1

DRC 1

DRC 2

+

The low-frequency information (LFE) is extracted from the left and right channels, removing
the high frequencies using a programmable biquad filter, and then computing the difference

Doc ID 018835 Rev 7 55/171

Register description: New Map STA381BW

with the original signal. Limiter 1 (DRC1) is then used to control the amplitude of the
left/right high-frequency components, while limiter 2 (DRC2) is used to control the low­frequency components (see Section 6.23: Dynamic control registers (addr 0x23 - 0x26 /

addr 0x43 - 0x46)).

The cutoff frequency of the high-pass filters can be user-defined, XO[3:0] = 0, or selected
from the pre-defined values.

DRC1 and DRC2 are then used to independently limit L/R high frequencies and LFE
channel amplitude (see Section 6.23: Dynamic control registers (addr 0x23 - 0x26 / addr

0x43 - 0x46)) as well as their volume control. To be noted that, in this configuration, the

dedicated channel 3 volume control can actually act as a bass boost enhancer as well (0.5
dB/step resolution).

The processed LFE channel is then recombined with the L and R channels in order to
reconstruct the 2.0 output signal.

Sub-band decomposition

The sub-band decomposition for B2DRC can be configured specifying the cutoff frequency.
The cutoff frequency can be programmed in two ways, using the XO bits in register 0x0C, or
using the “user programmable” mode (coefficients stored in RAM addresses 0x28 to 0x31).

For the user-programmable mode, use the formulas below to compute the high-pass filters:

b0 = (1 + alpha) / 2 a0 = 1

b1 = -(1 + alpha) / 2 a1 = -alpha

b2 = 0 a2 = 0

where alpha = (1-sin(ω0))/cos(ω0), and ω0 is the cutoff frequency.

A first-order filter is recommended to guarantee that for every ω

the corresponding

0

low-pass filter obtained as difference (as shown in Figure 24) will have a symmetric (relative
to the HP filter) frequency response, and the corresponding recombination after the DRC
has low ripple. Second-order filters can be used as well, but in this case the filter shape
must be carefully chosen to provide good low-pass response and minimum ripple
recombination. For second-order filters, it is not possible to give a closed formula to get the
best coefficients, but empirical adjustment should be done.

DRC settings

The DRC blocks used by B2DRC are the same as those described in Section 6.23: Dynamic

control registers (addr 0x23 - 0x26 / addr 0x43 - 0x46). B

DRC blocks in anticlipping mode. Attack and release thresholds can be selected using
registers 0x32, 0x33, 0x34, 0x35, while attack and release rates are configured by registers
0x12 and 0x14.

2

DRC configure automatically the

Band downmixing

The low-frequency band is down-mixed to the left and right channels at the B2DRC output.
Channel volume can be used to weight the bands recombination to fine-tune the overall
frequency response.

56/171 Doc ID 018835 Rev 7

STA381BW Register description: New Map

6.12 HPCFG register (addr 0x10)

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Reserved Reserved Reserved Reserved Reserved Reserved MUTE

00000001

Table 26. HPCFG register

Bit R/W RST Name Description

0R/W 1 MUTE

‘0’: HP/Line out is ON
‘1’: HP/LIne out is muted

6.13 Configuration register A (addr 0x11)

D7 D6 D5 D4 D3 D2 D1 D0

FDRB Reserved Reserved IR1 IR0 MCS2 MCS1 MCS0

01100111

6.13.1 Master clock select

Table 27. Master clock select

Bit R/W RST Name Description

0R/W 1 MCS0

1R/W 1 MCS1

2R/W 1 MCS2

The STA381BW supports sampling rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,

176.4 kHz, and 192 kHz. Therefore the internal clock is:

● 32.768 MHz for 32 kHz

● 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz

● 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz

Selects the ratio between the input I
frequency and the input clock.

2

S sampling

The external clock frequency provided to the XTI pin or BICKI pin (depending on the MCS
settings) must be a multiple of the input sampling frequency (f

).

s

The relationship between the input clock (either XTI or BICKI) and the input sampling rate is
determined by both the MCSx and the IR (input rate) register bits. The MCSx bits determine
the PLL factor generating the internal clock and the IR bit determines the oversampling ratio
used internally. In Ta bl e 2 8 MCS 111 and 110 indicate that BICKI has to be used as the
clock source, while XTI is used in all the other cases.

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Register description: New Map STA381BW

Table 28. Input sampling rates

Input

sampling rate

IR MCS[2:0]

fs (kHz)

111 110 101 100 011 010 001 000

32, 44.1, 48 00 64*fs(*) NA 576 * fs 128 * fs 256 * fs 384 * fs 512 * fs 768 * fs

88.2, 96 01 64*fs(*) 32*fs(*) NA 64 * fs 128 * fs 192 * fs 256 * fs 384 * fs

176.4, 192 1X 64*fs(*) 32*fs(*) NA 32 * fs 64 * fs 96 * fs 128 * fs 192 * fs

Note: (*): Clock is BICKI

6.13.2 Interpolation ratio selection

Table 29. Internal interpolation ratio

Bit R/W RST Name Description

2

4:3 R/W 00 IR [1:0]

Selects internal interpolation ratio based on input I
sampling frequency

S

The STA381BW has variable interpolation (oversampling) settings such that internal
processing and FFX output rates remain consistent. The first processing block interpolates
by either 3 times (Table 83: PLL register 0x56 bits D0), 2 times or 1 time (pass-through) or
provides a 2-times downsample. The oversampling ratio of this interpolation is determined
by the IR bits.

Table 30. IR bit settings as a function of the input sampling rate

Input sampling rate fs (kHz) IR 1st stage interpolation ratio

32 00 2-times oversampling

44.1 00 2-times oversampling

48 00 2-times oversampling

88.2 01 Pass-through

96 01 Pass-through

176.4 10 2-times downsampling

192 10 2-times downsampling

6.13.3 Fault-detect recovery bypass

Table 31. Fault-detect recovery bypass

Bit R/W RST Name Description

7R/W 0 FDRB

0: fault-detect recovery enabled
1: fault-detect recovery disabled

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STA381BW Register description: New Map

The on-chip STA381BW power output block provides feedback to the digital controller using
inputs to the power control block. The FAULT input is used to indicate a fault condition (either
overcurrent or thermal). When FAULT is asserted (set to 0), the power control block attempts
a recovery from the fault by asserting the tri-state output (setting it to 0 which directs the
power output block to begin recovery), holds it at 0 for period of time in the range of 0.1 ms
to 1 second as defined by the fault-detect recovery constant register (FDRC registers 0x3C­0x3D), then toggles it back to 1. This sequence is repeated as long as the fault indication
exists. This feature is enabled by default but can be bypassed by setting the FDRB control
bit to 1.

6.14 Configuration register B (addr 0x12)

D7 D6 D5 D4 D3 D2 D1 D0

C2IM C1IM DSCKE SAIFB SAI3 SAI2 SAI1 SAI0

10000000

6.14.1 Serial data interface

The STA381BW audio serial input was designed to interface with standard digital audio
components and to accept a number of serial data formats. The STA381BW always acts as
the slave when receiving audio input from standard digital audio components. Serial data for
two channels is provided using three inputs: left/right clock LRCKI, serial clock BICKI, and
serial data 1 and 2 SDI12.

The SAI bits (D3 to D0) and the SAIFB bit (D4) are used to specify the serial data format.
The default serial data format is I

2

S, MSB-first. Available formats are shown in the tables

that follow.

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Register description: New Map STA381BW

6.14.2 Serial data first bit

Table 32. Serial data first bit

SAIFB Format

0 MSB-first

1 LSB-first

Table 33. Support serial audio input formats for MSB-first (SAIFB = 0)

BICKI SAI [3:0] SAIFB Interface format

32 * fs

0000 0 I

0001 0 Left/right-justified 16-bit data

0000 0 I2S 16- to 23-bit data

0001 0 Left-justified 16- to 24-bit data

2

S 15-bit data

48 * fs

64 * fs

0010 0 Right-justified 24-bit data

0110 0 Right-justified 20-bit data

1010 0 Right-justified 18-bit data

1110 0 Right-justified 16-bit data

0000 0 I2S 16- to 24-bit data

0001 0 Left-justified 16- to 24-bit data

0010 0 Right-justified 24-bit data

0110 0 Right-justified 20-bit data

1010 0 Right-justified 18-bit data

1110 0 Right-justified 16-bit data

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STA381BW Register description: New Map

Table 34. Supported serial audio input formats for LSB-first (SAIFB = 1)

BICKI SAI [3:0] SAIFB Interface format

32 * fs

1100 1 I

1110 1 Left/right-justified 16-bit data

0100 1 I

0100 1 I

1000 1 I

1100 1 LSB first I

0001 1 Left-justified 24-bit data

0101 1 Left-justified 20-bit data

48 * fs

1001 1 Left-justified 18-bit data

1101 1 Left-justified 16-bit data

0010 1 Right-justified 24-bit data

0110 1 Right-justified 20-bit data

1010 1 Right-justified 18-bit data

1110 1 Right-justified 16-bit data

2

S 15-bit data

2

S 23-bit data

2

S 20-bit data

2

S 18-bit data

2

S 16-bit data

0000 1 I2S 24-bit data

2

0100 1 I

1000 1 I

1100 1 LSB first I

S 20-bit data

2

S 18-bit data

2

S 16-bit data

0001 1 Left-justified 24-bit data

0101 1 Left-justified 20-bit data

64 * fs

1001 1 Left-justified 18-bit data

1101 1 Left-justified 16-bit data

0010 1 Right-justified 24-bit data

0110 1 Right-justified 20-bit data

1010 1 Right-justified 18-bit data

1110 1 Right-justified 16-bit data

To make the STA381BW work properly, the serial audio interface LRCKI clock must be
synchronous to the PLL output clock. It means that:

● the frequency of PLL clock / frequency of LRCKI = N ±4 cycles, where N depends on

the settings in Ta bl e 3 0

● the PLL must be locked.

If these two conditions are not met, and the IDE bit (reg 0x05 bit 2) is set to 1, the
STA381BW will immediately mute the I

2

S PCM data out (provided to the processing block)

and it will freeze any active processing task.

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Register description: New Map STA381BW

To avoid any audio side effects (like pop noise), it is strongly recommended to soft mute any
audio streams flowing into the STA381BW data path before the desynchronization event
happens. At the same time any processing related to the I

2

C configuration should be issued

only after the serial audio interface and the internal PLL are synchronous again.

Note: Any mute or volume change causes some delay in the completion of the I

2

C operation due
to the soft volume feature. The soft volume phase change must be finished before any clock
desynchronization.

6.14.3 Delay serial clock enable

Table 35. Delay serial clock enable

Bit R/W RST Name Description

0: No serial clock delay

5R/W 0 DSCKE

1: Serial clock delay by 1 core clock cycle to tolerate
anomalies in some I2S master devices

6.14.4 Channel input mapping

Table 36. Channel input mapping

Bit R/W RST Name Description

6R/W 0 C1IM

7R/W 1 C2IM

0: Processing channel 1 receives left I
1: Processing channel 1 receives right I

0: Processing channel 2 receives left I
1: Processing channel 2 receives right I2S input

Each channel received via I2S can be mapped to any internal processing channel via the
channel input mapping registers. This allows for flexibility in processing. The default settings
of these registers map each I

2

S input channel to its corresponding processing channel.

6.15 Configuration register C (addr 0x13)

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Reserved CSZ3 CSZ2 CSZ1 CSZ0 Reserved Reserved

10010111

6.15.1 FFX compensating pulse size register

Table 37. FFX compensating pulse size bits

Bit R/W RST Name Description

2

S input

2

S input

2

S input

2R/W 1 CSZ0

3R/W 1 CSZ1

When OM[1,0] = 11, this register determines the
size of the FFX compensating pulse from 0 clock

4R/W 1 CSZ2

ticks to 15 clock periods.

5R/W 0 CSZ3

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STA381BW Register description: New Map

Table 6:

Table 38. Compensating pulse size

CSZ[3:0] Compensating pulse size

0000 0 ns (0 ticks) compensating pulse size

0001 20 ns (1 tick) clock period compensating pulse size

……

1111 300 ns (15 ticks) clock period compensating pulse size

6.16 Configuration register D (addr 0x14)

D7 D6 D5 D4 D3 D2 D1 D0

SME ZDE Reserved BQL PSL DSPB Reserved Reserved

00011000

6.16.1 DSP bypass

Table 39. DSP bypass

Bit R/W RST Name Description

2 R/W 0 DSPB

Setting the DSPB bit bypasses the EQ function of the STA381BW.

6.16.2 Post-scale link

Table 40. Post-scale link

Bit R/W RST Name Description

3 R/W 1 PSL

Post-scale functionality can be used for power-supply error correction. For multi-channel
applications running off the same power supply, the post-scale values can be linked to the
value of channel 1 for ease of use and in order to update the values faster.

6.16.3 Biquad coefficient link

Table 41. Biquad coefficient link

Bit R/W RST Name Description

4R/W 1 BQL

0: Normal operation
1: Bypass of biquad and bass/treble functions

0: Each channel uses individual post-scale values
1: Each channel uses channel 1 post-scale values

0: Each channel uses coefficient values
1: Each channel uses channel 1 coefficient values

For ease of use, all channels can use the biquad coefficients loaded into the channel 1
coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates only have to
be performed once.

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Register description: New Map STA381BW

6.16.4 Zero-detect mute enable

Table 42. Zero-detect mute enable

Bit R/W RST Name Description

6R/W 0 ZDE

Setting of 1 enables the automatic zero-detect mute
Setting of 0 disables the automatic zero-detect mute

Refer to 6.32: Enhanced zero-detect mute and input level measurement (address 0x61-

0x65, 0x3F, 0x40, 0x6F).

6.16.5 Submix mode enable

Table 43. Submix mode enable

Bit R/W RST Name Description

7R/W 0 SME

0: Submix into left/right disabled
1: Submix into left/right enabled

6.17 Configuration register E (addr 0x15)

D7 D6 D5 D4 D3 D2 D1 D0

Reserved ZCE Reserved PWMS AME NSBW Reserved Reserved

10000010

6.17.1 Noise-shaper bandwidth selection

Table 44. Noise-shaper bandwidth selection

Bit R/W RST Name Description

2 R/W 0 NSBW

6.17.2 AM mode enable

Table 45. AM mode enable

Bit R/W RST Name Description

3R/W 0 AME

The STA381BW features an FFX processing mode that minimizes the amount of noise
generated in the frequency range of AM radio. This mode is intended for use when FFX is
operating in a device with an active AM tuner. The SNR of the FFX processing is reduced to
approximately 83 dB in this mode, which is still greater than the SNR of AM radio.

1: Third order NS
0: Fourth order NS

0: Normal FFX operation
1: AM reduction mode FFX operation

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STA381BW Register description: New Map

6.17.3 PWM speed mode

Table 46. PWM speed mode

Bit R/W RST Name Description

0: Normal speed (384 kHz) all channels

4R/W 0 PWMS

1: Odd speed (341.3 kHz) all channels. Not suitable for
binary BTL mode.

6.17.4 Zero-crossing enable

Table 47. Zero-crossing enable

Bit R/W RST Name Description

6R/W 0 ZCE

‘1’: Volume adjustment only occurs at digital zero-crossing
‘0’: Volume adjustment occur immediately

The ZCE bit enables zero-crossing adjustment. When volume is adjusted on digital zero­crossing, no clicks are audible

6.18 Configuration register F (addr 0x16)

D7 D6 D5 D4 D3 D2 D1 D0

EAPD PWDN Reserved LDTE BCLE IDE Reserved Reserved

010111

6.18.1 Invalid input detect mute enable

Table 48. Invalid input detect mute enable

Bit R/W RST Name Description

2R/W 1 IDE

Setting the IDE bit enables this function, which looks at the input I2S data and automatically
mutes if the signals are perceived as invalid.

Setting of 1 enables the automatic invalid input
detect mute

6.18.2 Binary output mode clock loss detection

Table 49. Binary output mode clock loss detection

Bit R/W RST Name Description

3 R/W 1 BCLE Binary output mode clock loss detection enable

This bit detects loss of input MCLK in binary mode and will output 50% duty cycle.

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Register description: New Map STA381BW

6.18.3 LRCK double trigger protection

Table 50. LRCK double trigger protection

Bit R/W RST Name Description

4 R/W 1 LDTE LRCLK double trigger protection enable

This bit actively prevents double triggering of LRCLK.

6.18.4 Power-down

Table 51. IC power-down

Bit R/W RST Name Description

7R/W 1 PWDN

The PWDN register is used to place the IC in a low-power state. When PWDN is written
as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted
to power down the power stage, then the master clock to all internal hardware except the I
block is gated. This places the IC in a very low power consumption state.The register state
is preserved once the device recovers from power-down.

6.18.5 External amplifier power-down

Table 52. External amplifier power-down

Bit R/W RST Name Description

7 R/W 0 EAPD

The EAPD register directly disables/enables the internal power circuitry.

When EAPD = 0, the internal power section is placed in a low-power state (disabled). This
register also controls the EAPD/FFX4B output pin when OCFG = 11.

0: IC power-down low-power condition
1: IC normal operation

0: External power stage power-down active
1: Normal operation

2

C

6.19 Volume control registers (addr 0x17 - 0x1B)

6.19.1 Mute/line output configuration register (addr 0x17)

D7 D6 D5 D4 D3 D2 D1 D0

LOC1 LOC0 Reserved Reserved C3M C2M C1M MMUTE

00000000

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STA381BW Register description: New Map

Table 53. Line output configuration

LOC[1:0] Line output configuration

00 Line output fixed - no volume, no EQ

01 Line output variable - CH3 volume effects line output, no EQ

10 Line output variable with EQ - CH3 volume effects line output

11 Reserved

Line output is only active when OCFG = 00. In this case LOC determines the line output
configuration. The source of the line output is always the channel 1 and 2 inputs.

Table 54. Mute configuration

Bit R/W RST Name Description

Channel 3 mute

3R/W 0 C3M

2R/W 0 C2M

1R/W 0 C1M

0 R/W 0 MMUTE

0 - No mute condition. It is possible to set the channel
volume

1 - Channel 3 in hardware mute

Channel 2 mute
0 - No mute condition. It is possible to set the channel

volume
1 - Channel 2 in hardware mute

Channel 1 mute
0 - No mute condition. It is possible to set the channel

volume
1 - Channel 1 in hardware mute

Master mute
0 - Normal operation
1 - All channels are in mute condition

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Register description: New Map STA381BW

6.19.2 Channel 3 / line output volume (addr 0x1B)

D7 D6 D5 D4 D3 D2 D1 D0

CH3VOL

01100000

The volume structure of the STA381BW consists of individual volume registers for each
channel and a master volume register that provides an offset to each channel’s volume
setting. The individual channel volumes are adjustable in 0.5 dB steps from +48 dB to

-80 dB.

As an example, if CH3VOL = 0x00 or +48 dB and MVOL= -12 dB, then the total gain for
channel 3 = +36 dB.

The master mute, when set to 1, mutes all channels at once, whereas the individual channel
mute (CxM) mutes only that channel. Both the master mute and the channel mutes provide
a “soft mute” with the volume ramping down to mute in 4096 samples from the maximum
volume setting at the internal processing rate (approximately 96 kHz).

A “hard (instantaneous) mute” can be obtained by programming a value of 0xFF (255) to
any channel volume register or the master volume register. When volume offsets are
provided via the master volume register, any channel whose total volume is less than -80 dB
is muted.

All changes in volume take place at zero-crossings when ZCE = 1 (Section 6.17:

Configuration register E (addr 0x15)) on a per-channel basis as this creates the smoothest

possible volume transitions. When ZCE = 0, volume updates occur immediately.

Table 55. Channel 3 volume as a function of CH3VOL[7:0]

CH3VOL[7:0] Volume

00000000 (0x00) +48 dB

00000001 (0x01) +47.5 dB

00000010 (0x02) +47 dB

……

01011111 (0x5F) +0.5 dB

01100000 (0x60) 0 dB

01100001 (0x61) -0.5 dB

……

11010111 (0xD7) -59.5 dB

11011000 (0xD8) -60 dB

11011001 (0xD9) -61 dB

11011010 (0xDA) -62 dB

……

11101100 (0xEC) -80 dB

11101101 (0xED) Hard channel mute

……

11111111 (0xFF) Hard channel mute

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STA381BW Register description: New Map

6.20 Audio preset registers (0x1D)

D7 D6 D5 D4 D3 D2 D1 D0

XO3 XO2 XO1 XO0 AMAM2 AMAM1 AMAM0 AMAME

00000000

6.20.1 AM interference frequency switching

Table 56. AM interference frequency switching bits

Bit R/W RST Name Description

Audio preset AM enable

0 R/W 0 AMAME

Table 57. Audio preset AM switching frequency selection

AMAM[2:0] 48 kHz/96 kHz input fs 44.1 kHz/88.2 kHz input fs

000 0.535 MHz - 0.720 MHz 0.535 MHz - 0.670 MHz

001 0.721 MHz - 0.900 MHz 0.671 MHz - 0.800 MHz

010 0.901 MHz - 1.100 MHz 0.801 MHz - 1.000 MHz

0: switching frequency determined by PWMS setting
1: switching frequency determined by AMAM settings

011 1.101 MHz - 1.300 MHz 1.001 MHz - 1.180 MHz

100 1.301 MHz - 1.480 MHz 1.181 MHz - 1.340 MHz

101 1.481 MHz - 1.600 MHz 1.341 MHz - 1.500 MHz

110 1.601 MHz - 1.700 MHz 1.501 MHz - 1.700 MHz

6.20.2 Bass management crossover

Table 58. Bass management crossover

Bit R/W RST Name Description

4R/W 0 XO0

5R/W 0 XO1

6R/W 0 XO2

7R/W 0 XO3

Selects the bass management crossover frequency.

st

A 1

-order high-pass filter (channels 1 and 2) or a

nd

-order low-pass filter (channel 3) at the selected

2
frequency is performed.

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Register description: New Map STA381BW

Table 59. Bass management crossover frequency

XO[3:0] Crossover frequency

0000

Table 73.: RAM block for biquads, mixing, scaling and bass
management

0001 80 Hz

0010 100 Hz

0011 120 Hz

0100 140 Hz

0101 160 Hz

0110 180 Hz

0111 200 Hz

1000 220 Hz

1001 240 Hz

1010 260 Hz

1011 280 Hz

1100 300 Hz

1101 320 Hz

1110 340 Hz

1111 360 Hz

6.21 Channel configuration registers (addr 0x1F - 0x21)

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Reserved Reserved Reserved C1BO C1VPB C1EQBP C1TCB

00000000

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Reserved Reserved Reserved C2BO C2VPB C2EQBP C2TCB

01000000

D7 D6 D5 D4 D3 D2 D1 D0

C3OM1 C3OM0 C3LS1 C3LS0 C3BO C3VPB Reserved Reserved

10000000

6.21.1 Tone control bypass

Tone control (bass/treble) can be bypassed on a per-channel basis for channels 1 and 2.

Table 60. Tone control bypass

CxTCB Mode

0 Perform tone control on channel x - normal operation

1 Bypass tone control on channel x

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STA381BW Register description: New Map

6.21.2 EQ bypass

EQ control can be bypassed on a per-channel basis for channels 1 and 2. If EQ control is
bypassed on a given channel, the prescale and all filters (biquads, bass, treble in any
combination) are bypassed for that channel.

Table 61. EQ bypass

CxEQBP Mode

0 Perform EQ on channel x - normal operation

1 Bypass EQ on channel x

6.21.3 Volume bypass

Each channel contains an individual channel volume bypass. If a particular channel has
volume bypassed via the CxVBP = 1 register, then only the channel volume setting for that
particular channel affects the volume setting, the master volume setting will not affect that
channel.

Table 62. Volume bypass register

CxVBP Mode

0 Normal volume operations

1 Volume is bypassed

6.21.4 Binary output enable registers

Each individual channel output can be set to output a binary PWM stream. In this mode
output A of a channel is considered the positive output and output B is the negative inverse.

Table 63. Binary output enable registers

CxBO Mode

0 FFX 3-state output - normal operation

1 Binary output

6.21.5 Limiter select

Limiter selection can be made on a per-channel basis according to the channel limiter select
bits. CxLS bits are not considered in case of dual-band DRC (Section 6.11.1: Dual-band

DRC), EQ DRC (Section 6.26.1: Extended post-scale range) usage.

Table 64. Channel limiter mapping as a function of C3LS bits

C3LS[1:0] Channel limiter mapping

00 Channel has limiting disabled

01 Channel is mapped to limiter #1

10 Channel is mapped to limiter #2

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Register description: New Map STA381BW

6.21.6 Output mapping

Output mapping can be performed on a per-channel basis according to the CxOM channel
output mapping bits. Each input into the output configuration engine can receive data from
any of the three processing channel outputs.

.

Table 65. Channel output mapping as a function of C3OM bits

C3OM[1:0] Channel x output source from

00 Channel1

01 Channel 2

10 Channel 3

6.22 Tone control register (addr 0x22)

D7 D6 D5 D4 D3 D2 D1 D0

TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0

01110111

6.22.1 Tone control

Table 66. Tone control boost/cut as a function of BTC and TTC bits

BTC[3:0]/TTC[3:0] Boost/cut

0000 -12 dB

0001 -12 dB

……

0111 -4 dB

0110 -2 dB

0111 0 dB

1000 +2 dB

1001 +4 dB

……

1101 +12 dB

1110 +12 dB

1111 +12 dB

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STA381BW Register description: New Map

6.23 Dynamic control registers (addr 0x23 - 0x26 / addr 0x43 ­0x46)

6.23.1 Limiter 1 attack/release rate (L1AR addr 0x23)

D7 D6 D5 D4 D3 D2 D1 D0

L1A3 L1A2 L1A1 L1A0 L1R3 L1R2 L1R1 L1R0

01101010

6.23.2 Limiter 1 attack/release threshold (L1ATRT addr 0x24)

D7 D6 D5 D4 D3 D2 D1 D0

L1AT3 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 L1RT0

01101001

6.23.3 Limiter 2 attack/release rate ( L2AR addr 0x25)

D7 D6 D5 D4 D3 D2 D1 D0

L2A3 L2A2 L2A1 L2A0 L2R3 L2R2 L2R1 L2R0

01101010

6.23.4 Limiter 2 attack/release threshold ( L2 ATRT addr 0x26)

D7 D6 D5 D4 D3 D2 D1 D0

L2AT3 L2AT2 L2AT1 L2AT0 L2RT3 L2RT2 L2RT1 L2RT0

01101001

The STA381BW includes two independent limiter blocks. The purpose of the limiters is to
automatically reduce the dynamic range of a recording to prevent the outputs from clipping
in anticlipping mode or to actively reduce the dynamic range for a better listening
environment such as a nighttime listening mode which is often needed for DVDs. The two
modes are selected via the DRC bit in Section 6.11: FUNCT register (addr 0x0A). Each
channel can be mapped to either limiter or not mapped, meaning that the channel will clip
when 0 dBfs is exceeded. Each limiter looks at the present value of each channel that is
mapped to it, selects the maximum absolute value of all these channels, performs the
limiting algorithm on that value, and then, if needed, adjusts the gain of the mapped
channels in unison.

The limiter attack thresholds are determined by the LxAT registers if the EATHx[7] (bit D7 of
register 0x43 or 0x45) bits are set to 0, else the thresholds are determined by EATHx[6:0]. It
is recommended in anticlipping mode to set this to 0 dBfs, which corresponds to the
maximum unclipped output power of an FFX amplifier. Since gain can be added digitally
within the STA381BW it is possible to exceed 0 dBfs or any other LxAT setting. When this
occurs, the limiter, when active, automatically starts reducing the gain. The rate at which the
gain is reduced when the attack threshold is exceeded is dependent upon the attack rate
register setting for that limiter. Gain reduction occurs on a peak-detect algorithm. Setting the
EATHx[7] bits to 1 selects the anticlipping mode.

The limiter release thresholds are determined by the LxRT registers if the ERTHx[7] (bit D7
of register 0x44 or 0x46) bits are set to 0, else the thresholds are determined by

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Register description: New Map STA381BW

ERTHx[6:0]. Setting the ERTHx[7] bits to 1 automatically selects the anticlipping mode. The
release of the limiter, when the gain is again increased, is dependent on an RMS-detect
algorithm. The output of the volume/limiter block is passed through an RMS filter. The output
of this filter is compared to the release threshold, determined by the release threshold
register. When the RMS filter output falls below the release threshold, the gain is again
increased at a rate dependent upon the release rate register. The gain can never be
increased past its set value and, therefore, the release only occurs if the limiter has already
reduced the gain. The release threshold value can be used to set what is effectively a
minimum dynamic range, this is helpful as overlimiting can reduce the dynamic range to
virtually zero and cause program material to sound “lifeless”.

In anticlipping mode, the attack and release thresholds are set relative to full-scale. In DRC
mode (bit D0 reg 0x0A set to 1), the attack threshold is set relative to the maximum volume
setting of the channels mapped to that limiter and the release threshold is set relative to the
maximum volume setting plus the attack threshold.

74/171 Doc ID 018835 Rev 7

STA381BW Register description: New Map

Figure 25. Basic limiter and volume flow diagram

RMS

Limiter

Gain / Volume

+

Input

Gain

Table 67. Limiter attack rate as a

function of LxA bits

Attenuatio n Saturation

Table 68. Limiter release rate as a

function of LxR bits

Output

LxA[3:0] Attack rate dB/ms LxR[3:0] Release rate dB/ms

0000 3.1584

0001 2.7072 0001 0.1370

Fast

0000 0.5116

0010 2.2560 0010 0.0744

0011 1.8048 0011 0.0499

0100 1.3536 0100 0.0360

0101 0.9024 0101 0.0299

0110 0.4512 0110 0.0264

0111 0.2256 0111 0.0208

1000 0.1504 1000 0.0198

1001 0.1123 1001 0.0172

1010 0.0902 1010 0.0147

Fast

1011 0.0752 1011 0.0137

1100 0.0645 1100 0.0134

1101 0.0564 1101 0.0117

1110 0.0501 1110 0.0110

Slow

1111 0.0451 1111 0.0104

Doc ID 018835 Rev 7 75/171

Slow

Register description: New Map STA381BW

Anticlipping mode

Table 69. Limiter attack threshold

as a function of LxAT bits
(AC mode)

LxAT[3:0] AC (dB relative to fs) LxRT[3:0] AC (dB relative to fs)

0000 -12 0000 -∞

0001 -10 0001 -29 dB

0010 -8 0010 -20 dB

0011 -6 0011 -16 dB

0100 -4 0100 -14 dB

0101 -2 0101 -12 dB

0110 0 0110 -10 dB

0111 +2 0111 -8 dB

1000 +3 1000 -7 dB

1001 +4 1001 -6 dB

1010 +5 1010 -5 dB

Table 70. Limiter release threshold

as a function of LxRT bits
(AC mode)

1011 +6 1011 -4 dB

1100 +7 1100 -3 dB

1101 +8 1101 -2 dB

1110 +9 1110 -1 dB

1111 +10 1111 -0 dB

76/171 Doc ID 018835 Rev 7

STA381BW Register description: New Map

Dynamic range compression mode

Table 71. Limiter attack threshold

as a function of LxAT
bits (DRC mode)

Table 72. Limiter release threshold

as a function of LxRT bits
(DRC mode)

LxAT[3:0] DRC (dB relative to volume) LxRT[3:0]

DRC (dB relative to volume +

0000 -31 0000 -∞

0001 -29 0001 -38 dB

0010 -27 0010 -36 dB

0011 -25 0011 -33 dB

0100 -23 0100 -31 dB

0101 -21 0101 -30 dB

0110 -19

0110 -28 dB

0111 -17 0111 -26 dB

1000 -16 1000 -24 dB

1001 -15 1001 -22 dB

1010 -14 1010 -20 dB

1011 -13 1011 -18 dB

1100 -12 1100 -15 dB

1101 -10 1101 -12 dB

1110 -7 1110 -9 dB

1111 -4 1111 -6 dB

LxAT)

6.23.5 Limiter 1 extended attack threshold (addr 0x43)

D7 D6 D5 D4 D3 D2 D1 D0

EATHEN1 EATH1[6] EATH1[5] EATH1[4] EATH1[3] EATH1[2] EATH1[1] EATH1[0]

00110000

The extended attack threshold value is determined as follows:

attack threshold = -12 + EATH1 / 4

To enable this feature, the EATHEN1 bit must be set to 1.

6.23.6 Limiter 1 extended release threshold (addr 0x44)

D7 D6 D5 D4 D3 D2 D1 D0

ERTHEN1 ERTH1[6] ERTH1[5] ERTH1[4] ERTH1[3] ERTH1[2] ERTH1[1] ERTH1[0]

00110000

The extended release threshold value is determined as follows:

release threshold = -12 + ERTH1 / 4

To enable this feature, the ERTHEN1 bit must be set to 1.

Doc ID 018835 Rev 7 77/171

Register description: New Map STA381BW

6.23.7 Limiter 2 extended attack threshold (addr 0x45)

D7 D6 D5 D4 D3 D2 D1 D0

EATHEN2 EATH2[6] EATH2[5] EATH2[4] EATH2[3] EATH2[2] EATH2[1] EATH2[0]

00110000

The extended attack threshold value is determined as follows:

attack threshold = -12 + EATH2 / 4

To enable this feature, the EATHEN2 bit must be set to 1.

6.23.8 Limiter 2 extended release threshold (addr 0x46)

D7 D6 D5 D4 D3 D2 D1 D0

ERTHEN2 ERTH2[6] ERTH2[5] ERTH2[4] ERTH2[3] ERTH2[2] ERTH2[1] ERTH2[0]

00110000

The extended release threshold value is determined as follows:

release threshold = -12 + ERTH2 / 4

To enable this feature, the ERTHEN2 bit must be set to 1.

Note: Attack/release threshold step is 0.125 dB in the range -12 dB to 0 dB.

6.24 User-defined coefficient control registers (addr 0x27 - 0x37)

6.24.1 Coefficient address register

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Reserved CFA5 CFA4 CFA3 CFA2 CFA1 CFA0

00000000

6.24.2 Coefficient b1 data register bits 23:16

D7 D6 D5 D4 D3 D2 D1 D0

C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16

00000000

6.24.3 Coefficient b1 data register bits 15:8

D7 D6 D5 D4 D3 D2 D1 D0

C1B15 C1B14 C1B13 C1B12 C1B11 C1B10 C1B9 C1B8

00000000

6.24.4 Coefficient b1 data register bits 7:0

D7 D6 D5 D4 D3 D2 D1 D0

C1B7 C1B6 C1B5 C1B4 C1B3 C1B2 C1B1 C1B0

00000000

78/171 Doc ID 018835 Rev 7

STA381BW Register description: New Map

6.24.5 Coefficient b2 data register bits 23:16

D7 D6 D5 D4 D3 D2 D1 D0

C2B23 C2B22 C2B21 C2B20 C2B19 C2B18 C2B17 C2B16

00000000

6.24.6 Coefficient b2 data register bits 15:8

D7 D6 D5 D4 D3 D2 D1 D0

C2B15 C2B14 C2B13 C2B12 C2B11 C2B10 C2B9 C2B8

00000000

6.24.7 Coefficient b2 data register bits 7:0

D7 D6 D5 D4 D3 D2 D1 D0

C2B7 C2B6 C2B5 C2B4 C2B3 C2B2 C2B1 C2B0

00000000

6.24.8 Coefficient a1 data register bits 23:16

D7 D6 D5 D4 D3 D2 D1 D0

C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16

00000000

6.24.9 Coefficient a1 data register bits 15:8

D7 D6 D5 D4 D3 D2 D1 D0

C3B15 C3B14 C3B13 C3B12 C3B11 C3B10 C3B9 C3B8

00000000

6.24.10 Coefficient a1 data register bits 7:0

D7 D6 D5 D4 D3 D2 D1 D0

C3B7 C3B6 C3B5 C3B4 C3B3 C3B2 C3B1 C3B0

00000000

6.24.11 Coefficient a2 data register bits 23:16

D7 D6 D5 D4 D3 D2 D1 D0

C4B23 C4B22 C4B21 C4B20 C4B19 C4B18 C4B17 C4B16

00000000

Doc ID 018835 Rev 7 79/171

Register description: New Map STA381BW

6.24.12 Coefficient a2 data register bits 15:8

D7 D6 D5 D4 D3 D2 D1 D0

C4B15 C4B14 C4B13 C4B12 C4B11 C4B10 C4B9 C4B8

00000000

6.24.13 Coefficient a2 data register bits 7:0

D7 D6 D5 D4 D3 D2 D1 D0

C4B7 C4B6 C4B5 C4B4 C4B3 C4B2 C4B1 C4B0

00000000

6.24.14 Coefficient b0 data register bits 23:16

D7 D6 D5 D4 D3 D2 D1 D0

C5B23 C5B22 C5B21 C5B20 C5B19 C5B18 C5B17 C5B16

00000000

6.24.15 Coefficient b0 data register bits 15:8

D7 D6 D5 D4 D3 D2 D1 D0

C5B15 C5B14 C5B13 C5B12 C5B11 C5B10 C5B9 C5B8

00000000

6.24.16 Coefficient b0 data register bits 7:0

D7 D6 D5 D4 D3 D2 D1 D0

C5B7 C5B6 C5B5 C5B4 C5B3 C5B2 C5B1 C5B0

00000000

6.24.17 Coefficient write/read control register

D7 D6 D5 D4 D3 D2 D1 D0

Reserved RA R1 WA W1

0 0000

Coefficients for user-defined EQ, mixing, scaling, and bass management are handled
internally in the STA381BW via RAM. Access to this RAM is available to the user via an I
register interface. A collection of I
coefficient base address, five sets of three store the values of the 24-bit coefficients to be
written or that were read, and one contains bits used to control the write/read of the
coefficient(s) to/from RAM.

2

C registers is dedicated to this function. One contains a

2

C

Note: The read and write operation on RAM coefficients works only if the LRCKI pin is switching.

80/171 Doc ID 018835 Rev 7

STA381BW Register description: New Map

Reading a coefficient from RAM

1. Write 6 bits of the address to I2C register 0x27.

2. Write 1 to the R1 bit in I

3. Read the top 8 bits of the coefficient in I

4. Read the middle 8 bits of the coefficient in I

5. Read the bottom 8 bits of the coefficient in I

2

C address 0x37.

2

C address 0x28.

2

C address 0x29.

2

C address 0x2A.

Reading a set of coefficients from RAM

1. Write 6 bits of the address to I2C register 0x27.

2. Write 1 to the RA bit in I

3. Read the top 8 bits of the coefficient in I

4. Read the middle 8 bits of the coefficient in I

5. Read the bottom 8 bits of the coefficient in I

6. Read the top 8 bits of coefficient b2 in I

7. Read the middle 8 bits of coefficient b2 in I

8. Read the bottom 8 bits of coefficient b2 in I

9. Read the top 8 bits of coefficient a1 in I

10. Read the middle 8 bits of coefficient a1 in I

11. Read the bottom 8 bits of coefficient a1 in I

12. Read the top 8 bits of coefficient a2 in I

13. Read the middle 8 bits of coefficient a2 in I

14. Read the bottom 8 bits of coefficient a2 in I

15. Read the top 8 bits of coefficient b0 in I

16. Read the middle 8 bits of coefficient b0 in I

17. Read the bottom 8 bits of coefficient b0 in I

2

C address 0x37.

2

C address 0x28.

2

C address 0x29.

2

C address 0x2A.

2

C address 0x2B.

2

C address 0x2C.

2

C address 0x2D.

2

C address 0x2E.

2

C address 0x2F.

2

C address 0x30.

2

C address 0x31.

2

C address 0x32.

2

C address 0x33.

2

C address 0x34.

2

C address 0x35.

2

C address 0x36.

Writing a single coefficient to RAM

1. Write 6 bits of the address to I2C register 0x27.

2. Write the top 8 bits of the coefficient in I

3. Write the middle 8 bits of the coefficient in I

4. Write the bottom 8 bits of the coefficient in I

5. Write 1 to the W1 bit in I

2

C address 0x37.

Doc ID 018835 Rev 7 81/171

2

C address 0x28.

2

C address 0x29.

2

C address 0x2A.

Register description: New Map STA381BW

Writing a set of coefficients to RAM

1. Write 6 bits of the starting address to I2C register 0x27.

2. Write the top 8 bits of coefficient b1 in I

3. Write the middle 8 bits of coefficient b1 in I

4. Write the bottom 8 bits of coefficient b1 in I

5. Write the top 8 bits of coefficient b2 in I

6. Write the middle 8 bits of coefficient b2 in I

7. Write the bottom 8 bits of coefficient b2 in I

8. Write the top 8 bits of coefficient a1 in I

9. Write the middle 8 bits of coefficient a1 in I

10. Write the bottom 8 bits of coefficient a1 in I

11. Write the top 8 bits of coefficient a2 in I

12. Write the middle 8 bits of coefficient a2 in I

13. Write the bottom 8 bits of coefficient a2 in I

14. Write the top 8 bits of coefficient b0 in I

15. Write the middle 8 bits of coefficient b0 in I

16. Write the bottom 8 bits of coefficient b0 in I

17. Write 1 to the WA bit in I

2

C address 0x37.

2

C address 0x28.

2

C address 0x29.

2

C address 0x2A.

2

C address 0x2B.

2

C address 0x2C.

2

C address 0x2D.

2

C address 0x2E.

2

C address 0x2F.

2

C address 0x30.

2

C address 0x31.

2

C address 0x32.

2

C address 0x33.

2

C address 0x34.

2

C address 0x35.

2

C address 0x36.

The mechanism for writing a set of coefficients to RAM provides a method of updating the
five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible
unpleasant acoustic side effects. When using this technique, the 6-bit address specifies the
address of the biquad b1 coefficient (for example, 0, 5, 10, 20, 35 decimal), and the
STA381BW generates the RAM addresses as offsets from this base value to write the
complete set of coefficient data.

82/171 Doc ID 018835 Rev 7

STA381BW Register description: New Map

6.24.18 User-defined EQ

The STA381BW can be programmed for four EQ filters (biquads) per each of the two input
channels. The biquads use the following equation:

Y[n] = 2 * (b

= b

/ 2) * X[n] + 2 * (b1 / 2) * X[n-1] + b2 * X[n-2] - 2 * (a1 / 2) * Y[n-1] - a2 * Y[n-2]

0

* X[n] + b1 * X[n-1] + b2 * X[n-2] - a1 * Y[n-1] - a2 * Y[n-2]

0

where Y[n] represents the output and X[n] represents the input. Multipliers are 24-bit signed
fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF
(0.9999998808).

Coefficients stored in the user-defined coefficient RAM are referenced in the following
manner:

CxHy0 = b

CxHy1 = b

1

2

/ 2

CxHy2 = -a1 / 2

CxHy3 = -a

2

CxHy4 = b0 / 2

where x represents the channel and the y the biquad number. For example, C2H41 is the b
coefficient in the fourth biquad for channel 2.

Additionally, the STA381BW can be programmed for a high-pass filter (processing
channels 1 and 2) and a low-pass filter (processing channel 3) to be used for bass­management crossover when the XO setting is 000 (user-defined). Both of these filters
when defined by the user (rather than using the preset crossover filters) are second order
filters that use the biquad equation given above. They are loaded into the C12H0-4 and
C3Hy0-4 areas of RAM noted in Tab le 7 3 .

Channel 1 and channel 2 biquads use by default the extended coefficient range (-4, +4);
Xover filters use only the standard coefficients range (-1, +1).

2

By default, all user-defined filters are pass-through where all coefficients are set to 0, except
the channel 1 and 2 b
b

/2 coefficient which is set to 0x400000 (representing 0.5).

0

6.24.19 Pre-scale

The STA381BW provides a multiplication for each input channel for the purpose of scaling
the input prior to EQ. This pre-EQ scaling is accomplished by using a 24-bit signed
fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor
for this multiplication is loaded into RAM using the same I
coefficients and the bass management. All channels can use the channel-1 pre-scale factor
by setting the biquad link bit. By default, all pre-scale factors are set to 0x7FFFFF.

6.24.20 Post-scale

The STA381BW provides one additional multiplication after the last interpolation stage and
the distortion compensation on each channel. This post-scaling is accomplished by using a
24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The
scale factor for this multiplication is loaded into RAM using the same I
biquad coefficients and the bass management. This post-scale factor can be used in
conjunction with an ADC-equipped microcontroller to perform power-supply error correction.
All channels can use the channel-1 post-scale factor by setting the post-scale link bit. By

/2 coefficient which is set to 0x100000 (representing 0.5) and Xover

0

2

C registers as the biquad

2

C registers as the

Doc ID 018835 Rev 7 83/171

Register description: New Map STA381BW

default, all post-scale factors are set to 0x7FFFFF. When line output is being used,
channel-3 post-scale will affect both channels 3 and 4.

Table 73. RAM block for biquads, mixing, scaling and bass management

Index (decimal) Index (hex) Description Coefficient Default

0 0x00

1 0x01 C1H11(b2) 0x000000

2 0x02 C1H12(a1/2) 0x000000

Channel 1 - Biquad 1

3 0x03 C1H13(a2) 0x000000

4 0x04 C1H14(b0/2) 0x100000

5 0x05 Channel 1 - Biquad 2 C1H20 0x000000

…… … … …

19 0x13 Channel 1 - Biquad 4 C1H44 0x100000

20 0x14

21 0x15 C2H11 0x000000

Channel 2 - Biquad 1

…… … … …

39 0x27 Channel 2 - Biquad 4 C2H44 0x100000

40 0x28

41 0x29 C12H1(b2) 0x000000

42 0x2A C12H2(a1/2) 0x000000

43 0x2B C12H3(a2) 0x000000

Channel 1/2 - Biquad 5

for XO = 000

nd

High-pass 2

order filter

for XO≠000

44 0x2C C12H4(b0/2) 0x400000

45 0x2D

46 0x2E C3H1(b2) 0x000000

47 0x2F C3H2(a1/2) 0x000000

48 0x30 C3H3(a2) 0x000000

Channel 3 - Biquad

for XO = 000

nd

Low-pass 2

order filter

for XO≠000

49 0x31 C3H4(b0/2) 0x400000

50 0x32 Channel 1 - Pre-Scale C1PreS 0x7FFFFF

51 0x33 Channel 2 - Pre-Scale C2PreS 0x7FFFFF

52 0x34 Channel 1 - Post-Scale C1PstS 0x7FFFFF

53 0x35 Channel 2 - Post-Scale C2PstS 0x7FFFFF

54 0x36 Channel 3 - Post-Scale C3PstS 0x7FFFFF

55 0x37 Reserved reserved 0x5A9DF7

56 0x38 Channel 1 - Mix 1 C1MX1 0x7FFFFF

57 0x39 Channel 1 - Mix 2 C1MX2 0x000000

58 0x3A Channel 2 - Mix 1 C2MX1 0x000000

59 0x3B Channel 2 - Mix 2 C2MX2 0x7FFFFF

60 0x3C Channel 3 - Mix 1 C3MX1 0x400000

61 0x3D Channel 3 - Mix 2 C3MX2 0x400000

62 0x3E UNUSED

63 0x3F UNUSED

C1H10(b1/2) 0x000000

C2H10 0x000000

C12H0(b1/2) 0x000000

C3H0(b1/2) 0x000000

84/171 Doc ID 018835 Rev 7

STA381BW Register description: New Map

6.25 Fault-detect recovery constant registers (addr 0x3C - 0x3D)

D7 D6 D5 D4 D3 D2 D1 D0

FDRC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10 FDRC9 FDRC8

00110000

D7 D6 D5 D4 D3 D2 D1 D0

FDRC7 FDRC6 FDRC5 FDRC4 FDRC3 FDRC2 FDRC1 FDRC0

00001100

The FDRC bits specify the 16-bit fault-detect recovery time delay. When FAULT is asserted,
the TRISTATE output is immediately asserted low and held low for the time period specified
by this constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The
default value of 0x300C gives approximately 1 sec.

0x0000 is a reserved value.

6.26 Extended configuration register (addr 0x47)

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Reserved PS48DB XAR1 XAR2 BQ5 BQ6 BQ7

0 000111

The extended configuration register provides access to biquad 5, 6 and 7.

6.26.1 Extended post-scale range

Table 74. Extended post-scale range

PS48DB Mode

0 Post-scale value is applied as defined in the coefficient RAM

1

Post-scale value is applied with a +48 dB offset with respect to the
coefficient RAM value

Post-scale is an attenuation by default. When PS48DB is set to 1, a 48-dB offset is applied
to the coefficient RAM value, so post-scale can act as a gain too.

6.26.2 Extended attack rate

The attack rate shown in Ta bl e 67 can be extended to provide up to an 8 dB/ms attack rate
on both limiters.

Table 75. Extended attack rate, limiter 1

XAR1 Mode

0 Limiter1 attack rate is configured using Ta b le 6 7

1 Limiter1 attack rate is 8 dB/ms

Doc ID 018835 Rev 7 85/171

Register description: New Map STA381BW

Table 76. Extended attack rate, limiter 2

XAR2 Mode

0 Limiter2 attack rate is configured using Ta b le 6 7

1 Limiter2 attack rate is 8 dB/ms

6.26.3 Extended biquad selector

Bass and treble controls can be configured as user-defined filters when the equalization
coefficients link is activated (BQL = 1) and the corresponding BQx bit is set to 1.

Table 77. Extended biquad selector, biquad 5

BQ5 Mode

0 Reserved

1 User-defined biquad 5 coefficients are selected

Table 78. Extended biquad selector, biquad 6

BQ6 Mode

0 Pre-set bass filter selected as per Ta b le 6 6

1 User-defined biquad 6 coefficients are selected

Table 79. Extended biquad selector, biquad 7

BQ7 Mode

0 Pre-set treble filter selected as per Ta b le 6 6

1 User-defined biquad 7 coefficients are selected

When filters from the 5th to 7th are configured as user-programmable, the corresponding
coefficients are stored respectively in addresses 0x20-0x24 (BQ5), 0x25-0x29 (BQ6), 0x2A­0x2E (BQ7) as given in Ta bl e 7 3 .

Note: The BQx bits are ignored if BQL = 0 or if DEMP = 1 (relevant for BQ5) or CxTCB = 1

(relevant for BQ6 and BQ7).

86/171 Doc ID 018835 Rev 7

STA381BW Register description: New Map

6.27 PLL configuration registers (address 0x52; 0x53; 0x54; 0x55; 0x56; 0x57)

D7 D6 D5 D4 D3 D2 D1 D0

PLL_FRAC[15:8]

00000000

D7 D6 D5 D4 D3 D2 D1 D0

PLL_FRAC[7:0]

00000000

D7 D6 D5 D4 D3 D2 D1 D0

PLL_DITH[1:0] PLL_NDIV[5:0]

00000000

D7 D6 D5 D4 D3 D2 D1 D0

PLL_DPD PLL_FCT PLL_STB PLL_STBBYP PLL_IDIV[3:0]

00000000

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Reserved PLL_DIRP PLL_PWD PLL_BYP OSC_PD Reserved BOOST32K

00000000

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Reserved Reserved Reserved BYPSTATE PDSTATE OSCOK LOWCK

NA NA NA NA NA NA NA NA

By default, the STA381BW is able to configure the embedded PLL automatically depending
on the MCS bits (reg 0x00). For certain applications and to provide flexibility to the user, a
manual PLL configuration can be used (setting

PLL_DIRP to ‘1’)

The output PLL frequency formula is:

Fin

NDIV()

⎛⎞

---------------------------

×

⎝⎠

IDIV 1+()

FRAC

⎛⎞

-----------------

+

⎝⎠

65536

where Fin is the input clock frequency from the pad.

Table 80. PLL factors

PLL parameter Min Max

FRAC 0 65535

IDIV 0 3

NDIV 5 55

Doc ID 018835 Rev 7 87/171

Register description: New Map STA381BW

Table 81. PLL register 0x54 bits

Bit R/W RST Name Description

7R/W 0

6R/W 0

PLL_DITH[1:0]

“00”: PLL clock dithering disabled
“01”: PLL clock dithering enabled (triangular)
“10”: PLL clock dithering enabled (rectangular)
“11”: reserved

5R/W 0

4R/W 0

3R/W 0

2R/W 0

PLL_NDIV PLL loop divider

1R/W 0

0R/W 0

Table 82. PLL register 0x55 bits

Bit R/W RST Name Description

‘0’: any PLL dividers change is implemented via PLL

7 R/W 0 PLL_DPD

6 R/W 0 PLL_FCT

5 R/W 0 PLL_STB PLL synchronous divider changes strobe

4 R/W 0 PLL_STBBYP

3R/W 0

2R/W 0

PLL_IDIV[3:0] Input PLL divider

1R/W 0

0R/W 0

power-down
‘1’: PLL divider change will happen without PLL power-

down

‘0’: PLL use integer ratio
‘1’: PLL use fractional ratio

‘0’: PLL_STB is active
‘1’: PLL_STB control is bypassed

Table 83. PLL register 0x56 bits

Bit R/W RST Name Description

5 R/W 0 PLL_DIRP

4 R/W 0 PLL_PWD

3R/W 0PLL_BYP

2R/W 0 OSC_PD

0 R/W 0 BOOST32K

‘0’: PLL configuration is determined by the MCS bits
‘1’: PLL configuration is determined by FRAC, IDIV and NDIV

‘0’: PLL normal behavior
‘1’: PLL is in power-down mode

‘0’: sys clock is from PLL
‘1’: sys clock is from external pin (PLL is bypassed)

‘0’: Normal behavior
‘1’: Internal oscillator is in power-down

‘0’: Input oversampling selected by the IR bits
‘1’: Input oversampling is selected x3

88/171 Doc ID 018835 Rev 7

STA381BW Register description: New Map

Table 84. PLL register 0x57 bits

Bit R/W RST Name Description

3 R/W BYPSTATE PLL bypass state

2 R/W PDSTATE PLL PD state

1 R/W OSCOK OSCI locked

0 R/W LOWCK Clock input low-frequency check

6.28 Short-circuit protection mode registers SHOK (address 0x58)

D7 D6 D5 D4 D3 D2 D1 D0

reserved reserved reserved reserved reserved GNDSH VCCSH OUTSH

NA NA NA NA NA NA NA NA

The following power bridge pins short-circuit protections are implemented in the
STA381BW:

● OUTxx vs. GNDx

● OUTxx vs. VCCx

● OUT1B vs. OUT2A

The protection is enabled when reg. 0x50 bit 0 (SHEN) is set to ‘1’. The protection will check
the short-circuit when the EAPD bit is toggled from ‘0’ to ‘1’ (i.e. the power bridge is switched
on), and only if the test passes (no short), does the power bridge leave the tristate condition.

Register 0x58 (read-only registers) will give more information about the detected short type.

GNDSH equal to ‘0’ means that OUTxx is shorted to ground, while the same value on
VCCSH means that OUTxx is shorted to Vcc, finally OUTSH=’0’ means that OUT1B is
shorted to OUT2A.

To be noted that once the check is performed, and the tristate released, the short protection
is not active anymore until the next EAPD 0->1 toggling which means that shorts that
happened during normal operation cannot be detected.

To be noted that register SHOK is meaningful only after the EAPD bit is set to ‘1’ at least
once.

The short-circuit protections implemented are effective only in BTL configuration, and they
must not be activated if a single-ended application scheme is needed.

Doc ID 018835 Rev 7 89/171

Register description: New Map STA381BW

Figure 26. Short-circuit detection timing diagram (no short detected)

Start out test

EAPD

OUT1A

OUT1B

OUT2A

OUT2B

GNDSH]

VCCSH

tset trohS fo dnEtset ccv tratStset dng tratS

OUTSH]

44

cycles

50005 cyc les

50005 cyc les

TBD cycles

1cycle

In Figure 26 the short protection timing diagram is shown. The time information is expressed
in clock cycles, where the clock frequency is defined as in section Section 6.13.1: Master

clock select. The gray color is used for the short status bits to indicate that the bits are

carrying the status of the previous EAPD 0->1 toggling (to be noted that after reset this state
is meaningless since no EAPD transition occurs). The GND-related SHOK bits are updated
as soon as the gnd test is completed, the VCC bits are updated after vcc test is completed,
and the SOUT bit is updated after the shorted output test is completed. The gnd test, vcc
test and output test, are always run (if the SHEN bit is active and EAPD toggled to ‘1’), and
only if both tests are successful (no short) do the bridge outputs leave the tristate (indicated
by dotted lines in the figure). If one of the three tests (or all) fail, the power bridge outputs
are kept in the tristate until the procedure is restarted with a new EAPD toggling.

In this figure EAPD is intended to be bit 7 of register 0x05.

6.29 Extended coefficient range up to -4...4 (address 0x5A)

D7 D6 D5 D4 D3 D2 D1 D0

CEXT_B4[1] CEXT_B4[0] CEXT_B3[1] CEXT_B3[0] CEXT_B2[1] CEXT_B2[0] CEXT_B1[1] CEXT_B1[0]

10101010

D7 D6 D5 D4 D3 D2 D1 D0

reserved reserved CEXT_B7[1] CEXT_B7[0] CEXT_B6[1] CEXT_B6[0] CEXT_B51] CEXT_B5[0]

00101010

Biquads from 1 to 7 have in the STA381BW the possibility to extend the coefficient range
from [-1,1) to [-4..4) which allows the use of high-shelf filters that may require a coefficient
dynamic greater in absolute value than 1.

Three ranges are available, [-1;1) [-2;2) [-4;4). By default, the extended range is activated.
Each biquad has its independent setting according to the following table.

90/171 Doc ID 018835 Rev 7

STA381BW Register description: New Map

Table 85. Coefficients extended range configuration

CEXT_Bx[1] CEXT_Bx[0] Range

00

01

10

1 1 Reserved

In this case the user can decide, for each filter stage, the right coefficient range. Note that for
a given biquad the same range will be applied to the left and right (channel 1 and channel

2).

The crossover biquad does not have the availability of this feature, maintaining the [-1;1)
range unchanged.

6.30 Miscellaneous registers (address 0x5C, 0x5D)

D7 D6 D5 D4 D3 D2 D1 D0

RPDNEN Reserved BRIDGOFF Reserved Reserved CPWMEN Reserved Reserved

01100100

D7 D6 D5 D4 D3 D2 D1 D0

LPDP LPD LPDE PNDLSL[2] PNDLSL[1] PNDLSL[0] Reserved SHEN

01001100

[-1;1)

[-2;2)

[-4;4)

6.30.1 Rate power-down enable (RPDNEN) bit

In the STA381BW, by default, the power-down pin and I2C power-down act on mute
commands to perform the fade-out. This default can be changed so that the fade-out can be
started using the master volume. The RPDNEN bit, when set, activates this feature.

6.30.2 Bridge immediately off (BRIDGOFF) bit (address 0x4B, bit D5)

A fade-out procedure is started in the STA381BW once the PWDN function is enabled, and
after 13 million clock cycles (PLL internal frequency) the bridge is put in power-down
(tristate mode). There is also the possibility to change this behavior so that the power bridge
will be switched off immediately after the PWDN pin is tied to ground, without waiting for the
13 million clock cycles. The BRIDGOFF bit, when set, activates this function. Obviously the
immediate power-down will generate a pop noise at the output, therefore this procedure
must be used only in cases where pop noise is not relevant in the application. Note that this
feature works only for hardware PWDN assertion and not for a power-down applied through
the IIC interface. Refer to Section 6.30.5 if programming a different number of clock cycles is
needed.

Doc ID 018835 Rev 7 91/171

Register description: New Map STA381BW

6.30.3 Channel PWM enable (CPWMEN) bit

This bit, when set, activates a mute output in case the volume reaches a value lower
than -76 dBFS.

6.30.4 External amplifier hardware pin enabler (LPDP, LPD LPDE) bits

Pin 42 (INTLINE), normally indicating a fault condition, using the following 3 register settings
can be reconfigured as a hardware pin enabler for an external headphone or line amplifier.

In particular the LPDE bit, when set, activates this function. Accordingly, the LPD value (0 or

1) is exported on pin 42 and in case of power-down assertion, pin 42 is tied to LPDP.

The LPDP bit, when set, negates the value programmed as the LPD value, refer to the
following table.

Table 86. External amplifier enabler configuration bits

LPDP LPD LPDE Pin 42 output

x

0

0

1

1

x0

01

11

01

11

Figure 27. Alternate function for INTLINE pin

Power Bridge Fault

‘0’

LPD

“is the device in powerdown?”

Y

N

LPDP

INT_LINE

0

1

1

0

0

0

1

LPDE

INTLIN E

1

6.30.5 Power-down delay selector (PNDLSL[2:0]) bits

The assertion of PWDN activates a counter that, by default, after 13 million clock cycles puts
the power bridge in tristate mode, independently from the fade-out time. Using these
registers it is possible to program this counter according to the following table.

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STA381BW Register description: New Map

Table 87. PNDLSL bits configuration

PNDLSL[2] PNDLSL[1] PNDLSL[2] Fade-out time

00

00

01

01

10

10

11

11 1

0 Default time (13M PLL clock cycles)

1 Default time divided by 2

0 Default time divided by 4

1 Default time divided by 8

0 Default time divided by 16

1 Default time divided by 32

0 Default time divided by 64

Default time divided by 128

6.30.6 Short-circuit check enable bit

This bit, when enabled, will activate the short-circuit checks before any power bridge
activation (EAPD bit 0->1). See section Section 6.28: Short-circuit protection mode registers

SHOK (address 0x58) for more details.

6.31 Bad PWM detection registers (address 0x5E, 0x5F, 0x60)

D7 D6 D5 D4 D3 D2 D1 D0

BPTH[5] BPTH[4] BPTH[3] BPTH[2] BPTH[1] BPTH[0] reserved reserved

00110010

D7 D6 D5 D4 D3 D2 D1 D0

BPTIM[7] BPTIM[6] BPTIM[5] BPTIM[4] BPTIM[3] BPTIM[2] BPTIM[1] BPTIM[0]

01011110

The STA381BW implements a detection on PWM outputs able to verify if the output signal
has no zero-crossing in a configurable time window. This check can be useful to detect the
DC level in the PWM outputs. To be noted that the checks are performed on logic level PWM
(i.e. not the power bridge ones, nor the PWM on DDX3 and DDX4 IOs).

In case of ternary modulation, the detection threshold is computed as:

TH=[(BPTH*2+1)/128]*100%

If the measured PWM duty cycle is detected greater than or equal to TH for more than
BPTIM PWM periods, the corresponding PWM bit will be set in register 0x01.

In case of binary modulation, there are two thresholds:

TH1=[(64+BPTH)/128]*100%

TH2=[(64-BPTH)/128]*100%

In this case if the measured PWM duty cycle is outside the TH1-TH2 range for more than
BPTIM PWM periods, the corresponding bit will be set in register 0x4E.

Doc ID 018835 Rev 7 93/171

Register description: New Map STA381BW

6.32 Enhanced zero-detect mute and input level measurement (address 0x61-0x65, 0x3F, 0x40, 0x6F)

D7 D6 D5 D4 D3 D2 D1 D0

WTHH WTHL FINETH HSEL[1:0] ZMTH[2:0]

00000111

D7 D6 D5 D4 D3 D2 D1 D0

RMS_CH0[7:0]

N/A N/A N/A N/A N/A N/A N/A N/A

D7 D6 D5 D4 D3 D2 D1 D0

RMS_CH0[15:8]

N/A N/A N/A N/A N/A N/A N/A N/A

D7 D6 D5 D4 D3 D2 D1 D0

RMS_CH1[7:0]

N/A N/A N/A N/A N/A N/A N/A N/A

D7 D6 D5 D4 D3 D2 D1 D0

RMS_CH1[15:8]

N/A N/A N/A N/A N/A N/A N/A N/A

The STA381BW implements an RMS-based zero-detect function (on serial input interface
data) able to detect in a very reliable way the presence of an input signal, so that the power
bridge outputs can be automatically connected to ground.

When active, the function will mute the output PWM when the input level becomes less than
“threshold - hysteresis”. Once muted, the PWM will be unmuted when the input level is
detected greater than “threshold + hysteresis”.

The measured level is then reported (for each input channel) on registers ZCCCFG1 ­ZCCCFG2, ZCCCFG3 - ZCCCFG4 according to the following equation:

Value_in_dB = 20*Log

Table 88. Zero-detect threshold

ZMTH[2:0] Equivalent input level (dB)

000 -78

001 -84

010 -90

011 -96

100 -102

101 -108

110 -114

111 -114

(Reg_value/(216*0.635))

10

94/171 Doc ID 018835 Rev 7

STA381BW Register description: New Map

Table 89. Zero-detect hysteresis

HSEL[1:0] Equivalent input level hysteresis(dB)

00 3

01 4

10 5

11 6

The thresholds and hysteresis table above can be overridden and the low-level threshold
and high-level threshold can be set by the MTH[21:0] bits.

To activate the manual thresholds the FINETH bit has to be set to ‘1’.

To configure the low threshold, the WTHL bit must be set to ‘1’ so that any write operation to
the MTH bits will set the low threshold.

To configure the low threshold, the WTHH bit must be set to ‘1’ so that any write operation to
the MTH bits will set the low threshold.

If the zero-mute block does not detect mute, it will mute the output when the current RMS
value falls below the low threshold.

If the zero-mute block does not detect mute, it will unmute the output when the current RMS
value rises above the high threshold.

Table 90. Manual threshold register 0x3F, 0x40 and 0x6F

D7 D6 D5 D4 D3 D2 D1 D0

ReservedT Reserved MTH[21:16]

00000000

D7 D6 D5 D4 D3 D2 D1 D0

MTH[15:8]

00000000

D7 D6 D5 D4 D3 D2 D1 D0

MTH[7:0]

00000000

Doc ID 018835 Rev 7 95/171

Register description: New Map STA381BW

6.33 Headphone/Line out configuration register (address 0x66)

D7 D6 D5 D4 D3 D2 D1 D0

HPLN Reserved Reserved Reserved CPFEN CPOK ABFAULT DCROK

00100NANANA

Table 91. Headphone/Line out configuration bits

Bit R/W RST Name Description

When F3X is connected to the internal HP/Line
driver this bit selects the gain of the F3X->analog
out path.

‘0’: HP out. When the MVOL+Channel Vol is

7R/W 0 HPLN

3 R/W 0 CPFEN

2RNA CPOK

1 R NA ABFAULT

0 R NA DCROK ‘1’: Core supply OK

0 dBFs, a 0 dBFs input will generate a 40 mW
output on a 32 ohm load (+/- 3.3V supply).

‘1’: Line out. When the MVOL+Channel Vol is
0 dBFs, a 0 dBFs input will generate a 2 Vrms
output (+/- 3.3 V supply)

‘0’: Charge pump auto-enable when unmute
‘1’: Charge pump is always enabled

‘0’: Charge pump is not working
‘1’: Charge pump is working and it is OK

‘0’: No fault on class-AB
‘1’: Overcurrent fault detected on class-AB

96/171 Doc ID 018835 Rev 7

STA381BW Register description: New Map

6.34 F3XCFG (address 0x69; 0x6A)

D7 D6 D5 D4 D3 D2 D1 D0

F3XLNK reserved reserved reserved reserved reserved reserved reserved

00000000

D7 D6 D5 D4 D3 D2 D1 D0

F3X_FAULT reserved reserved F3X_SM_SLOPE[2:0] F3X_MUTE F3X_ENA

11101110

Table 92. F3X configuration register 1

Bit R/W RST Name Description

7R/W 0 F3XLNK

‘0’: F3X normal control mode
‘1’: F3X mute/unmute linked to HP/Line mute

Table 93. F3X configuration register 2

Bit R/W RST Name Description

7 R 1 F3X_FAULT ‘0’: Normal operation

4R/W 0

3R/W 1

F3X_SM_SLOPE

2R/W 1

1 R/W 1 F3X_MUTE ‘1’: Mute

0 R/W 0 F3X_ENA ‘1’: F3X enable

‘000’: 0 ms
‘001’: 25 ms
‘010’: 50 ms
‘011’: 100 ms
‘100’: 200 ms
‘101’: 250 ms
‘110’: 500 ms
‘111’: 1000 ms

Doc ID 018835 Rev 7 97/171

Register description: New Map STA381BW

6.35 STCompressorTM configuration register (address 0x6B; 0x6C)

Table 94. Register STCCFG0

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Reserved Reserved Reserved Reserved CRC_RES Reserved Reserved

00010000

Table 95. STCCFG0 register

Bit R/W RST Name Description

2 R/W 0 CRC_RES

‘0’ = CRC comparison successful
‘1’ = CRC comparison error

Table 96. Register STCCFG1

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Reserved Reserved Reserved Reserved Reserved STC_LNK Reserved

00000000

Table 97. STCCFG1 register

Bit R/W RST Name Description

‘0’ = normal operations

1R/W 0 STC_LNK

‘1’ = stereo link enabled. See

Stereo link

6.36 Charge pump synchronization (address 0x70)

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Reserved CHPI INITCNT[3:0] CHPRD

00011001

Table 98. Charge pump sync configuration bits

Bit R/W RST Name Description

Section 4.3.8:

5 R/W 0 CHPI

‘0’: Charge pump phase: 0 deg
‘1’: Charge pump phase: 180 deg

4R/W 1

3R/W 1

INITCNT[3:0] Change charge pump phase at one clock step

2R/W 0

1R/W 0

0 R/W 1 CHPRD

‘0’: Charge pump synchronized with PWM frame
‘0’: Charge pump not synchronized with PWM frame

98/171 Doc ID 018835 Rev 7

STA381BW Register description: New Map

The charge pump can be synchronized with the PWM frame in order to minimize the
crosstalk between the charge pump and the PWM waveform.

This functionality cannot be activated when the PWMS bit (address 0x15 bit D4) is set to 1.

6.37 Coefficient RAM CRC protection (address 0x71-0x7D)

D7 D6 D5 D4 D3 D2 D1 D0

BQCKE[7] BQCKE[6] BQCKE[5] BQCKE[4] BQCKE[3] BQCKE[2] BQCKE[1] BQCKE[0]

00000000

D7 D6 D5 D4 D3 D2 D1 D0

BQCKE[15] BQCKE[14] BQCKE[13] BQCKE[12] BQCKE[11] BQCKE[10] BQCKE[9] BQCKE[8]

00000000

D7 D6 D5 D4 D3 D2 D1 D0

BQCKE[23] BQCKE[22] BQCKE[21] BQCKE[20] BQCKE[19] BQCKE[18] BQCKE[17] BQCKE[16]

00000000

D7 D6 D5 D4 D3 D2 D1 D0

XCCKE[7] XCCKE[6] XCCKE[5] XCCKE[4] XCCKE[3] XCCKE[2] XCCKE[1] XCCKE[0]

00000000

D7 D6 D5 D4 D3 D2 D1 D0

XCCKE[15] XCCKE[14] XCCKE[13] XCCKE[12] XCCKE[11] XCCKE[10] XCCKE[9] XCCKE[8]

00000000

D7 D6 D5 D4 D3 D2 D1 D0

XCCKE[23] XCCKE[22] XCCKE[21] XCCKE[20] XCCKE[19] XCCKE[18] XCCKE[17] XCCKE[16]

00000000

D7 D6 D5 D4 D3 D2 D1 D0

BQCKR[7] BQCKR[6] BQCKR[5] BQCKR[4] BQCKR[3] BQCKR[2] BQCKR[1] BQCKR[0]

00000000

D7 D6 D5 D4 D3 D2 D1 D0

BQCKR[15] BQCKR[14] BQCKR[13] BQCKR[12] BQCKR[11] BQCKR[10] BQCKR[9] BQCKR[8]

00000000

D7 D6 D5 D4 D3 D2 D1 D0

BQCKR[23] BQCKR[22] BQCKR[21] BQCKR[20] BQCKR[19] BQCKR[18] BQCKR[17] BQCKR[16]

00000000

D7 D6 D5 D4 D3 D2 D1 D0

XCCKR[23] XCCKR[22] XCCKR[21] XCCKR[20] XCCKR[19] XCCKR[18] XCCKR[17] XCCKR[16]

00000000

D7 D6 D5 D4 D3 D2 D1 D0

XCCKR[23] XCCKR[22] XCCKR[21] XCCKR[20] XCCKR[19] XCCKR[18] XCCKR[17] XCCKR[16]

00000000

D7 D6 D5 D4 D3 D2 D1 D0

XCCKR[23] XCCKR[22] XCCKR[21] XCCKR[20] XCCKR[19] XCCKR[18] XCCKR[17] XCCKR[16]

Doc ID 018835 Rev 7 99/171

Register description: New Map STA381BW

D7 D6 D5 D4 D3 D2 D1 D0

00000000

D7 D6 D5 D4 D3 D2 D1 D0

XCAUTO XCRES XCCMP XCGO BCAUTO BCCRES BCCMP BCCGO

00000000

The STA381BW implements an automatic CRC computation for the biquad and
MDRC/XOver coefficient memory (Ta bl e 7 3). Memory cell contents from address 0x00 to
0x27 will be bit XORed to obtain the BQCHKE checksum, while cells from 0x28 to 0x31 will
be XORed to obtain the XCCHKE checksum. Both checksums (24-bit wide) are exported on

2

I

C registers from 0x60 to 0x65. The checksum computation will start as soon as the BCGO
(for biquad RAM bank) or the XCGO bit (for MDRC/XOver coefficients) is set to 1. The
checksum is computed at the processing sample rate if the IR bits equal “01” or “10”,
otherwise the checksum is computed to half of the processing sample rate.

When BCCMP or XCCMP is set to ‘1’, the relative checksum (BQCHKE and XCCHKE) is
continuously compared with BQCHKR and XCCHKR respectively. If the checksum matches
its own reference value, the respective result bits (BCRES and XCRES) will be set to ‘0’.
The compare bits have no effect if the respective GO bit is not set.

In case of checksum errors (i.e. the internally computed didn’t match the reference), an
automatic device reset action can be activated. This function is enabled when the BCAUTO
or XCAUTO bit is set to ‘1’. The automatic reset bits have no effect if the respective compare
bits are not set.

The recommended procedure for automatic reset activation is the following:

● Download the set of coefficients (RAM locations 0x00…0x27)

● Download the externally computed biquad checksum into registers BQCHKR

● Enable the checksum of the biquad coefficients by setting the BCGO bit. The

checksum will start to be automatically computed by the STA381BW and its value
exposed on registers BQCHECKE. The checksum value is computed and updated.

● Enable the checksum comparison by setting the BCCMP bit. The internally computed

checksum will start to be compared with the reference one and the result will be
exposed on the BCRES bit. The following operation will be executed on each audio
frame:

if ((BQCHKE == BQCHKR))

{

BC_RES = 0;// Checksum is ok, reset the error bit

}

100/171 Doc ID 018835 Rev 7