ST STA369BWS User Manual

2.1-channel 40-watt high-efficiency digital audio system

Features

 Wide-range supply voltage, 4.5 V to 21.5 V

 Three power output configurations:

– 2 channels of ternary PWM

(2 x 20 W into 8 Ω at 18 V) + PWM output

– 2 channels of ternary PWM

(2 x 20 W into 8 Ω at 18 V) + ternary stereo line-out

– 2.1 channels of binary PWM (left, right,

LFE) (2 x 9 W into 4 Ω +1 x 20 W into 8 Ω at 18 V)

 FFX with 100-dB SNR and dynamic range

 Scalable FFX modulation index (up to 100%)

 Selectable 32- to 192-kHz input sample rates

2

 I

C control with selectable device address

 Digital gain/attenuation +48 dB to -80 dB with

0.125-dB/step resolution

 Soft volume update with programmable ratio

 Individual channel and master gain/attenuation

 Two independent DRCs configurable as a

dual-band anti-clipper (B independent limiters/compressors with optional global DRC capability

 EQ-DRC for DRC based on filtered signals

 Dedicated LFE processing for bass boosting

with 0.125-dB/step resolution

 Audio presets:

– 15 preset crossover filters – 5 preset anti-clipping modes – Preset night-time listening mode

 Individual channel soft/hard mute

 Independent channel volume and DSP bypass

2

 I

S input data interface

 Input and output channel mapping

2

DRC) or as

STA369BWS

Sound Terminal™

PowerSSO-36 with exposed pad down (EPD)

 Automatic invalid input-detect mute

 Up to 8 user-programmable biquads/channel

 Three coefficients banks for EQ presets storing

with fast recall via I

 Extended filter dynamics +4/-4 for better sound

shaping and easier filter implementation

 Bass/treble tones and de-emphasis control

 Selectable high-pass filter for DC blocking

 Advanced AM interference frequency

switching and noise suppression modes

 F3X™ advanced PWM modulation scheme for

carrier suppression (headphone or line output)

 Selectable high- or low-bandwidth

noise-shaping topologies

 Selectable clock input ratio

 96-kHz internal processing sample rate with

quantization error noise shaping for very low cut-off frequency filters

 Thermal overload and short-circuit protection

embedded

 Video apps: 576 x f

 PCB manufacturing short-circuit protection

technology

Table 1. Device summary

Order code Package Packaging

STA369BWS PowerSSO-36 EPD Tube

STA369BWSTR PowerSSO-36 EPD Tape and reel

2

C interface

input mode supported

S

November 2010 Doc ID 16861 Rev 4 1/89

www.st.com

89

Contents STA369BWS

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 2. Pin connection PowerSSO-36 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 3. Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 4. Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 5. Power-off sequence for pop-free turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 6. Left and right processing, section 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 7. Left and right processing, section 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 8. Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 9. Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 10. OCFG = 00 (default value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 11. OCFG = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 12. OCFG = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 13. OCFG = 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 14. Output mapping scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 15. 2.0 channels (OCFG = 00) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 16. 2.1 channels (OCFG = 01) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 17. 2.1 channels (OCFG = 10) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 18. Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 19. B

Figure 20. EQDRC scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 21. Extra resolution volume scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 22. Short-circuit detection timing diagram (no short detected) . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 23. Biquad filter structure with quantization-error noise shaping . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 24. External active filter with connection for F3X output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 25. Alternate function for INT_LINE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 26. Global DRC after B2DRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 27. Applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 28. Output configuration for stereo BTL mode (R

Figure 29. PowerSSO-36 power derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 30. PowerSSO-36 EPD outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

2

DRC scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

= 8 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

L

6/89 Doc ID 16861 Rev 4

STA369BWS List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 5. Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 6. Electrical specifications - digital section (T

Table 7. Electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 8. Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 9. Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 10. Input sampling rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 11. Internal interpolation ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 12. IR bit settings as a function of input sample rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 13. Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 14. Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 15. Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 16. Serial audio input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 17. Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 18. Support serial audio input formats for MSB-first (SAIFB = 0) . . . . . . . . . . . . . . . . . . . . . . . 29

Table 19. Supported serial audio input formats for LSB-first (SAIFB = 1) . . . . . . . . . . . . . . . . . . . . . 29

Table 20. Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 21. Channel input mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 22. FFX power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 23. FFX compensating pulse size bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 24. Compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 25. Overcurrent warning bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 26. High-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 27. De-emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 28. DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 29. Postscale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 30. Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 31. Dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 32. Zero-detect mute enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 33. Submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 34. Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 35. Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 36. Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 37. AM mode enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 38. PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 39. Distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 40. Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 41. Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 42. Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 43. Output configuration engine selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 44. Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 45. Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 46. LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 47. Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 48. IC power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

= 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

amb

Doc ID 16861 Rev 4 7/89

List of tables STA369BWS

Table 49. External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 50. Line output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 51. Master volume offset as a function of MVOL[7:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 52. Channel volume as a function of CxVOL[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 53. Audio preset gain compression/limiters selection for AMGC[3:2] = 00. . . . . . . . . . . . . . . . 47

Table 54. AM interference frequency switching bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 55. Audio preset AM switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 56. Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 57. Bass management crossover frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 58. Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 59. EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 60. Volume bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 61. Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 62. Channel limiter mapping as a function of CxLS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 63. Channel output mapping as a function of CxOM bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 64. Tone control boost/cut as a function of BTC and TTC bits . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 65. Limiter attack rate vs LxA bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 66. Limiter release rate vs LxR bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 67. Limiter attack threshold vs LxAT bits (AC mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 68. Limiter release threshold vs LxRT bits (AC mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 69. Limiter attack threshold vs LxAT bits (DRC mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 70. Limiter release threshold vs LxRT bits (DRC mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 71. RAM block for biquads, mixing, scaling, bass management. . . . . . . . . . . . . . . . . . . . . . . . 61

Table 72. Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 73. EQ RAM select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 74. Anti clipping and DRC preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 75. Anti-clipping selection for AMGC[3:2] = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 76. Bit PS48DB description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 77. Bit XAR1 description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 78. Bit XAR2 description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 79. Bit BQ5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 80. Bit BQ6 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 81. Bit BQ7 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 82. Bit SVUPE description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 83. Bit SVDWE description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 84. Bits CxVR description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 85. Bits VRESEN and VRESTG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 86. Coefficients extended range configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 87. F3X bits configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 88. External amplifier enabler configuration bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 89. PNDLSL bits configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 90. PowerSSO-36 EPD dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 91. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

8/89 Doc ID 16861 Rev 4

STA369BWS Description

1 Description

The STA369BWS is an integrated solution of digital audio processing, digital amplifier controls and power output stage to create a high-power single-chip FFX digital amplifier with high-quality and high-efficiency. Three channels of FFX processing are provided. The FFX processor implements the ternary, binary and binary differential processing capabilities of the full FFX processor.

The STA369BWS is part of the Sound Terminal™ family that provides full digital audio streaming to the speakers and offers cost effectiveness, low power dissipation and sound enrichment.

The power section consists of four independent half-bridges. These can be configured via digital control to operate in different modes.

For example, 2.1 channels can be provided by two half-bridges and a single full-bridge, supplying up to 2 x 9 W + 1 x 20 W of output power or two channels can be provided by two full-bridges, supplying up to 2 x 20 W of output power.

The IC can also be configured as 2.1 channels with 2 x 20 W supplied by the device plus a drive for an external FFX power amplifier, such as STA533WF or STA515W.

Also provided in the STA369BWS are a full assortment of digital processing features. This includes up to 8 programmable biquads (EQ) per channel. Special digital signal processing techniques are available to manage low-frequency quantization noise in filters with very low cut-off frequencies. The coefficient range -4 to +4 allows easy high-shelf filter usage and better sound shaping. Available presets enable a time-to-market advantage by substantially reducing the amount of software development needed for functions such as audio preset volume loudness, preset volume curves and preset EQ settings. There are also new advanced AM radio interference reduction modes. Dual-band DRC dynamically equalizes the system to provide linear frequency speaker response regardless of output power level. This feature separates the audio frequency band into two sub-bands independently processed to provide better sound clarity and to avoid speaker saturation.

The serial audio data input interface accepts all possible formats, including the popular I format. The high-quality conversion from PCM audio to FFX PWM switching provides over 100 dB of SNR and of dynamic range.

2

S

The new F3X™ modulation is capable of digitally filtering the PWM carrier to simplify external filtering requirements, AM interference and EMI. F3X™ is implemented in the auxiliary output of STA369BWS and it is specifically designed for application where a simple op-amp can be used to drive an auxiliary headphone line.

Doc ID 16861 Rev 4 9/89

Description STA369BWS

Figure 1. Block diagram

I2S

interface

Volume

control

PLL

FFX

I2C

Power control

Protection

current/thermal

Logic

Regulators

Bias

Channel

1A

Channel

1B

Channel

2A

Channel

2B

PowerDigital DSP

10/89 Doc ID 16861 Rev 4

STA369BWS Pin connections

2 Pin connections

2.1 Connection diagram

Figure 2. Pin connection PowerSSO-36 (top view)

GND_SUB

SA

TEST_MODE

VSS

VCC_REG

OUT2B

GND2

VCC2

OUT2A

OUT1B

VCC1

GND1

OUT1A

GND_REG

VDD

CONFIG

OUT3B / FFX3B

OUT3A / FFX3A

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

EP, exposed pad (device ground)

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

D05AU1638

VDD_DIG

GND_DIG

SCL

SDA

INT_LINE

RESET

SDI

LRCKI

BICKI

XTI

GND_PLL

FILTER_PLL

VDD_PLL

PWRDN

GND_DIG

VDD_DIG

TWARN / OUT4A

EAPD / OUT4B

2.2 Pin description

Table 2. Pin description

Pin Type Name Description

1 GND GND_SUB Substrate ground

2I SA I

3 I TEST_MODE This pin must be connected to ground (pull-down)

4 I/O VSS Internal reference at V

5 I/O VCC_REG Internal V

6 O OUT2B Output half-bridge channel 2B

7 GND GND2 Power negative supply

8 Power VCC2 Power positive supply

9 O OUT2A Output half-bridge channel 2A

10 O OUT1B Output half-bridge channel 1B

2

C select address (pull-down)

- 3.3 V

CC

reference

CC

Doc ID 16861 Rev 4 11/89

Pin connections STA369BWS

Table 2. Pin description (continued)

Pin Type Name Description

11 Power VCC1 Power positive supply

12 GND GND1 Power negative supply

13 O OUT1A Output half-bridge channel 1A

14 GND GND_REG Internal ground reference

15 Power VDD Internal 3.3 V reference voltage

16 I CONFIG Parallel mode command

17 O OUT3B / FFX3B PWM out channel 3B / external bridge driver

18 O OUT3A / FFX3A PWM out channel 3A / external bridge driver

19 O EAPD / OUT4B Power down for external bridge / PWM out channel 4B

20 I/O TWARN / OUT4A

21 Power VDD_DIG Digital supply voltage

22 GND GND_DIG Digital ground

23 I PWRDN Power down (pull-up)

24 Power VDD_PLL Positive supply for PLL

Thermal warning from external bridge (pull-up when input) / PWM out channel 4A

25 I FILTER_PLL Connection to PLL filter

26 GND GND_PLL Negative supply for PLL

27 I XTI PLL input clock

2

28 I BICKI I

29 I LRCKI I

30 I SDI I

S serial clock

2

S left/right clock

2

S serial data channels 1 and 2

31 I RESET Reset (pull-up)

32 O INT_LINE Fault interrupt

2

33 I/O SDA I

34 I SCL I

C serial data

2

C serial clock

35 GND GND_DIG Digital ground

36 Power VDD_DIG Digital supply voltage

- - EP Exposed pad for PCB heatsink, to be connected to GND

12/89 Doc ID 16861 Rev 4

STA369BWS Electrical specifications

3 Electrical specifications

3.1 Absolute maximum ratings

Table 3. Absolute maximum ratings

Symbol Parameter Min Typ Max Unit

V

CC

V

DD

V

DD

T

Operating junction temperature -20 - 150 °C

op

Storage temperature -40 - 150 °C

T

stg

Power supply voltage (pins VCCx) -0.3 - 24 V

Digital supply voltage (pins VDD_DIG) -0.3 - 4.0 V

PLL supply voltage (pin VDD_PLL) -0.3 - 4.0 V

Warning: Stresses beyond those listed in Table 3 above may cause

permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended operating conditions” are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. In the real application, power supplies with nominal values rated within the recommended operating conditions, may experience some rising beyond the maximum operating conditions for a short time when no or very low current is sinked (amplifier in mute state). In this case the reliability of the device is guaranteed, provided that the absolute maximum ratings are not exceeded.

3.2 Thermal data

Table 4. Thermal data

R

th j-case

T

th-sdj

T

th-w

T

th-sdh

R

th j-amb

1. See Chapter 8: Package thermal characteristics on page 85 for details.

Thermal resistance junction-case (thermal pad) - - 1.5 °C/W

Thermal shut-down junction temperature - 150 - °C

Thermal warning temperature - 130 - °C

Thermal shut-down hysteresis - 20 - °C

Thermal resistance junction-ambient

Parameter Min Typ Max Unit

(1)

-24-°C/W

Doc ID 16861 Rev 4 13/89

Electrical specifications STA369BWS

3.3 Recommended operating conditions

Table 5. Recommended operating condition

Symbol Parameter Min Typ Max Unit

V

CC

V

DD_DIG

V

DD_PLL

T

amb

Power supply voltage (VCCxA, VCCxB) 4.5 - 21.5 V

Digital supply voltage 2.7 3.3 3.6 V

PLL supply voltage 2.7 3.3 3.6 V

Ambient temperature -20 - 70 °C

3.4 Electrical specifications for the digital section

Table 6. Electrical specifications - digital section (T

Symbol Parameter Conditions Min Typ Max Unit

I

il

I

ih

V

il

V

ih

V

ol

V

oh

R

pu

Low level input current without pull-up/down device

High level input current without pull-up/down device

Low level input voltage - - -

High level input voltage -

Low level output voltage Iol = 2 mA -

High level output voltage Ioh = 2 mA

Equivalent pull-up/down resistance

Vi = 0 V --1 µA

Vi = VDD_DIG = 3.6 V

--50-kΩ

= 25 °C)

amb

--1µA

0.8 *

VDD_DIG

0.8 *

VDD_DIG

--V

0.2 *

VDD_DIG

0.4 *

VDD_DIG

V

14/89 Doc ID 16861 Rev 4

STA369BWS Electrical specifications

3.5 Electrical specifications for the power section

The specifications given in this section are valid for the operating conditions: VCC=18V, f=1kHz, f

Table 7. Electrical specifications - power section

Symbol Parameter Conditions Min Typ Max Unit

= 384 kHz, T

sw

= 25 °C and RL = 8 Ω, unless otherwise specified.

amb

Output power BTL

W

THD = 10% - 20 -

Po

THD = 1% - 16 -

Output power SE

R

dsON

Power P-channel or N-channel MOSFET ld = 0.75 A - - 250 mΩ

gP Power P-channel RdsON matching l

gN Power N-channel RdsON matching l

Idss Power P-channel/N-channel leakage V

t

r

t

f

Rise time

Fall time - - 10 ns

THD = 1%,R

THD = 10%,R

= 0.75 A - 100 - %

d

= 0.75 A - 100 - %

d

= 20 V - - 1 µA

CC

Resistive load, see Figure 3 below

= 4 Ω -7-

L

= 4 Ω -9-

L

- - 10 ns

W

Supply current from VCC in power down PWRDN = 0 - 0.3 - µA

I

VCC

I

VDD

I

LIM

I

SCP

V

t

min

UVP

Supply current from V

Supply current FFX processing

Overcurrent limit

in operation PWRDN = 1 - 15 - mA

CC

Internal clock =

49.152 MHz

(1)

-55-mA

2.2 3.0 - A

Short -circuit protection RL = 0 Ω 2.7 3.6 - A

Undervoltage protection - - - 4.3 V

Output minimum pulse width No load 20 40 60 ns

DR Dynamic range - - 100 - dB

Signal to noise ratio, ternary mode A-Weighted - 100 - dB

SNR

Signal to noise ratio binary mode - - 90 - dB

FFX stereo mode,

THD+N Total harmonic distortion + noise

Po = 1 W

-0.2-%

f=1kHz

FFX stereo mode, <5 kHz

X

TA LK

Crosstalk

One channel driven

-80-dB

at 1 W, other channel measured

Peak efficiency, FFX mode

η

Peak efficiency, binary modes

Po = 2 x 2 0 W into 8 Ω

Po = 2 x 9 W into 4 Ω + 1 x 20 W into 8 Ω

-90-

%

-87-

1. Limit the current if overcurrent warning detect adjustment bypass is enabled (register bit CONFC.OCRB on

page 32). When disabled refer to I

SCP

.

Doc ID 16861 Rev 4 15/89

Electrical specifications STA369BWS

Figure 3. Test circuit

Low current dead time = MAX(DTr, DTf)

Duty cycle = 50%

INxY

gnd

+Vcc

OUTxY

DTr DTf

Rload = 8

Ω

vdc = Vcc/2

+

-

Vcc

(3/4)Vcc

(1/2)Vcc

(1/4)Vcc

t

16/89 Doc ID 16861 Rev 4

STA369BWS Electrical specifications

3.6 Power on/off sequence

Figure 4. Power-on sequence

VCC

VDD_Dig

XTI

Reset

2

C

I

PWDN

Note: no specific VCC and VDD_DIG turn is required

Don’t care

−

on sequence

TR

Don’t care

TC

CMD0 CMD1 CMD2

TR = minimum time between XTI master clock stable and Reset removal: 1 ms TC = minimum time between Reset removal and I

Note: The definition of a stable clock is when f

Section : Serial data interface on page 28 gives information on setting up the I

Figure 5. Power-off sequence for pop-free turn-off

VCC

VDD_Dig

XTI

Soft Mute

Reg. 0x07

Reg. 0x07 Data 0xFE

Data 0xFE

Soft EAPD

Reg. 0x05

Reg. 0x05 Bit 7 = 0

Bit 7 = 0

Don’t care

2

C program, sequence start: 1ms

- f

max

< 1 MHz.

min

FE

2

S interface.

Note: no specific VCC and VDD_DIG turn is required

Don’t care

−

off sequence

Don’t care

Doc ID 16861 Rev 4 17/89

Processing data paths STA369BWS

4 Processing data paths

Figure 6 and Figure 7 below show the data processing paths inside STA369BWS. The

whole processing chain is composed of two consecutive sections. In the first one, dual-channel processing is implemented and in the second section each channel is fed into the post-mixing block either to generate a third channel (typically used in 2.1 output configuration and with crossover filters enabled) or to have the channels processed by the dual-band DRC block (2.0 output configuration with crossover filters used to define the cut-off frequency of the two bands).

The first section, Figure 6, begins with a 2x oversampling FIR filter providing 2 * f

audio

S

processing. Then a selectable high-pass filter removes the DC level (enabled if HPB = 0). The left and right channel processing paths can include up to 8 filters, depending on the selected configuration (bits BQL, BQ5, BQ6, BQ7 and XO[3:0]). By default, four user programmable, independent filters per channel are enabled, plus the preconfigured de-emphasis, bass and treble controls (BQL = 0, BQ5 = 0, BQ6 = 0, BQ7 = 0).

If the coefficient sets for the two channels are linked (BQL = 1) it is possible to use the de-emphasis, bass and treble filters in a user defined configuration (provided the relevant BQx bits are set). In this case both channels use the same processing coefficients and can have up to seven filters each. If BQL = 0 the BQx bits are ignored and the fifth, sixth and seventh filters are configured as de-emphasis, bass and treble controls, respectively.

Figure 6. Left and right processing, section 1

Sampling

Sampling frequency=Fs

frequency=Fs

From

From I2S input

I2S input

I2S input interface

interface

sampling

x2

FIR

x2

over

FIR

FIR over

over

x2

FIR

x2

over

FIR

FIR over

over

Sampling

Sampling frequency=2xFs

frequency=2xFs

Hi-Pass

PreScale

If HPB=0

Hi-Pass

PreScale

Filter

Biquad#1Biquad#2Biquad#3Biquad

User Defined Filters

If DSPB=0 and C1EQBP=0

Biquad#1Biquad#2Biquad#3Biquad

#4

If BQ5=1

and BQL=1

Biquad

#5

De-Emph.

If DEMP=0

If BQ5=1

and BQL=1

Biquad

#5

De-Emph.

IF BQ7=1

If BQ6=1

and BQL=1

If C1TCB=0

If C1TCB=0 BTC: Bass Boost/Cut

BTC: Bass Boost/Cut TTC: Treble Boost/Cut

TTC: Treble Boost/Cut

If BQ6=1

and BQL=1

Biquad

#6

Bass Treble

IF BQ7=1

and BQL=1

Biquad

#6

Bass Treble

#7

L

R

L

R

If HPB=0

User Defined Filters

If DSPB=0 and C2EQBP=0

Moreover, the common 8th filter can be available on both channels provided the predefined crossover frequencies are not used, XO[3:0] = 0, and the dual-band DRC is not used.

In the second section, Figure 7, mixing and crossover filters are available. If B enabled they are fully user-programmable and allow the generation of a third channel (2.1 outputs). Alternatively, in mode B

2

DRC, these blocks are used to split the sub-band and define the cut-off frequencies of the two bands. A prescaler and a final postscaler allow full control over the signal dynamics before and after the filtering stages. A mixer function is also available.

18/89 Doc ID 16861 Rev 4

If DEMP=0

If C2TCB=0

If C2TCB=0 BTC: Bass Boost/Cut

BTC: Bass Boost/Cut TTC: Treble Boost/Cut

TTC: Treble Boost/Cut

2

DRC is not

STA369BWS Processing data paths

In all the available configurations high-pass filtering with a 2-Hz cut-off frequency is applied before the postscale block. This filter cannot be disabled.

Figure 7. Left and right processing, section 2

Dual-band DRC enabled

CH3

Volume

C1Mx1

C1Mx1=

C1Mx1

C1Mx1= 0x7fffff

L

R

0x7fffff

C1Mx2

C1Mx2=

C1Mx2

C1Mx2= 0x00000

0x00000

C2Mx1

C2Mx1=

C2Mx1

C2Mx1= 0x000000

0x000000

C2Mx2

C2Mx2=

C2Mx2

C2Mx2= 0x7fffff

0x7fffff

C3Mx1

C3Mx1=

C3Mx1

C3Mx1= 0x40000

0x40000

C3Mx2

C3Mx2=

C3Mx2

C3Mx2= 0x400000

0x400000

Hi-Pass XO

B2DRC

Filter

+

Filter

Hi-pass

filter

Hi-Pass XO

B2DRC

Filter

Hi-pass

filter

-

-++

+

-

-++

+

CH1

Volume

CH2

Volume

CH3

Volume

DRC2

DRC1

Limiter

DRC1

DRC2

Vol

Vol And

And

+

Post scale

DC cut

filter

Post scale

DC cut

filter

Post scale

Post scale Post scale

Post scale

User-Defined Mix Coefficients

Dual-band DRC disabled

L

R

User-Defined Mix Coefficie nts

Crossover Frequency determined by XO Setting

Crossover Frequency determined by XO Setting User Defined If XO =0000

User Defined If XO =0000

C1Mx1

+

C1Mx2

C2Mx1

+

C2Mx2

C3Mx1

+

C3Mx2

Channel ½

Hi-Pass XO

#8

Biquad #5

Filter

--------------

Hi-pass XO

filter

Channel ½

Hi-Pass XO

#8

Biquad #5

Filter

--------------

Hi-pass XO

filter

Channel 3

Lo-Pass XO

Biquad

Filter

--------------

Low-pass XO

filter

Crossover Frequency determined by XO Setting

Crossover Frequency determined by XO Setting User Defined If XO=0000

User Defined If XO=0000

Vol

And

Limiter

Vol

Vol And

And

Limiter

Vol

And

Limiter

B2DRC Enabled

DC cutt

Post scale

filter

DC cutt

Post scale

filter

DC cutt

Post scale

filter

Post scale

B2DRC Disabled

Doc ID 16861 Rev 4 19/89

I2C bus specification STA369BWS

5 I2C bus specification

The STA369BWS supports the I2C protocol via the input ports SCL and SDA_IN (master to slave) and the output port SDA_OUT (slave to master). This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. The STA369BWS is always a slave device in all of its communications. It supports up to 400 kb/s (fast-mode bit rate).

For correct operation of the I has a frequency at least 10 times higher than the frequency of the applied SCL clock.

5.1 Communication protocol

5.1.1 Data transition or change

Data changes on the SDA line must only occur when the clock SCL is low. A SDA transition while the clock is high is used to identify a START or STOP condition.

2

C interface ensure that the master clock generated by the PLL

5.1.2 Start condition

START is identified by a high to low transition of the data bus, SDA, while the clock, SCL, is stable in the high state. A START condition must precede any command for data transfer.

5.1.3 Stop condition

STOP is identified by low to high transition of SDA while SCL is stable in the high state. A STOP condition terminates communication between STA369BWS and the bus master.

5.1.4 Data input

During the data input the STA369BWS samples the SDA signal on the rising edge of SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low.

5.2 Device addressing

To start communication between the master and the STA369BWS, the master must initiate with a start condition. Following this, the master sends onto the SDA line 8-bits (MSB first) corresponding to the device select address and read or write mode bit.

The seven most significant bits are the device address identifiers, corresponding to the I bus definition. In the STA369BWS the I the SA pin configuration, 0x38 when SA = 0, and 0x3A when SA = 1.

2

C interface has two device addresses depending on

C

The eighth bit (LSB) identifies a read or write operation (R/W); this is set to 1 for read and to 0 for write. After a START condition the STA369BWS identifies the device address on the SDA bus and if a match is found, acknowledges the identification during the 9th bit time frame. The byte following the device identification is the address of a device register.

20/89 Doc ID 16861 Rev 4

STA369BWS I2C bus specification

5.3 Write operation

Following the START condition the master sends a device select code with the RW bit set to 0. The STA369BWS acknowledges this and then waits for the byte of internal address. After receiving the internal byte address the STA369BWS again responds with an acknowledgement.

5.3.1 Byte write

In the byte write mode the master sends one data byte, this is acknowledged by the STA369BWS. The master then terminates the transfer by generating a STOP condition.

5.3.2 Multi-byte write

The multi-byte write modes can start from any internal address. The master generating a STOP condition terminates the transfer.

Figure 8. Write mode sequence

BYTE

WRITE

MULTIBYTE

WRITE

START

DEV-ADDR

ACK

SUB-ADDR

RW

ACK

SUB-ADDR

RW

ACK

DATA IN

ACK

STOP

DATA IN

ACK

STOP

5.4 Read operation

5.4.1 Current address byte read

Following the START condition the master sends a device select code with the RW bit set to 1. The STA369BWS acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.

5.4.2 Current address multi-byte read

The multi-byte read modes can start from any internal address. Sequential data bytes are read from sequential addresses within the STA369BWS. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer.

5.4.3 Random address byte read

Following the START condition the master sends a device select code with the RW bit set to 0. The STA369BWS acknowledges this and then the master writes the internal address byte. After receiving, the internal byte address the STA369BWS again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA369BWS acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.

Doc ID 16861 Rev 4 21/89

I2C bus specification STA369BWS

5.4.4 Random address multi-byte read

The multi-byte read modes could start from any internal address. Sequential data bytes are read from sequential addresses within the STA369BWS. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer.

Figure 9. Read mode sequence

CURRENT

CURRENT ADDRESS

ADDRESS

READ

RANDOM

RANDOM ADDRESS

ADDRESS

READ

SEQUENTIAL

CURRENT

READ

SEQUENTIAL

RANDOM

READ

START

DEV-ADDR

RW=

RW= HIGH

HIGH

ACK

RW

ACK

RW

ACK

RW

DATA

SUB-ADDR

DATA

SUB-ADDR

NO ACK

STOP

ACK

DEV-ADDR

START RW

DATA

DEV-ADDR

START RW

ACK

DATA

NO ACK

ACK

STOP

DATA

ACK NO ACK

DATA

STOP

22/89 Doc ID 16861 Rev 4

STA369BWS Register description

6 Register description

Note: Addresses exceeding the maximum address number must not be written.

Table 8. Register summary

Addr Name D7 D6 D5 D4 D3 D2 D1 D0

0x00 CONFA

0x01 CONFB

0x02 CONFC

0x03 CONFD

0x04 CONFE

0x05 CONFF

0x06 MUTELOC

0x07 MVOL

0x08 C1VOL

0x09 C2VOL

0x0A C3VOL

0x0B AUTO1

0x0C AUTO2

0x0D AUTO3

0x0E C1CFG

0x0F C2CFG

0x10 C3CFG

0x11 TONE

0x12 L1AR

0x13 L1ATRT

0x14 L2AR

0x15 L2ATRT

0x16 CFADDR

0x17 B1CF1

0x18 B1CF2

0x19 B1CF3

0x1A B2CF1

0x1B B2CF2

0x1C B2CF3

0x1D A1CF1

0x1E A1CF2

FDRB TWAB TWRB IR1 IR0 MCS2 MCS1 MCS0

C2IM C1IM DSCKE SAIFB SAI3 SAI2 SAI1 SAI0

OCRB Reserved CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0

SME ZDE DRC BQL PSL DSPB DEMP HPB

SVE ZCE DCCV PWMS AME NSBW MPC MPCV

EAPD PWDN ECLE LDTE BCLE IDE OCFG1 OCFG0

LOC1 LOC0 Reserved Reserved C3M C2M C1M Reserved

MVOL[7:0]

C1VOL[7:0]

C2VOL[7:0]

C3VOL[7:0]

Reserved Reserved AMGC[1:0] Reserved Reserved Reserved Reserved

XO3 XO2 XO1 XO0 AMAM2 AMAM1 AMAM0 AMAME

Reserved

C1OM1 C1OM0 C1LS1 C1LS0 C1BO C1VBP C1EQBP C1TCB

C2OM1 C2OM0 C2LS1 C2LS0 C2BO C2VBP C2EQBP C2TCB

C3OM1 C3OM0 C3LS1 C3LS0 C3BO C3VBP Reserved Reserved

TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0

L1A3 L1A2 L1A1 L1A0 L1R3 L1R2 L1R1 L1R0

L1AT3 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 L1RT0

L2A3 L2A2 L2A1 L2A0 L2R3 L2R2 L2R1 L2R0

L2AT3 L2AT2 L2AT1 L2AT0 L2RT3 L2RT2 L2RT1 L2RT0

Reserved Reserved CFA[5:0]

C1B[23:16]

C1B[15:8]

C1B[7:0]

C2B[23:16]

C2B[15:8]

C2B[7:0]

C3B[23:16]

C3B[15:8]

Doc ID 16861 Rev 4 23/89

Register description STA369BWS

Table 8. Register summary (continued)

Addr Name D7 D6 D5 D4 D3 D2 D1 D0

0x1F A1CF3

0x20 A2CF1

0x21 A2CF2

0x22 A2CF3

0x23 B0CF1

0x24 B0CF2

0x25 B0CF3

0x26 CFUD

0x27 MPCC1

0x28 MPCC2

0x29 DCC1

0x2A DCC2

0x2B FDRC1

0x2C FDRC2

0x2D STATUS

0x2E Reserved

0x2F Reserved

0x30 Reserved

0x31 EQCFG

0x32 EATH1

0x33 ERTH1

0x34 EATH2

0x35 ERTH2

0x36 CONFX

0x37 SVCA

0x38 SVCB

0x39 RMS0A

0x3A RMS0B

0x3B RMS0C

0x3C RMS1A

0x3D RMS1B

0x3E RMS1C

0x3F EVOLRES

0x40 Reserved

0x41 Reserved

C3B[7:0]

C4B[23:16]

C4B[15:8]

C4B[7:0]

C5B[23:16]

C5B[15:8]

C5B[7:0]

Reserved RA R1 WA W1

MPCC[15:8]

MPCC[7:0]

DCC[15:8]

DCC[7:0]

FDRC[15:8]

FDRC[7:0]

PLLUL FAULT UVFAULT Reserved OCFAULT OCWARN TFAULT TWARN

Reserved

XOB Reserved Reserved AMGC[3:2] Reserved SEL[1:0]

EATHEN1 EATH1[6:0]

ERTHEN1 ERTH1[6:0]

EATHEN2 EATH2[6:0]

ERTHEN2 ERTH2[6:0]

MDRC[1:0] PS48DB XAR1 XAR2 BQ5 BQ6 BQ7

Reserved Reserved SVUPE SVUP[4:0]

Reserved Reserved SVDWE SVDW[4:0]

R_C0[23:16]

R_C0[15:8]

R_C0[7:0]

R_C1[23:16]

R_C1[15:8]

R_C1[7:0]

VRESEN VRESTG C3VR[1:0] C2VR[1:0] C1VR[1:0]

Reserved

24/89 Doc ID 16861 Rev 4

STA369BWS Register description

Table 8. Register summary (continued)

Addr Name D7 D6 D5 D4 D3 D2 D1 D0

0x42 Reserved

0x43 Reserved

0x44 Reserved

0x45 Reserved

0x46 SHOK

0x47 Reserved

0x48 NSHAPE

0x49 CXTB4B1

0x4A CXTB7B5

0x4B MISC1

0x4C MISC2

0x4D BPTH

0x4E BADPWM

0x4F BPTIM

0x50 Reserved

0x51 Reserved

0x52 Reserved

0x53 Reserved

0x54 Reserved

0x55 Reserved

0x56 Reserved

0x60 BQCHKE0

0x61 BQCHKE1

0x62 BQCHKE2

0x63 XCCHKE0

0x64 XCCHKE1

0x65 XCCHKE2

0x66 BQCHKR0

0x67 BQCHKR1

0x68 BQCHKR2

0x69 XCCHKR0

0x6A XCCHKR1

0x6B XCCHKR2

0x6C CHKCTRL

Reserved

GND1A GND1B GND2A GND2B VCC1A VCC1B VCC2A VCC2B

Reserved

NSHXEN NSHB7EN NSHB6EN NSHB5EN NSHB4EN NSHB3EN NSHB2EN NSHB1EN

CXTB4[1:0] CXTB3[1:0] CXTB2[1:0] CXTB1[1:0]

Reserved Reserved CXTB7[1:0] CXTB6[1:0] CXTB5[1:0]

RPDNEN NSHHPEN BRIDGOFF F3XEN[1:0] CPWMEN Reserved BOOST

LPDP LPD LPDE PNDLSL[2:0] Reserved SHEN

BPTH[5:0] Reserved GDRC

BP4B BP4A BP3B BP3A BP2B BP2A BP1B BP1A

BPTIM[7:0]

Reserved

BQCHKE[7:0]

BQCHKE[15:8]

BQCHKE[23:16]

XCCHKE[7:0]

XCCHKE[15:8]

XCCHKE[23:16]

BQCHKR[7:0]

BQCHKR[15:8]

BQCHKR[23:16]

XCCHKR[7:0]

XCCHKR[15:8]

XCCHKR[23:16]

XCAUTO XCRES XCCMP XCGO BCAUTO BCRES BCCMP BCGO

Doc ID 16861 Rev 4 25/89

Register description STA369BWS

6.1 Configuration registers (addr 0x00 to 0x05)

6.1.1 Configuration register A (addr 0x00)

D7 D6 D5 D4 D3 D2 D1 D0

FDRB TWAB TWRB IR1 IR0 MCS2 MCS1 MCS0

01100011

Master clock select

Table 9. Master clock select

Bit R/W RST Name Description

0R/W1 MCS0

1R/W1 MCS1

Selects the ratio between the input I frequency and the input clock.

2

S sample

2R/W0 MCS2

The STA369BWS supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,

176.4 kHz, and 192 kHz. Therefore the internal clock is:

z 32.768 MHz for 32 kHz

z 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz

z 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz

The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (f

).

s

The relationship between the input clock and the input sample rate is determined by both the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio used internally.

Table 10. Input sampling rates

Input sample rate

fs (kHz)

IR MCS[2:0]

101 100 011 010 001 000

32, 44.1, 48 00 576 * fs 128 * fs 256 * fs 384 * fs 512 * fs 768 * fs

88.2, 96 01 NA 64 * fs 128 * fs 192 * fs 256 * fs 384 * fs

176.4, 192 1X NA 32 * fs 64 * fs 96 * fs 128 * fs 192 * fs

Interpolation ratio select

Table 11. Internal interpolation ratio

Bit R/W RST Name Description

4:3 R/W 00 IR [1:0]

26/89 Doc ID 16861 Rev 4

Selects internal interpolation ratio based on input I sample frequency

2

S

STA369BWS Register description

The STA369BWS has variable interpolation (oversampling) settings such that internal processing and FFX output rates remain consistent. The first processing block interpolates by either 2-times or 1-time (pass-through) or provides a 2-times downsample. The oversampling ratio of this interpolation is determined by the IR bits.

Table 12. IR bit settings as a function of input sample rate

Input sample rate fs (kHz) IR 1st stage interpolation ratio

32 00 2-times oversampling

44.1 00 2-times oversampling

48 00 2-times oversampling

88.2 01 Pass-through

96 01 Pass-through

176.4 10 2-times downsampling

192 10 2-times downsampling

Thermal warning recovery bypass

Table 13. Thermal warning recovery bypass

Bit R/W RST Name Description

5R/W1 TWRB

0: thermal warning recovery enabled 1: thermal warning recovery disabled

This bit sets the behavior of the IC after a thermal warning disappears. If TWRB is enabled the device automatically restores the normal gain and output limiting is no longer active. If it is disabled the device keeps the output limit active until a reset is asserted or until TWRB set to 0. This bit works in conjunction with TWAB

Thermal warning adjustment bypass

Table 14. Thermal warning adjustment bypass

Bit R/W RST Name Description

6R/W1 TWAB

Bit TWAB enables automatic output limiting when a power stage thermal warning condition persists for longer than 400ms. When the feature is active (TWAB = 0) the desired output limiting, set through bit TWOCL (-3 dB by default) at address 0x37 in the RAM coefficients bank, is applied. The way the limiting acts after the warning condition disappears is controlled by bit TWRB.

0: thermal warning adjustment enabled 1: thermal warning adjustment disabled

Doc ID 16861 Rev 4 27/89