ST SPC56EL60L3, SPC56EL60L5 User Manual

SPC56EL60L3 SPC56EL60L5

32-bit Power Architecture® microcontroller for automotive

SIL3/ASILD chassis and safety applications

Features

■ High-performance e200z4d dual core

– 32-bit Power Architecture – Core frequency as high as 120 MHz – Dual issue five-stage pipeline core – Variable Length Encoding (VLE) – Memory Management Unit (MMU) – 4 KB instruction cache with error detection

code

– Signal processing engine (SPE)

■ Memory available

– 1 MB Flash memory with ECC – 128 KB on-chip SRAM with ECC – Built-in RWW capabilities for EEPROM

emulation

■ SIL3/ASILD innovative safety concept:

LockStep mode and Fail-safe protection – Sphere of replication (SoR) for key

components (such as CPU core, eDMA,

crossbar switch) – Fault collection and control unit (FCCU) – Redundancy control and checker unit

(RCCU) on outputs of the SoR connected

to FCCU – Boot-time Built-In Self-Test for Memory

(MBIST) and Logic (LBIST) triggered by

hardware – Boot-time Built-In Self-Test for ADC and

Flash memory triggered by software – Replicated safety enhanced watchdog – Replicated junction temperature sensor – Non-maskable interrupt (NMI) – 16-region memory protection unit (MPU) – Clock monitoring units (CMU) – Power management unit (PMU) – Cyclic redundancy check (CRC) unit

technology CPU

LQFP100

1. For development purpose only.

■ Decoupled Parallel mode for high-performance

LQFP144 20 x 20 mm

LBGA257 14 x 14 mm

(1)

use of replicated cores

■ Nexus Class 3+ interface

■ Interrupts

– Replicated 16-priority controller – Replicated 16-channel eDMA controller

■ GPIOs individually programmable as input,

output or special function

■ Three 6-channel general-purpose eTimer units

■ 2 FlexPWM units: four 16-bit channels per

module

■ Communications interfaces

– 2 LINFlexD channels – 3 DSPI channels with automatic chip select

generation

– 2 FlexCAN interfaces (2.0B Active) with 32

message objects

– FlexRay module (V 2.1 Rev. A) with 2

channels, 64 message buffers and data rates up to 10 Mbit/s

■ Two 12-bit analog-to-digital converters (ADCs)

– 16 input channels – Programmable cross triggering unit (CTU)

to synchronize ADCs conversion with timer and PWM

■ Sine wave generator (D/A with low pass filter)

■ On-chip CAN/UART bootstrap loader

■ Single 3.0 V to 3.6 V voltage supply

■ Ambient temperature range –40 °C to 125 °C

■ Junction temperature range –40 °C to 150 °C

April 2011 Doc ID 15461 Rev 5 1/38

www.st.com

SPC56EL60L3, SPC56EL60L5 Contents

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3 Operating parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.4 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4.1 Lock Step Mode (LSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4.2 Decoupled Parallel Mode (DPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.5 Mode-specific performance parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.6 Functional safety suitability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.7 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.7.1 High-performance e200z4d core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.7.2 Crossbar switch (XBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.7.3 Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.7.4 Enhanced Direct Memory Access (eDMA) . . . . . . . . . . . . . . . . . . . . . . 15

2.7.5 On-chip Flash memory with ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.7.6 On-chip SRAM with ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.7.7 Platform Flash memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.7.8 Platform Static RAM Controller (SRAMC) . . . . . . . . . . . . . . . . . . . . . . . 18

2.7.9 Memory subsystem access time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.7.10 Error Correction Status Module (ECSM) . . . . . . . . . . . . . . . . . . . . . . . . 18

2.7.11 Peripheral bridge (PBRIDGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.7.12 Interrupt Controller (INTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.7.13 System clocks and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.7.14 Frequency-Modulated Phase-Locked Loop (FMPLL) . . . . . . . . . . . . . . 20

2.7.15 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.7.16 Internal Reference Clock (RC) oscillator . . . . . . . . . . . . . . . . . . . . . . . . 21

2.7.17 Clock, reset, power, mode and test control modules (MC_CGM,

MC_RGM, MC_PCU, and MC_ME) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.7.18 Periodic Interrupt Timer Module (PIT) . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.7.19 System Timer Module (STM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.7.20 Software Watchdog Timer (SWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.7.21 Fault Collection and Control Unit (FCCU) . . . . . . . . . . . . . . . . . . . . . . . 22

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SPC56EL60L3, SPC56EL60L5 Contents

2.7.22 System Integration Unit Lite (SIUL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.7.23 Non-Maskable Interrupt (NMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.7.24 Boot Assist Module (BAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.7.25 System Status and Configuration Module (SSCM) . . . . . . . . . . . . . . . . 23

2.7.26 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.7.27 FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.7.28 Serial communication interface module (LINFlexD) . . . . . . . . . . . . . . . . 26

2.7.29 Deserial Serial Peripheral Interface (DSPI) . . . . . . . . . . . . . . . . . . . . . . 26

2.7.30 FlexPWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.7.31 eTimer module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.7.32 Sine Wave Generator (SWG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.7.33 Analog-to-Digital Converter module (ADC) . . . . . . . . . . . . . . . . . . . . . . 30

2.7.34 Cross Triggering Unit (CTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.7.35 Cyclic Redundancy Checker (CRC) Unit . . . . . . . . . . . . . . . . . . . . . . . . 31

2.7.36 Redundancy Control and Checker Unit (RCCU) . . . . . . . . . . . . . . . . . . 32

2.7.37 Junction temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.7.38 Nexus Port Controller (NPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.7.39 IEEE 1149.1 JTAG Controller (JTAGC) . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.7.40 Voltage regulator / Power Management Unit (PMU) . . . . . . . . . . . . . . . 34

2.7.41 Built-In Self-Test (BIST) capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Doc ID 15461 Rev 5 3/38

SPC56EL60L3, SPC56EL60L5 List of tables

List of tables

Table 1. SPC56EL60 device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Platform memory access time summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 3. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 4. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Doc ID 15461 Rev 5 4/38

SPC56EL60L3, SPC56EL60L5 List of figures

List of figures

Figure 1. SPC56EL60 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 2. Commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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SPC56EL60L3, SPC56EL60L5 Introduction

1 Introduction

The SPC56EL60 series microcontrollers are system-on-chip devices that are built on Power Architecture technology and:

● Are 100% user-mode compatible with the classic Power Architecture instruction set

● Contain enhancements that improve the architecture’s fit in embedded applications

● Include additional instruction support for digital signal processing (DSP)

● Integrate technologies such as an enhanced time processor unit, enhanced queued

analog-to-digital converter, Controller Area Network, and an enhanced modular inputoutput system

The SPC56EL60 is a compatible extension to the STMicroelectronics product roadmap for Safety and Chassis application field. It targets the Electric Power Steering and those applications requiring a high Safety Integrity Level (SIL).

All devices in this family are built around a dual core safety platform with an innovative safety concept targeting ISO 26262 ASILD and IEC 61508 SIL3 integrity levels. In order to minimize additional software and module level features to reach this target, on-chip redundancy is offered for the critical components of the microcontroller (CPU core, DMA controller, interrupt controller, crossbar bus system, memory protection unit, flash memory and RAM controllers, peripheral bus bridge, system timers, and watchdog timer). Lock Step Redundancy Checking Units are implemented at each output of this Sphere of Replication (SoR). ECC is available for on-chip RAM and flash memories. A programmable fault collection and control unit monitors the integrity status of the device and provides flexible safe state control.

The host processor core of the SPC56EL60 is the latest CPU from the e200 family of compatible Power Architecture cores. The e200z4d 5-stage pipeline dual issue core provides a very high level of efficiency, allowing high performance with minimum power consumption.

The peripheral set is compatible with the SPC56EL60 family, providing high-end electrical motor control capability with very low CPU intervention, thanks to the on-chip Cross Triggering Unit (CTU).

This device incorporates high-performance 90 nm embedded Flash-memory technology to provide substantial cost reduction per feature and significant performance improvement.

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Features SPC56EL60L3, SPC56EL60L5

2 Features

2.1 Device comparison

Table 1. SPC56EL60 device summary

CPU

Buses

Crossbar Master × slave ports

Memory

Feature SPC56EL60

Ty p e

Architecture Harvard

Execution speed 0 – 120 MHz (+2% FM)

DMIPS intrinsic performance > 240 MIPS

SIMD (DSP + FPU) Yes

MMU 16 entry

Instruction set PPC Yes

Instruction set VLE Yes

Instruction cache 4 KB, EDC

MPU-16 regions Yes, replicated module

Semaphore unit (SEMA4) Yes

Core bus AHB, 32-bit address, 64-bit data

Internal periphery bus 32-bit address, 32-bit data

Code/data flash 1 MB, ECC, RWW

Static RAM 128 KB, ECC

2 × e200z4

(in lock-step or decoupled operation)

Lock Step Mode: 4 × 3

Decoupled Parallel Mode: 6 × 3

Interrupt controller 16 interrupt levels, replicated module

Periodic Interrupt Timer (PIT) 1 × 4 channels

System timer module 1 × 4 channels, replicated module

Software watchdog timer Yes, replicated module

eDMA 16 channels, replicated module

FlexRay 1 × 64 message buffer, dual channel

Modules

7/38 Doc ID 15461 Rev 5

FlexCAN 2 × 32 message buffer

LINFlexD (UART and LIN with DMA support) 2

Clock out Yes

Fault control & collection unit (FCCU) Yes

Cross triggering unit (CTU) Yes

eTimer 3 × 6 channels

FlexPWM 2 Module 4 × (2 + 1) channels

(1)

(2)

SPC56EL60L3, SPC56EL60L5 Features

Table 1. SPC56EL60 device summary (continued)

Feature SPC56EL60

ADC

2 × 12-bit ADC, 16 channels per ADC

(3 internal, 4 shared and 9 external)

Sine-wave generator (SWG) 32 point

Modules (continued)

DSPI

as many as 8 chip selects

3 × DSPI

Cyclic redundancy checker (CRC) unit Yes

Junction temperature sensor (TSENS) Yes, replicated module

Digital I/Os ≥ 16

Supply

Device power supply

3.3 V with integrated bypassable ballast transistor External ballast transistor not needed for bare die

Analog reference voltage 3.0 V – 3.6 V and 4.5 V – 5.5 V

Clocking

Frequency-modulated phase-locked loop (FMPLL)

Internal RC oscillator 16 MHz

External crystal oscillator 4–40 MHz

Debug Nexus Level 3+

Known Good Die (KGD) Yes

Packages

LQFP

100 pins 144 pins

LBGA LBGA257

Temperature range (junction) –40 to 150 °C

Temperature

1. The third eTimer is available only in the BGA package.

2. The second FlexPWM module is available only in the BGA package.

3. LBGA257 available only as development package.

Ambient temperature range using external ballast transistor (LQFP)

–40 to 125 °C

(3)

Doc ID 15461 Rev 5 8/38

Features SPC56EL60L3, SPC56EL60L5

2.2 Block diagram

Figure 1 shows the block diagram of the SPC56EL60.

Figure 1. SPC56EL60 block diagram

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SPC56EL60L3, SPC56EL60L5 Features

2.3 Operating parameters

The SPC56EL60 operating parameters are listed as follows:

● Operating range 0 – 120 MHz

● –40 to 150 °C junction temperature

● Fabricated in 90 nm low power process

● 1.2 V internal logic

● Internal voltage regulator (VREG) with integrated ballast transistor

– Single-supply designs offering high integration level to the customer

– Possibility to use external ballast transistor and for KGD bypass internal ballast

transistor

● 3.3 V ±10% for digital I/O input supply voltage

● Low power design

– Dynamic clock gating of core and peripherals

– Software controlled clock gating of peripherals

– Power consumption less than 400 mA

● Selectable current slew rate (slow/medium/fast)

● 3.3 V ± 10% Nexus pin rail. Same as digital I/O rail

● Unused pins configurable as GPIO or GPI for unused A/D channel inputs

● 3.3–5 V ±10% for A/Donverter reference and analog input pins

● Designed with EMI reduction techniques

– Phase-locked loop (PLL)

– System clock with frequency modulation

– On-chip by-pass capacitance

– Software selectable current slew rate control

– Schmitt trigger on selected inputs

● Configurable pins

– Selectable pull-up, pull-down or no pull on all pins on all SIU controlled pins

– Selectable open drain

● Redundant temperature sensors in separate safety channels

● Multiple low/high voltage detector and inhibit units

– High voltage detection and inhibit with off-line testing capability on 1.2 V only

– Low voltage detection and inhibit with off-line testing capability on 1.2 V and 3.3 V

supply

● Redundant bandgap to duplicate internal reference

● Deep N-well and wide column multiplexing where required to reduce Soft Error Rate

(SER) effect for SRAM

● Physical separation of replicated functional blocks achieved by layout

Doc ID 15461 Rev 5 10/38

Features SPC56EL60L3, SPC56EL60L5

2.4 Modes of operation

SPC56EL60 devices can operate in two modes of operation:

● Lock Step Mode (LSM)

● Decoupled Parallel Mode (DPM)

One of the two modes is statically selected at power-up. The selected mode may be changed only going through a full power-on reset.

2.4.1 Lock Step Mode (LSM)

Lock Step Mode (LSM) allows reaching the highest safety level. It has been defined to allow reaching SIL3 with minimum software overhead.

The Sphere of Replication (SoR) refers to a set of replicated IP modules where at the outputs a formal check is performed to ensure that the same operations or transactions are executed on a clock per clock basis (Lock Step Mode of operation).

The current concept assumes as premise that the most important goal for a functional safety SIL3-capable device is to detect (or diagnose) faults as they leave the SoR. In fact, a fault as long as it remains confined within the SoR and therefore does not generate an action visible outside the SoC or influence the effective operability of the periphery (and so the ECU), is not to be considered as a dangerous fault.

The presence of checkers (RC) at the outputs of the SoR for the periphery bus, the Flashmemory subsystem and the SRAM subsystem represents a minimum guarantee that noncommon cause faults are detected when the two channels redundantly are merged into a single actuator or recipient, on the action that is to be performed.

2.4.2 Decoupled Parallel Mode (DPM)

In Decoupled Parallel Mode (DPM), each CPU core and connected channel run independently from the other one and redundancy checkers (RC) are disabled.

The DPM mode increased performances can be estimated in first approximation as about

1.6× the performance of the LSM mode at the same frequency for shared program flash configuration (up to 2×, depending on software).

SPC56EL60 devices support only static configuration at power-on (either LSM or DPM).

2.5 Mode-specific performance parameters

● LSM:

– Up to 240 million integer instructions per second (dual integer unit)

– Up to 240 million floating point instructions per second (FPU)

– Up to 480 million multiply and accumulate instructions per second (SPE)

● DPM:

– 384–480 million integer/floating point instructions per second

– 768–960 million multiply and accumulate instructions per second

11/38 Doc ID 15461 Rev 5

SPC56EL60L3, SPC56EL60L5 Features

2.6 Functional safety suitability

The SPC56EL60 has been successfully assessed by Exida Certification (Official Certification issued on Nov. 30th 2007) to be fit for purpose to achieve a safety integrity level 3 (SIL3) as per IEC61508-part 2 standard with an overall SoC PFH of 0.1 FIT in LSM mode.

The mode of operation which allows to reach the highest safety level with minimum software requirement is the Lock Step mode (LSM).

● High-performance e200z4d dual core

– 32-bit Power Architecture technology CPU

– Core frequency as high as 120 MHz

– Dual issue five-stage pipeline core

– Variable Length Encoding (VLE)

– Memory Management Unit (MMU)

– 4 KB instruction cache with error detection code

– Signal processing engine (SPE)

● Memory available

– 1 MB Flash memory with ECC

– 128 KB on-chip SRAM with ECC

– Built-in RWW capabilities for EEPROM emulation

● SIL3/ASILD innovative safety concept: LockStep mode and Fail-safe protection

– Sphere of replication (SoR) for key components (such as CPU core, DMA,

crossbar switch)

– Fault collection and control unit (FCCU)

– Redundancy control and checker unit (RCCU) on outputs of the SoR connected to

FCCU

– Boot-time Built-In Self-Test for Memory (MBIST) and Logic (LBIST) triggered by

hardware

– Boot-time Built-In Self-Test for ADC and Flash memory triggered by software

– Replicated safety enhanced watchdog

– Replicated junction temperature sensor

– Non-maskable interrupt (NMI)

– 16-region memory protection unit (MPU)

– Clock monitoring units (CMU)

– Power management unit (PMU)

– Cyclic redundancy check (CRC) unit

● Decoupled Parallel mode for high performance use of replicated cores

● Nexus Class 3+ interface

● Interrupts

– Replicated 16-priority controller

– Replicated 16-channel eDMA controller

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