ST SPC563M64L5, SPC563M64L7 User Manual

SPC563M64L5, SPC563M64L7
32-bit Power Architecture® based MCU for automotive
powertrain applications
Features
Single issue, 32-bit Power Architecture
E compliant e200z335 CPU core complex – Includes variable length encoding (VLE)
enhancements for code size reduction
32-channel direct memory access controller
(DMA)
Interrupt controller (INTC) capable of handling
364 selectable-priority interrupt sources: 191 peripheral interrupt sources, 8 software interrupts and 165 reserved interrupts.
Frequency-modulated phase-locked loop
(FMPLL)
Calibration external bus interface (EBI)
System integration unit (SIU)
Up to 1.5 Mbyte on-chip Flash with Flash
controller – Fetch Accelerator for single cycle Flash
access @80 MHz
Up to 94 Kbyte on-chip static RAM (including
up to 32 Kbyte standby RAM)
Boot assist module (BAM)
32-channel second-generation enhanced time
processor unit (eTPU)
a. The external bus interface is only accessible when
using the calibration tool. It is not available on production packages.
Table 1. Device summary
Memory Flash size
Package: LQFP100 Package: LQFP144 Package: LQFP176 Package: LBGA208
®
Book
(a)
144 LQFP 20 mm x 20 mm
176 LQFP
24 mm x 24 m
m
100 LQFP 14 mm x 14 mm
LFBGA208 17 mm x 17 mm x1.5mm
– 32 standard eTPU channels – Architectural enhancements to improve
code efficiency and added flexibility
16-channels enhanced modular input-output
system (eMIOS)
Enhanced queued analog-to-digital converter
(eQADC)
Decimation filter (part of eQADC)
Silicon die temperature sensor
2 deserial serial peripheral interface (DSPI)
modules (compatible with Microsecond Bus)
2 enhanced serial communication interface
(eSCI) modules compatible with LIN
2 controller area network (FlexCAN) modules
that support CAN 2.0B
Nexus port controller (NPC) per IEEE-ISTO
5001-2003 standard
IEEE 1149.1 (JTAG) support
Nexus interface
On-chip voltage regulator controller that
provides 1.2 V and 3.3 V internal supplies from a 5 V external source.
Designed for LQFP100, LQFP144, LQFP176
and LBGA208.
Part number
1536 Kbyte SPC563M64L5 SPC563M64L7
June 2012 Doc ID 14642 Rev 9 1/142
This is information on a product in full production.
www.st.com
1
Contents SPC563M64L5, SPC563M64L7
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 SPC563Mxx features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 SPC563Mxx feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.1 e200z335 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.2 Crossbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.3 eDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.4 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3.5 FMPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3.6 Calibration EBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3.7 SIU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3.8 ECSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3.9 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3.10 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.3.11 BAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.3.12 eMIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.3.13 eTPU2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.3.14 eQADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.3.15 DSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.3.16 eSCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.3.17 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.3.18 System timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.3.19 Software Watchdog Timer (SWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.3.20 Debug features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.4 SPC563Mxx series architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.4.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.4.2 Block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3 Pinout and signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.1 LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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SPC563M64L5, SPC563M64L7 Contents
3.2 LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3 LQFP176 pinout (SPC563M64) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.4 LQFP176 pinout (SPC563M60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.5 LBGA208 ballmap (SPC563M64) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.6 Signal summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.7 Signal details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.1 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.3.1 General notes for specifications at maximum junction temperature . . . 76
4.4 Electromagnetic Interference (EMI) characteristics . . . . . . . . . . . . . . . . . 79
4.5 Electromagnetic static discharge (ESD) characteristics . . . . . . . . . . . . . . 79
4.6 Power Management Control (PMC) and Power On Reset (POR) electrical
specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.6.1 Regulator example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.6.2 Recommended power transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.7 Power up/down sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.8 DC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.9 I/O Pad current specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.9.1 I/O pad VRC33 current specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.9.2 LVDS pad specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.10 Oscillator and PLLMRFM electrical characteristics . . . . . . . . . . . . . . . . . 97
4.11 Temperature sensor electrical characteristics . . . . . . . . . . . . . . . . . . . . . 99
4.12 eQADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.13 Platform flash controller electrical characteristics . . . . . . . . . . . . . . . . . 102
4.14 Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.15 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.15.1 Pad AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.16 AC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.16.1 IEEE 1149.1 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.16.2 Nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.16.3 Calibration bus interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4.16.4 eMIOS timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Doc ID 14642 Rev 9 3/142
Contents SPC563M64L5, SPC563M64L7
4.16.5 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.16.6 eQADC SSI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.2.1 LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.2.2 LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.2.3 LQFP176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.2.4 LBGA208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
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SPC563M64L5, SPC563M64L7 List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. SPC563Mxx family device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. SPC563Mxx series block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 4. SPC563Mx signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 5. Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 6. Signal details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 7. SPC563Mx Power/Ground Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 8. Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 10. Thermal characteristics for 100-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 11. Thermal characteristics for 144-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 12. Thermal characteristics for 176-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 13. Thermal characteristics for 208-pin LBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 14. EMI testing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 15. ESD ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 16. PMC Operating conditions and external regulators supply voltage . . . . . . . . . . . . . . . . . . 80
Table 17. PMC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 18. Required external PMC component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 19. Network 1 component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 20. Network 2 component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 21. Network 3 component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 22. Recommended operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 23. Power sequence pin states for fast pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 24. Power sequence pin states for medium, slow and multi-voltage pads . . . . . . . . . . . . . . . . 87
Table 25. DC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 26. I/O pad average I Table 27. I/O pad V Table 28. V
pad average DC current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
RC33
RC33
average I
Table 29. DSPI LVDS pad specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 30. PLLMRFM electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 31. Temperature sensor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 32. eQADC conversion specifications (operating) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 33. APC, RWSC, WWSC settings vs. frequency of operation . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 34. Program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 35. Flash module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 36. Pad AC specifications (5.0 V)
Table 37. Pad AC specifications (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 38. Pad AC specifications (1.8 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 39. JTAG pin AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 40. Nexus debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 41. Calibration bus operation timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 42. eMIOS timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 43. DSPI timing
,
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 44. eQADC SSI timing characteristics (pads at 3.3 V or at 5.0 V) . . . . . . . . . . . . . . . . . . . . . 123
Table 45. LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 46. LQFP176 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 47. LBGA208 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 48. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
DDE
specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
DDE
,
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Doc ID 14642 Rev 9 5/142
List of figures SPC563M64L5, SPC563M64L7
List of figures
Figure 1. SPC563Mxx series block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 2. 100-pin LQFP pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 3. 144-pin LQFP pinout (top view; all 144-pin devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 4. 176-pin LQFP pinout (SPC563M64; top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 5. 176-pin LQFP pinout (SPC563M60; top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 6. 208-pin LBGA ballmap (SPC563M64; top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 7. Core voltage regulator controller external components preferred configuration. . . . . . . . . 84
Figure 8. Pad output delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 9. JTAG test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 10. JTAG test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 11. JTAG JCOMP timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 12. JTAG boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 13. Nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 14. Nexus event trigger and test clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 15. Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 16. CLKOUT timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 17. Synchronous output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 18. Synchronous input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 19. ALE signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 20. DSPI classic SPI timing – master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 21. DSPI classic SPI timing – master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 22. DSPI classic SPI timing – slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 23. DSPI classic SPI timing – slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 24. DSPI modified transfer format timing – master, CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 25. DSPI modified transfer format timing – master, CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 26. DSPI modified transfer format timing – slave, CPHA =0 . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 27. DSPI modified transfer format timing – slave, CPHA =1 . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 28. DSPI PCS strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 29. eQADC SSI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 30. LQFP100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 31. LQFP144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 32. LQFP176 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 33. LBGA208 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 34. Commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
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SPC563M64L5, SPC563M64L7 Introduction

1 Introduction

1.1 Document overview

This document provides an overview and describes the features of the SPC563Mxx series of microcontroller units (MCUs). For functional characteristics, refer to the device reference manual. Electrical specifications and package mechanical drawings are included in this device data sheet. Pin assignments can be found in both the reference manual and data sheet.

1.2 Description

These 32-bit automotive microcontrollers are a family of system-on-chip (SoC) devices that contain many new features coupled with high performance 90 nm CMOS technology to provide substantial reduction of cost per feature and significant performance improvement. The advanced and cost-efficient host processor core of this automotive controller family is built on Power Architecture the architecture’s fit in embedded applications, includes additional instruction support for digital signal processing (DSP), integrates technologies—such as an enhanced time processor unit, enhanced queued analog-to-digital converter, Controller Area Network, and an enhanced modular input-output system—that are important for today’s lower-end powertrain applications. The device has a single level of memory hierarchy consisting of up to 94 KB on-chip SRAM and up to 1.5 MB of internal flash memory. The device also has an external bus interface (EBI) for ‘calibration’.
®
technology. This family contains enhancements that improve
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Overview SPC563M64L5, SPC563M64L7

2 Overview

This document provides electrical specifications, pin assignments, and package diagrams for the SPC563Mxx series of microcontroller units (MCUs). For functional characteristics, refer to the SPC563Mxx Microcontroller Reference Manual.
The SPC563Mxx series microcontrollers are system-on-chip devices that are built on Power Architecture
Are 100% user-mode compatible with the Power Architecture instruction set
Contain enhancements that improve the architecture’s fit in embedded applications
Include additional instruction support for digital signal processing (DSP)
Integrate technologies such as an enhanced time processor unit, enhanced queued
®
technology and:
analog-to-digital converter, Controller Area Network, and an enhanced modular input­output system
Operating Parameters
Fully static operation, 0 MHz – 80 MHz (plus 2% frequency modulation - 82 MHz) – –40 °C – 150 °C junction temperature operating range
Low power design
Less than 400 mW power dissipation (nominal)
Designed for dynamic power management of core and peripherals
Software controlled clock gating of peripherals
Low power stop mode, with all clocks stopped
Fabricated in 90 nm process
1.2 V internal logic
High performance e200z335 core processor
Advanced microcontroller bus architecture (AMBA) crossbar switch (XBAR)
Enhanced direct memory access (eDMA) controller
Interrupt controller (INTC)
191 peripheral interrupt request sources, plus 165 reserved positions
Low latency—three clocks from receipt of interrupt request from peripheral to
interrupt request to processor
Frequency Modulating Phase-locked loop (FMPLL)
Calibration bus interface (EBI) (available only in the calibration package)
System integration unit (SIU) centralizes control of pads, GPIO pins and external
interrupts.
Error correction status module (ECSM) provides configurable error-correcting codes
(ECC) reporting
Up to 1.5 MB on-chip flash memory
Up to 94 KB on-chip static RAM
Boot assist module (BAM) enables and manages the transition of MCU from reset to
user code execution from internal flash memory, external memory on the calibration bus or download and execution of code via FlexCAN or eSCI.
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Periodic interrupt timer (PIT)
32-bit wide down counter with automatic reload
4 channels clocked by system clock
1 channel clocked by crystal clock
System timer module (STM)
32-bit up counter with 8-bit prescaler
Clocked from system clock
4 channel timer compare hardware
Software watchdog timer (SWT) 32-bit timer
Enhanced modular I/O system (eMIOS)
16 standard timer channels (up to 14 channels connected to pins in LQFP144)
24-bit timer resolution
Second-generation enhanced time processor unit (eTPU2)
High level assembler/compiler
Enhancements to make ‘C’ compiler more efficient
New ‘engine relative’ addressing mode
Enhanced queued A/D converter (eQADC)
2 independent on-chip RSD Cyclic ADCs
Up to 34 input channels available to the two on-chip ADCs
4 pairs of differential analog input channels
2 deserial serial peripheral interface modules (DSPI)
SPI provides full duplex communication ports with interrupt and DMA request
support
Deserial serial interface (DSI) achieves pin reduction by hardware serialization
and deserialization of eTPU, eMIOS channels and GPIO
2 enhanced serial communication interface (eSCI) modules
2 FlexCAN modules
Nexus port controller (NPC) per IEEE-ISTO 5001-2003 standard
IEEE 1149.1 JTAG controller (JTAGC)
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Overview SPC563M64L5, SPC563M64L7

2.1 Device comparison

Table 2. SPC563Mxx family device summary
Feature SPC563M64 SPC563M60P SPC563M54P
Flash memory size (KB) 1536 1024 768
Total SRAM size (KB) 94 64 48
Standby SRAM size (KB) 32 32 24
Processor core
32-bit e200z335
with SPE and FPU
support
32-bit e200z335
with SPE and FPU
support
32-bit e200z335
with SPE and FPU
support
Core frequency (MHz) 64/80 40/64/80 40/64
Calibration bus width
(1)
16 bits 16 bits
DMA (direct memory access) channels 32 32 32
eMIOS (enhanced modular input-output system) channels
eQADC (enhanced queued analog-to-digital converter) channels (on-chip)
16 16 16
Up to 34
(2)
Up to 34
(2)
Up to 32
eSCI (serial communication interface) 2 2 2
DSPI (deserial serial peripheral interface) 2 2 2
Microsecond Channel compatible interface 2 2 2
(2)
eTPU (enhanced time processor unit) Yes Yes Yes
Channels 32 32 32
Code memory (KB) 14 14 14
Parameter RAM (KB) 3 3 3
FlexCAN (controller area network)
(3)
222
FMPLL (frequency-modulated phase-locked loop) Yes Yes Yes
INTC (interrupt controller) channels 364
(4)
364
(4)
364
(4)
JTAG controller Yes Yes Yes
NDI (Nexus development interface) level Class 2+ Class 2+ Class 2+
Non-maskable interrupt and critical interrupt Yes Yes Yes
PIT (periodic interrupt timers) 5 5 5
Task monitor timer 4 channels 4 channels 4 channels
Temperature sensor Yes Yes Yes
Windowing software watchdog Yes Yes Yes
Packages
1. Calibration package only.
2. The 176-pin and 208-pin packages have 34 input channels; 144-pin package has 32; 100-pin package has 23.
3. One FlexCAN module has 64 message buffers; the other has 32 message buffers.
LQFP144 LQFP176
LQFP100 LQFP144 LQFP176
LQFP100 LQFP144
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4. 165 interrupt channels are reserved for compatibility with future devices. This device has 191 peripheral interrupt sources
plus 8 software interrupts available to the user.
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Overview SPC563M64L5, SPC563M64L7

2.2 SPC563Mxx features

Operating Parameters
Fully static operation, 0 MHz – 80 MHz (plus 2% frequency modulation - 82 MHz) – –40 °C to 150 °C junction temperature operating range
Low power design
Less than 400 mW power dissipation (nominal)
Designed for dynamic power management of core and peripherals
Software controlled clock gating of peripherals
Low power stop mode, with all clocks stopped
Fabricated in 90 nm process
1.2 V internal logic – Single power supply with 5.0 V −10% / +5% (4.5 V to 5.25 V) with internal
regulator to provide 3.3 V and 1.2 V for the core
Input and output pins with 5.0 V −10% / +5% (4.5 V to 5.25 V) range
35%/65% V
Selectable hysteresis
Selectable slew rate control
Nexus pins powered by 3.3 V supply
Designed with EMI reduction techniques
Phase-locked loop
Frequency modulation of system clock frequency
On-chip bypass capacitance
Selectable slew rate and drive strength
High performance e200z335 core processor
32-bit Power Architecture Book E programmer’s model
Variable Length Encoding Enhancements
Allows Power Architecture instruction set to be optionally encoded in a mixed 16 and 32-bit instructions
Results in smaller code size
Single issue, 32-bit Power Architecture technology compliant CPU
In-order execution and retirement
Precise exception handling
Branch processing unit
Dedicated branch address calculation adder
Branch acceleration using Branch Lookahead Instruction Buffer
Load/store unit
One-cycle load latency
Fully pipelined
Big and Little Endian support
Misaligned access support
Zero load-to-use pipeline bubbles
Thirty-two 64-bit general purpose registers (GPRs)
CMOS switch levels (with hysteresis)
DDE
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Memory management unit (MMU) with 16-entry fully-associative translation look-
aside buffer (TLB)
Separate instruction bus and load/store bus
Vectored interrupt support
Interrupt latency < 120 ns @ 80 MHz (measured from interrupt request to
execution of first instruction of interrupt exception handler)
Non-maskable interrupt (NMI) input for handling external events that must produce
an immediate response, e.g., power down detection. On this device, the NMI input is connected to the Critical Interrupt Input. (May not be recoverable)
Critical Interrupt input. For external interrupt sources that are higher priority than
provided by the Interrupt Controller. (Always recoverable)
New ‘Wait for Interrupt’ instruction, to be used with new low power modes
Reservation instructions for implementing read-modify-write accesses
Signal processing extension (SPE) APU
Operating on all 32 GPRs that are all extended to 64 bits wide
Provides a full compliment of vector and scalar integer and floating point arithmetic operations (including integer vector MAC and MUL operations) (SIMD)
Provides rich array of extended 64-bit loads and stores to/from extended GPRs
Fully code compatible with e200z6 core
Floating point (FPU)
IEEE 754 compatible with software wrapper
Scalar single precision in hardware, double precision with software library
Conversion instructions between single precision floating point and fixed point
Fully code compatible with e200z6 core
Long cycle time instructions, except for guarded loads, do not increase interrupt
latency
Extensive system development support through Nexus debug port
Advanced microcontroller bus architecture (AMBA) crossbar switch (XBAR)
Three master ports, four slave ports
Masters: CPU Instruction bus; CPU Load/store bus (Nexus); eDMA
Slave: Flash; SRAM; Peripheral Bridge; calibration EBI
32-bit internal address bus, 64-bit internal data bus
Enhanced direct memory access (eDMA) controller
32 channels support independent 8-bit, 16-bit, or 32-bit single value or block
transfers
Supports variable sized queues and circular queues
Source and destination address registers are independently configured to post-
increment or remain constant
Each transfer is initiated by a peripheral, CPU, or eDMA channel request
Each eDMA channel can optionally send an interrupt request to the CPU on
completion of a single value or block transfer
Interrupt controller (INTC)
191 peripheral interrupt request sources
8 software setable interrupt request sources
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Overview SPC563M64L5, SPC563M64L7
–9-bit vector
Unique vector for each interrupt request source
Provided by hardware connection to processor or read from register
Each interrupt source can be programmed to one of 16 priorities
–Preemption
Preemptive prioritized interrupt requests to processor
ISR at a higher priority preempts ISRs or tasks at lower priorities
Automatic pushing or popping of preempted priority to or from a LIFO
Ability to modify the ISR or task priority. Modifying the priority can be used to implement the Priority Ceiling Protocol for accessing shared resources.
Low latency—three clocks from receipt of interrupt request from peripheral to
interrupt request to processor
Frequency Modulating Phase-locked loop (FMPLL)
Reference clock pre-divider (PREDIV) for finer frequency synthesis resolution
Reduced frequency divider (RFD) for reducing the FMPLL output clock frequency
without forcing the FMPLL to re-lock
System clock divider (SYSDIV) for reducing the system clock frequency in normal
or bypass mode
Input clock frequency range from 4 MHz to 20 MHz before the pre-divider, and
from 4 MHz to 16 MHz at the FMPLL input
Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz
VCO free-running frequency range from 25 MHz to 125 MHz
Four bypass modes: crystal or external reference with PLL on or off
Two normal modes: crystal or external reference
Programmable frequency modulation
Triangle wave modulation
Register programmable modulation frequency and depth
Lock detect circuitry reports when the FMPLL has achieved frequency lock and
continuously monitors lock status to report loss of lock conditions
User-selectable ability to generate an interrupt request upon loss of lock
User-selectable ability to generate a system reset upon loss of lock
Clock quality monitor (CQM) module provides loss-of-clock detection for the
FMPLL reference and output clocks
User-selectable ability to generate an interrupt request upon loss of clock
User-selectable ability to generate a system reset upon loss of clock
Backup clock (reference clock or FMPLL free-running) can be applied to the system in case of loss of clock
Calibration bus interface (EBI)
Available only in the calibration package (496 CSP package)
1.8 V to 3.3 V ± 10% I/O (1.6 V to 3.6 V)
Memory controller with support for various memory types
16-bit data bus, up to 22-bit address bus
Selectable drive strength
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Configurable bus speed modes
–Bus monitor
Configurable wait states
System integration unit (SIU)
Centralized GPIO control of 80 I/O pins
Centralized pad control on a per-pin basis
Pin function selection
Configurable weak pull-up or pull-down
Drive strength
Slew rate
Hysteresis
System reset monitoring and generation
External interrupt inputs, filtering and control
Critical Interrupt control
Non-Maskable Interrupt control
Internal multiplexer subblock (IMUX)
Allows flexible selection of eQADC trigger inputs (eTPU, eMIOS and external signals)
Allows selection of interrupt requests between external pins and DSPI
Error correction status module (ECSM)
Configurable error-correcting codes (ECC) reporting
Single-bit error correction reporting
On-chip flash memory
Up to 1.5 MB flash memory, accessed via a 64-bit wide bus interface
16 KB shadow block
Fetch Accelerator
Provide single cycle flash access at 80 MHz
Quadruple 128-bit wide prefetch/burst buffers
Prefetch buffers can be configured to prefetch code or data or both
Censorship protection scheme to prevent flash content visibility
Flash divided into two independent arrays, allowing reading from one array while
erasing/programming the other array (used for EEPROM emulation)
Memory block:
For SPC563M64: 18 blocks (4 × 16 KB, 2 × 32 KB, 2 × 64 KB, 10 × 128 KB) For SPC563M60P: 14 blocks (4 × 16 KB, 2 × 32 KB, 2 × 64 KB, 6 × 128 KB) For SPC563M54P: 12 blocks (4 × 16 KB, 2 × 32 KB, 2 × 64 KB, 4 × 128 KB)
Hardware programming state machine
On-chip static RAM
For SPC563M64: 94 KB general purpose RAM of which 32 KB are on standby
power supply
For SPC563M60P: 64 KB general purpose RAM of which 32 KB are on standby
power supply
For SPC563M54P: 48 KB general purpose RAM of which 24 KB are on standby
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Overview SPC563M64L5, SPC563M64L7
power supply
Boot assist module (BAM)
Enables and manages the transition of MCU from reset to user code execution in
the following configurations:
Execution from internal flash memory
Execution from external memory on the calibration bus
Download and execution of code via FlexCAN or eSCI
Periodic interrupt timer (PIT)
32-bit wide down counter with automatic reload
Four channels clocked by system clock
One channel clocked by crystal clock
Each channel can produce periodic software interrupt
Each channel can produce periodic triggers for eQADC queue triggering
One channel out of the five can be used as wake-up timer to wake device from low
power stop mode
System timer module (STM)
32-bit up counter with 8-bit prescaler
Clocked from system clock
Four-channel timer compare hardware
Each channel can generate a unique interrupt request
Designed to address AUTOSAR task monitor function
Software watchdog timer (SWT)
32-bit timer
Clock by system clock or crystal clock
Can generate either system reset or non-maskable interrupt followed by system
reset
Enabled out of reset
Enhanced modular I/O system (eMIOS)
16 timer channels (up to 14 channels in LQFP144)
24-bit timer resolution
3 selectable time bases plus shared time or angle counter bus from eTPU2
DMA and interrupt request support
Motor control capability
Second-generation enhanced time processor unit (eTPU2)
Object-code compatible with eTPU—no changes are required to hardware or
software if only eTPU features are used
Intelligent co-processor designed for timing control
High level tools, assembler and compiler available
32 channels (each channel has dedicated I/O pin in all packages except
LQFP100)
24-bit timer resolution
14 KB code memory and 3 KB data memory
Double match and capture on all channels
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Angle clock hardware support
Shared time or angle counter bus with eMIOS
DMA and interrupt request support
Nexus Class 1 debug support
eTPU2 enhancements
Counters and channels can run at full system clock speed
Software watchdog
Real-time performance monitor
Instruction set enhancements for smaller more flexible code generation
Programmable channel mode for customization of channel operation
Enhanced queued A/D converter (eQADC)
Two independent on-chip redundant signed digit (RSD) cyclic ADCs
8-, 10-, and 12-bit resolution
Differential conversions
Targets up to 10-bit accuracy at 500 KSample/s (ADC_CLK = 7.5 MHz) and 8-bit accuracy at 1 MSample/s (ADC_CLK = 15 MHz) for differential conversions
Differential channels include variable gain amplifier (VGA) for improved dynamic range (×1; ×2; ×4)
Differential channels include programmable pull-up and pull-down resistors for biasing and sensor diagnostics (200 kΩ; 100 kΩ; low value of 5 kΩ)
Single-ended signal range from 0 to 5 V
Sample times of 2 (default), 8, 64 or 128 ADC clock cycles
Provides time stamp information when requested
Parallel interface to eQADC command FIFOs (CFIFOs) and result FIFOs (RFIFOs)
Supports both right-justified unsigned and signed formats for conversion results
Temperature sensor to enable measurement of die temperature
Ability to measure all power supply pins directly
Automatic application of ADC calibration constants
Provision of reference voltages (25% VREF
and 75% VREF) for ADC calibration
purposes
Up to 34
(b)
input channels available to the two on-chip ADCs
Four pairs of differential analog input channels
Full duplex synchronous serial interface to an external device
Has a free-running clock for use by the external device
Supports a 26-bit message length
Transmits a null message when there are no triggered CFIFOs with commands bound for external CBuffers, or when there are triggered CFIFOs with commands bound for external CBuffers but the external CBuffers are full
Parallel Side Interface to communicate with an on-chip companion module
Zero jitter triggering for queue 0. (Queue 0 trigger causes current conversion to be
b. 176-pin and 208-pin packages have 34 input channels; 144-pin package has 32; 100-pin package has 23.
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Overview SPC563M64L5, SPC563M64L7
aborted and the queued conversions in the CBUFFER to be bypassed. Delay from Trigger to start of conversion is 13 system clocks + 1 ADC clock.)
eQADC Result Streaming. Generation of a continuous stream of ADC conversion
results from a single eQADC command word. Controlled by two different trigger signals; one to define the rate at which results are generated and the other to define the beginning and ending of the stream. Used to digitize waveforms during specific time/angle windows, e.g., engine knock sensor sampling.
Angular Decimation. The ability of the eQADC to sample an analog waveform in
the time domain, perform Finite Impulse Response (FIR) or Infinite Impulse Response (IIR) filtering also in the time domain, but to down sample the results in the angle domain. Resulting in a time domain filtered result at a given engine angle.
Priority Based CFIFOs
Supports six CFIFOs with fixed priority. The lower the CFIFO number, the higher its priority. When commands of distinct CFIFOs are bound for the same CBuffer, the higher priority CFIFO is always served first.
Supports software and several hardware trigger modes to arm a particular CFIFO
Generates interrupt when command coherency is not achieved
External Hardware Triggers
Supports rising edge, falling edge, high level and low level triggers
Supports configurable digital filter
Supports four external 8-to-1 muxes which can expand the input channel number
from 34
Two deserial serial peripheral interface modules (DSPI)
(c)
to 59
–SPI
Full duplex communication ports with interrupt and DMA request support
Support for queues in RAM
6 chip selects, expandable to 64 with external demultiplexers
Programmable frame size, baud rate, clock delay and clock phase on a per frame basis
Modified SPI mode for interfacing to peripherals with longer setup time requirements
LVDS option for output clock and data to allow higher speed communication
Deserial serial interface (DSI)
Pin reduction by hardware serialization and deserialization of eTPU, eMIOS channels and GPIO
32 bits per DSPI module
Triggered transfer control and change in data transfer control (for reduced EMI)
Compatible with Microsecond Channel Version 1.0 downstream
c.176-pin and 208-ball packages.
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Two enhanced serial communication interface (eSCI) modules
UART mode provides NRZ format and half or full duplex interface
eSCI bit rate up to 1 Mbps
Advanced error detection, and optional parity generation and detection
Word length programmable as 8, 9, 12 or 13 bits
Separately enabled transmitter and receiver
LIN support
DMA support
Interrupt request support
Programmable clock source: system clock or oscillator clock
Support Microsecond Channel (Timed Serial Bus - TSB) upstream Version 1.0
Tw o F l e xC A N
One with 32 message buffers; the second with 64 message buffers
Full implementation of the CAN protocol specification, Version 2.0B
Programmable acceptance filters
Short latency time for high priority transmit messages
Arbitration scheme according to message ID or message buffer number
Listen only mode capabilities
Programmable clock source: system clock or oscillator clock
Message buffers may be configured as mailboxes or as FIFO
Nexus port controller (NPC)
Per IEEE-ISTO 5001-2003
Real time development support for Power Architecture core and eTPU engine
through Nexus class 2/1
Read and write access (Nexus class 3 feature that is supported on this device)
Run-time access of entire memory map
Calibration
Support for data value breakpoints / watchpoints
Run-time access of entire memory map
Calibration
Table constants calibrated using MMU and internal and external RAM
Scalar constants calibrated using cache line locking
Configured via the IEEE 1149.1 (JTAG) port
IEEE 1149.1 JTAG controller (JTAGC)
IEEE 1149.1-2001 Test Access Port (TAP) interface
5-bit instruction register that supports IEEE 1149.1-2001 defined instructions
5-bit instruction register that supports additional public instructions
Three test data registers: a bypass register, a boundary scan register, and a
device identification register
Censorship disable register. By writing the 64-bit serial boot password to this
register, Censorship may be disabled until the next reset
TAP controller state machine that controls the operation of the data registers,
instruction register and associated circuitry
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On-chip Voltage Regulator for single 5 V supply operation
On-chip regulator 5 V to 3.3 V for internal supplies
On-chip regulator controller 5 V to 1.2 V (with external bypass transistor) for core
logic
Low-power modes
SLOW Mode. Allows device to be run at very low speed (approximately 1 MHz),
with modules (including the PLL) selectively disabled in software
STOP Mode. System clock stopped to all modules including the CPU. Wake-up
timer used to restart the system clock after a predetermined time

2.3 SPC563Mxx feature details

2.3.1 e200z335 core

The e200z335 processor utilizes a four stage pipeline for instruction execution. The Instruction Fetch (stage 1), Instruction Decode/Register file Read/Effective Address Calculation (stage 2), Execute/Memory Access (stage 3), and Register Writeback (stage 4) stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions.
The integer execution unit consists of a 32-bit Arithmetic Unit (AU), a Logic Unit (LU), a 32­bit Barrel shifter (Shifter), a Mask-Insertion Unit (MIU), a Condition Register manipulation Unit (CRU), a Count-Leading-Zeros unit (CLZ), a 32×32 Hardware Multiplier array, result feed-forward hardware, and support hardware for division.
Most arithmetic and logical operations are executed in a single cycle with the exception of the divide instructions. A Count-Leading-Zeros unit operates in a single clock cycle. The Instruction Unit contains a PC incrementer and a dedicated Branch Address adder to minimize delays during change of flow operations. Sequential prefetching is performed to ensure a supply of instructions into the execution pipeline. Branch target prefetching is performed to accelerate taken branches. Prefetched instructions are placed into an instruction buffer capable of holding six instructions.
Branches can also be decoded at the instruction buffer and branch target addresses calculated prior to the branch reaching the instruction decode stage, allowing the branch target to be prefetched early. When a branch is detected at the instruction buffer, a prediction may be made on whether the branch is taken or not. If the branch is predicted to be taken, a target fetch is initiated and its target instructions are placed in the instruction buffer following the branch instruction. Many branches take zero cycle to execute by using branch folding. Branches are folded out from the instruction execution pipe whenever possible. These include unconditional branches and conditional branches with condition codes that can be resolved early.
Conditional branches which are not taken and not folded execute in a single clock. Branches with successful target prefetching which are not folded have an effective execution time of one clock. All other taken branches have an execution time of two clocks. Memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic zero or sign extension of byte and halfword load data as well as optional byte reversal of data. These instructions can be pipelined to allow effective single cycle throughput. Load and store multiple word instructions allow low overhead context save and restore operations. The load/store unit contains a dedicated effective address adder to allow effective address
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generation to be optimized. Also, a load-to-use dependency does not incur any pipeline bubbles for most cases.
The Condition Register unit supports the condition register (CR) and condition register operations defined by the Power Architecture. The condition register consists of eight 4-bit fields that reflect the results of certain operations, such as move, integer and floating-point compare, arithmetic, and logical instructions, and provide a mechanism for testing and branching. Vectored and autovectored interrupts are supported by the CPU. Vectored interrupt support is provided to allow multiple interrupt sources to have unique interrupt handlers invoked with no software overhead.
The hardware floating-point unit utilizes the IEEE-754 single-precision floating-point format and supports single-precision floating-point operations in a pipelined fashion. The general purpose register file is used for source and destination operands, thus there is a unified storage model for single-precision floating-point data types of 32 bits and the normal integer type. Single-cycle floating-point add, subtract, multiply, compare, and conversion operations are provided. Divide instructions are multi-cycle and are not pipelined.
The Signal Processing Extension (SPE) Auxiliary Processing Unit (APU) provides hardware SIMD operations and supports a full complement of dual integer arithmetic operation including Multiply Accumulate (MAC) and dual integer multiply (MUL) in a pipelined fashion. The general purpose register file is enhanced such that all 32 of the GPRs are extended to 64 bits wide and are used for source and destination operands, thus there is a unified storage model for 32×32 MAC operations which generate greater than 32-bit results.
The majority of both scalar and vector operations (including MAC and MUL) are executed in a single clock cycle. Both scalar and vector divides take multiple clocks. The SPE APU also provides extended load and store operations to support the transfer of data to and from the extended 64-bit GPRs.
The CPU includes support for Variable Length Encoding (VLE) instruction enhancements. This enables the classic Power Architecture instruction set to be represented by a modified instruction set made up from a mixture of 16- and 32-bit instructions. This results in a significantly smaller code size footprint without noticeably affecting performance. The Power Architecture instruction set and VLE instruction set are available concurrently. Regions of the memory map are designated as PPC or VLE using an additional configuration bit in each of Table Look-aside Buffers (TLB) entries in the MMU.
The CPU core is enhanced by the addition of two additional interrupt sources; Non­Maskable Interrupt and Critical Interrupt. These two sources are routed directly from package pins, via edge detection logic in the SIU to the CPU, bypassing completely the Interrupt Controller. Once the edge detection logic is programmed, it cannot be disabled, except by reset. The non-maskable Interrupt is, as the name suggests, completely un­maskable and when asserted will always result in the immediate execution of the respective interrupt service routine. The non-maskable interrupt is not guaranteed to be recoverable. The Critical Interrupt is very similar to the non-maskable interrupt, but it can be masked by other exceptional interrupts in the CPU and is guaranteed to be recoverable (code execution may be resumed from where it stopped).
The CPU core has an additional ‘Wait for Interrupt’ instruction that is used in conjunction with low power STOP mode. When Low Power Stop mode is selected, this instruction is executed to allow the system clock to be stopped. An external interrupt source or the system wake-up timer is used to restart the system clock and allow the CPU to service the interrupt.
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2.3.2 Crossbar

The XBAR multi-port crossbar switch supports simultaneous connections between three master ports and four slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width.
The crossbar allows three concurrent transactions to occur from the master ports to any slave port; but each master must access a different slave. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the higher priority master completes its transactions. Requesting masters are treated with equal priority and are granted access to a slave port in round-robin fashion, based upon the ID of the last master to be granted access. The crossbar provides the following features:
3 master ports:
e200z335 core complex Instruction port
e200z335 core complex Load/Store port
–eDMA
4 slave ports
FLASH
calibration bus
–SRAM
Peripheral bridge A/B (eTPU2, eMIOS, SIU, DSPI, eSCI, FlexCAN, eQADC, BAM,
decimation filter, PIT, STM and SWT)
32-bit internal address, 64-bit internal data paths

2.3.3 eDMA

The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data movements via 32 programmable channels, with minimal intervention from the host processor. The hardware micro architecture includes a DMA engine which performs source and destination address calculations, and the actual data movement operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation is utilized to minimize the overall block size. The eDMA module provides the following features:
All data movement via dual-address transfers: read from source, write to destination
Programmable source and destination addresses, transfer size, plus support for
enhanced addressing modes
Transfer control descriptor organized to support two-deep, nested transfer operations
An inner data transfer loop defined by a “minor” byte transfer count
An outer data transfer loop defined by a “major” iteration count
Channel activation via one of three methods:
Explicit software initiation
Initiation via a channel-to-channel linking mechanism for continuous transfers
Peripheral-paced hardware requests (one per channel)
Support for fixed-priority and round-robin channel arbitration
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Channel completion reported via optional interrupt requests
1 interrupt per channel, optionally asserted at completion of major iteration count
Error termination interrupts are optionally enabled
Support for scatter/gather DMA processing
Channel transfers can be suspended by a higher priority channel

2.3.4 Interrupt controller

The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems. The INTC allows interrupt request servicing from up to 191 peripheral interrupt request sources, plus 165 sources reserved for compatibility with other family members).
For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource can not preempt each other.
Multiple processors can assert interrupt requests to each other through software setable interrupt requests. These same software setable interrupt requests also can be used to break the work involved in servicing an interrupt request into a high priority portion and a low priority portion. The high priority portion is initiated by a peripheral interrupt request, but then the ISR asserts a software setable interrupt request to finish the servicing in a lower priority ISR. Therefore these software setable interrupt requests can be used instead of the peripheral ISR scheduling a task through the RTOS.
The INTC provides the following features:
356 peripheral interrupt request sources
8 software setable interrupt request sources
9-bit vector addresses
Unique vector for each interrupt request source
Hardware connection to processor or read from register
Each interrupt source can be programmed to one of 16 priorities
Preemptive prioritized interrupt requests to processor
ISR at a higher priority preempts executing ISRs or tasks at lower priorities
Automatic pushing or popping of preempted priority to or from a LIFO
Ability to modify the ISR or task priority to implement the priority ceiling protocol for
accessing shared resources
Low latency—three clocks from receipt of interrupt request from peripheral to interrupt
request to processor
This device also includes a non-maskable interrupt (NMI) pin that bypasses the INTC and multiplexing logic.
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2.3.5 FMPLL

The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 20 MHz crystal oscillator or external clock generator. Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication factor, output clock divider ratio are all software configurable. The PLL has the following major features:
Input clock frequency from 4 MHz to 20 MHz
Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz, resulting in
system clock frequencies from 16 MHz to 80 MHz with granularity of 4 MHz or better
Reduced frequency divider (RFD) for reduced frequency operation without forcing the
PLL to relock
3 modes of operation
Bypass mode with PLL off
Bypass mode with PLL running (default mode out of reset)
PLL normal mode
Each of the three modes may be run with a crystal oscillator or an external clock
reference
Programmable frequency modulation
Modulation enabled/disabled through software
Triangle wave modulation up to 100 kHz modulation frequency
Programmable modulation depth (0% to 2% modulation depth)
Programmable modulation frequency dependent on reference frequency
Lock detect circuitry reports when the PLL has achieved frequency lock and
continuously monitors lock status to report loss of lock conditions
Clock Quality Module
detects the quality of the crystal clock and cause interrupt request or system reset
if error is detected
detects the quality of the PLL output clock. If an error is detected, causes a system
reset or switches the system clock to the crystal clock and causes an interrupt request
Programmable interrupt request or system reset on loss of lock

2.3.6 Calibration EBI

The Calibration EBI controls data transfer across the crossbar switch to/from memories or peripherals attached to the calibration tool connector in the calibration address space. The Calibration EBI is only available in the calibration tool. The Calibration EBI includes a memory controller that generates interface signals to support a variety of external memories. The Calibration EBI memory controller supports legacy flash, SRAM, and asynchronous memories. In addition, the calibration EBI supports up to three regions via chip selects (two chip selects are multiplexed with two address bits), along with programmed region-specific attributes. The calibration EBI supports the following features:
22-bit address bus (two most significant signals multiplexed with two chip selects)
16-bit data bus
Multiplexed mode with addresses and data signals present on the data lines
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Note: The calibration EBI must be configured in multiplexed mode when the extended Nexus trace
is used on the calibration tool. This is because Nexus signals and address lines of the calibration bus share the same balls in the calibration package.
Memory controller with support for various memory types:
Asynchronous/legacy flash and SRAM
Bus monitor
User selectable
Programmable timeout period (with 8 external bus clock resolution)
Configurable wait states (via chip selects)
3 chip-select (Cal_CS[0], Cal_CS[2:3]) signals (Multiplexed with 2 most significant
address signals)
2 write/byte enable (WE[0:1]/BE[0:1]) signals
Configurable bus speed modes
system frequency
1/2 of system frequency
1/4 of system frequency
Optional automatic CLKOUT gating to save power and reduce EMI
Selectable drive strengths; 10 pF, 20 pF, 30 pF, 50 pF

2.3.7 SIU

The SPC563Mxx SIU controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and the system reset operation. The reset configuration block contains the external pin boot configuration logic. The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU. The reset controller performs reset monitoring of internal and external reset sources, and drives the RSTOUT via the crossbar switch. The SIU provides the following features:
System configuration
MCU reset configuration via external pins
Pad configuration control for each pad
Pad configuration control for virtual I/O via DSPI serialization
System reset monitoring and generation
Power-on reset support
Reset status register provides last reset source to software
Glitch detection on reset input
Software controlled reset assertion
External interrupt
11 interrupt requests
Rising or falling edge event detection
Programmable digital filter for glitch rejection
Critical Interrupt request
Non-Maskable Interrupt request
pin. Communication between the SIU and the e200z335 CPU core is
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GPIO
GPIO function on 80 I/O pins
Virtual GPIO on 64 I/O pins via DSPI serialization (requires external
deserialization device)
Dedicated input and output registers for setting each GPIO and Virtual GPIO pin
Internal multiplexing
Allows serial and parallel chaining of DSPIs
Allows flexible selection of eQADC trigger inputs
Allows selection of interrupt requests between external pins and DSPI

2.3.8 ECSM

The error correction status module provides status information regarding platform memory errors reported by error-correcting codes.

2.3.9 Flash

Devices in the SPC563Mxx family provide up to 1.5 MB of programmable, non-volatile, flash memory. The non-volatile memory (NVM) can be used for instruction and/or data storage. The flash module includes a Fetch Accelerator, that optimizes the performance of the flash array to match the CPU architecture and provides single cycle random access to the flash @ 80 MHz. The flash module interfaces the system bus to a dedicated flash memory array controller. For CPU ‘loads’, DMA transfers and CPU instruction fetch, it supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory. The module contains a four-entry, 128-bit prefetch buffer and a prefetch controller which prefetches sequential lines of data from the flash array into the buffer. Prefetch buffer hits allow no-wait responses. Normal flash array accesses are registered and are forwarded to the system bus on the following cycle, incurring three wait-states. Prefetch operations may be automatically controlled, and are restricted to instruction fetch.
The flash memory provides the following features:
Supports a 64-bit data bus for instruction fetch, CPU loads and DMA access. Byte,
halfword, word and doubleword reads are supported. Only aligned word and doubleword writes are supported.
Fetch Accelerator
Architected to optimize the performance of the flash with the CPU to provide single
cycle random access to the flash up to 80 MHz system clock speed
Configurable read buffering and line prefetch support
Four line read buffers (128 bits wide) and a prefetch controller
Hardware and software configurable read and write access protections on a per-master
basis
Interface to the flash array controller is pipelined with a depth of one, allowing
overlapped accesses to proceed in parallel for interleaved or pipelined flash array designs
Configurable access timing allowing use in a wide range of system frequencies
Multiple-mapping support and mapping-based block access timing (0-31 additional
cycles) allowing use for emulation of other memory types
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Software programmable block program/erase restriction control
Erase of selected block(s)
Read page size of 128 bits (four words)
ECC with single-bit correction, double-bit detection
Program page size of 64 bits (two words)
ECC single-bit error corrections are visible to software
Minimum program size is two consecutive 32-bit words, aligned on a 0-modulo-8 byte
address, due to ECC
Embedded hardware program and erase algorithm
Erase suspend
Shadow information stored in non-volatile shadow block
Independent program/erase of the shadow block

2.3.10 SRAM

The SPC563Mxx SRAM module provides a general-purpose up to 94 KB memory block. The SRAM controller includes these features:
Supports read/write accesses mapped to the SRAM memory from any master
32 KB or 24 KB block powered by separate supply for standby operation
Byte, halfword, word and doubleword addressable
ECC performs single-bit correction, double-bit detection on 32-bit data element

2.3.11 BAM

The BAM (Boot Assist Module) is a block of read-only memory that is programmed once by ST and is identical for all SPC563Mxx MCUs. The BAM program is executed every time the MCU is powered-on or reset in normal mode. The BAM supports different modes of booting. They are:
Booting from internal flash memory
Serial boot loading (A program is downloaded into RAM via eSCI or the FlexCAN and
then executed)
Booting from external memory on calibration bus
The BAM also reads the reset configuration half word (RCHW) from internal flash memory and configures the SPC563Mxx hardware accordingly. The BAM provides the following features:
Sets up MMU to cover all resources and mapping all physical address to logical
addresses with minimum address translation
Sets up the MMU to allow user boot code to execute as either Power Architecture code
(default) or as VLE code
Detection of user boot code
Automatic switch to serial boot mode if internal flash is blank or invalid
Supports user programmable 64-bit password protection for serial boot mode
Supports serial bootloading via FlexCAN bus and eSCI using fixed baudrate protocol
Supports serial bootloading via FlexCAN bus and eSCI with auto baud rate sensing
Supports serial bootloading of either Power Architecture code (default) or VLE code
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Supports booting from calibration bus interface
Supports censorship protection for internal flash memory
Provides an option to enable the core watchdog timer
Provides an option to disable the software watchdog timer

2.3.12 eMIOS

The eMIOS (Enhanced Modular Input Output System) module provides the functionality to generate or measuretime events. The channels on this module provide a range of operating modes including the capability to perform dual input capture or dual output compare as well as PWM output.
The eMIOS provides the following features:
16 channels (24-bit timer resolution)
For compatibility with other family members selected channels and timebases are
implemented:
Channels 0 to 6, 8 to 15, and 23
Timebases A, B and C
Channels 1, 3, 5 and 6 support modes:
General Purpose Input/Output (GPIO)
Single Action Input Capture (SAIC)
Single Action Output Compare (SAOC)
Channels 2, 4, 11 and 13 support all the modes above plus:
Output Pulse Width Modulation Buffered (OPWMB)
Channels 0, 8, 9, 10, 12, 14, 15, 23 support all the modes above plus:
Input Period Measurement (IPM)
Input Pulse Width Measurement (IPWM)
Double Action Output Compare (set flag on both matches) (DAOC)
Modulus Counter Buffered (MCB)
Output Pulse Width and Frequency Modulation Buffered (OPWFMB)
Three 24-bit wide counter buses
Counter bus A can be driven by channel 23 or by the eTPU2 and all channels can
use it as a reference
Counter bus B is driven by channel 0 and channels 0 to 6 can use it as a reference
Counter bus C is driven by channel 8 and channels 8 to 15 can use it as a
reference
Shared time bases with the eTPU2 through the counter buses
Synchronization among internal and external time bases

2.3.13 eTPU2

The eTPU2 is an enhanced co-processor designed for timing control. Operating in parallel with the host CPU, eTPU2 processes instructions and real-time input events, performs output waveform generation, and accesses shared data without host intervention. Consequently, for each timer event, the host CPU setup and service times are minimized or eliminated. A powerful timer subsystem is formed by combining the eTPU2 with its own
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instruction and data RAM. High-level assembler/compiler and documentation allows customers to develop their own functions on the eTPU2.
The eTPU2 includes these distinctive features:
The Timer Counter (TCR1), channel logic and digital filters (both channel and the
external timer clock input [TCRCLK]) now have an option to run at full system clock speed or system clock / 2.
Channels support unordered transitions: transition 2 can now be detected before
transition 1. Related to this enhancement, the transition detection latches (TDL1 and TDL2) can now be independently negated by microcode.
A new User Programmable Channel Mode has been added: the blocking, enabling,
service request and capture characteristics of this channel mode can be programmed via microcode.
Microinstructions now provide an option to issue Interrupt and Data Transfer requests
selected by channel. They can also be requested simultaneously at the same instruction.
Channel Flags 0 and 1 can now be tested for branching, in addition to selecting the
entry point.
Channel digital filters can be bypassed.
The Timer Counter (TCR1), channel logic and digital filters (both channel and the
external timer clock input [TCRCLK]) now have an option to run at full system clock speed or system clock / 2.
Channels support unordered transitions: transition 2 can now be detected before
transition 1. Related to this enhancement, the transition detection latches (TDL1 and TDL2) can now be independently negated by microcode.
A new User Programmable Channel Mode has been added: the blocking, enabling,
service request and capture characteristics of this channel mode can be programmed via microcode.
Microinstructions now provide an option to issue Interrupt and Data Transfer requests
selected by channel. They can also be requested simultaneously at the same instruction.
Channel Flags 0 and 1 can now be tested for branching, in addition to selecting the
entry point.
Channel digital filters can be bypassed.
32 channels, each channel is associated with one input and one output signal
Enhanced input digital filters on the input pins for improved noise immunity.
Identical, orthogonal channels: each channel can perform any time function. Each
time function can be assigned to more than one channel at a given time, so each signal can have any functionality.
Each channel has an event mechanism which supports single and double action
functionality in various combinations. It includes two 24-bit capture registers, two 24-bit match registers, 24-bit greater-equal and equal-only comparators
Input and output signal states visible from the host
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2 independent 24-bit time bases for channel synchronization:
First time base clocked by system clock with programmable prescale division from
2 to 512 (in steps of 2), or by output of second time base prescaler
Second time base counter can work as a continuous angle counter, enabling
angle based applications to match angle instead of time
Both time bases can be exported to the eMIOS timer module
Both time bases visible from the host
Event-triggered microengine:
Fixed-length instruction execution in two-system-clock microcycle
14 KB of code memory (SCM)
3 KB of parameter (data) RAM (SPRAM)
Parallel execution of data memory, ALU, channel control and flow control sub-
instructions in selected combinations
32-bit microengine registers and 24-bit wide ALU, with 1 microcycle addition and
subtraction, absolute value, bitwise logical operations on 24-bit, 16-bit, or byte operands, single-bit manipulation, shift operations, sign extension and conditional execution
Additional 24-bit Multiply/MAC/Divide unit which supports all signed/unsigned
Multiply/MAC combinations, and unsigned 24-bit divide. The MAC/Divide unit works in parallel with the regular microcode commands
Resource sharing features support channel use of common channel registers, memory
and microengine time:
Hardware scheduler works as a “task management” unit, dispatching event
service routines by predefined, host-configured priority
Automatic channel context switch when a “task switch” occurs, i.e., one function
thread ends and another begins to service a request from other channel: channel­specific registers, flags and parameter base address are automatically loaded for the next serviced channel
SPRAM shared between host CPU and eTPU2, supporting communication either
between channels and host or inter-channel
Dual-parameter coherency hardware support allows atomic access to two
parameters by host
Test and development support features:
Nexus Class 1 debug, supporting single-step execution, arbitrary microinstruction
execution, hardware breakpoints and watchpoints on several conditions
Software breakpoints
SCM continuous signature-check built-in self test (MISC — multiple input
signature calculator), runs concurrently with eTPU2 normal operation
System enhancements
Software watchdog with programmable timeout
Real-time performance information
Channel enhancements
Channels 1 and 2 can optionally drive angle clock hardware
Programming enhancements
Engine relative addressing mode
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2.3.14 eQADC

The enhanced queued analog to digital converter (eQADC) block provides accurate and fast conversions for a wide range of applications. The eQADC provides a parallel interface to two on-chip analog to digital converters (ADC), and a single master to single slave serial interface to an off-chip external device. Both on-chip ADCs have access to all the analog channels.
The eQADC prioritizes and transfers commands from six command conversion command ‘queues’ to the on-chip ADCs or to the external device. The block can also receive data from the on-chip ADCs or from an off-chip external device into the six result queues, in parallel, independently of the command queues. The six command queues are prioritized with Queue_0 having the highest priority and Queue_5 the lowest. Queue_0 also has the added ability to bypass all buffering and queuing and abort a currently running conversion on either ADC and start a Queue_0 conversion. This means that Queue_0 will always have a deterministic time from trigger to start of conversion, irrespective of what tasks the ADCs were performing when the trigger occurred. The eQADC supports software and external hardware triggers from other blocks to initiate transfers of commands from the queues to the on-chip ADCs or to the external device. It also monitors the fullness of command queues and result queues, and accordingly generates DMA or interrupt requests to control data movement between the queues and the system memory, which is external to the eQADC.
The ADCs also support features designed to allow the direct connection of high impedance acoustic sensors that might be used in a system for detecting engine knock. These features include differential inputs; integrated variable gain amplifiers for increasing the dynamic range; programmable pull-up and pull-down resistors for biasing and sensor diagnostics.
The eQADC also integrates a programmable decimation filter capable of taking in ADC conversion results at a high rate, passing them through a hardware low pass filter, then down-sampling the output of the filter and feeding the lower sample rate results to the result FIFOs. This allows the ADCs to sample the sensor at a rate high enough to avoid aliasing of out-of-band noise; while providing a reduced sample rate output to minimize the amount DSP processing bandwidth required to fully process the digitized waveform.
The eQADC provides the following features:
Dual on-chip ADCs
–2 × 12-bit ADC resolution
Programmable resolution for increased conversion speed (12 bit, 10 bit, 8 bit)
12-bit conversion time – 1 μs (1M sample/sec)
10-bit conversion time – 867 ns (1.2M sample/second)
8-bit conversion time – 733 ns (1.4M sample/second)
Up to 10-bit accuracy at 500 KSample/s and 9-bit accuracy at 1 MSample/s
Differential conversions
Single-ended signal range from 0 to 5 V – Variable gain amplifiers on differential inputs (×1, ×2, ×4)
Sample times of 2 (default), 8, 64 or 128 ADC clock cycles
Provides time stamp information when requested
Parallel interface to eQADC CFIFOs and RFIFOs
Supports both right-justified unsigned and signed formats for conversion results
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Up to 34
23 additional internal channels for measuring control and monitoring voltages inside
(d)
input channels (accessible by both ADCs)
the device
Including Core voltage, I/O voltage, LVI voltages, etc.
An internal bandgap reference to allow absolute voltage measurements
4 pairs of differential analog input channels
Programmable pull-up/pull-down resistors on each differential input for biasing and
sensor diagnostic (200 kΩ, 100 kΩ, 5 kΩ)
Silicon die temperature sensor
provides temperature of silicon as an analog value
read using an internal ADC analog channel
may be read with either ADC
Decimation Filter
Programmable decimation factor (2 to 16)
Selectable IIR or FIR filter
Up to 4th order IIR or 8th order FIR
Programmable coefficients
Saturated or non-saturated modes
Programmable Rounding (Convergent; Two’s Complement; Truncated)
Pre-fill mode to pre-condition the filter before the sample window opens
Full duplex synchronous serial interface to an external device
Free-running clock for use by an external device
Supports a 26-bit message length
Priority based Queues
Supports six Queues with fixed priority. When commands of distinct Queues are
bound for the same ADC, the higher priority Queue is always served first
Queue_0 can bypass all prioritization, buffering and abort current conversions to
start a Queue_0 conversion a deterministic time after the queue trigger
Streaming mode operation of Queue_0 to execute some commands several times
Supports software and hardware trigger modes to arm a particular Queue
Generates interrupt when command coherency is not achieved
External hardware triggers
Supports rising edge, falling edge, high level and low level triggers
Supports configurable digital filter
Supports four external 8-to-1 muxes which can expand the input channels to 56
channels total

2.3.15 DSPI

The deserial serial peripheral interface (DSPI) block provides a synchronous serial interface for communication between the SPC563Mxx MCU and external devices. The DSPI supports
d. 176-pin and 208-pin packages have 34 input channels; 144-pin package has 32; 100-pin package has 23.
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pin count reduction through serialization and deserialization of eTPU and eMIOS channels and memory-mapped registers. The channels and register content are transmitted using a SPI-like protocol. This SPI-like protocol is completely configurable for baud rate, polarity and phase, frame length, chip select assertion, etc. Each bit in the frame may be configured to serialize either eTPU channels, eMIOS channels or GPIO signals. The DSPI can be configured to serialize data to an external device that supports the Microsecond Channel protocol. There are two identical DSPI blocks on the SPC563Mxx MCU. The DSPI output pins support 5 V logic levels or Low Voltage Differential Signalling (LVDS) according to the Microsecond Channel specification.
The DSPIs have three configurations:
Serial peripheral interface (SPI) configuration where the DSPI operates as an up to 16-
bit SPI with support for queues
Enhanced deserial serial interface (DSI) configuration where DSPI serializes up to 32
bits with three possible sources per bit
eTPU, eMIOS, new virtual GPIO registers as possible bit source
Programmable inter-frame gap in continuous mode
Bit source selection allows microsecond channel downstream with command or
data frames up to 32 bits
Microsecond channel dual receiver mode
Combined serial interface (CSI) configuration where the DSPI operates in both SPI and
DSI configurations interleaving DSI frames with SPI frames, giving priority to SPI frames
For queued operations, the SPI queues reside in system memory external to the DSPI. Data transfers between the memory and the DSPI FIFOs are accomplished through the use of the eDMA controller or through host software.
The DSPI supports these SPI features:
Full-duplex, synchronous transfers
Selectable LVDS Pads working at 40 MHz for SOUT and SCK pins
Master and Slave Mode
Buffered transmit operation using the TX FIFO with parameterized depth of 4 entries
Buffered receive operation using the RX FIFO with parameterized depth of 4 entries
TX and RX FIFOs can be disabled individually for low-latency updates to SPI queues
Visibility into the TX and RX FIFOs for ease of debugging
FIFO Bypass Mode for low-latency updates to SPI queues
Programmable transfer attributes on a per-frame basis:
Parameterized number of transfer attribute registers (from two to eight)
Serial clock with programmable polarity and phase
Various programmable delays:
PCS to SCK delay
SCK to PCS delay
Delay between frames
Programmable serial frame size of 4 to 16 bits, expandable with software control
Continuously held chip select capability
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6 Peripheral Chip Selects, expandable to 64 with external demultiplexer
Deglitching support for up to 32 Peripheral Chip Selects with external demultiplexer
DMA support for adding entries to TX FIFO and removing entries from RX FIFO:
TX FIFO is not full (TFFF)
RX FIFO is not empty (RFDF)
6 Interrupt conditions:
End of queue reached (EOQF)
TX FIFO is not full (TFFF)
Transfer of current frame complete (TCF)
Attempt to transmit with an empty Transmit FIFO (TFUF)
RX FIFO is not empty (RFDF)
FIFO Underrun (slave only and SPI mode, the slave is asked to transfer data when
the TxFIFO is empty)
FIFO Overrun (serial frame received while RX FIFO is full)
Modified transfer formats for communication with slower peripheral devices
Continuous Serial Communications Clock (SCK)
Power savings via support for Stop Mode
Enhanced DSI logic to implement a 32-bit Timed Serial Bus (TSB) configuration,
supporting the Microsecond Channel downstream frame format
The DSPIs also support these features unique to the DSI and CSI configurations:
2 sources of the serialized data:
eTPU_A and eMIOS output channels
Memory-mapped register in the DSPI
Destinations for the deserialized data:
eTPU_A and eMIOS input channels
SIU External Interrupt Request inputs
Memory-mapped register in the DSPI
Deserialized data is provided as Parallel Output signals and as bits in a memory-
mapped register
Transfer initiation conditions:
Continuous
Edge sensitive hardware trigger
Change in data
Pin serialization/deserialization with interleaved SPI frames for control and diagnostics
Continuous serial communications clock
Support for parallel and serial chaining of up to four DSPI blocks

2.3.16 eSCI

The enhanced serial communications interface (eSCI) allows asynchronous serial communications with peripheral devices and other MCUs. It includes special support to
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interface to Local Interconnect Network (LIN) slave devices. The eSCI block provides the following features:
Full-duplex operation
Standard mark/space non-return-to-zero (NRZ) format
13-bit baud rate selection
Programmable 8-bit or 9-bit, data format
Programmable 12-bit or 13-bit data format for Timed Serial Bus (TSB) configuration to
support the Microsecond Channel upstream
Automatic parity generation
LIN support
Autonomous transmission of entire frames
Configurable to support all revisions of the LIN standard
Automatic parity bit generation
Double stop bit after bit error
10- or 13-bit break support
Separately enabled transmitter and receiver
Programmable transmitter output parity
2 receiver wake up methods:
Idle line wake-up
Address mark wake-up
Interrupt-driven operation with flags
Receiver framing error detection
Hardware parity checking
1/16 bit-time noise detection
DMA support for both transmit and receive data
Global error bit stored with receive data in system RAM to allow post processing of
errors

2.3.17 FlexCAN

The SPC563Mxx MCU contains two controller area network (FlexCAN) blocks. The FlexCAN module is a communication controller implementing the CAN protocol according to Bosch Specification version 2.0B. The CAN protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. FlexCAN module ‘A’ contains 64 message buffers (MB); FlexCAN module ‘C’ contains 32 message buffers.
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The FlexCAN module provides the following features:
Full Implementation of the CAN protocol specification, Version 2.0B
Standard data and remote frames
Extended data and remote frames
Zero to eight bytes data length
Programmable bit rate up to 1 Mbit/s
Content-related addressing
64 / 32 message buffers of zero to eight bytes data length
Individual Rx Mask Register per message buffer
Each message buffer configurable as Rx or Tx, all supporting standard and extended
messages
Includes 1056 / 544 bytes of embedded memory for message buffer storage
Includes a 256-byte and a 128-byte memories for storing individual Rx mask registers
Full featured Rx FIFO with storage capacity for six frames and internal pointer handling
Powerful Rx FIFO ID filtering, capable of matching incoming IDs against 8 extended, 16
standard or 32 partial (8 bits) IDs, with individual masking capability
Selectable backwards compatibility with previous FlexCAN versions
Programmable clock source to the CAN Protocol Interface, either system clock or
oscillator clock
Listen only mode capability
Programmable loop-back mode supporting self-test operation
3 programmable Mask Registers
Programmable transmit-first scheme: lowest ID, lowest buffer number or highest priority
Time Stamp based on 16-bit free-running timer
Global network time, synchronized by a specific message
Maskable interrupts
Warning interrupts when the Rx and Tx Error Counters reach 96
Independent of the transmission medium (an external transceiver is assumed)
Multi master concept
High immunity to EMI
Short latency time due to an arbitration scheme for high-priority messages
Low power mode, with programmable wake-up on bus activity

2.3.18 System timers

The system timers provide two distinct types of system timer:
Periodic interrupts/triggers using the Periodic Interrupt Timer (PIT)
Operating system task monitors using the System Timer Module (STM)
Periodic Interrupt Timer (PIT)
The PIT provides five independent timer channels, capable of producing periodic interrupts and periodic triggers. The PIT has no external input or output pins and is intended to be used to provide system ‘tick’ signals to the operating system, as well as periodic triggers for eQADC queues. Of the five channels in the PIT, four are clocked by the system clock, one is
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clocked by the crystal clock. This one channel is also referred to as Real Time Interrupt (RTI) and is used to wakeup the device from low power stop mode.
The following features are implemented in the PIT:
5 independent timer channels
Each channel includes 32-bit wide down counter with automatic reload
4 channels clocked from system clock
1 channel clocked from crystal clock (wake-up timer)
Wake-up timer remains active when System STOP mode is entered. Used to restart
system clock after predefined timeout period
Each channel can optionally generate an interrupt request or a trigger event (to trigger
eQADC queues) when the timer reaches zero
System Timer Module (STM)
The System Timer Module (STM) is designed to implement the software task monitor as defined by AUTOSAR (see http://www.autosar.org). It consists of a single 32-bit counter, clocked by the system clock, and four independent timer comparators. These comparators produce a CPU interrupt when the timer exceeds the programmed value.
The following features are implemented in the STM:
One 32-bit up counter with 8-bit prescaler
Four 32-bit compare channels
Independent interrupt source for each channel
Counter can be stopped in debug mode

2.3.19 Software Watchdog Timer (SWT)

The Software Watchdog Timer (SWT) is a second watchdog module to complement the standard Power Architecture watchdog integrated in the CPU core. The SWT is a 32-bit modulus counter, clocked by the system clock or the crystal clock, that can provide a system reset or interrupt request when the correct software key is not written within the required time window.
The following features are implemented:
32-bit modulus counter
Clocked by system clock or crystal clock
Optional programmable watchdog window mode
Can optionally cause system reset or interrupt request on timeout
Reset by writing a software key to memory mapped register
Enabled out of reset
Configuration is protected by a software key or a write-once register

2.3.20 Debug features

Nexus port controller
The NPC (Nexus Port Controller) block provides real-time development support capabilities for the SPC563Mxx Power Architecture-based MCU in compliance with the IEEE-ISTO 5001-2003 standard. This development support is supplied for MCUs without requiring
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Overview SPC563M64L5, SPC563M64L7
external address and data pins for internal visibility. The NPC block is an integration of several individual Nexus blocks that are selected to provide the development support interface for SPC563Mxx. The NPC block interfaces to the host processor (e200z335), eTPU, and internal buses to provide development support as per the IEEE-ISTO 5001-2003 standard. The development support provided includes program trace and run-time access to the MCUs internal memory map and access to the Power Architecture and eTPU internal registers during halt. The Nexus interface also supports a JTAG only mode using only the JTAG pins. SPC563Mxx in the production LQFP144 supports a 3.3 V reduced (4-bit wide) Auxiliary port. These Nexus port pins can also be used as 5 V I/O signals to increase usable I/O count of the device. When using this Nexus port as IO, Nexus trace is still possible using calibration tool calibration. In the calibration tool calibration package, the full 12-bit Auxiliary port is available.
Note: In the calibration tool package, the full Nexus Auxiliary port shares balls with the addresses
of the calibration bus. Therefore multiplexed address/data bus mode must be used for the calibration bus when using full width Nexus trace in calibration tool assembly.
The following features are implemented:
5-pin JTAG port (JCOMP, TDI, TDO, TMS, and TCK)
Always available in production package
Supports both JTAG Boundary Scan and debug modes
–3.3V interface
Supports Nexus class 1 features
Supports Nexus class 3 read/write feature
9-pin Reduced Port interface in LQFP144 production package
Alternate function as IO
5 V (in GPIO or alternate function mode), 3.3 V (in Nexus mode) interface
Auxiliary Output port
1 MCKO (message clock out) pin
4 MDO (message data out) pins
2 MSEO
1 EVTO
(message start/end out) pins
(event out) pin
Auxiliary input port
1 EVTI
17-pin Full Port interface in calibration package used on calibration tool boards
(event in) pin
–3.3V interface
Auxiliary Output port
1 MCKO (message clock out) pin
4 (reduced port mode) or 12 (full port mode) MDO (message data out) pins; 8 extra full port pins shared with calibration bus
2 MSEO
1 EVTO
(message start/end out) pins
(event out) pin
Auxiliary input port
1 EVTI
(event in) pin
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Host processor (e200) development support features
IEEE-ISTO 5001-2003 standard class 2 compliant
Program trace via branch trace messaging (BTM). Branch trace messaging
displays program flow discontinuities (direct branches, indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the discontinuities. Thus, static code may be traced.
Watchpoint trigger enable of program trace messaging
Data Value Breakpoints (JTAG feature of the e200z335 core): allows CPU to be
halted when the CPU writes a specific value to a memory location
4 data value breakpoints
CPU only
Detects ‘equal’ and ‘not equal’
Byte, half word, word (naturally aligned)
Note: This feature is imprecise due to CPU pipelining.
Subset of Power Architecture software debug facilities with OnCE block (Nexus
class 1 features)
eTPU development support features
IEEE-ISTO 5001-2003 standard class 1 compliant for the eTPU
Nexus based breakpoint configuration and single step support (JTAG feature of
the eTPU)
Run-time access to the on-chip memory map via the Nexus read/write access protocol.
This feature supports accesses for run-time internal visibility, calibration variable acquisition, calibration constant tuning, and external rapid prototyping for powertrain automotive development systems.
All features are independently configurable and controllable via the IEEE 1149.1 I/O
port
Power-on-reset status indication during reset via MDO[0] in disabled and reset modes
JTAG
The JTAGC (JTAG Controller) block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. Testing is performed via a boundary scan technique, as defined in the IEEE 1149.1-2001 standard. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block is compliant with the IEEE 1149.1-2001 standard and supports the following features:
IEEE 1149.1-2001 Test Access Port (TAP) interface 4 pins (TDI, TMS, TCK, and TDO)
A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined
instructions:
BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD, HIGHZ, CLAMP
A 5-bit instruction register that supports the additional following public instructions:
ACCESS_AUX_TAP_NPC
ACCESS_AUX_TAP_ONCE
ACCESS_AUX_TAP_eTPU
ACCESS_CENSOR
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3 test data registers to support JTAG Boundary Scan mode
Bypass register
Boundary scan register
Device identification register
A TAP controller state machine that controls the operation of the data registers,
instruction register and associated circuitry
Censorship Inhibit Register
64-bit Censorship password register
If the external tool writes a 64-bit password that matches the Serial Boot password
stored in the internal flash shadow row, Censorship is disabled until the next system reset.

2.4 SPC563Mxx series architecture

2.4.1 Block diagram

Figure 1 shows a top-level block diagram of the SPC563Mxx series.
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JTAG Port
Nexus Port
NMI
Clocks
Interrupt Request
Nexus
eTPU
PLL
SIU
Reset Control
External
Interrupt Request
IMUX
GPIO &
Pad Control
JTAG
NMI
SIU
critical
Interrupt
Requests from
Peripheral
Blocks & eDMA
CQM
STM
Nexus
eTPU
NEXUS 1
32 Ch.+
Engine
RAM
14 KB/3 KB
MMU
Controller
SWT
e200z335
SPE
Nexus 2+
Interrupt
(INTC)
PIT
Peripheral Bridge
16 Ch.
eMIOS
eDMA
DMA Requests from Peripheral Blocks
2x
DSPIs
Instructions
M
Data
M
M
eDMA, FLASH, Bridge B,
crossbar, SRAM
Configuration
2x
eSCIs
S
S
64-bit
S
3 x 4
S
Crossbar Switch
2x
CANs
Calibration
Bus
Interface
Flash
1.5 MB
SRAM 62 KB
Vol ta ge
Regulator (1.2V, 3.3V,
STB RAM)
BAM
eQADC
ADC
Decimation
32 KB
ADCI
AMUX
Filter
ADC
Serial Analog IF
Analog
V
stby
Temp. Sensor
I/O
. . .
. . .
. . .
. . .
Figure 1. SPC563Mxx series block diagram

2.4.2 Block summary

Ta bl e 3 summarizes the functions of the blocks present on the SPC563Mxx series
microcontrollers.
Table 3. SPC563Mxx series block summary
e200z3 core Executes programs and interrupt handlers.
Flash memory Provides storage for program code, constants, and variables
RAM (random-access memory) Provides storage for program code, constants, and variables
Block Function
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Table 3. SPC563Mxx series block summary (continued)
Block Function
Calibration bus
DMA (direct memory access)
DSPI (deserial serial peripheral interface)
eMIOS (enhanced modular input-output system)
eQADC (enhanced queued analog-to-digital converter)
eSCI (serial communication interface)
eTPU (enhanced time processor unit)
Transfers data across the crossbar switch to/from peripherals attached to the VertiCal connector
Performs complex data movements with minimal intervention from the core
Provides a synchronous serial interface for communication with external devices
Provides the functionality to generate or measure events
Provides accurate and fast conversions for a wide range of applications
Allows asynchronous serial communications with peripheral devices and other microcontroller units
Processes real-time input events, performs output waveform generation, and accesses shared data without host intervention
FlexCAN (controller area network) Supports the standard CAN communications protocol
FMPLL (frequency-modulated phase-locked loop)
Generates high-speed system clocks and supports the programmable frequency modulation of these clocks
INTC (interrupt controller) Provides priority-based preemptive scheduling of interrupt requests
JTAG controller
NPC (Nexus Port Controller)
Provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode
Provides real-time development support capabilities in compliance with the IEEE-ISTO 5001-2003 standard
PIT (peripheral interrupt timer) Produces periodic interrupts and triggers
Temperature sensor Provides the temperature of the device as an analog value
SWT (Software Watchdog Timer) Provides protection from runaway code
STM (System Timer Module)
Timer providing a set of output compare events to support AutoSAR and operating system tasks
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3 Pinout and signal description

This section contains the pinouts for all production packages for the SPC563Mxx family of devices. Please note the following:
Pins labeled “NC” are to be left unconnected. Any connection to an external circuit or
voltage may cause unpredictable device behavior or damage.
Pins labeled “NIC” have no internal connection.

3.1 LQFP100 pinout

Figure 2 shows the pinout for the 100-pin LQFP.
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Figure 2. 100-pin LQFP pinout (top view)
AN[13] / MA[1] / ETPU_A[21] / SDO
AN[14] / MA[2] / ETPU_A[27] / SDI
AN[15] / FCK / ETPU_A[29]
VSS
VDDEH7
AN[12] / MA[0] / ETPU_A[19] / SDS
76
75
TMS
74
TDI / eMIOS[5] / GPIO[232]
73
TCK
72
VSS
71
VDDEH7
70
TDO / eMIOS[6] / GPIO[228]
69
JCOMP
68
DSPI_B_PCS[3] / DSPI_C_SIN / GPIO[108]
67
DSPI_B_SIN / DSPI_C_PCS[2] / GPIO[103]
66
VDDEH6B
65
VSS
64
DSPI_B_SCK / DSPI_C_PCS[1] / GPIO[102]
63
DSPI_B_PCS[4] / DSPI_C_SCK / GPIO[109]
62
VDD
61
RSTOUT
60
CAN_C_TX / GPIO[87]
59
CAN_C_RX / GPIO[88]
58
RESET
57
VSS
56
VDDEH6A
55
VSSPLL
54
XTAL
53
EXTAL / EXTCLK
52
VDDPLL
51
VSS
AN[11] / ANZ
AN[9] / ANX
AN[39] / AN[10] / ANY
AN[38] / AN[8] / ANW
VDDREG
VRCCTL
eTPU_A[31] / DSPI_C_PCS[4] / eTPU_A[13] / GPIO[145] eTPU_A[30] / DSPI_C_PCS[3] / eTPU_A[11] / GPIO[144]
eTPU_A[26] / IRQ
eTPU_A[25] / IRQ eTPU_A[24] / IRQ
eTPU_A[29] / DSPI_C_PCS[2] / GPIO[143] eTPU_A[28] / DSPI_C_PCS[1] / GPIO[142]
[14] / DSPI_C_SOUT_LVDS– / GPIO[140]
[13] / DSPI_C_SCK_LVDS+ / GPIO[139] [12] / DSPI_C_SCK_LVDS– / GPIO[138]
eTPU_A[15] / DSPI_B_PCS[5] / GPIO[129]
eTPU_A[14] / DSPI_B_PCS[4] / eTPU_A[9] / GPIO[128]
(see signal details, pin 15
VDDEH1A
VDDEH1B
VDDA VSSA
VSTBY VRC33
VSS
VDD
VSS
AN[21]
AN[0] (DAN0+)
AN[1] (DAN0–)
AN[2] (DAN1+)
AN[3] (DAN1–)
AN[4] (DAN2+)
AN[5] (DAN2–)
AN[6] (DAN3+)
AN[7] (DAN3–)
REFBYPC
VRH
VRL
AN[23]
AN[25]
AN[28]
AN[31]
AN[33]
AN[35]
VDD
9998979695949392919089888786858483828180797877
100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
signal details:
21 22
pin 15: eTPU_A[27] / IRQ[15] / DSPI_C_SOUT_LVDS+ /
23 24 25
DSPI_B_SOUT / GPIO[141]
100–Pin
LQFP
26272829303132333435363738394041424344454647484950
VSS
VDDEH1B
eTPU_A[4] / eTPU_A[16] / GPIO[118]
eTPU_A[3] / eTPU_A[15] / GPIO[117]
eTPU_A[2] / eTPU_A[14] / GPIO[116]
eTPU_A[1] / eTPU_A[13] / GPIO[115]
eTPU_A[13] / DSPI_B_PCS[3] / GPIO[127]
eTPU_A[5] / eTPU_A[17] / DSPI_B_SCK_LVDS– / GPIO[119]
eTPU_A[6] / eTPU_A[18] / DSPI_B_SCK_LVDS+ / GPIO[120]
eTPU_A[8] / eTPU_A[20] / DSPI_B_SOUT_LVDS+ / GPIO[122]
eTPU_A[7] / eTPU_A[19] / DSPI_B_SOUT_LVDS– / eTPU_A[6] / GPIO[121]
eTPU_A[0] / eTPU_A[12] / eTPU_A[19] / GPIO[114]
VSS
VDD
VDDEH6A
[4]/ETRIG[2] / GPIO[208]
[3] / ETRIG[3] / GPIO[212]
[0] / eTPU_A[29] / GPIO[193]
/ DSPI_B_SOUT / GPIO[213]
CAN_A_TX / SCI_A_TX / GPIO[83]
CAN_A_RX / SCI_A_RX / GPIO[84]
PLLREF / IRQ
BOOTCFG1 / IRQ
WKPCFG / NMI
eMIOS[14] / IRQ
eMIOS[8] / eTPU_A[8] / SCI_B_TX / GPIO[187]
eMIOS[9] / eTPU_A[9] / SCI_B_RX / GPIO[188]
eMIOS[0] / eTPU_A[0] / eTPU_A[25] / GPIO[179]
eMIOS[12] / DSPI_C_SOUT / eTPU_A[27] / GPIO[191]
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3.2 LQFP144 pinout

Figure 3 shows the pinout for the 144-pin LQFP.
Figure 3. 144-pin LQFP pinout (top view; all 144-pin devices)
[0] / eTPU_A[27] / GPIO[224]
AN[21]
AN[0] (DAN0+)
AN[1] (DAN0–)
AN[2] (DAN1+)
AN[3] (DAN1–)
AN[4] (DAN2+)
AN[5] (DAN2–)
AN[6] (DAN3+)
AN[7] (DAN3–)
REFBYPC
VRH
VRL
AN[22]
AN[23]
AN[24]
AN[25]
AN[27]
AN[28]
AN[30]
AN[31]
AN[32]
AN[33]
AN[34]
AN[35]
VDD
AN[12] / MA[0] / ETPU_A[19] / SDS
AN[13] / MA[1] / ETPU_A[21] / SDO
AN[14] / MA[2] / ETPU_A[27] / SDI
AN[15] / FCK / ETPU_A[29]
VSS
MDO[3] / eTPU_A[25] / GPIO[223]
VDDEH7
MDO[2] / eTPU_A[21] / GPIO[222]
MDO[1] / eTPU_A[19] / GPIO[221]
MDO[0] / eTPU_A[13] / GPIO[220]
MSEO
AN[18] AN[17] AN[16]
AN[11] / ANZ
AN[9] / ANX
VDDA
AN[39] / AN[10] / ANY
AN[38] / AN[8] / ANW
(see signal details, pin 14)
eTPU_A[29] / DSPI_C_PCS[2] / GPIO[1 43] eTPU_A[28] / DSPI_C_PCS[1] / GPIO[1 42]
eTPU_A[15] / DSPI_B_PCS[5] / GPIO[129]
(see signal details, pin 15)
(see signal details, pin 18) (see signal details, pin 19) (see signal details, pin 20) (see signal details, pin 21)
(see signal details, pin 23)
(see signal details, pin 25)
eTPU_A[21] / IRQ eTPU_A[20] / IRQ
eTPU_A[19] / GPIO[133] eTPU_A[18] / GPIO[132] eTPU_A[17] / GPIO[131] eTPU_A[16] / GPIO[130]
(see signal details, pin 35)
VSSA
VDDREG
VRCCTL
VSTBY VRC33
VSS
VDDEH1A
VDD [9] / GPIO[135] [8] / GPIO[134]
VDDEH1B
VSS
119
118
117
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
signal details:
22
pin 14: eTPU_A[31] / DSPI_C_PCS[4] / eTPU_A[13] / GPIO[145]
23 24
pin 15: eTPU_A[30] / DSPI_C_PCS[3] / eTPU_A [11] / GPIO[144]
25
pin 18: eTPU_A[27] / IRQ
26
GPIO[141]
27
pin 19: eTPU_A[26] / IRQ
28 29
pin 20: eTPU_A[25] / IRQ[13] / SCK_C_LVDS+ / GPIO[139]
30
pin 21: eTPU_A[24] / IRQ[12] / SCK_ C_LVDS– / GPIO[138]
31
pin 23: eTPU_A[23] / IRQ[11] / eTPU_A[21] / GPIO[137]
32 33
pin 25: eTPU_A[22] / IRQ
34
pin 35: eTPU_A[14] / DSPI_B_PCS[4] / eTPU_A[9] / GPIO[128]
35 36
3738394041424344454647484950515253545556575859606162636465666768697071
144-Pin
LQFP
[15] / DSPI_C_SOUT_LVDS+ / DSPI_B_SOUT /
[14] / DSPI_C_SOUT_LVDS– / GPIO[140]
[10] / eTPU_A[17] / GPIO[136]
121
120
116
111
115
114
113
112
110
109
108
TMS
107
TDI / eMIOS[5] / GPIO[232]
106
EVTO
/ eTPU_A[4] / GPIO[227]
105
TCK
104
VSS
103
EVTI
/ eTPU_A[2] / GPIO[231]
102
VDDEH7
101
MSEO
100
[1] / eTPU_A[29] / GPIO[225]
TDO / eMIOS[6] / GPIO[228]
99
MCKO / GPIO[219]
98
JCOMP
97
DSPI_B_PCS[3] / DSPI_C_SIN / GPIO[108]
96
DSPI_B_SOUT / DSPI_C_PCS[5] / GPIO[104]
95
DSPI_B_SIN / DSPI_C_PCS[2] / GPIO[103]
94
DSPI_B_PCS[0] / GPIO[105]
93
VDDEH6B
92
DSPI_B_PCS[1] / GPIO[106]
91
VSS
90
DSPI_B_PCS[2] / DSPI_C_SOUT / GPIO[107]
89
DSPI_B_SCK / DSPI_C_PCS[1] / GPIO[102]
88
DSPI_B_PCS[4] / DSPI_C_SCK / GPIO[109]
87
DSPI_B_PCS[5] / DSPI_C_PCS[0] / GP IO[110]
86
VDD
85
RSTOUT
84
CAN_C_TX / GPIO[87]
83
SCI_A_TX / eMIOS[13] / GPIO[89]
82
SCI_A_RX / eMIOS[15] / GPIO[90]
81
CAN_C_RX / GPIO[88]
80
RESET
79
VSS
78
VDDEH6A
77
VSSPLL
76
XTAL
75
EXTAL / EXTCLK
74
VDDPLL
73
VSS
72
eTPU_A[13] / DSPI_B_PCS[3] / GPIO[127]
eTPU_A[12] / DSPI_B_PCS[1] / GPIO[126]
eTPU_A[11] / eTPU_A[23] / GPIO[125]
eTPU_A[10] / eTPU_A[22] / GPIO[124]
eTPU_A[9] / eTPU_A[21] / GPIO[123]
eTPU_A[8] / eTPU_A[20] / DSPI_B_SOUT_LVDS+ / GPIO[122]
eTPU_A[6] / eTPU_A[18] / DSPI_B_SCK_LVDS+ / GPIO[120]
eTPU_A[7] / eTPU_A[19] / DSPI_B_SOUT_LVDS– / eTPU_A[6] / GPIO[121]
VSS
VDDEH1B
eTPU_A[4] / eTPU_A[16] / GPIO[118]
eTPU_A[5] / eTPU_A[17] / DSPI_B_SCK_LVDS– / GPIO[119]
VDD
eTPU_A[3] / eTPU_A[15] / GPIO[117]
eTPU_A[2] / eTPU_A[14] / GPIO[116]
eTPU_A[1] / eTPU_A[13] / GPIO[115]
eMIOS[0] / eTPU_A[0] / eTPU_A[25] / GPIO[179]
eTPU_A[0] / eTPU_A[12] / eTPU_A[19] / GPIO[114]
eMIOS[2] / eTPU_A[2] / GPIO[181]
eMIOS[4] / eTPU_A[4] / GPIO[183]
eMIOS[8] / eTPU_A[8] / SCI_B_TX / GPIO[187]
eMIOS[9] / eTPU_A[9] / SCI_B_RX / GPIO[188]
VSS
VDDEH6A
eMIOS[10] / GPIO[189]
eMIOS[11] / GPIO[190]
eMIOS[12] / DSPI_C_SOUT / eTPU_A[27] / GPIO[191]
eMIOS[23] / GPIO[202]
[0] / eTPU_A[29] / GPIO[193]
eMIOS[14] / IRQ
CAN_A_TX / SCI_A_TX / GPIO[83]
[4]/ETRIG[2] / GPIO[208]
CAN_A_RX / SCI_A_RX / GPIO[84]
PLLREF / IRQ
SCI_B_RX / GPIO[92]
[3] / ETRIG[3] / GPIO[212]
BOOTCFG1 / IRQ
SCI_B_TX / GPIO[91]
/ DSPI_B_SOUT / GPIO[213]
WKPCFG / NMI
Doc ID 14642 Rev 9 45/142
Pinout and signal description SPC563M64L5, SPC563M64L7

3.3 LQFP176 pinout (SPC563M64)

Figure 4 shows the 176-pin LQFP pinout for the SPC563M64 (1536 KB flash memory).
Figure 4. 176-pin LQFP pinout (SPC563M64; top view)
NIC
AN[37]
AN[36]
AN[21]
AN[0] (DAN0+)
AN[1] (DAN0–)
AN[2] (DAN1+)
AN[3] (DAN1–)
AN[4] (DAN2+)
AN[5] (DAN2–)
AN[6] (DAN3+)
AN[7] (DAN3–)
REFBYPC
VRH
VRL
AN[22]
AN[23]
AN[24]
AN[25]
AN[27]
AN[28]
AN[30]
AN[31]
AN[32]
AN[33]
AN[34]
AN[35]
VDD
AN[12] / MA[0] / ETPU_A[19] / SDS
AN[13] / MA[1] / ETPU_A[21] / SDO
AN[14] / MA[2] / ETPU_A[27] / SDI
AN[15] / FCK / ETPU_A[29]
GPIO[207]
GPIO[206]
GPIO[99]
GPIO[98]
VSS
eTPU_A[25] / GPIO[223]
VDDEH7
eTPU_A[21] / GPIO[222]
eTPU_A[19] / GPIO[221]
eTPU_A[13] / GPIO[220]
eTPU_A[27] / GPIO[224]
VSS
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
NIC
132
TMS
131
TDI / eMIOS[5] / GPIO[232]
130
eTPU_A[4] / GPIO[227]
129
TCK
128
VSS
127
eTPU_A[2] / GPIO[231]
126
VDDEH7
125
eTPU_A[29] / GPIO[225]
124
TDO / eMIOS[6] / GPIO[228]
123
GPIO[219]
122
JCOMP
121
ALT_EVTO
120
VDDE12
119
ALT_MSEO[0]
118
ALT_MSEO
117 116 115 114 113 112
111 110 109 108 107 106 105 104 103 102 101 100
99 98 97 96 95 94 93 92 91 90 89
88
NIC
[1] ALT_EVTI VSS DSPI_B_PCS[3] / DSPI_C_SIN / GPIO[108] DSPI_B_SOUT / DSPI_C_PCS[5] / GPIO[104] DSPI_B_SIN / DSPI_C_PCS[2] / GPIO[103] DSPI_B_PCS[0] / GPIO[105] VDDEH6B DSPI_B_PCS[1] / GPIO[106] VSS DSPI_B_PCS[2] / DSPI_C_SOUT / GPIO[107] DSPI_B_SCK / DSPI_C_PCS[1] / GPIO[102] DSPI_B_PCS[4] / DSPI_C_SCK / GPIO[109] DSPI_B_PCS[5] / DSPI_C_PCS[0] / GPIO[110] VDD RSTOUT CAN_C_TX / GPIO[87] SCI_A_TX / eMIOS[13] / GPIO[89] SCI_A_RX / eMIOS[15] / GPIO[90] CAN_C_RX / GPIO[88] RESET VSS VDDEH6A VSSPLL XTAL EXTAL / EXTCLK VDDPLL VSS NIC
AN[39] / AN[10] / ANY
AN[38] / AN[8] / ANW
(see signal details, pin 21) (see signal details, pin 22) (see signal details, pin 23) (see signal details, pin 24) (see signal details, pin 25) (see signal details, pin 26) (see signal details, pin 27) (see signal details, pin 28)
(see signal details, pin 30)
(see signal details, pin 32)
eTPU_A[21] / IRQ eTPU_A[20] / IRQ
eTPU_A[19] / GPIO[133] eTPU_A[18] / GPIO[132] eTPU_A[17] / GPIO[131] eTPU_A[16] / GPIO[130]
(see signal details, pin 40)
(see signal details, pin 42)
AN[18] AN[17] AN[16]
AN[11] / ANZ
AN[9] / ANX
VDDA VSSA
VDDREG
VRCCTL
VSTBY VRC33
ALT_MCKO
VSS
VDDE12 ALT_MDO[0] ALT_MDO[1] ALT_MDO[2] ALT_MDO[3]
VSS
VDDEH1A
VDD [9] / GPIO[135] [8] / GPIO[134]
VDDEH1B
VSS
NIC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
signal details:
23
pin 21: eTPU_A[31] / DSPI_C_PCS[4] / eTPU_A[13] / GPIO[145]
24 25
pin 22: eTPU_A[30] / DSPI_C_PCS[3] / eTPU_A[11] / GPIO[144]
26 27
pin 23: eTPU_A[29] / DSPI_C_PCS[2] / GPIO[143]
28
pin 24: eTPU_A[28] / DSPI_C_PCS[1] / GPIO[142]
29 30
pin 25:
31 32 33 34 35 36 37 38 39 40 41 42 43 44
eTPU_A[27] / IRQ[15] / DSPI_C_SOUT_LVDS+ / DSPI_B_SOUT / GPIO[141]
pin 26: eTPU_A[26] / IRQ
pin 27: eTPU_A[25] / IRQ
pin 28: eTPU_A[24] / IRQ
pin 30: eTPU_A[23] / IRQ
pin 32: eTPU_A[22] / IRQ
pin 40: eTPU_A[15] / DSPI_B_PCS[5] / GPIO[129]
pin 42: eTPU_A[14] / DSPI_B_PCS[4] / eTPU_A[9] / GPIO[128]
45464748495051525354555657585960616263646566676869707172737475767778798081828384858687
NIC
VDDEH1B
176 - Pin
LQFP
[14] / DSPI_C_SOUT_LVDS– / GPIO[140]
[13] / DSPI_C_SCK_LVDS+ / GPIO[139]
[12] / DSPI_C_SCK_LVDS– / GPIO[138]
[11] / eTPU_A[21] / GPIO[137]
[10] / eTPU_A[17] / GPIO[136]
NIC
NIC
VSS
VDD
NIC
VSS
VDDEH6A
eMIOS[11] / GPIO[190]
eMIOS[10] / GPIO[189]
eMIOS[1] / eTPU_A[1] / GPIO[180]
eMIOS[2] / eTPU_A[2] / GPIO[181]
eMIOS[0] / eTPU_A[0] / eTPU_A[25] / GPIO[179]
eMIOS[4] / eTPU_A[4] / GPIO[183]
eMIOS[8] / eTPU_A[8] / SCI_B_TX / GPIO[187]
eMIOS[9] / eTPU_A[9] / SCI_B_RX / GPIO[188]
eTPU_A[13] / DSPI_B_PCS[3] / GPIO[127]
eTPU_A[12] / DSPI_B_PCS[1] / GPIO[126]
eTPU_A[11] / eTPU_A[23] / GPIO[125]
eTPU_A[10] / eTPU_A[22] / GPIO[124]
eTPU_A[9] / eTPU_A[21] / GPIO[123]
eTPU_A[8] / eTPU_A[20] / DSPI_B_SOUT_LVDS+ / GPIO[122]
eTPU_A[6] / eTPU_A[18] / DSPI_B_SCK_LVDS+ / GPIO[120]
eTPU_A[7] / eTPU_A[19] / DSPI_B_SOUT_LVDS– / eTPU_A[6] / GPIO[121]
eTPU_A[4] / eTPU_A[16] / GPIO[118]
eTPU_A[3] / eTPU_A[15] / GPIO[117]
eTPU_A[2] / eTPU_A[14] / GPIO[116]
eTPU_A[1] / eTPU_A[13] / GPIO[115]
eTPU_A[0] / eTPU_A[12] / eTPU_A[19] / GPIO[114]
eTPU_A[5] / eTPU_A[17] / DSPI_B_SCK_LVDS– / GPIO[119]
Note: Pins marked “NIC” have no internal connection.
46/142 Doc ID 14642 Rev 9
eMIOS[13] / GPIO[192]
eMIOS[12] / DSPI_C_SOUT / eTPU_A[27] / GPIO[191]
[0] / eTPU_A[29] / GPIO[193]
eMIOS[15] / IRQ[1] / GPIO[194]
eMIOS[14] / IRQ
eMIOS[23] / GPIO[202]
CAN_A_TX / SCI_A_TX / GPIO[83]
CAN_A_RX / SCI_A_RX / GPIO[84
SCI_B_RX / GPIO[92]
[4]/ETRIG[2] / GPIO[208]
PLLREF / IRQ
[3] / ETRIG[3] / GPIO[212]
/ DSPI_B_SOUT / GPIO[213]
BOOTCFG1 / IRQ
WKPCFG / NMI
SCI_B_TX / GPIO[91]
SPC563M64L5, SPC563M64L7 Pinout and signal description

3.4 LQFP176 pinout (SPC563M60)

Figure 5 shows the pinout for the 176-pin LQFP for the SPC563M60 (1024 KB flash
memory).
Figure 5. 176-pin LQFP pinout (SPC563M60; top view)
NICNCNC
AN[21]
AN[0] (DAN0+)
AN[1] (DAN0-)
AN[2] (DAN1+)
AN[3] (DAN1-)
AN[4] (DAN2+)
AN[5] (DAN2-)
AN[6] (DAN3+)
AN[7] (DAN3-)
REFBYPC
VRH
VRL
AN[22]
AN[23]
AN[24]
AN[25]
AN[27]
AN[28]
AN[30]
AN[31]
AN[32]
AN[33]
AN[34]
AN[35]
VDD
AN[12] / MA[0] / ETPU_A[19] / SDSAN[13] / MA[1] / ETPU_A[21] / SDOAN[14] / MA[2] / ETPU_A[27] / SDI
AN[15] / FCK / ETPU_A[29]NCNCNCNC
VSS
eTPU_A[25] / GPIO[223]
VDDEH7
eTPU_A[21] / GPIO[222]
eTPU_A[19] / GPIO[221]
eTPU_A[13] / GPIO[220]
eTPU_A[27] / GPIO[224]
VSS
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
NIC
132
TMS
131
TDI / eMIOS[5] / GPIO[232]
130
eTPU_A[4] / GPIO[227]
129
TCK
128
VSS
127
eTPU_A[2] / GPIO[231]
126
VDDEH7
125
eTPU_A[29] / GPIO[225]
124
TDO / eMIOS[6] / GPIO[228]
123
GPIO[219]
122
JCOMP
121
ALT_EVTO
120
VDDE12
119
ALT_MSEO[0]
118
ALT_MSEO
117 116 115 114 113 112 111
110 109 108 107 106 105 104 103 102 101 100
99 98 97 96 95 94 93 92 91 90 89
88
NIC
[1] ALT_EVTI VSS DSPI_B_PCS[3] / DSPI_C_SIN / GPIO[108] DSPI_B_SOUT / DSPI_C_PCS[5] / GPIO[104] DSPI_B_SIN / DSPI_C_PCS[2] / GPIO[103] DSPI_B_PCS[0] / GPIO[105] VDDEH6B DSPI_B_PCS[1] / GPIO[106] VSS DSPI_B_PCS[2] / DSPI_C_SOUT / GPIO[107] DSPI_B_SCK / DSPI_C_PCS[1] / GPIO[102] DSPI_B_PCS[4] / DSPI_C_SCK / GPIO[109] DSPI_B_PCS[5] / DSPI_C_PCS[0] / GPIO[110] VDD RSTOUT CAN_C_TX / GPIO[87] SCI_A_TX / eMIOS[13] / GPIO[89] SCI_A_RX / eMIOS[15] / GPIO[90] CAN_C_RX / GPIO[88] RESET VSS VDDEH6A VSSPLL XTAL EXTAL / EXTCLK VDDPLL VSS NIC
AN[39] / AN[10] / ANY
AN[38] / AN[8] / ANW
(see signal details, pin 21) (see signal details, pin 22) (see signal details, pin 23) (see signal details, pin 24) (see signal details, pin 25) (see signal details, pin 26) (see signal details, pin 27) (see signal details, pin 28)
(see signal details, pin 30)
(see signal details, pin 32)
eTPU_A[21] / IRQ eTPU_A[20] / IRQ
eTPU_A[19] / GPIO[133] eTPU_A[18] / GPIO[132] eTPU_A[17] / GPIO[131] eTPU_A[16] / GPIO[130]
(see signal details, pin 40)
(see signal details, pin 42)
AN[18] AN[17] AN[16]
AN[11] / ANZ
AN[9] / ANX
VDDA
VSSA
VDDREG
VRCCTL
VSTBY VRC33
ALT_MCKO
VSS
VDDE12 ALT_MDO[0] ALT_MDO[1] ALT_MDO[2] ALT_MDO[3]
VSS
VDDEH1A
VDD [9] / GPIO[135] [8] / GPIO[134]
VDDEH1B
VSS
NIC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
signal details:
23 24
Pin 21: eTPU_A[31] / DSPI_C_PCS[4] / eTPU_A[13] / GPIO[145]
25 26
Pin 22: eTPU_A[30] / DSPI_C_PCS[3] / eTPU_A[11] / GPIO[144]
27
Pin 23: eTPU_A[29] / DSPI_C_PCS[2] / GPIO[143]
28 29
Pin 24: eTPU_A[28]/ DSPI_C_PCS[1] / GPIO[142]
30
Pin 25: eTPU_A[27] / IRQ[15] / DSPI_C_SOUT_LVDS+ / DSPI_B_SOUT / GPIO[141]
31 32
Pin 26: eTPU_A[26] / IRQ
33 34
Pin 27: eTPU_A[25] / IRQ
35 36
Pin 28: eTPU_A[24] / IRQ
37
Pin 30: eTPU_A[23] / IRQ
38 39
Pin 32: eTPU_A[22] / IRQ
40 41
Pin 40: eTPU_A[15] / DSPI_B_PCS[5] / GPIO[129]
42 43
Pin 42: eTPU_A[14] / DSPI_B_PCS[4] / eTPU_A[9] / GPIO[128]
44
45464748495051525354555657585960616263646566676869707172737475767778798081828384858687
NIC
VSS
VDDEH1B
176-Pin
LQFP
[14] / DSPI_C_SOUT_LVDS- / GPIO[140]
[13] / DSPI_C_SCK_LVDS+ / GPIO[139]
[12] / DSPI_C_SCK_LVDS- / GPIO[138]
[11] / eTPU_A[21] / GPIO[137]
[10] / eTPU_A[17] / GPIO[136]
NC
NIC
NIC
NIC
VDD
VSS
VDDEH6A
NC
NC
eMIOS[23] / GPIO[202]
CAN_A_TX / SCI_A_TX / GPIO[83]
[4]/ETRIG[2] / GPIO[208]
CAN_A_RX / SCI_A_RX / GPIO[84]
PLLREF / IRQ
SCI_B_RX / GPIO[92]
[3] / ETRIG[3] / GPIO[212]
BOOTCFG1 / IRQ
/ DSPI_B_SOUT / GPIO[213]
WKPCFG / NMI
eTPU_A[9] / eTPU_A[21] / GPIO[123]
eTPU_A[11] / eTPU_A[23] / GPIO[125]
eTPU_A[10] / eTPU_A[22] / GPIO[124]
eTPU_A[13] / DSPI_B_PCS[3] / GPIO[127]
eTPU_A[12] / DSPI_B_PCS[1] / GPIO[126]
eTPU_A[8]/eTPU_A[20]/DSPI_B_SOUT_LVDS+/GPIO[122]
eTPU_A[5] / eTPU_A[17] / DSPI_B_SCK_LVDS- / GPIO[119]
eTPU_A[6] / eTPU_A[18] / DSPI_B_SCK_LVDS+ / GPIO[120]
Notes:
1
. Pins marked “NIC” have no internal connection.
eTPU_A[7]/eTPU_A[19]/DSPI_B_SOUT_LVDS-/eTPU_A[6]/GPIO[121]
eMIOS[11] / GPIO[190]
eMIOS[10] / GPIO[189]
[0] / eTPU_A[29] / GPIO[193]
eMIOS[2] / eTPU_A[2] / GPIO[181]
eMIOS[0] / eTPU_A[0] / eTPU_A[25] / GPIO[179]
eMIOS[4] / eTPU_A[4] / GPIO[183]
eMIOS[8] / eTPU_A[8] / SCI_B_TX / GPIO[187]
eMIOS[9] / eTPU_A[9] / SCI_B_RX / GPIO[188]
eMIOS[14] / IRQ
eMIOS[12] / DSPI_C_SOUT / eTPU_A[27] / GPIO[191]
eTPU_A[4] / eTPU_A[16] / GPIO[118]
eTPU_A[3] / eTPU_A[15] / GPIO[117]
eTPU_A[2] / eTPU_A[14] / GPIO[116]
eTPU_A[1] / eTPU_A[13] / GPIO[115]
eTPU_A[0] / eTPU_A[12] / eTPU_A[19] / GPIO[114]
SCI_B_TX / GPIO[91]
2. Pins marked “NC” are not functional pins but may be connected to internal circuitry. Connections to external circuits or other pins on this device can result in unpredictable system behavior or damage.
Doc ID 14642 Rev 9 47/142
48/142 Doc ID 14642 Rev 9

3.5 LBGA208 ballmap (SPC563M64)

Figure 6 shows the 208-pin LBGA ballmap for the SPC563M64 (1536 KB flash memory) as viewed from above.
Figure 6. 208-pin LBGA ballmap (SPC563M64; top view)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Pinout and signal description SPC563M64L5, SPC563M64L7
A VSS AN9 AN11 VDDA1 VSSA1 AN1 AN5 VRH VRL AN27 VSSA0 AN12- SDS
B VDD VSS AN38 AN21 AN0 AN4 REFBYPC AN22 AN25 AN28 VDDA0 AN13-SDO
C VSTBY VDD VSS AN17 AN34 AN16 AN3 AN7 AN23 AN32 AN33 AN14-SDI
ALT_
MDO2
ALT_
MDO3
AN15
FCK
D VRC33 AN39 VDD VSS AN18 AN2 AN6 AN24 AN30 AN31 AN35 VDDEH7 VSS TMS ALT_EVTO NIC
E ETPUA30 ETPUA31 AN37 VDD VDDE7 TDI ALT_EVTI
ALT_
MDO0
ALT_
MDO1
VSS
VRC33 VSS
VSS VDD
ALT_
MSEO0
TCK
ALT_
MSEO1
(1)
F ETPUA28 ETPUA29 ETPUA26 AN36 VDDEH6 TDO ALT_MCKO JCOMP
G ETPUA24 ETPUA27 ETPUA25 ETPUA21 VSS VSS VSS VSS
DSPI_B_
SOUT
H ETPUA23 ETPUA22 ETPUA17 ETPUA18 VSS VSS VSS VSS GPIO99
J ETPUA20 ETPUA19 ETPUA14 ETPUA13 VSS VSS VSS VSS
K ETPUA16 ETPUA15 ETPUA7 VDDEH1 VSS VSS VSS VSS
DSPI_B_
PCS5
CAN_C_
TX
L ETPUA12 ETPUA11 ETPUA6 ETPUA0 SCI_B_TX
DSPI_B_
PCS3
DSPI_B_
PCS4
SCI_A_TX GPIO98
DSPI_B_
SIN
DSPI_B_
PCS2
DSPI_B_
PCS0
DSPI_B_
PCS1
DSPI_B_
SCK
SCI_A_RX RSTOUT VDDREG
CAN_C_
RX
WKPCFG RESET
M ETPUA10 ETPUA9 ETPUA1 ETPUA5 SCI_B_RX PLLREF BOOTCFG1 VSSPLL
N ETPUA8 ETPUA4 ETPUA0 VSS VDD VRC33 EMIOS2 EMIOS10
P ETPUA3 ETPUA2 VSS VDD GPIO207 VDDE7 NIC
(1)
RNIC
TVSS VDD NIC
VSS VDD GPIO206 EMIOS4 NIC
(1)
EMIOS0 EMIOS1 GPIO219
(1)
(1)
EMIOS8
EMIOS9 EMIOS11 EMIOS14
(
eTPU_A25
EMIOS13 EMIOS15 eTPU_A4
3)
VDDEH1/6
(2)
eTPU_A29
3)
EMIOS12
(
eTPU_A2
eTPU_A27
eTPU_A19
(3)
eTPU_A21
(3)
3)
(
EMIOS23
3)
eTPU_A13
(3)
3)
VRC33 VSS VRCCTL NIC
(
(
CAN_A_
TX
CAN_A_
RX
NIC
VDD VSS NIC
(1)
NIC
(1)
VDDE5 CLKOUT VDD VSS
VDD VSS VDDPLL
(1)
EXTAL
(1)
XTAL
1. Pins marked “NIC” have no internal connection.
2. This ball may be changed to “NC” (no connection) in a future revision.
3. eTPU output only channel.

3.6 Signal summary

SPC563M64L5, SPC563M64L7 Pinout and signal description
Table 4. SPC563Mx signal properties
Name Function
GPIO[98] GPIO PCR[98] I/O
GPIO[99] GPIO PCR[99] I/O
Doc ID 14642 Rev 9 49/142
GPIO[206]
GPIO[207]
(8)
(8)
RESET
RSTOUT
PLLREF
[4]
IRQ
ETRIG[2]
GPIO[208]
BOOTCFG1
[3]
IRQ
ETRIG[3]
GPIO[212]
WKPCFG
NMI
DSPI_B_SOUT
GPIO[213]
GPIO PCR[206] I/O
GPIO PCR[207] I/O
External Reset Input I
External Reset Output PCR[230] O
FMPLL Mode Selection
External Interrupt Request
eQADC Trigger Input
GPIO
Boot Config. Input
External Interrupt Request
eQADC Trigger Input
GPIO
Weak Pull Config. Input
Non-Maskable Interrupt
DSPI_B Data Output
GPIO
LQFP
144
Pin No.
LQFP
176
LBGA208
Pad
(1)
Config.
Register
(PCR)
(2)
PCR PA
(3)
Field
I/O
Typ e
Vol tag e
Pad Type
(4)
/
Reset
(5)
State
Function /
State After
(6)
Reset
LQFP
100
Dedicated GPIO
VDDEH7
Slow
VDDEH7
Slow
VDDEH7
Slow
VDDEH7
Slow
– / Up GPIO[98]/Up 141
– / Up GPIO[99]/Up 142
– / Up GPIO[206]/Up 143
– / Up GPIO[207]/Up 144
(7)
(7)
(7)
(7)
J15
H13
R4
P5
Reset / Configuration
PCR[208]
PCR[212]
PCR[213]
011
010
100
000
011
010
100
000
01
11
10
00
I/O
I/O
O
I/O
I
I
I
I
I
I
I
I
VDDEH6a
Slow
VDDEH6a
Slow
VDDEH6a
Slow
VDDEH6a
Slow
VDDEH6a
Slow
I / Up
RSTOUT/
Low
PLLREF / Up – / Up 48 68 83 M14
BOOTCFG1 /
Down
WKPCFG /
Up
RESET
/
Up
RSTOUT/
High
58 80 97 L16
61 85 102 K15
– / Down 49 70 85 M15
– / Up 50 71 86 L15
50/142 Doc ID 14642 Rev 9
Table 4. SPC563Mx signal properties (continued)
Name Function
(1)
Pad
Config.
Register
(2)
(PCR)
PCR PA
(3)
Field
I/O
Vol tag e
Typ e
Calibration
(4)
Pad Type
(9)
Pinout and signal description SPC563M64L5, SPC563M64L7
LQFP
144
Pin No.
LQFP
176
LBGA208
/
Reset
(5)
State
Function /
State After
(6)
Reset
LQFP
100
CAL_ADDR[12:15]
CAL_ADDR[16]
ALT_MDO[0]
CAL_ADDR[17]
ALT_MDO[1]
CAL_ADDR[18]
ALT_MDO[2]
CAL_ADDR[19]
ALT_MDO[3]
(20)
(11)
(20)
(11)
(20)
(11)
(20)
(11)
CAL_ADDR[20:27]
ALT_MDO[4:11]
CAL_ADDR[28]
ALT_MSEO[0]
CAL_ADDR[29]
ALT_MSEO[1]
CAL_ADDR[30]
ALT_EVTI
(20)
(11)
(20)
(11)
(20)
(11)
(10)
Calibration Address Bus PCR[340] O
Calibration Address Bus
Nexus Msg Data Out
Calibration Address Bus
Nexus Msg Data Out
Calibration Address Bus
Nexus Msg Data Out
Calibration Address Bus
Nexus Msg Data Out
Calibration Address Bus
Nexus Msg Data Out
Calibration Address Bus
Nexus Msg Start/End Out
Calibration Address Bus
Nexus Msg Start/End Out
Calibration Address Bus
Nexus Event In
PCR[345]
PCR[345]
PCR[345]
PCR[345]
PCR[345]
PCR[345]
PCR[345]
PCR[345]
VDDE12
Fast
VDDE12
O
VDDE7
O
O
O
O
O
O
O
Fast
VDDE12
VDDE7
Fast
VDDE12
VDDE7
Fast
VDDE12
VDDE7
Fast
OOVDDE12
Fast
VDDE12
O
VDDE7
O
O
O
O
I
Fast
VDDE12
VDDE7
Fast
VDDE12
VDDE7
Fast
(12)
(13)
(12)
(13)
(12)
(13)
(12)
(13)
(12)
(12)
(13)
(12)
(13)
(12)
(13)
O / Low
O / Low
O / Low
O / Low
O / Low
O / Low
O / Low
O / Low
(17)
(14)
(14)
(14)
(14)
(16)
(16)
CAL_ADDR /
Low
MDO /
ALT_ADDR
Low
ALT_MDO /
CAL_ADDR
Low
ALT_MDO /
CAL_ADDR
Low
ALT_MDO /
CAL_ADDR
Low
ALT_MDO /
CAL_ADDR
Low
ALT_MSEO
CAL_ADDR
Low
ALT_MSEO
CAL_ADDR
Low
ALT_EVTI /
CAL_ADDR
(11)
(11)
(11)
(11)
(15)
(15)
(16)
(15)
(16)
(18)
——— —
/
——17 A14
/
——18 B14
/
——19 A13
/
——20 B13
/
——— —
/
/
118 C15
/
/
117 E16
116 E15
Table 4. SPC563Mx signal properties (continued)
(1)
Doc ID 14642 Rev 9 51/142
Name Function
ALT_EVTO Nexus Event Out PCR[344] O
ALT_MCKO Nexus Msg Clock Out PCR[344] O
Nexus/Calibration bus selector
Calibration Chip Selects PCR[336] O
Calibration Chip Selects
Calibration Address Bus
Calibration Chip Selects
Calibration Address Bus
Calibration Data Bus PCR[341] I/O
Calibration Data Bus PCR[341] I/O
Calibration Output Enable PCR[342] O
Calibration Read/Write PCR[342] O
Calibration Transfer Start
Address Latch Enable
Calibration Write Enable
Byte Enable
[0]
[2]
(10)
(10)
(10)
NEXUSCFG
CAL_CS
CAL_CS
CAL_ADDR[10]
(10)
CAL_CS
[3]
CAL_ADDR[11]
CAL_DATA[0:9]
(10)
CAL_DATA[10:15]
CAL_OE
CAL_RD_WR
CAL_TS
CAL_WE
(10)
(10)
(10)
_ALE
_BE[0:1]
(10)
(10)
Pad
Config.
Register
(PCR)
(2)
PCR PA
(3)
Field
I/O
Typ e
——I
PCR[338]
PCR[339]
11
10
11
10
TS=0b1
PCR[343]
ALE=0b
0
PCR[342] O
NEXUS
O
O
O
O
O
O
Vol tag e
Pad Type
VDDE12
VDDE7
Fast
VDDE12
VDDE7
Fast
VDDE12
Fast
VDDE12
Fast
VDDE12
Fast
VDDE12
Fast
VDDE12
Fast
VDDE12
Fast
VDDE12
Fast
VDDE12
Fast
VDDE12
Fast
VDDE12
Fast
(19)
(4)
(12)
(13)
(12)
(13)
/
Reset
(5)
State
O / Low
O / Low
I / Down
Function /
State After
(6)
Reset
ALT_EVTO
/
High
ALT_MCKO /
Enabled
NEXUSCFG /
Down
LQFP
100
120 D15
——14 F15
——— —
Pin No.
LQFP
144
O / High CAL_CS / High
O / High CAL_CS
O / High CAL_CS
/ High
/ High
– / Up – / Up
– / Up – / Up
O / High CAL_OE / High
O / High
CAL_RD_WR
/High
O / High CAL_TS
O / High
CAL_WE /
High
——— —
/ High
——— —
LQFP
176
SPC563M64L5, SPC563M64L7 Pinout and signal description
LBGA208
52/142 Doc ID 14642 Rev 9
Table 4. SPC563Mx signal properties (continued)
Name Function
(20)
EVTI
eTPU_A[2]
GPIO[231]
(20)
EVTO
eTPU_A[4]
GPIO[227]
(20)
MCKO
GPIO[219]
(20)
MDO[0]
eTPU_A[13]
GPIO[220]
(20)
MDO[1]
eTPU_A[19]
GPIO[221]
(20)
MDO[2]
eTPU_A[21]
GPIO[222]
(20)
MDO[3]
eTPU_A[25]
GPIO[223]
(20)
[0]
MSEO
eTPU_A[27]
GPIO[224]
(20)
[1]
MSEO
eTPU_A[29]
GPIO[225]
Nexus Event In
eTPU A Ch.
GPIO
Nexus Event Out
eTPU A Ch.
GPIO
Nexus Msg Clock Out
GPIO
Nexus Msg Data Out
eTPU A Ch.
GPIO
Nexus Msg Data Out
eTPU A Ch.
GPIO
Nexus Msg Data Out
eTPU A Ch.
GPIO
Nexus Msg Data Out
eTPU A Ch.
GPIO
Nexus Msg Start/End Out
eTPU A Ch.
GPIO
Nexus Msg Start/End Out
eTPU A Ch.
GPIO
(1)
Pad
Config.
Register
(PCR)
PCR[231]
PCR[227]
PCR[219]
PCR[220]
PCR[221]
PCR[222]
PCR[223]
PCR[224]
PCR[225]
(2)
PCR PA
(3)
Field
01
10
00
(21)
01
10
00
(21)
N/A
00
01
10
00
(21)
01
10
00
(21)
01
10
00
(21)
01
10
00
(21)
01
10
00
(21)
01
10
00
I/O
Typ e
I
O
I/O
O
O
I/O
O
I/O
O
O
I/O
O
O
I/O
O
O
I/O
O
O
I/O
O
O
I/O
O
O
I/O
Vol tag e
Pad Type
VDDEH7
Multi-V
VDDEH7
Multi-V
VDDEH7
Multi-V
VDDEH7
Multi-V
VDDEH7
Multi-V
VDDEH7
Multi-V
VDDEH7
Multi-V
VDDEH7
Multi-V
VDDEH7
Multi-V
Pinout and signal description SPC563M64L5, SPC563M64L7
LQFP
144
Pin No.
LQFP
176
LBGA208
(4)
/
Reset
(5)
State
Function /
State After
(6)
Reset
LQFP
100
– / – – / – 103 126 P10
I / Up I / Up 106 129 T10
– / – – / – 99 122 T6
– / – – / – 110 135 T11
– / – – / – 111 136 N11
– / – – / – 112 137 P11
– / – – / – 114 139 T7
– / – – / – 109 134 R10
– / – – / – 101 124 P9
JTAG / TEST
TC K JTAG Te s t C l oc k I np u t I
VDDEH7
Multi-V
TCK / Down TCK / Down 73 105 128 C16
Table 4. SPC563Mx signal properties (continued)
(1)
Doc ID 14642 Rev 9 53/142
Name Function
(22)
TDI
eMIOS[5]
GPIO[232]
(22)
TDO
eMIOS[6]
GPIO[228]
JTAG Test Data Input
eMIOS Ch.
GPIO
JTAG Test Data Output
eMIOS Ch.
GPIO
TMS JTAG Test Mode Select Input I
JCOMP JTAG TAP Controller Enable I
Pad
Config.
Register
(PCR)
PCR[232]
PCR[228]
(2)
PCR PA
(3)
Field
(23)
01
10
00
(23)
01
10
00
I/O
Typ e
I
O
I/O
O
O
I/O
CAN
Vol tag e
Pad Type
VDDEH7
Multi-V
VDDEH7
Multi-V
VDDEH7
Multi-V
VDDEH7
Multi-V
(4)
/
Reset
(5)
State
Function /
State After
(6)
Reset
LQFP
100
LQFP
144
– / – – / – 74 107 130 E14
– / – – / – 70 100 123 F14
TMS / Up TMS / Up 75 108 131 D14
JCOMP /
Down
JCOMP / Down 69 98 121 F16
Pin No.
LQFP
176
SPC563M64L5, SPC563M64L7 Pinout and signal description
LBGA208
CAN_A_TX
SCI_A_TX
GPIO[83]
CAN_A_RX
SCI_A_RX
GPIO[84]
CAN_C_TX
GPIO[87]
CAN_C_RX
GPIO[88]
SCI_A_TX
eMIOS[13]
GPIO[89]
SCI_A_RX
eMIOS[15]
GPIO[90]
(25)
CAN_A Transmit
eSCI_A Transmit
GPIO
CAN_A Receive
eSCI_A Receive
GPIO
CAN_C Transmit
GPIO
CAN_C Receive
GPIO
eSCI_A Transmit
eMIOS Ch.
GPIO
eSCI_A Receive
eMIOS Ch.
GPIO
PCR[83]
PCR[84]
PCR[87]
PCR[88]
PCR[89]
PCR[90]
01
10
00
01
10
00
01
00
01
00
01
10
00
01
10
00
O
O
I/O
I/O
O
I/O
I/O
O
O
I/O
O
I/O
I
I
I
I
eSCI
VDDEH6a
Slow
VDDEH6a
Slow
VDDEH6a
Medium
VDDEH6a
Slow
VDDEH6a
Slow
VDDEH6a
Slow
– / Up – / Up
(24)
46 66 81 P12
– / Up – / Up 47 67 82 R12
– / Up – / Up 60 84 101 K13
– / Up – / Up 59 81 98 L14
– / Up – / Up 83 100 J14
– / Up – / Up 82 99 K14
54/142 Doc ID 14642 Rev 9
Table 4. SPC563Mx signal properties (continued)
Name Function
(1)
Pad
Config.
Register
(2)
(PCR)
PCR PA
(3)
Field
I/O
Typ e
Vol tag e
Pad Type
Pinout and signal description SPC563M64L5, SPC563M64L7
LQFP
144
Pin No.
LQFP
176
LBGA208
(4)
/
Reset
(5)
State
Function /
State After
(6)
Reset
LQFP
100
SCI_B_TX
GPIO[91]
SCI_B_RX
GPIO[92]
DSPI_B_SCK
DSPI_C_PCS[1]
GPIO[102]
DSPI_B_SIN
DSPI_C_PCS[2]
GPIO[103]
DSPI_B_SOUT
DSPI_C_PCS[5]
GPIO[104]
DSPI_B_PCS[0]
GPIO[105]
DSPI_B_PCS[1]
GPIO[106]
DSPI_B_PCS[2]
DSPI_C_SOUT
GPIO[107]
DSPI_B_PCS[3]
DSPI_C_SIN
GPIO[108]
DSPI_B_PCS[4]
DSPI_C_SCK
GPIO[109]
eSCI_B Transmit
GPIO
eSCI_B Receive
GPIO
DSPI_B Clock
DSPI_C Periph Chip Select
GPIO
DSPI_B Data Input
DSPI_C Periph Chip Select
GPIO
DSPI_B Data Output
DSPI_C Periph Chip Select
GPIO
DSPI_B Periph Chip Select
GPIO
DSPI_B Periph Chip Select
GPIO
DSPI_B Periph Chip Select
DSPI_C Data Output
GPIO
DSPI_B Periph Chip Select
DSPI_C Data Input
GPIO
DSPI_B Periph Chip Select
DSPI_C Clock
GPIO
PCR[91]
PCR[92]
PCR[102]
PCR[103]
PCR[104]
PCR[105]
PCR[106]
PCR[107]
PCR[108]
PCR[109]
01
00
01
00
01
10
00
01
10
00
01
10
00
01
00
01
00
01
10
00
01
10
00
01
10
00
I/O
I/O
I/O
I/O
O
I/O
O
I/O
O
O
I/O
O
I/O
O
I/O
O
O
I/O
O
I/O
O
I/O
I/O
I
I
I
DSPI
VDDEH6a
Slow
VDDEH6a
Slow
VDDEH6b
Medium
VDDEH6b
Medium
VDDEH6b
Medium
VDDEH6b
Medium
VDDEH6b
Medium
VDDEH6b
Medium
VDDEH6b
Medium
VDDEH6b
Medium
– / Up – / Up 72 87 L13
– / Up – / Up 69 84 M13
– / Up – / Up 64 89 106 J16
– / Up – / Up 67 95 112 G15
– / Up – / Up 96 113 G13
– / Up – / Up 94 111 G16
– / Up – / Up 92 109 H16
– / Up – / Up 90 107 H15
– / Up – / Up 68 97 114 G14
– / Up – / Up 63 88 105 H14
Table 4. SPC563Mx signal properties (continued)
Pad
Name Function
(1)
Config.
Register
(2)
(PCR)
PCR PA
(3)
Field
I/O
Typ e
Vol tag e
Pad Type
SPC563M64L5, SPC563M64L7 Pinout and signal description
LQFP
144
Pin No.
LQFP
176
LBGA208
(4)
/
Reset
(5)
State
Function /
State After
(6)
Reset
LQFP
100
Doc ID 14642 Rev 9 55/142
DSPI_B_PCS[5]
DSPI_C_PCS[0]
GPIO[110]
(26)
AN[0]
DAN0+
(26)
AN[1]
DAN0-
(26)
AN[2]
DAN1+
(26)
AN[3]
DAN1-
(26)
AN[4]
DAN2+
(26)
AN[5]
DAN2-
(26)
AN[6]
DAN3+
(26)
AN[7]
DAN3-
DSPI_B Periph Chip Select
DSPI_C Periph Chip Select
GPIO
Single Ended Analog Input
Positive Terminal Diff. Input
Single Ended Analog Input
Negative Terminal Diff. Input
Single Ended Analog Input
Positive Terminal Diff. Input
Single Ended Analog Input
Negative Terminal Diff. Input
Single Ended Analog Input
Positive Terminal Diff. Input
Single Ended Analog Input
Negative Terminal Diff. Input
Single Ended Analog Input
Positive Terminal Diff. Input
Single Ended Analog Input
Negative Terminal Diff. Input
AN[8] See AN[38]-AN[8]-ANW
AN[9]
ANX
Single Ended Analog Input
External Multiplexed Analog Input
AN[10] See AN[39]-AN[10]-ANY
AN[11]
ANZ
Single Ended Analog Input
External Multiplexed Analog Input
01
PCR[110]
10
00
——
——
——
——
——
——
——
——
——
——
O
O
I/O
eQADC
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
VDDEH6b
Medium
– / Up – / Up 87 104 J13
VDDA I / – AN[0] / – 99 143 172 B5
VDDA I / – AN[1] / – 98 142 171 A6
VDDA I / – AN[2] / – 97 141 170 D6
VDDA I / – AN[3] / – 96 140 169 C7
VDDA I / – AN[4] / – 95 139 168 B6
VDDA I / – AN[5] / – 94 138 167 A7
VDDA I / – AN[6] / – 93 137 166 D7
VDDA I / – AN[7] / – 92 136 165 C8
VDDA I / – AN[9] / – 2 5 5 A2
VDDA I / – AN[11] / – 1 4 4 A3
56/142 Doc ID 14642 Rev 9
Table 4. SPC563Mx signal properties (continued)
Name Function
(1)
Pad
Config.
Register
(2)
(PCR)
PCR PA
(3)
Field
I/O
Typ e
Vol tag e
Pad Type
Pinout and signal description SPC563M64L5, SPC563M64L7
LQFP
144
Pin No.
LQFP
176
LBGA208
(4)
/
Reset
(5)
State
Function /
State After
(6)
Reset
LQFP
100
AN[12]
MA[0]
ETPU_A[19]
SDS
AN[13]
MA[1]
ETPU_A[21]
SDO
AN[14]
MA[2]
ETPU_A[27]
SDI
AN[15]
FCK
ETPU_A[29]
Single Ended Analog Input
Mux Address
ETPU_A Ch.
eQADC Serial Data Strobe
Single Ended Analog Input
Mux Address
ETPU_A Ch.
eQADC Serial Data Out
Single Ended Analog Input
Mux Address
ETPU_A Ch.
eQADC Serial Data In
Single Ended Analog Input
eQADC Free Running Clock
ETPU_A Ch.
PCR[215]
PCR[216]
PCR[217]
PCR[218]
011
010
100
000
011
010
100
000
011
010
100
000
011
010
000
I
O
VDDEH7 I / – AN[12] / – 81 119 148 A12
O
O
I
O
VDDEH7 I / – AN[13] / – 80 118 147 B12
O
O
I
O
VDDEH7 I / – AN[14] / – 79 117 146 C12
O
I
I
O
VDDEH7 I / – AN[15] / – 78 116 145 C13
O
AN[16] Single Ended Analog Input I VDDA I / – AN[x] / – 3 3 C6
AN[17] Single Ended Analog Input I VDDA I / – AN[x] / – 2 2 C4
AN[18] Single Ended Analog Input I VDDA I / – AN[x] / – 1 1 D5
AN[21] Single Ended Analog Input I VDDA I / – AN[x] / – 100 144 173 B4
AN[22] Single Ended Analog Input I VDDA I / – AN[x] / – 132 161 B8
AN[23] Single Ended Analog Input I VDDA I / – AN[x] / – 88 131 160 C9
AN[24] Single Ended Analog Input I VDDA I / – AN[x] / – 130 159 D8
AN[25] Single Ended Analog Input I VDDA I / – AN[x] / – 87 129 158 B9
AN[27] Single Ended Analog Input I VDDA I / – AN[x] / – 128 157 A10
AN[28] Single Ended Analog Input I VDDA I / – AN[x] / – 86 127 156 B10
AN[30] Single Ended Analog Input I VDDA I / – AN[x] / – 126 155 D9
AN[31] Single Ended Analog Input I VDDA I / – AN[x] / – 85 125 154 D10
Table 4. SPC563Mx signal properties (continued)
(1)
Doc ID 14642 Rev 9 57/142
Name Function
AN[32] Single Ended Analog Input I VDDA I / – AN[x] / – 124 153 C10
AN[33] Single Ended Analog Input I VDDA I / – AN[x] / – 84 123 152 C11
AN[34] Single Ended Analog Input I VDDA I / – AN[x] / – 122 151 C5
AN[35] Single Ended Analog Input I VDDA I / – AN[x] / – 83 121 150 D11
AN[36] Single Ended Analog Input I VDDA I / – AN[x] / – 174
AN[37] Single Ended Analog Input I VDDA I / – AN[x] / – 175
AN[38]-AN[8]-
ANW
AN[39]-AN[10]-
ANY
Single Ended Analog Input
Multiplexed Analog Input
Single Ended Analog Input
Multiplexed Analog Input
VRH Voltage Reference High I VDDA – / – VRH 90 134 163 A8
VRL Voltage Reference Low I VSSA0 – / – VRL 89 133 162 A9
REFBYPC Bypass Capacitor Input I VRL – / – REFBYPC 91 135 164 B7
LQFP
144
Pin No.
LQFP
176
(7)
(7)
Pad
Config.
Register
(2)
(PCR)
PCR PA
(3)
Field
I/O
Typ e
Vol tag e
Pad Type
(4)
/
Reset
(5)
State
Function /
State After
(6)
Reset
LQFP
100
I VDDA I / – AN[38] / – 6 9 9 B3
I VDDA I / – AN[39] / – 5 8 8 D2
eTPU2
LBGA208
(8)
F4
(8)
E3
SPC563M64L5, SPC563M64L7 Pinout and signal description
eTPU_A[0]
eTPU_A[12]
eTPU_A[19]
GPIO[114]
eTPU_A[1]
eTPU_A[13]
GPIO[115]
eTPU_A[2]
eTPU_A[14]
GPIO[116]
eTPU_A[3]
eTPU_A[15]
GPIO[117]
eTPU_A Ch.
eTPU_A Ch.
eTPU_A Ch.
GPIO
eTPU_A Ch.
eTPU_A Ch.
GPIO
eTPU_A Ch.
eTPU_A Ch.
GPIO
eTPU_A Ch.
eTPU_A Ch.
GPIO
PCR[114]
PCR[115]
PCR[116]
PCR[117]
011
010
100
000
01
10
00
01
10
00
01
10
00
I/O
O
O
I/O
I/O
O
I/O
I/O
O
I/O
I/O
O
I/O
VDDEH1b
Slow
VDDEH1b
Slow
VDDEH1b
Slow
VDDEH1b
Slow
– / WKPCFG – / WKPCFG 37 52 61 L4, N3
– / WKPCFG – / WKPCFG 36 51 60 M3
– / WKPCFG – / WKPCFG 35 50 59 P2
– / WKPCFG – / WKPCFG 34 49 58 P1
58/142 Doc ID 14642 Rev 9
Table 4. SPC563Mx signal properties (continued)
Name Function
(1)
Pad
Config.
Register
(2)
(PCR)
PCR PA
(3)
Field
I/O
Typ e
Vol tag e
Pad Type
Pinout and signal description SPC563M64L5, SPC563M64L7
LQFP
144
Pin No.
LQFP
176
LBGA208
(4)
/
Reset
(5)
State
Function /
State After
(6)
Reset
LQFP
100
eTPU_A[4]
eTPU_A[16]
GPIO[118]
eTPU_A[5]
eTPU_A[17]
DSPI_B_SCK_LVDS-
GPIO[119]
eTPU_A[6]
eTPU_A[18]
DSPI_B_SCK_LVDS+
GPIO[120]
eTPU_A[7]
eTPU_A[19]
DSPI_B_SOUT_LVDS-
eTPU_A[6]
GPIO[121]
eTPU_A[8]
eTPU_A[20]
DSPI_B_SOUT_LVDS+
GPIO[122]
eTPU_A[9]
eTPU_A[21]
GPIO[123]
eTPU_A[10]
eTPU_A[22]
GPIO[124]
eTPU_A[11]
eTPU_A[23]
GPIO[125]
eTPU_A Ch.
eTPU_A Ch.
GPIO
eTPU_A Ch.
eTPU_A Ch.
DSPI_B CLOCK LVDS-
GPIO
eTPU_A Ch.
eTPU_A Ch.
DSPI_B Clock LVDS+
GPIO
eTPU_A Ch.
eTPU_A Ch.
DSPI_B Data Output LVDS-
eTPU_A Ch.
GPIO
eTPU_A Ch.
eTPU_A Ch.
DSPI_B Data Output LVDS+
GPIO
eTPU_A Ch.
eTPU_A Ch.
GPIO
eTPU_A Ch.
eTPU_A Ch.
GPIO
eTPU_A Ch.
eTPU_A Ch.
GPIO
PCR[118]
PCR[119]
PCR[120]
PCR[121]
PCR[122]
PCR[123]
PCR[124]
PCR[125]
01
10
00
001
010
100
000
001
010
100
000
0001
0010
0100
1000
0000
001
010
100
000
01
10
00
01
10
00
01
10
00
I/O
O
I/O
I/O
O
O
I/O
I/O
O
O
I/O
I/O
O
O
O
I/O
I/O
O
O
I/O
I/O
O
I/O
I/O
O
I/O
I/O
O
I/O
VDDEH1b
Slow
VDDEH1b
Slow
VDDEH1b
Medium
VDDEH1b
Slow
VDDEH1b
Slow
VDDEH1b
Slow
VDDEH1b
Slow
VDDEH1b
Slow
– / WKPCFG – / WKPCFG 32 47 56 N2
– / WKPCFG – / WKPCFG 30 45 54 M4
– / WKPCFG – / WKPCFG 29 44 53 L3
– / WKPCFG – / WKPCFG 28 43 52 K3
– / WKPCFG – / WKPCFG 27 42 51 N1
– / WKPCFG – / WKPCFG 41 50 M2
– / WKPCFG – / WKPCFG 40 49 M1
– / WKPCFG – / WKPCFG 39 48 L2
Table 4. SPC563Mx signal properties (continued)
Pad
Name Function
(1)
Config.
Register
(2)
(PCR)
PCR PA
(3)
Field
I/O
Typ e
Vol tag e
Pad Type
SPC563M64L5, SPC563M64L7 Pinout and signal description
LQFP
144
Pin No.
LQFP
176
LBGA208
(4)
/
Reset
(5)
State
Function /
State After
(6)
Reset
LQFP
100
Doc ID 14642 Rev 9 59/142
eTPU_A[12]
DSPI_B_PCS[1]
GPIO[126]
eTPU_A[13]
DSPI_B_PCS[3]
GPIO[127]
eTPU_A[14]
DSPI_B_PCS[4]
eTPU_A[9]
GPIO[128]
eTPU_A[15]
DSPI_B_PCS[5]
GPIO[129]
eTPU_A[16]
GPIO[130]
eTPU_A[17]
GPIO[131]
eTPU_A[18]
GPIO[132]
eTPU_A[19]
GPIO[133]
eTPU_A[20]
IRQ[8]
GPIO[134]
eTPU_A[21]
[9]
IRQ
GPIO[135]
eTPU_A Ch.
DSPI_B Periph Chip Select
GPIO
eTPU_A Ch.
DSPI_B Periph Chip Select
GPIO
eTPU_A Ch.
DSPI_B Periph Chip Select
eTPU_A Ch.
GPIO
eTPU_A Ch.
DSPI_B Periph Chip Select
GPIO
eTPU_A Ch.
GPIO
eTPU_A Ch.
GPIO
eTPU_A Ch.
GPIO
eTPU_A Ch.
GPIO
eTPU_A Ch.
External Interrupt Request
GPIO
eTPU_A Ch.
External Interrupt Request
GPIO
PCR[126]
PCR[127]
PCR[128]
PCR[129]
PCR[130]
PCR[131]
PCR[132]
PCR[133]
PCR[134]
PCR[135]
01
10
00
01
10
00
001
010
100
000
01
10
00
01
00
01
00
01
00
01
00
01
10
00
01
10
00
I/O
O
I/O
I/O
O
I/O
I/O
O
O
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
VDDEH1b
Medium
VDDEH1b
Medium
VDDEH1b
Medium
VDDEH1b
Medium
VDDEH1b
Slow
VDDEH1b
Slow
VDDEH1b
Slow
VDDEH1b
Slow
VDDEH1b
Slow
VDDEH1a
Slow
– / WKPCFG – / WKPCFG 38 47 L1
– / WKPCFG – / WKPCFG 26 37 46 J4
– / WKPCFG – / WKPCFG 24 35 42 J3
– / WKPCFG – / WKPCFG 22 33 40 K2
– / WKPCFG – / WKPCFG 32 39 K1
– / WKPCFG – / WKPCFG 31 38 H3
– / WKPCFG – / WKPCFG 30 37 H4
– / WKPCFG – / WKPCFG 29 36 J2
– / WKPCFG – / WKPCFG 28 35 J1
– / WKPCFG – / WKPCFG 27 34 G4
60/142 Doc ID 14642 Rev 9
Table 4. SPC563Mx signal properties (continued)
Name Function
(1)
Pad
Config.
Register
(2)
(PCR)
PCR PA
(3)
Field
I/O
Typ e
Vol tag e
Pad Type
Pinout and signal description SPC563M64L5, SPC563M64L7
LQFP
144
Pin No.
LQFP
176
LBGA208
(4)
/
Reset
(5)
State
Function /
State After
(6)
Reset
LQFP
100
eTPU_A[22]
[10]
IRQ
eTPU_A[17]
GPIO[136]
eTPU_A[23]
[11]
IRQ
eTPU_A[21]
GPIO[137]
eTPU_A[24]
(27)
IRQ[12]
DSPI_C_SCK_LVDS-
GPIO[138]
eTPU_A[25]
(27)
IRQ[13]
DSPI_C_SCK_LVDS+
GPIO[139]
eTPU_A[26]
(27)
IRQ[14]
DSPI_C_SOUT_LVDS-
GPIO[140]
eTPU_A[27]
(27)
IRQ[15]
DSPI_C_SOUT_LVDS+
DSPI_B_SOUT
GPIO[141]
eTPU_A[28]
(27)
DSPI_C_PCS[1]
GPIO[142]
eTPU_A Ch.
External Interrupt Request
eTPU_A Ch. External
GPIO
eTPU_A Ch.
External Interrupt Request
eTPU_A Ch. External
GPIO
eTPU_A Ch.
External Interrupt Request
DSPI_C Clock LVDS-
GPIO
eTPU_A Ch.
External Interrupt Request
DSPI _C Clock LVDS+
GPIO
eTPU_A Ch.
External Interrupt Request
DSPI_C Data Output LVDS-
GPIO
eTPU_A Ch.
External Interrupt Request
DSPI_C Data Output LVDS+
DSPI_B Data Output
GPIO
eTPU_A Ch. (Input and Output)
DSPI_C Periph Chip Select
GPIO
PCR[136]
PCR[137]
PCR[138]
PCR[139]
PCR[140]
PCR[141]
PCR[142]
001
010
100
000
001
010
100
000
001
010
100
000
001
010
100
000
001
010
100
000
0001
0010
0100
1000
0000
10
01
00
I/O
O
I/O
I/O
O
I/O
I/O
O
I/O
I/O
O
I/O
I/O
O
I/O
I/O
O
O
I/O
I/O
O
I/O
I
I
I
I
I
I
VDDEH1a
Slow
VDDEH1a
Slow
VDDEH1a
Slow
VDDEH1a
Medium
VDDEH1a
Slow
VDDEH1a
Slow
VDDEH1a
Medium
– / WKPCFG – / WKPCFG 25 32 H2
– / WKPCFG – / WKPCFG 23 30 H1
– / WKPCFG – / WKPCFG 18 21 28 G1
– / WKPCFG – / WKPCFG 17 20 27 G3
– / WKPCFG – / WKPCFG 16 19 26 F3
– / WKPCFG – / WKPCFG 15 18 25 G2
– / WKPCFG – / WKPCFG 14 17 24 F1
Table 4. SPC563Mx signal properties (continued)
Pad
Name Function
(1)
Config.
Register
(2)
(PCR)
PCR PA
(3)
Field
I/O
Typ e
Vol tag e
Pad Type
SPC563M64L5, SPC563M64L7 Pinout and signal description
LQFP
144
Pin No.
LQFP
176
LBGA208
(4)
/
Reset
(5)
State
Function /
State After
(6)
Reset
LQFP
100
Doc ID 14642 Rev 9 61/142
eTPU_A[29]
(27)
DSPI_C_PCS[2]
GPIO[143]
eTPU_A[30]
DSPI_C_PCS[3]
eTPU_A[11]
GPIO[144]
eTPU_A[31]
DSPI_C_PCS[4]
eTPU_A[13]
GPIO[145]
eMIOS[0]
eTPU_A[0]
eTPU_A[25]
(28)
GPIO[179]
eMIOS[1]
eTPU_A[1]
GPIO[180]
eMIOS[2]
eTPU_A[2]
GPIO[181]
eMIOS[4]
eTPU_A[4]
GPIO[183]
eTPU_A Ch. (Input and Output)
DSPI_C Periph Chip Select
GPIO
eTPU_A Ch.
DSPI_C Periph Chip Select
eTPU_A Ch.
GPIO
eTPU_A Ch.
DSPI_C Periph Chip Select
eTPU_A Ch.
GPIO
eMIOS Ch.
eTPU_A Ch.
eTPU_A Ch.
GPIO
eMIOS Ch.
eTPU_A Ch.
GPIO
eMIOS Ch.
eTPU_A Ch.
GPIO
eMIOS Ch.
eTPU_A Ch.
GPIO
PCR[143]
PCR[144]
PCR[145]
PCR[179]
PCR[180]
PCR[181]
PCR[183]
10
01
00
011
010
001
000
011
010
001
000
001
010
100
000
01
10
00
01
10
00
01
10
00
I/O
O
I/O
I/O
O
O
I/O
I/O
O
O
I/O
eMIOS
I/O
O
O
I/O
I/O
O
I/O
I/O
O
I/O
I/O
O
I/O
VDDEH1a
Medium
VDDEH1a
Medium
VDDEH1a
Medium
VDDEH1b
Slow
VDDEH1b
Slow
VDDEH1b
Slow
VDDEH6a
Slow
– / WKPCFG – / WKPCFG 13 16 23 F2
– / WKPCFG – / WKPCFG 12 15 22 E1
– / WKPCFG – / WKPCFG 11 14 21 E2
– / WKPCFG – / WKPCFG 39 54 63 T4
– / WKPCFG – / WKPCFG 64
(7)
T5
– / WKPCFG – / WKPCFG 55 65 N7
– / WKPCFG – / WKPCFG 56 67 R5
(8)
62/142 Doc ID 14642 Rev 9
Table 4. SPC563Mx signal properties (continued)
Name Function
(1)
Pad
Config.
Register
(2)
(PCR)
PCR PA
(3)
Field
I/O
Typ e
Vol tag e
Pad Type
Pinout and signal description SPC563M64L5, SPC563M64L7
LQFP
144
Pin No.
LQFP
176
LBGA208
(4)
/
Reset
(5)
State
Function /
State After
(6)
Reset
LQFP
100
eMIOS[8]
eTPU_A[8]
(29)
SCI_B_TX
GPIO[187]
eMIOS[9]
eTPU_A[9]
(29)
SCI_B_RX
GPIO[188]
eMIOS[10]
GPIO[189]
eMIOS[11]
GPIO[190]
eMIOS[12]
DSPI_C_SOUT
eTPU_A[27]
GPIO[191]
eMIOS[13]
GPIO[192]
eMIOS[14]
[0]
IRQ
eTPU_A[29]
GPIO[193]
eMIOS[15]
[1]
IRQ
GPIO[194]
eMIOS[23]
GPIO[202]
eMIOS Ch.
eTPU_A Ch.
eSCI_B Transmit
GPIO
eMIOS Ch.
eTPU_A Ch.
eSCI_B Receive
GPIO
eMIOS Ch.
GPIO
eMIOS Ch.
GPIO
eMIOS Ch.
DSPI C Data Output
eTPU_A Ch.
GPIO
eMIOS Ch.
GPIO
eMIOS Ch.
External Interrupt Request
eTPU_A Ch.
GPIO
eMIOS Ch.
External Interrupt Request
GPIO
eMIOS Ch.
GPIO
PCR[187]
PCR[188]
PCR[189]
PCR[190]
PCR[191]
PCR[192]
PCR[193]
PCR[194]
PCR[202]
001
010
100
000
001
010
100
000
01
00
01
00
001
010
100
000
01
00
001
010
100
000
01
10
00
01
00
I/O
O
O
VDDEH6a
Slow
– / WKPCFG – / WKPCFG 40 57 70 P8
I/O
I/O
O
I
VDDEH6a
Slow
– / WKPCFG – / WKPCFG 41 58 71 R7
I/O
I/O
I/O
I/O
I/O
VDDEH6a
Slow
VDDEH6a
Slow
– / WKPCFG – / WKPCFG 60 73 N8
– / WKPCFG – / WKPCFG 62 75 R8
I/O
O
O
VDDEH6a
Medium
– / WKPCFG – / WKPCFG 44 63 76 N10
I/O
I/O
VDDEH6a – / WKPCFG – / WKPCFG 77
I/O
O
I
O
VDDEH6a
Slow
– / WKPCFG – / WKPCFG 45 64 78 R9
I/O
O
VDDEH6a
I/O
I/O
I/O
I
Slow
VDDEH6a
Slow
– / WKPCFG – / WKPCFG 79
– / WKPCFG – / WKPCFG 65 80 R11
(7)
(7)
T8
T9
(8)
(8)
Clock Synthesizer
XTAL Crystal Oscillator Output O VDDEH6a O / – XTAL
(30)
/ – 54 76 93 P16
Table 4. SPC563Mx signal properties (continued)
Pad
Name Function
(1)
Config.
Register
(2)
(PCR)
PCR PA
(3)
Field
I/O
Typ e
Vol tag e
Pad Type
SPC563M64L5, SPC563M64L7 Pinout and signal description
LQFP
144
Pin No.
LQFP
176
LBGA208
(4)
/
Reset
(5)
State
Function /
State After
(6)
Reset
LQFP
100
Doc ID 14642 Rev 9 63/142
EXTAL
EXTCLK
Crystal Oscillator Input
External Clock Input
I VDDEH6a I / – EXTAL
CLKOUT System Clock Output PCR[229] O
Power / Ground
VDDPLL PLL Supply Voltage I
(33)
(34)
(32)
PLL Ground I VSSPLL I / – 55 77 94 M16
Power Supply for Standby RAM
3.3V Voltage Regulator Bypass Capacitor
Voltage Regulator Control Output
Analog Power Input for eQADC
Analog Power Input for eQADC
Analog Ground Input for eQADC
Analog Power Input for eQADC
Analog Ground Input for eQADC
Analog Ground Input for eQADC
I VSTBY I / – 9 12 12 C1
O VRC33 O / – 10 13 13
O NA O / – 8 11 11 N14
I VDDA (5.0 V) I / – 3 6 6
I VDDA I / – B11
I VSSA I / – A11
I VDDA I / – A4
I VSSA I / – A5
I VSSA I / – 4 7 7
VSSPLL
VSTBY
VRC33
VRCCTL
VDDA
VDDA0
VSSA0
VDDA1
VSSA1
VSSA
VDDREG Voltage Regulator Supply I
VDDE5
Fast
VDDPLL
(1.2V)
VDDREG
(5.0 V)
(31)
/ – 53 75 92 N16
CLKOUT /
Enabled
CLKOUT /
Enabled
——— T14
I / – 52 74 91 R16
I / – 7 10 10 K16
A15, D1,
N6, N12
64/142 Doc ID 14642 Rev 9
Table 4. SPC563Mx signal properties (continued)
Name Function
Pad
(1)
Config.
Register
(PCR)
(2)
PCR PA
(3)
Field
I/O
Typ e
Vol tag e
Pad Type
(4)
/
Reset
(5)
State
VDD Internal Logic Supply Input I VDD (1.2 V) I / –
VSS Ground VSS0 I / –
VDDEH1A
VDDEH1B
(35)
(35)
I/O Supply Input I
VDDEH1
(3.3V – 5.0V)
(36)
I / –
Function /
State After
(6)
Reset
LQFP
100
21, 38,
62, 82
19, 25, 33, 42, 51, 57, 65, 72,
77
20, 23
31
LQFP
144
26, 53,
86, 120
22, 36, 48, 59, 73, 79,
91,
104,
115
24, 34,
46
VDDE5 I/O Supply Input I VDDE5 I / – T13
VDDEH6a
VDDEH6b
(37), (38)
(38)
I/O Supply Input I
VDDEH6
(3.3V – 5.0V)
I / –
56, 66, 4378, 93,
61
VDDEH6 I/O Supply Input I VDDEH6 I / – F13
VDDE7
(3.3V)
(39)
I / – 71, 76
I / –
102,
113
VDDEH7 I/O Supply Input I
(40)
VDDE7
I/O Supply Input I
VDDEH7
(3.3V – 5.0V)
1. For each pin in the table, each line in the Function column is a separate function of the pin. For all I/O pins the selection of primary pin function or secondary function or GPIO is done in the SIU except where explicitly noted.
Pin No.
LQFP
176
33, 62,
103,
149
15, 29, 43, 57, 72, 90,
96,
108,
115
127, 133,
140
31, 41
55
95,
110,
74
125,
138
16,
119
C2, D3, E4,
H7, H8, H9, H10, J7, J8,
7
J9, J10, K7,
,
(7)
Pinout and signal description SPC563M64L5, SPC563M64L7
LBGA208
B1, B16,
N5, P4, P13, R3, R14, T2,
T15
A1, A16, B2, B15, C3, C14, D4, D13,
G7, G8,
G9, G10,
K8, K9, K10, N4, N13, P3, P14, R2, R15, T1,
T16
K4
D12
E13, P6
2. Values in this column refer to registers in the System Integration Unit (SIU). The actual register name is “SIU_PCR” suffixed by the PCR number. For example, PCR[190] refers to the SIU register named SIU_PCR190.
3. The Pad Configuration Register (PCR) PA field is used by software to select pin function.
4. The VDDE and VDDEH supply inputs are broken into segments. Each segment of slow I/O pins (VDDEH) may have a separate supply in the 3.3 V to 5.0 V range (– 10%/+5%). Each segment of fast I/O (VDDE) may have a separate supply in the 1.8 V to 3.3 V range (+/– 10%).
5. Terminology is O — output, I — input, Up — weak pull up enabled, Down — weak pull down enabled, Low — output driven low, High — output driven high. A dash for the function in this column denotes that both the input and output buffer are turned off.
6. Function after reset of GPI is general purpose input. A dash for the function in this column denotes that both the input and output buffer are turned off.
7. Not available on 1 MB version of 176-pin package.
8. The GPIO functions on GPIO[206] and GPIO[207] can be selected as trigger functions in the SIU for the ADC by making the proper selections in the SIU_ETISR and SIU_ISEL3 registers in the SIU.
9. Some signals in this section are available only on calibration package.
10. These pins are only available in the 496 CSP/MAPBGA calibration/development package.
11. On the calibration package, the Nexus function on this pin is enabled when the NEXUSCFG pin is high and Nexus is configured to full port mode. On the 176-pin and 208­pin packages, the Nexus function on this pin is enabled permanently. Do not connect the Nexus MDO or MSEO pins directly to a power supply or ground.
12. In the calibration package, the I/O segment containing this pin is called VDDE12.
Doc ID 14642 Rev 9 65/142
13. 208-ball BGA package only
14. When configured as Nexus (208-pin package or calibration package with NEXUSCFG=1), and JCOMP is asserted during reset, MDO[0] is driven high until the crystal oscillator becomes stable, at which time it is then negated.
15. The function of this pin is Nexus when NEXUSCFG is high.
16. High when the pin is configured to Nexus, low otherwise.
17. O/Low for the calibration with NEXUSCFG=0; I/Up otherwise.
18. ALT_ADDR/Low for the calibration package with NEXUSCFG=0; EVTI
19. In 176-pin and 208-pin packages, the Nexus function is disabled and the pin/ball has the secondary function
20. This signal is not available in the 176-pin and 208-pin packages.
21. The primary function is not selected via the PA field when the pin is a Nexus signal. Instead, it is activated by the Nexus controller.
22. TDI and TDO are required for JTAG operation.
23. The primary function is not selected via the PA field when the pin is a JTAG signal. Instead, it is activated by the JTAG controller.
24. The function and state of the CAN_A and eSCI_A pins after execution of the BAM program is determined by the BOOTCFG1 pin.
25. Connect an external 10K pull-up resistor to the SCI_A_RX pin to ensure that the pin is driven high during CAN serial boot.
26. For pins AN[0:7], during and just after POR negates, internal pull resistors can be enabled, resulting in as much as 4 mA of current draw. The pull resistors are disabled when the system clock propagates through the device.
27. ETPUA[24:29] are input and output. The input muxing is controlled by SIU_ISEL8 register.
28. eTPU_A[25] is an output only function.
29. Only the output channels of eTPU[8:9] are connected to pins.
30. The function after reset of the XTAL pin is determined by the value of the signal on the PLLCFG[1] pin. When bypass mode is chosen XTAL has no function and should be grounded.
/Up otherwise.
SPC563M64L5, SPC563M64L7 Pinout and signal description
66/142 Doc ID 14642 Rev 9
31. The function after reset of the EXTAL_EXTCLK pin is determined by the value of the signal on the PLLCFG[1] pin. If the EXTCLK function is chosen, the valid operating voltage for the pin is 1.62 V to 3.6 V. If the EXTAL function is chosen, the valid operating voltage is 3.3 V.
32. VSSPLL and VSSREG are connected to the same pin.
33. This pin is shared by two pads: VDDA_AN, using pad_vdde_hv, and VDDA_DIG, using pad_vdde_int_hv.
34. This pin is shared by two pads: VSSA_AN, using pad_vsse_hv, and VSSA_DIG, using pad_vsse_int_hv.
35. VDDEH1A, VDDEH1B, and VDDEH1AB are shorted together in all production packages. The separation of the signal names is present to support legacy naming, however they should be considered as the same signal in this document.
36. LVDS pins will not work at 3.3 V.
37. The VDDEH6 segment may be powered from 3.0 V to 5.0 V for mux address or SSI functions, but must meet the VDDA specifications of 4.5 V to 5.25 V for analog input function.
38. VDDEH6A and VDDEH6B are shorted together in all production packages. The separation of the signal names is present to support legacy naming, however they should be considered as the same signal in this document.
39. If using JTAG or Nexus, the I/O segment that contains the JTAG and Nexus pins must be powered by a 5 V supply. The 3.3 V Nexus/JTAG signals are derived from the 5 volt power supply.
40. In the calibration package this signal is named VDDE12.
Pinout and signal description SPC563M64L5, SPC563M64L7
SPC563M64L5, SPC563M64L7 Pinout and signal description
Table 5. Pad types
Pad Type Name Supply Voltage
Slow pad_ssr_hv 3.0 V – 5.25 V
Medium pad_msr_hv 3.0 V – 5.25 V
Fast pad_fc 3.0 V – 3.6 V
MultiV pad_multv_hv
3.0 V – 5.25 V (high swing mode)
4.5 V – 5.25 V (low swing mode)
Analog pad_ae_hv 0.0 – 5.25 V
LVDS pad_lo_lv —

3.7 Signal details

Ta bl e 6 contains details on the multiplexed signals that appear in Tab l e 4 .
Table 6. Signal details
Signal Module or Function Description
CLKOUT Clock Generation
EXTAL Clock Generation
SPC563Mxx clock output for the external/calibration bus interface
Input pin for an external crystal oscillator or an external clock source based on the value driven on the PLLREF pin at reset.
EXTCLK Clock Generation External clock input
PLLREF is used to select whether the oscillator operates in xtal
PLLREF Clock Generation
mode or external reference mode from reset. PLLREF=0 selects external reference mode.
XTAL Clock Generation Crystal oscillator input
SCK_B_LVDS– SCK_B_LVDS+
SOUT_B_LVDS– SOUT_B_LVDS+
SCK_C_LVDS– SCK_C_LVDS+
SOUT_C_LVDS– SOUT_C_LVDS+
PCS_B[0] PCS_C[0]
PCS_B[1:5] PCS_C[1:5]
SCK_B SCK_C
SIN_B SIN_C
DSPI LVDS pair used for DSPI_B TSB mode transmission
DSPI LVDS pair used for DSPI_B TSB mode transmission
DSPI LVDS pair used for DSPI_C TSB mode transmission
DSPI LVDS pair used for DSPI_C TSB mode transmission
DSPI_B – DSPI_C
DSPI_B – DSPI_C
DSPI_B – DSPI_C
Peripheral chip select when device is in master mode—slave select when used in slave mode
Peripheral chip select when device is in master mode—not used in slave mode
DSPI clock—output when device is in master mode; input when in slave mode
DSPI_B – DSPI_C DSPI data in
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Pinout and signal description SPC563M64L5, SPC563M64L7
Table 6. Signal details (continued)
Signal Module or Function Description
SOUT_B SOUT_C
CAL_ADDR[12:30] Calibration Bus
CAL_CS
CAL_DATA[0:15] Calibration Bus
CAL_OE
CAL_RD_WR
CAL_TS_ALE Calibration Bus
CAL_EVTO Calibration Bus Nexus Event Out
CAL_MCKO Calibration Bus Nexus Message Clock Out
NEXUSCFG Nexus/Calibration Bus Nexus/Calibration Bus selector
eMIOS[0:23] eMIOS eMIOS I/O channels
[0:3] Calibration Bus
DSPI_B – DSPI_C DSPI data out
The CAL_ADDR[12:30] signals specify the physical address of the bus transaction.
CSx is asserted by the master to indicate that this transaction is targeted for a particular memory bank on the Primary external bus.
The CAL_DATA[0:15] signals contain the data to be transferred for the current transaction.
is used to indicate when an external memory is permitted to
OE
Calibration Bus
Calibration Bus
drive back read data. External memories must have their data output buffers off when OE is negated. OE is only asserted for chip-select accesses.
RD_WR access or a write access.
The Transfer Start signal (TS to indicate the start of a transfer.
The Address Latch Enable (ALE) signal is used to demultiplex the address from the data bus.
indicates whether the current transaction is a read
) is asserted by the SPC563Mxx
AN[0:39] eQADC Single-ended analog inputs for analog-to-digital converter
FCK eQADC eQADC free running clock for eQADC SSI.
MA[0:2] eQADC
REFBYPC eQADC Bypass capacitor input
SDI eQADC Serial data in
SDO eQADC Serial data out
SDS eQADC Serial data select
VRH eQADC Voltage reference high input
VRL eQADC Voltage reference low input
SCI_A_RX SCI_B_RX
SCI_A_TX SCI_B_TX
ETPU_A[0:31] eTPU eTPU I/O channel
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eSCI_A – eSCI_B eSCI receive
eSCI_A – eSCI_B eSCI transmit
These three control bits are output to enable the selection for an external Analog Mux for expansion channels.
SPC563M64L5, SPC563M64L7 Pinout and signal description
Table 6. Signal details (continued)
Signal Module or Function Description
CAN_A_TX CAN_C_TX
CAN_A_RX CAN_C_RX
JCOMP JTAG Enables the JTAG TAP controller.
TCK JTAG Clock input for the on-chip test and debug logic.
TDI JTAG
TDO JTAG Serial test data output for the on-chip test logic.
TMS JTAG
EVTI
EVTO
MCKO Nexus
MDO[3:0] Nexus
[1:0] Nexus
MSEO
FlexCan_A – FlexCAN_C
FlexCAN_A – FlexCAN_C
Nexus
Nexus
FlexCAN transmit
FlexCAN receive
Serial test instruction and data input for the on-chip test and debug logic.
Controls test mode operations for the on-chip test and debug logic.
is an input that is read on the negation of RESET to
EVTI enable or disable the Nexus Debug port. After reset, the EVTI pin is used to initiate program synchronization messages or generate a breakpoint.
Output that provides timing to a development tool for a single watchpoint or breakpoint occurrence.
MCKO is a free running clock output to the development tools which is used for timing of the MDO and MSEO
Trace message output to development tools. This pin also indicates the status of the crystal oscillator clock following a power-on reset, when MDO[0] is driven high until the crystal oscillator clock achieves stability and is then negated.
Output pin—Indicates the start or end of the variable length message on the MDO pins
signals.
BOOTCFG[1] SIU – Configuration
The BOOTCFG1 pin is sampled during the assertion of the RSTOUT signal, and the value is used to update the RSR and the BAM boot mode
The following values are for BOOTCFG[0:1}: 0 Boot from internal flash memory
1 FlexCAN/eSCI boot
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Pinout and signal description SPC563M64L5, SPC563M64L7
Table 6. Signal details (continued)
Signal Module or Function Description
The WKPCFG pin is applied at the assertion of the internal reset signal (assertion of RSTOUT cycles before the negation of the RSTOUT pin.
The value is used to configure whether the eTPU and eMIOS pins are connected to internal weak pull up or weak pull down
WKPCFG SIU – Configuration
devices after reset. The value latched on the WKPCFG pin at reset is stored in the Reset Status Register (RSR), and is updated for all reset sources except the Debug Port Reset and Software External Reset.
0:Weak pulldown applied to eTPU and eMIOS pins at reset 1:Weak pullup applied to eTPU and eMIOS pins at reset.
ETRIG[2:3] SIU – eQADC Triggers External signal eTRIGx triggers eQADC CFIFOx
), and is sampled 4 clock
IRQ[0:15]
NMI
SIU – External Interrupts
SIU – External Interrupts
GPIO[n] SIU – GPIO
RESET
RSTOUT
SIU – Reset
SIU – Reset
The IRQ[0:15] pins connect to the SIU IRQ inputs. IMUX Select Register 1 is used to select the IRQ[0:15] pins as inputs to the IRQs.
Non-Maskable Interrupt
Configurable general purpose I/O pins. Each GPIO input and output is separately controlled by an 8-bit input (GPDI) or output (GPDO) register. Additionally, each GPIO pins is configured using a dedicated SIU_PCR register.
The GPIO pins are generally multiplexed with other I/O pin functions.
The RESET
pin is an active low input. The RESET pin is asserted by an external device during a power-on or external reset. The internal reset signal asserts only if the RESET pin asserts for 10 clock cycles. Assertion of the RESET
pin while
the device is in reset causes the reset cycle to start over.
The RESET
pin has a glitch detector which detects spikes greater than two clock cycles in duration that fall below the switch point of the input buffer logic of the VDDEH input pins. The switch point lies between the maximum VIL and minimum VIH specifications for the VDDEH input pins.
The RSTOUT
pin is an active low output that uses a push/pull configuration. The RSTOUT pin is driven to the low state by the MCU for all internal and external reset sources. There is a delay between initiation of the reset and the assertion of the RSTOUT pin.
Ta bl e 7 gives the power/ground segmentation of the SPC563Mx MCU. Each segment
provides the power and ground for the given set of I/O pins, and can be powered by any of the allowed voltages regardless of the power on the other segments.
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SPC563M64L5, SPC563M64L7 Pinout and signal description
.
Table 7. SPC563Mx Power/Ground Segmentation
Power
Segment
100-LQFP
Pin
Number
144-LQFP
Pin
Number
176-LQFP
Pin
Number
208-BGA
Pin
Number
Voltage
Range
VDDA0 3 6 6 B11 5.0 V
VDDE5 T13
VDDEH1
(a,b)
VDDEH6
(a,b)
20, 23 24, 34 31, 41 K4
56, 66 78, 93 95, 110 F13
1.8 V –
3.3 V
3.3 V –
5.0 V
3.3 V –
5.0 V
I/O Pins Powered
(1)
by Segment
AN[0:7], AN[9], AN[11],
AN[16:18], AN[21:25], AN[27:28], AN[30:37],
AN38, AN39, VRL,
REFBYPC,
CLKOUT
PCKCFG[2],
eTPU_A[0:31],
eMIOS[0:2]
RESET
WKPCFG, BOOTCFG1,
PLLREF, SCK_B,
PCKCFG[0],
CAN_A_TX, CAN_A_RX, CAN_C_TX, CAN_C_RX,
SCI_A_TX, SCI_A_RX, SCI_B_TX, SCI_B_RX,
SCK_B, SIN_B, SOUT_B,
DSPI_B_PCS_B[0:5],
eMIOS[4],
eMIOS[8:15], eMIOS[23],
XTAL, EXTAL
VRH
, RSTOUT,
PCKCFG[1],
VDDEH7
(2)
71, 76 102, 113 125, 138 D12
3.3 V –
5.0 V
MDO[0:3], EVTI
MCKO, MSEO
TDI, TMS, TCK, JCOMP,
AN[12:15]
, EVTO,
[0:1], TDO,
(GPIO[98:99],
GPIO[206:207])
CAL_ADDR[12:30],
CAL_DATA[0:15],
VDDE12
(3)
VDDE7
16, 119 E13, P6
1.8 V –
3.3 V
CAL_CS
CAL_CS[2:3],
CAL_RD_WR,
CAL_WE
[0],
[0:1], CAL_OE,
CAL_TS, ALT_MCKO,
ALT_EVTO, NEXUSCFG
1. These are nominal voltages. All VDDE and VDDEH voltages are –5%, +10% (VDDE 1.62 V to 3.6 V, VDDEH 3.0 V to 5.5 V). VDDA is +5%, –10%.
2. The VDDEH7 segment may be powered from 3.0 V to 5.0 V for mux address or SSI functions, but must meet the VDDA specifications of 4.5 V to 5.25 V for analog input function.
3. In the calibration package this signal is named VDDE12; it is named VDDE7 in all other packages.
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Electrical characteristics SPC563M64L5, SPC563M64L7

4 Electrical characteristics

This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the SPC563Mxx series of MCUs.In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol column.
In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol “SR” for System Requirement is included in the Symbol column.

4.1 Parameter classification

The electrical parameters shown in this document are guaranteed by various methods. To provide a better understanding, the classifications listed in Tab le 8 are used and the parameters are tagged accordingly in the tables. Note that only controller characteristics (“CC”) are classified. System requirements (“SR”) are operating conditions that must be provided to ensure normal device operation.
Table 8. Parameter classifications
Classification tag Tag description
P Those parameters are guaranteed during production testing on each individual device.
C
T
D Those parameters are derived mainly from simulations.
Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations.
Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category.
Note: The classification is shown in the column labeled “C” in the parameter tables where
appropriate.

4.2 Maximum ratings

Table 9. Absolute maximum ratings
V
V
FLASH
V
STBY
V
DDPLL
V
RC33
Symbol Parameter Conditions
DD
(5)
SR 1.2 V core supply voltage
SR Flash core voltage
SR SRAM standby voltage
SR Clock synthesizer voltage – 0.3 1.32 V
Voltage regulator control
SR
input voltage
(3)
(1)
(4)
(2)
Value
min max
– 0.3 1.32 V
– 0.3 5.5 V
– 0.3 5.5 V
– 0.3 3.6 V
Unit
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SPC563M64L5, SPC563M64L7 Electrical characteristics
Table 9. Absolute maximum ratings
(1)
(continued)
Symbol Parameter Conditions
(6)
(4)
(4)
Reference to V
V
V
V
DDEH
DDA
DDE
SR Analog supply voltage
SR I/O supply voltage
SR I/O supply voltage
V
V
IN
SR DC input voltage
(7)
pads
V
V
V
DDREG
VSS – V
V
RH
VRL – V
V
SSPLL
V
– V
RH
SSA
SSA
– V
RL
SS
Voltage regulator supply
SR
SR
(6)
voltage
Analog reference high voltage
Reference to VRL – 0.3 5.5 V
SR VSS differential voltage – 0.1 0.1 V
SR V
SR
SR
differential voltage
REF
VRL to V
SSA
voltage
to VSS differential
V
SSPLL
voltage
differential
(6)
min max
SSA
– 0.3 5.5 V
– 0.3 3.6 V
– 0.3 5.5 V
powered I/O
DDEH
powered I/O pads –1.0
DDE
powered I/O pads –1.0 V
DDA
–1.0
– 0.3 5.5 V
– 0.3 5.5 V
– 0.3 0.3 V
– 0.1 0.1 V
(8)
(10)
Value
V
DDEH
V
DDE
+0.3V
DDA
+0.3V
+0.3V
(10)
Unit
(9)
V
I
MAXD
I
MAXA
T
Maximum DC digital input
SR
SR
J
SR
(11)
current
Maximum DC analog input
(12)
current
Maximum operating temperature range
(13)
Per pin, applies to all digital pins
Per pin, applies to all analog pins
– die
– 3 3 mA
—5mA
– 40.0 150.0
junction temperature
T
STG
T
SDR
MSL SR Moisture sensitivity level
1. Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device.
2. Allowed 2 V for 10 hours cumulative time, remaining time at 1.2 V +10%.
3. The V
4. Allowed 6.8 V for 10 hours cumulative time, remaining time at 5 V +10%.
5. The pin named as V
6. All functional non-supply I/O pins are clamped to V
7. AC signal overshoot and undershoot of up to 2.0 V of the input voltages is permitted for an accumulative duration of 60
8. Internal structures hold the voltage greater than –1.0 V if the injection current limit of 2 mA is met.
FLASH
apply when the internal regulator is disabled and V
hours over the complete lifetime of the device (injection current not limited for this duration).
SR Storage temperature range – 55.0 150.0
Maximum solder
SR
temperature
supply is connected to V
is internally connected to the pads V
RC33
(14)
DDEH1
(15)
.
and V
FLASH
power is supplied externally.
RC33
SS
and V
DDE
, or V
DDEH
RC33
.
260.0
—3—
in the LQFP144 package. These limits
o
C
o
C
o
C
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Electrical characteristics SPC563M64L5, SPC563M64L7
9. Internal structures hold the input voltage less than the maximum voltage on all pads powered by V maximum injection current specification is met (2 mA for all pins) and V
10. Internal structures hold the input voltage less than the maximum voltage on all pads powered by V maximum injection current specification is met (2 mA for all pins) and V
11. Total injection current for all pins (including both digital and analog) must not exceed 25 mA.
12. Total injection current for all analog input pins must not exceed 15 mA.
13. Lifetime operation at these specification limits is not guaranteed.
14. Solder profile per CDF-AEC-Q100.
15. Moisture sensitivity per JEDEC test method A112.
is within the operating voltage specifications.
DDEH
is within the operating voltage specifications.
DDE
supplies, if the
DDEH
supplies, if the
DDE

4.3 Thermal characteristics

Table 10. Thermal characteristics for 100-pin LQFP
Symbol C Parameter Conditions Value Unit
R
θJA
R
θJA
R
θJMA
R
θJMA
R
θJB
R
θJCtop
Ψ
JT
1. Thermal characteristics are targets based on simulation that are subject to change per device characterization.
2. Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package.
3. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package.
4. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
5. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
CC D Junction-to-Ambient, Natural Convection
CC D Junction-to-Ambient, Natural Convection
CC D Junction-to-Ambient (@ 200 ft/min)
CC D Junction-to-Ambient (@ 200 ft/min)
CC D Junction-to-Board
CC D Junction-to-Case (Top)
CC D
Junction-to-Package Top, Natural Convection
(3)
(4)
(5)
(2)
(2)
(1)
(2)
Single layer board - 1s 47 °C/W
(2)
Four layer board - 2s2p 35 °C/W
Single layer board 37 °C/W
Four layer board 2s2p 29 °C/W
20 °C/W
C/W
C/W
Table 11. Thermal characteristics for 144-pin LQFP
Symbol C Parameter Conditions Value Unit
(2)
(2)
(1)
Single layer board – 1s 43 °C/W
(2)
Four layer board – 2s2p 35 °C/W
Single layer board –1s 34 °C/W
Four layer board – 2s2p 29 °C/W
22 °C/W
C/W
C/W
R
R
R
R
R
R
θJCtop
Ψ
θJA
θJA
θJMA
θJMA
θJB
JT
CC D Junction-to-Ambient, Natural Convection
CC D Junction-to-Ambient, Natural Convection
CC D Junction-to-Ambient (@200 ft/min)
CC D Junction-to-Ambient (@200 ft/min)
CC D Junction-to-Board
CC D Junction-to-Case (Top)
CC D
Junction-to-Package Top, Natural Convection
(2)
(3)
(4)
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SPC563M64L5, SPC563M64L7 Electrical characteristics
1. Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package.
2. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package.
3. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
4. Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
Table 12. Thermal characteristics for 176-pin LQFP
Symbol C Parameter Conditions Value Unit
R
θJA
R
θJA
R
θJMA
R
θJMA
R
θJB
R
θJCtop
Ψ
JT
1. Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package.
2. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package.
3. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
4. Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
CC D Junction-to-Ambient, Natural Convection
CC D Junction-to-Ambient, Natural Convection
CC D Junction-to-Moving-Air, Ambient
CC D Junction-to-Moving-Air, Ambient
CC D Junction-to-Board
CC D Junction-to-Case
CC D
Junction-to-Package Top, Natural Convection
(2)
(3)
(4)
(2)
(2)
(1)
Single layer board - 1s 38 °C/W
(2)
Four layer board - 2s2p 31 °C/W
@200 ft./min., single layer board - 1s
@200 ft./min., four layer board - 2s2p
30 °C/W
25 °C/W
20 °C/W
C/W
C/W
Table 13. Thermal characteristics for 208-pin LBGA
(1)
Symbol C Parameter Conditions Value Unit
R
θJA
R
θJMA
R
θJA
R
θJMA
R
θJB
R
θJC
Ψ
JT
1. Thermal characteristics are targets based on simulation that are subject to change per device characterization.
CC D
CC D Junction-to-ambient natural convection
CC D Junction-to-ambient (@200 ft/min)
CC D Junction-to-ambient (@200 ft/min)
CC D Junction-to-board
CC D Junction-to-case
CC D
Junction-to-ambient, natural convection
Junction-to-package top natural convection
(2),(3)
(5)
(6)
(7)
(2),(4)
(2),(4)
One layer board - 1s 39 °C/W
2,(4)
Four layer board - 2s2p 24 °C/W
Single layer board 31 °C/W
Four layer board 2s2p 20 °C/W
Four layer board - 2s2p 13 °C/W
C/W
C/W
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Electrical characteristics SPC563M64L5, SPC563M64L7
2. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
3. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
4. Per JEDEC JESD51-6 with the board horizontal.
5. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.
6. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.
7. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

4.3.1 General notes for specifications at maximum junction temperature

An estimation of the chip junction temperature, TJ, can be obtained from the equation:
Equation 1 T
= TA + (R
J
θJA
* PD)
where:
T
= ambient temperature for the package (oC)
A
R
= junction-to-ambient thermal resistance (oC/W)
θJA
P
= power dissipation in the package (W)
D
The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance depends on the:
Construction of the application board (number of planes)
Effective size of the board which cools the component
Quality of the thermal and electrical connections to the planes
Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced.
As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. The value obtained on a board with the internal planes is usually within the normal range if the application board has:
One oz. (35 micron nominal thickness) internal planes
Components are well separated
Overall power dissipation on the board is less than 0.02 W/cm2
The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device.
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SPC563M64L5, SPC563M64L7 Electrical characteristics
At a known board temperature, the junction temperature is estimated using the following equation:
Equation 2 T
= TB + (R
J
θJB
* PD)
where:
T
= board temperature for the package perimeter (oC)
B
R
= junction-to-board thermal resistance (oC/W) per JESD51-8S
θJB
P
= power dissipation in the package (W)
D
When the heat loss from the package case to the air does not factor into the calculation, an acceptable value for the junction temperature is predictable. Ensure the application board is similar to the thermal test condition, with the component soldered to a board with internal planes.
The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal resistance:
Equation 3 R
θJA
= R
θJC
+ R
θCA
where:
R
= junction-to-ambient thermal resistance (oC/W)
θJA
R
= junction-to-case thermal resistance (oC/W)
θJC
R
= case to ambient thermal resistance (oC/W)
θCA
R
is device related and is not affected by other factors. The thermal environment can be
θJC
controlled to change the case-to-ambient thermal resistance, R
. For example, change
θCA
the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient. For most packages, a better model is required.
A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple estimations and for computational fluid dynamics (CFD) thermal models.
To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization parameter (Ψ
) to determine the junction temperature by
JT
measuring the temperature at the top center of the package case using the following equation:
Equation 4 T
= TT + (ΨJT x PD)
J
where:
T
Ψ
P
= thermocouple temperature on top of the package (oC)
T
= thermal characterization parameter (oC/W)
JT
= power dissipation in the package (W)
D
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Electrical characteristics SPC563M64L5, SPC563M64L7
The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire.
References:
Semiconductor Equipment and Materials International 3081 Zanker Road San Jose, CA 95134 USA (408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956.
JEDEC specifications are available on the web at http://www.jedec.org.
C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an
Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.
G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled
Applications”, Electronic Packaging and Production, pp. 53-58, March 1998.
B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal
Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.
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SPC563M64L5, SPC563M64L7 Electrical characteristics

4.4 Electromagnetic Interference (EMI) characteristics

Table 14. EMI testing specifications
(1)
Symbol Parameter Conditions f
Device Configuration, test conditions and EM testing per
Radiated Emissions
V
EME
standard IEC61967-2; Supply Voltage =
5.0V DC, Ambient Temperature = 25°C, Worst-case Orientation
1. IEC Classification Level: L = 24dBuV; K = 30dBuV.
OSC/fBUS
Oscillator
Frequency = 8
MHz;
System Bus
Frequency = 80
MHz;
No PLL
Frequency
Modulation
Oscillator
Frequency = 8
MHz;
System Bus
Frequency = 80
MHz;
1% PLL
Frequency
Modulation
Frequency
150 kHz – 50
MHz
Level
(Typ)
26
50–150 MHz 24
150–500 MHz 24
500–1000 MHz 21
IEC Level K
150 kHz – 50
MHz
20
50–150 MHz 19
150–500 MHz 14
500–1000 MHz 7
IEC Level L
Unit
dBμV
dBμV

4.5 Electromagnetic static discharge (ESD) characteristics

Table 15. ESD ratings
Symbol Parameter Conditions Value Unit
SR ESD for Human Body Model (HBM) 2000 V
R1 SR
C SR 100 pF
—SR
SR Number of pulses per pin
SR Number of pulses 1
1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2. Device failure is defined as: “If after exposure to ESD pulses, the device does not meet the device specification requirements, which includes the complete DC parametric and functional testing at room temperature and hot temperature.”
(1),(2)
HBM circuit description
ESD for field induced charge Model (FCDM)
—1500Ω
All pins 500
Corner pins 750
Positive pulses (HBM) 1
Negative pulses (HBM) 1
V
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Electrical characteristics SPC563M64L5, SPC563M64L7
4.6 Power Management Control (PMC) and Power On Reset
(POR) electrical specifications
Table 16. PMC Operating conditions and external regulators supply voltage
ID Name C Parameter Min Typ Max Unit
1 Jtemp SR — Junction temperature –40 27 150 °C
2 Vddreg SR — PMC 5 V supply voltage VDDREG 4.75
(1)
55.25V
Core supply voltage 1.2 V VDD when external
3VddSR
regulator is used without disabling the internal regulator (PMC unit turned on, LVI monitor active)
(2)
1.26
(3)
1.3 1.32 V
Core supply voltage 1.2 V VDD when external
3a SR —
regulator is used with a disabled internal regulator (PMC unit turned-off, LVI monitor
1.14 1.2 1.32 V
disabled)
4IvddSR
Voltage regulator core supply maximum DC output current
(4)
400 mA
Regulated 3.3 V supply voltage when external regulator is used without disabling the internal
5 Vdd33 SR —
regulator (PMC unit turned-on, internal 3.3V
3.3 3.45 3.6 V
regulator enabled, LVI monitor active)
(5)
Regulated 3.3 V supply voltage when external
5a SR —
regulator is used with a disabled internal regulator (PMC unit turned-off, LVI monitor
33.33.6V
disabled)
6—SR
1. During start up operation the minimum required voltage to come out of reset state is 4.6 V.
2. An internal regulator controller can be used to regulate core supply.
3. The minimum supply required for the part to exit reset and enter in normal run mode is 1.28 V.
4. The onchip regulator can support a minimum of 400 ma although the worst case core current is 180 ma.
5. An internal regulator can be used to regulate 3.3 V supply.
Voltage regulator 3.3 V supply maximum required DC output current
80 mA
Table 17. PMC electrical characteristics
ID Name C Parameter Min Typ Max Unit Notes
1VbgCCC
1a CC P
1b CC P
1c CC C
Nominal bandgap voltage reference
Untrimmed bandgap reference voltage
Trimmed bandgap reference voltage (5 V, 27 °C)
(1)
Bandgap reference temperature variation
—1.219—V
Vbg–7% Vbg Vbg+6% V
Vbg–10mV Vbg Vbg+10mV V
100
ppm
/°C
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SPC563M64L5, SPC563M64L7 Electrical characteristics
Table 17. PMC electrical characteristics (continued)
ID Name C Parameter Min Typ Max Unit Notes
1d CC C
Bandgap reference supply voltage variation
—3000—
ppm
/V
Nominal VDD core supply
2VddCCC
internal regulator target DC output voltage
(2)
—1.28—V
Nominal VDD core supply
2a CC P
internal regulator target DC output voltage variation at
Vdd–6% Vdd Vdd+10% V
power-on reset
Nominal VDD core supply
2b CC P
internal regulator target DC output voltage variation
Vdd–10
(3)
Vdd Vdd + 3% V
after power-on reset
2c CC C Trimming step Vdd 20 mV
Voltage regulator controller
2d Ivrcctl CC C
for core supply maximum
20 mA
DC output current
3 Lvi1p2 CC C
Nominal LVI for rising core
(4),(5)
supply
—1.160—V
Variation of LVI for rising
3a CC C
core supply at power-on
(5),(6)
reset
1.120 1.200 1.280 V
Variation of LVI for rising
3b CC C
3c CC C
3d Lvi1p2_h CC C LVI core supply hysteresis
core supply after power-on
(5),(6)
reset
Trimming step LVI core
(5)
supply
Lvi1p2–3% Lvi1p2 Lvi1p2+3% V
—20—mV
(5)
—40—mV
4 Por1.2V_r CC C POR 1.2 V rising 0.709 V
4a CC C POR 1.2 V rising variation
Por1.2V_r–
35%
Por1.2V_rPor1.2V_r+
35%
4b Por1.2V_f CC C POR 1.2 V falling 0.638 V
4c CC C POR 1.2 V falling variation
Por1.2V_f–
35%
Por1.2V_fPor1.2V_f+
35%
Nominal 3.3 V supply
5 Vdd33 CC C
internal regulator DC output
—3.39—V
voltage
Nominal 3.3 V supply
5a CC P
internal regulator DC output voltage variation at power­on reset
(6)
Vdd33 –
8.5%
Vdd33 Vdd3 + 7% V
V
V
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Electrical characteristics SPC563M64L5, SPC563M64L7
Table 17. PMC electrical characteristics (continued)
ID Name C Parameter Min Typ Max Unit Notes
Nominal 3.3 V supply
5b CC P
5c CC D
internal regulator DC output voltage variation after power-on reset
Voltage regulator 3.3 V output impedance at maximum DC load
Vdd33 –
7.5%
Vdd33
Vdd33 +
7%
—— 2Ω
With internal load
V
up to Idd3p3
5d Idd3p3 CC P
Vdd33
5e
ILim
(6)
CC C
6 Lvi3p3 CC C
Voltage regulator 3.3 V maximum DC output current
Voltage regulator 3.3 V DC current limit
Nominal LVI for rising 3.3 V
(5)
supply
Variation of LVI for rising
6a CC C
3.3 V supply at power-on
(5)
reset
Variation of LVI for rising
6b CC C
3.3 V supply after power-on
(5)
reset
6c CC C Trimming step LVI 3.3 V
6d Lvi3p3_h CC C LVI 3.3 V hysteresis
7 Por3.3V_r CC C
7a CC C
7b Por3.3V_f CC C
Nominal POR for rising
3.3 V supply
Variation of POR for rising
3.3 V supply
Nominal POR for falling
3.3 V supply
(5)
80 mA
130 mA
—3.090—V
Lvi3p3–6% Lvi3p3 Lvi3p3+6% V See note
Lvi3p3–3% Lvi3p3 Lvi3p3+3% V See note 7
(5)
—20—mV
—60—mV
—2.07—V
Por3.3V_r–
35%
Por3.3V_rPor3.3V_r+
35%
V
—1.95—V
The Lvi3p3 specs are also valid for the Vddeh LVI
(7)
The 3.3V POR specs
are also valid for the
Vddeh POR
7c CC C
8 Lvi5p0 CC C
Variation of POR for falling
3.3 V supply
Nominal LVI for rising 5 V VDDREG supply
(5)
Por3.3V_f–
35%
—4.290—V
Variation of LVI for rising 5 V
8a CC C
VDDREG supply at power­on reset
(5)
Lvi5p0–6% Lvi5p0 Lvi5p0+6% V
Variation of LVI for rising 5 V
8b CC C
8c CC C Trimming step LVI 5 V
8d Lvi5p0_h CC C LVI 5 V hysteresis
VDDREG supply power-on
(5)
reset
(5)
(5)
Lvi5p0–3% Lvi5p0 Lvi5p0+3% V
—20—mV
—60—mV
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Por3.3V_fPor3.3V_f+
35%
V
SPC563M64L5, SPC563M64L7 Electrical characteristics
Table 17. PMC electrical characteristics (continued)
ID Name C Parameter Min Typ Max Unit Notes
9 Por5V_r CC C
9a CC C
9b Por5V_f CC C
9c CC C
1. The limits will be reviewed after data collection from 3 different lots in a full production environment.
2. Using external ballast transistor.
3. Min range is extended to 10% since Lvi1p2 is reprogrammed from 1.2 V to 1.16 V after power-on reset.
4. LVI for falling supply is calculated as LVI rising - LVI hysteresis.
5. The internal voltage regulator can be disabled by tying the VDDREG pin to ground. When the internal voltage regulator is disabled, the LVI specifications are not applicable because all LVI monitors are disabled. POR specifications remain valid when the internal voltage regulator is disabled as long as VDDEH and VDD33 supplies are within the required ranges.
6. This parameter is the “inrush” current of the internal 3.3V regulator when it is turned on. This spec. is the current at which the regulator will go into current limit mode.
7. Lvi3p3 tracks DC target variation of internal Vdd33 regulator. Minimum and maximum Lvi3p3 correspond to minimum and maximum Vdd33 DC target respectively.
Nominal POR for rising 5 V VDDREG supply
Variation of POR for rising 5 V VDDREG supply
Nominal POR for falling 5 V VDDREG supply
Variation of POR for falling 5 V VDDREG supply
—2.67—V
Por5V_r –
35%
Por5V_r
Por5V_r +
50%
—2.47—V
Por5V_f –
35%
Por5V_f
Por5V_f + 5
0%
V
V
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Electrical characteristics SPC563M64L5, SPC563M64L7

4.6.1 Regulator example

Keep inductance from 5V supply
5V from
power supply
to the transistor collector and
VDDREG below 1 μH if not using R
C
R
C
REG
C
Required only if R
V
DDREG
is used
C
C
C
C
T1
V
RCCTL
R
B
Keep inductance below 20 nH
R
E
E
C
B
V
DD
V
SS
C
D
MCU
Figure 7. Core voltage regulator controller external components preferred
configuration
There are three options for the bypassing and compensation networks for the 1.2V regulator controller. The component values in the following table are the same for all PMC network requirements.
Table 18. Required external PMC component values
Component Symbol Minimum Typical Maximum Units Comment
Pass Transistor T1
VDDREG capacitor C
Pass transistor Collector bypass capacitor
Collector resistor
1. The collector resistor may not be required. It depends on the allowable power dissipation of the pass transistor (T1).
(1)
C
R
REG
C
C
1.1
10 µF X7R, -50%/+35%
13.3 µF X7R, -50%/+35%
5.6
NJD2873 or BCP68
Ω
Ta bl e 1 9 , Ta bl e 2 0 and Tab l e 2 1 show the required component values for the three different
options.
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SPC563M64L5, SPC563M64L7 Electrical characteristics
Table 19. Network 1 component values
Component Symbol Minimum Typical Maximum Units Comment
4 x 2.35 4 x 4.7 4 x 6.35 µF X7R, -50%/+35%
C
Transistor emitter bypass
E
1 x 5 1 x 10 1 x 13.5 µF X7R, -50%/+35%
capacitance
R
ESR
MCU decoupling capacitor
Base "snubber" capacitor
Base "snubber" resistor R
Emitter resistor R
Table 20. Network 2 component values
C
D
C
B
B
E
4 x 50 4 x 100 4 x 135 nF X7R, -50%/+35%
1.1 2.2 2.97 µF X7R, -50%/+35%
6.12 6.8 7.48 ±10%
550m
000
Ω
Ω
Ω
Component Symbol Minimum Typical Maximum Units Comment
3 x 2.35 3 x 4.7 3 x 6.35 µF X7R, -50%/+35%
C
Transistor emitter bypass
E
1 x 5 1 x 10 1 x 13.5 µF X7R, -50%/+35%
capacitance
MCU decoupling capacitor
R
C
ESR
D
550m
4 x 50 4 x 100 4 x 135 nF X7R, -50%/+35%
Ω
Equivalent ESR of
capacitors
C
E
Not required (short)
Equivalent ESR of
capacitors
C
E
Base "snubber" capacitor
Base "snubber" resistor R
Emitter resistor R
C
B
B
E
1.1 2.2 2.97 µF X7R, -50%/+35%
9 10 11 ±10%
0.252 0.280 0.308
Ω
Ω
The following component configuration is acceptable when using the BCP68 transistor, however, is not recommended for new designs. Either option 1 or option 2 should be used for new designs. This option should not be used with the NJD2873 transistor.
Table 21. Network 3 component values
Transistor emitter bypass capacitance
MCU decoupling capacitor
Base "snubber" capacitor
Component Symbol Minimum Typical Maximum Units Comment
C
R
C
C
E
ESR
D
B
4 x 3.4 4 x 6.8 4 x 9.18 µF X7R, -50%/+35%
550m
Ω
4 x 110 4 x 220 4 x 297 nF X7R, -50%/+35%
1.1 2.2 2.97 µF X7R, -50%/+35%
Not required (short)
Equivalent ESR of
capacitors
C
E
Doc ID 14642 Rev 9 85/142
Electrical characteristics SPC563M64L5, SPC563M64L7
Table 21. Network 3 component values (continued)
Component Symbol Minimum Typical Maximum Units Comment
Base "snubber" resistor R
Emitter resistor R
B
E
13.5 15 16.5 ±10%
000

4.6.2 Recommended power transistors

The following NPN transistors are recommended for use with the on-chip voltage regulator controller: ON Semiconductor BCP68. The collector of the external transistor is preferably connected to the same voltage supply source as the output stage of the regulator.
Table 22. Recommended operating characteristics
Symbol Parameter Value Unit
h
(β) DC current gain (Beta) 60 – 550
FE
P
I
CMaxDC
VCE
V
1. Adjust resistor at bipolar transistor collector for 3.3 V/5.0 V to avoid VCE < VCE
Absolute minimum power dissipation
D
Minimum peak collector current 1.0 A
Collector-to-emitter saturation voltage 200–600
SAT
Base-to-emitter voltage 0.4–1.0 V
BE
TM
BCP68T1 or NJD2873 as well as Philips SemiconductorTM
Ω
Ω
>1.0
(1.5 preferred)
(1)
SAT
Not required (short)
W
mV

4.7 Power up/down sequencing

There is no power sequencing required among power sources during power up and power down, in order to operate within specification but use of the following sequence is strongly recommended when the internal regulator is bypassed:
5V → 3.3 V and 1.2 V
This is also the normal sequence when the internal regulator is enabled.
Although there are no power up/down sequencing requirements to prevent issues like latch­up, excessive current spikes, etc., the state of the I/O pins during power up/down varies according to table Tab le 2 3 for all pins with fast pads and Ta bl e 2 4 for all pins with medium, slow and multi-voltage pads.
Table 23. Power sequence pin states for fast pads
V
DDE
LOW X X LOW
V
DDE
e. If an external 3.3V external regulator is used to supply current to the 1.2V pass transistor and this supply also
supplies current for the other 3.3V supplies, then the 5V supply must always be greater than or equal to the external 3.3V supply.
(e)
V
RC33
LOW X HIGH
V
DD
Fast (pad_fc)
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SPC563M64L5, SPC563M64L7 Electrical characteristics
Table 23. Power sequence pin states for fast pads (continued)
V
DDE
V
DDE
V
DDE
Table 24. Power sequence pin states for medium, slow and multi-voltage pads
V
DDEH
V
V
V
RC33
RC33
RC33
V
DD
LOW X LOW
V
V
DDEH
DDEH
LOW HIGH IMPEDANCE
V
DD

4.8 DC electrical specifications

Table 25. DC electrical specifications
Symbol C Parameter Conditions
V
V
V
DDEH
V
V
DD
DDE
RC33
DDA
SR — Core supply voltage 1.14 1.32 V
SR — I/O supply voltage 1.62 3.6
SR — I/O supply voltage 3.0 5.25 V
SR
SR
3.3 V external
(4)
voltage
Analog supply voltage
(1)
—3.0—3.6V
—4.75
V
DD
Fast (pad_fc)
LOW HIGH IMPEDANCE
V
DD
FUNCTIONAL
Medium (pad_msr_hv)
Slow (pad_ssr_hv)
Multi-voltage (pad_multv_hv)
FUNCTIONAL
(2)
Value
min typ max
(3)
(5)
—5.25V
Unit
V
V
V
V
V
SS
RL
RH
V
FLASH
INDC
– V
V
– V
V
– V
V
DDF
RL
RH
SSA
SSA
RL
(8)
SR
SR
SR
SR
SR
SR
SR
Analog input
(6)
voltage
differential
V
SS
voltage
Analog reference low voltage
V
differential
RL
voltage
Analog reference high voltage
differential
V
REF
voltage
Flash operating voltage
(7)
—V
– 0.3 V
SSA
+0.3 V
DDA
—–100—100mV
—V
SSA
—V
+0.1 V
SSA
—–100—100mV
—V
– 0.1 V
DDA
DDA
4.75 5.25 V
1.14 1.32 V
SR — Flash read voltage 4.75 5.25 V
Doc ID 14642 Rev 9 87/142
V
Electrical characteristics SPC563M64L5, SPC563M64L7
Table 25. DC electrical specifications
Symbol C Parameter Conditions
SRAM standby voltage
Voltage regulator supply voltage
Clock synthesizer operating voltage
to VSS
V
SSPLL
differential voltage
C
Slow/medium pad I/O input low voltage
P
C
Fast pad I/O input low voltage
P
(9)
V
SSPLL
V
STBY
V
DDREG
V
DDPLL
V
IL_S
V
IL_F
– V
SS
SR
SR
SR
SR
CC
CC
(1)
(continued)
Unregulated mode
Regulated mode
Hysteresis enabled
hysteresis disabled
Hysteresis enabled
hysteresis disabled
(2)
Value
Unit
min typ max
0.95 1.2
V
2.0 5.5
4.75 5.25 V
1.14 1.32 V
—–100—100mV
–0.3 0.35*V
V
SS
DDEH
V
V
–0.3 0.40*V
SS
–0.3 0.35*V
V
SS
DDEH
DDE
V
VSS–0.3 0.40*V
DDE
V
IL_LS
V
IL_HS
V
V
V
IH_LS
IH_S
IH_F
CC
CC
CC
CC
CC
Multi-voltage pad I/O
C
input low voltage in low-swing
P
C
(10),(11),(12),(13)
mode
Multi-voltage pad I/O input low voltage in high-swing mode
P
C
Slow/medium pad I/O input high voltage
P
C
Fast pad I/O input high voltage
P
Multi-voltage pad I/O
C
input high voltage in low-swing
P
(10),(11),(12),(13)
mode
Hysteresis enabled
Hysteresis disabled
Hysteresis enabled
Hysteresis disabled
Hysteresis enabled
hysteresis disabled
Hysteresis enabled
hysteresis disabled
Hysteresis enabled
Hysteresis disabled
–0.3 0.8
V
SS
–0.3 1.1
V
SS
V
–0.3 0.35 V
SS
V
–0.3 0.4 V
SS
0.65 V
0.55 V
0.65 V
0.55 V
DDEH
DDEH
DDE
DDE
—V
—V
—V
—V
2.5 V
2.2 V
DDEH
DDEH
DDE
DDE
DDEH
DDEH
V
DDEH
V
DDEH
+0.3
V
+0.3
+0.3
V
+0.3
+0.3
V
+0.3
88/142 Doc ID 14642 Rev 9
SPC563M64L5, SPC563M64L7 Electrical characteristics
Table 25. DC electrical specifications
Symbol C Parameter Conditions
C
Multi-voltage pad I/O
V
IH_HS
V
OL_S
V
OL_F
V
OL_LS
V
OL_HS
CC
CC P
CC P
CC P
CC P
input high voltage in high-swing mode
P
Slow/medium multi­voltage pad I/O output low
(17),(15)
voltage
Fast pad I/O output low voltage
(16),(17)
Multi-voltage pad I/O output low voltage in low-swing
(10),(11),(12),(13),(
mode
16)
Multi-voltage pad I/O output low voltage in high-swing mode
(1)
(continued)
Hysteresis enabled
(14)
Hysteresis disabled
IOL=2mA 0.6 V
(16)
(2)
Value
Unit
min typ max
0.65 V
DDEH
—V
DDEH
+0.3
V
0.55 V
DDEH
———0.2*V
———0.2*V
———0.2V
—V
DDEH
DDEH
DDEH
+0.3
DDE
V
V
V
V
OH_S
V
OH_F
V
OH_LS
V
OH_HS
V
HYS_S
V
HYS_F
V
HYS_LS
CC P
CC P
CC P
CC P
CC C
CC C
CC C
Slow/medium pad I/O output high
(17),(15)
voltage
Fast pad I/O output high voltage
(16),(17)
Multi-voltage pad I/O output high voltage in low-swing
(10),(11),(12),(13),(
mode
16)
Multi-voltage pad I/O output high voltage in high-swing mode
(16)
Slow/medium/multi­voltage I/O input hysteresis
Fast I/O input hysteresis
Low-Swing-Mode Multi-Voltage I/O Input Hysteresis
—0.8V
—0.8V
=
I
OH_LS
0.5 mA
DDEH
=
Min V
4.75 V
—0.8V
0.1 * V
0.1 * V
hysteresis enabled
DDEH
DDE
——V
——V
2.1 3.7 V
DDEH
DDEH
DDE
——V
——V
——V
0.25 V
Doc ID 14642 Rev 9 89/142
Electrical characteristics SPC563M64L5, SPC563M64L7
Table 25. DC electrical specifications
Symbol C Parameter Conditions
CC P
IDD+I
DDPLL
I
DDSTBY
I
DDSTBY150
I
DDSLOW
I
DDSTOP
I
DD33
I
DDA
I
REF
I
DDREG
(18)
CC P
CC T
CC T T
CC P Operating current TJ=150oC— —700μA
CC
CC T
CC
Operating current
1.2 V supplies
Operating current 1 V supplies
P
V
low-power mode
DD
operating current @
1.32 V
C
Operating current
3.3 V supplies @ 80 MHz
P
Operating current
5.0 V supplies @ 80 MHz
(1)
(continued)
(2)
Value
Unit
min typ max
= 1.32 V,
V
DD
80 MHz
= 1.32 V,
V
DD
64 MHz
V
= 1.32 V,
DD
40 MHz
——195
——135
mACC P
——98
TJ=25oC— — 8A
=55oC— —10A
J
Slow mode
(19)
——50
mA
Stop mode
V
RC33
V
DDA
(20)
(4)
,
(21)
——50
——70mA
——30
Analog reference supply
——1.0
mAP
current
I
DDH1
I
DDH6
I
DDH7
I
DD7
I
DDH9
I
DD12
I
ACT_S
I
ACT_F
CV
D
DV
Operating current
DV
CC
DV
(22)
V
DDE
80 MHz
supplies @
DV
DV
C
Slow/medium I/O
CC
weak pull up/down current
(23)
P
D
CC
Fast I/O weak pull
D
up/down current
(23)
DDREG
V
DDEH1
DDEH6
DDEH7
DDE7
DDEH9
DDE12
3.0 V – 3.6 V 15 95
4.75 V –
5.25 V
1.62 V –
1.98 V
2.25 V –
2.75 V
——70
——
——
——
——
——
——
35 200
36 120
34 139
D 3.0 V – 3.6 V 42 158
See note
(22)
mA
μA
μA
90/142 Doc ID 14642 Rev 9
SPC563M64L5, SPC563M64L7 Electrical characteristics
Table 25. DC electrical specifications
Symbol C Parameter Conditions
C
I
ACT_MV_PU
I
ACT_MV_PD
I
INACT_D
I
IC
CC
CC
CC P
CC T
Multi-voltage pad weak pullup current
P
C
Multivoltage pad weak pulldown current
P
I/O input leakage
(24)
current
DC injection current (per pin)
(1)
(continued)
V
DDEH
3.0–3.6 V pad_multv_h v, all process corners, high swing mode only
4.75 V –
5.25 V
V
DDEH
3.0–3.6 V pad_multv_h v, all process corners, high swing mode only
4.75 V –
5.25 V
(2)
Value
Unit
min typ max
=
(10)
,
10 75
μA
25 200
=
(10)
,
10 60
μA
25 200
–2.5 2.5 μA
–1.0 1.0 mA
I
INACT_A
C
L
C
IN
C
IN_A
CC
CC
CC D
CC D
Analog input current,
P
channel off, AN[0:7], AN38, AN39
Analog input current,
P
channel off, all other analog pins (ANx)
D
D
Load capacitance (fast I/O)
(26)
D
D
Input capacitance (digital pins)
Input capacitance (analog pins)
(25)
(25)
—–250—250
nA
—–150—150
DSC(PCR[8: 9]) = 0b00
DSC(PCR[8: 9]) = 0b01
——10
——20
pF
DSC(PCR[8: 9]) = 0b10
DSC(PCR[8: 9]) = 0b11
——30
——50
———7pF
———10pF
Doc ID 14642 Rev 9 91/142
Electrical characteristics SPC563M64L5, SPC563M64L7
Table 25. DC electrical specifications
Symbol C Parameter Conditions
Input capacitance
C
IN_M
R
PUPD200K
R
PUPDMATCH
R
PUPD100K
R
PUPDMATCH
R
PUPD5K
to TH)SR—
T
A (TL
CC D
CC P
(digital and analog
(27)
pins
)
Weak Pull-Up/Down Resistance
(28),(29)
200 kΩ Option
CC C 200KΩ Option –2.5 2.5 %
CC P
Weak Pull-Up/Down Resistance
(28),(29)
100 kΩ Option
CC C 100KΩ Option –2.5 2.5 %
CC D
Weak Pull-Up/Down Resistance
(28)
5kΩ Option
Operating temperature range ­ambient (packaged)
(1)
(continued)
5V±5% supply
(2)
Value
Unit
min typ max
———12pF
130 280 kΩ
—65—140kΩ
1.4 7.5 kΩ
–40.0 125.0
ο
C
—SR
1. These specifications are design targets and subject to change per device characterization.
2. TBD: To Be Defined.
3. V
4. These specifications apply when V
5. ADC is functional with 4 V ≤ V
6. Internal structures hold the input voltage less than V
7. The V
8. V
9. Regulator is functional, with derated performance, with supply voltage down to 4.0 V.
10. Multi-voltage pads (type pad_multv_hv) must be supplied with a power supply between 4.75 V and 5.25 V.
11. The slew rate (SRC) setting must be 0b11 when in low-swing mode.
12. While in low-swing mode there are no restrictions in transitioning to high-swing mode.
13. Pin in low-swing mode can accept a 5 V input.
14. Pin in low-swing mode can accept a 5 V input.
15. Characterization based capability:
16. Characterization based capability:
17. All VOL/VOH values 100% tested with ± 2 mA load.
must be lower than V
DDE
speed with no bad behavior, but the accuracy will be degraded.
injection current specification is met (3 mA for all pins) and V
supply is connected to VDD in the package substrate. This specification applies to calibration package devices
DDF
only.
is only available in the calibration package.
FLASH
IOH_S = {6, 11.6} mA and IOL_S = {9.2, 17.7} mA for {slow, medium} I/O with VDDEH=4.5 V; IOH_S = {2.8, 5.4} mA and IOL_S = {4.2, 8.1} mA for {slow, medium} I/O with VDDEH=3.0 V
IOH_F = {12, 20, 30, 40} mA and IOL_F = {24, 40, 50, 65} mA for {00, 01,10, 11} drive mode with VDDE=3.0 V;
IOH_F = {7, 13, 18, 25} mA and IOL_F = {18, 30, 35, 50} mA for {00, 01, 10, 11} drive mode with VDDE=2.25 V;
IOH_F = {3, 7, 10, 15} mA and IOL_F = {12, 20, 27, 35} mA for {00, 01, 10, 11} drive mode with VDDE=1.62 V
Slew rate on power supply pins
, otherwise there is additional leakage on pins supplied by V
RC33
is supplied externally, after disabling the internal regulator (V
RC33
4.75 V but with derated accuracy. This means the ADC will continue to function at full
DDA
DDA
———50V/ms
.
DDE
DDREG
+ 1.0 V on all pads powered by V
is within the operating voltage specifications.
DDA
supplies, if the maximum
DDA
= 0).
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SPC563M64L5, SPC563M64L7 Electrical characteristics
18. Run mode as follows:
System clock = 40/60/80 MHz + FM 2% Code executed from flash memory ADC0 at 16 MHz with DMA enabled ADC1 at 8 MHz eMIOS pads toggle in PWM mode with a rate between 100 kHz and 500 kHz eTPU pads toggle in PWM mode with a rate between 10 kHz and 500 kHz CAN configured for a bit rate of 500 kHz DSPI configured in master mode with a bit rate of 2 MHz eSCI transmission configured with a bit rate of 100 kHz
19. Bypass mode, system clock at 1 MHz (using system clock divider), PLL shut down, CPU running simple executive code, 4 x ADC conversion every 10 ms, 2 × PWM channels at 1 kHz, all other modules stopped.
20. Bypass mode, system clock at 1 MHz (using system clock divider), CPU stopped, PIT running, all other modules stopped.
21. When using the internal regulator only, a bypass capacitor should be connected to this pin. External circuits should not be powered by the internal regulator. The internal regulator can be used as a reference for an external debugger.
22. Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a particular I/O segment, and the voltage of the I/O segment. See Table 26 for values to calculate power dissipation for specific operation. The total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment.
23. Absolute value of current, measured at V
24. Weak pull up/down inactive. Measured at V
25. Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8 to 12
o
C, in the ambient temperature range of 50 to 125 oC. Applies to pad types: pad_a and pad_ae.
26. Applies to CLKOUT, external bus pins, and Nexus pins.
27. Applies to the FCK, SDI, SDO, and SDS
28. This programmable option applies only to eQADC differential input channels and is used for biasing and sensor diagnostics.
29. When the pull-up and pull-down of the same nominal 200 KΩ or 100 KΩ value are both enabled, assuming no interference from external devices, the resulting pad voltage will be 0.5*V
and VIH.
IL
DDE
pins.
= 3.6 V and V
= 5.25 V. Applies to pad types: fast (pad_fc).
DDEH
±2.5%
DDE
Doc ID 14642 Rev 9 93/142
Electrical characteristics SPC563M64L5, SPC563M64L7

4.9 I/O Pad current specifications

Note: SPC563Mxx devices use two sets of I/O pads (5 V and 3.3 V). See Tab l e 4 and Tab l e 5 in
Section 3.6, Signal summary, for the pad type associated with each signal.
The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption is the sum of all output pin currents for a particular segment. The output pin current can be calculated from Ta bl e 2 6 based on the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Tab le 2 6 .
Table 26. I/O pad average I
DDE
Pad Type Symbol C
CC D 37 50 5.25 11 9
CC D 130 50 5.25 01 2.5
Slow I
DRV_SSR_HV
CC D 650 50 5.25 00 0.5
CC D 840 200 5.25 00 1.5
CC D 24 50 5.25 11 14
CC D 62 50 5.25 01 5.3
Medium I
DRV_MSR_HV
CC D 317 50 5.25 00 1.1
specifications
Period
(ns)
(1)
Load
(pF)
(2)
V
DDE
(V)
Drive/Slew
Rate Select
I
DDE
(mA)
Avg
(3)
I
DDE
RMS
(mA)
CC D 425 200 5.25 00 3
CC D 10 50 3.6 11 22.7 68.3
CC D 10 30 3.6 10 12.1 41.1
CC D 10 20 3.6 01 8.3 27.7
CC D 10 10 3.6 00 4.44 14.3
Fast I
DRV_FC
CC D 10 50 1.98 11 12.5 31
CC D 10 30 1.98 10 7.3 18.6
CC D 10 20 1.98 01 5.42 12.6
CC D 10 10 1.98 00 2.84 6.4
CC D 15 50 5.25 11 21.2
MultiV
(High Swing Mode)
I
DRV_MULTV_HV
CC D 30 50 5.25 10
CC D 50 50 5.25 01 6.2
CC D 300 50 5.25 00 1.1
CC D 300 200 5.25 00 4.0
MultiV
(Low
Swing
I
DRV_MULTV_HV
CC D 15 30 5.25 11 20.2
CC D 30 30 5.25 11 NA
Mode)
1. Numbers from simulations at best case process, 150 °C.
2. All loads are lumped.
3. Average current is for pad configured as output only.
(5)
(4)
4
4
4
(6)
94/142 Doc ID 14642 Rev 9
SPC563M64L5, SPC563M64L7 Electrical characteristics
4. Ratio from 5.5 V pad spec to 5.25 V data sheet.
5. Not specified.
6. Low swing mode is not a strong function of V
DDE
.

4.9.1 I/O pad VRC33 current specifications

The power consumption of the VRC33 supply is dependent on the usage of the pins on all I/O segments. The power consumption is the sum of all output pin V segments. The output pin V voltage, frequency, and load on all medium, slow, and multv_hv pins. The output pin VRC33 current can be calculated from Tab le 2 8 based on the voltage, frequency, and load on all fast pins. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Ta bl e 2 7 and Ta bl e 2 8.
Table 27. I/O pad V
Pad Type Symbol C
Slow I
RC33
DRV_SSR_HV
average I
CC D 100 50 11 0.8 235.7
CC D 200 50 01 0.04 87.4
CC D 800 50 00 0.06 47.4
current can be calculated from Tab l e 2 7 based on the
RC33
specifications
DDE
Period
(ns)
Load
(pF)
(1)
(2)
Slew Rate
Select
currents for all I/O
RC33
I
Avg
DD33
(µA)
I
DD33
RMS
(µA)
CC D 800 200 00 0.009 47
CC D 40 50 11 2.75 258
CC D 100 50 01 0.11 76.5
Medium I
DRV_MSR_HV
CC D 500 50 00 0.02 56.2
CC D 500 200 00 0.01 56.2
CC D 40 50 11 2.75 258
(3)
MultiV
(High
Swing Mode)
I
DRV_MULTV_HV
CC D 100 50 01 0.11 76.5
CC D 500 50 00 0.02 56.2
CC D 500 200 00 0.01 56.2
CC D 40 30 11 2.75 258
(4)
MultiV
(Low
Swing Mode)
I
DRV_MULTV_HV
CC D 100 30 11 0.11 76.5
CC D 500 30 11 0.02 56.2
CC D 500 30 11 0.01 56.2
1. These are typical values that are estimated from simulation and not tested. Currents apply to output pins only.
2. All loads are lumped.
3. Average current is for pad configured as output only.
4. In low swing mode, multi-voltage pads (pad_multv_hv) must operate in highest slew rate setting.
Doc ID 14642 Rev 9 95/142
Electrical characteristics SPC563M64L5, SPC563M64L7
Table 28 . V
Pad
Type
Symbol C
pad average DC current
RC33
Period
(ns)
CC D 10 50 3.6 3.6 11 2.35 6.12
CC D 10 30 3.6 3.6 10 1.75 4.3
CC D 10 20 3.6 3.6 01 1.41 3.43
CC D 10 10 3.6 3.6 00 1.06 2.9
Fast I
DRV_FC
CC D 10 50 3.6 1.98 11 1.75 4.56
CC D 10 30 3.6 1.98 10 1.32 3.44
CC D 10 20 3.6 1.98 01 1.14 2.95
CC D 10 10 3.6 1.98 00 0.95 2.62
1. These are typical values that are estimated from simulation and not tested. Currents apply to output pins only.
2. All loads are lumped.

4.9.2 LVDS pad specifications

LVDS pads are implemented to support the MSC (Microsecond Channel) protocol which is an enhanced feature of the DSPI module. The LVDS pads are compliant with LVDS specifications and support data rates up to 50 MHz.
Table 29. DSPI LVDS pad specification
(1)
Load
(pF)
(2)
(1)
V
RC33
(V)
V
DDE
(V)
Drive
Select
I
DD33
(µA)
Avg
I
DD33
RMS
(µA)
# Characteristic Symbol C Condition
Data Rate
4 Data Frequency F
LVD S C LK
CC D 50 MHz
Driver Specs
SRC=0b00 or
0b11
5 Differential output voltage V
OD
CC P
CC P SRC=0b01 90 340
CC P SRC=0b10 155 480
Common mode voltage
6
(LVDS), V
OS
7 Rise/Fall time TR/T
Propagation delay (Low to
8
High)
Propagation delay (High to
9
Low)
10 Delay (H/L), sync Mode t
11 Delay, Z to Normal (High/Low) T
V
OS
F
T
PLH
T
PHL
PDSYNC
DZ
CC P 0.8 1.2 1.6 V
CC D 2 ns
CC D 4 ns
CC D 4 ns
CC D 4 ns
CC D 500 ns
Min.
Val ue
Typ .
Value
Max.
Value
150 430
Unit
mV
96/142 Doc ID 14642 Rev 9
SPC563M64L5, SPC563M64L7 Electrical characteristics
Table 29. DSPI LVDS pad specification
# Characteristic Symbol C Condition
Diff Skew Itphla-tplhbI or
12
Itplhb-tphlaI
T
SKEW
(1)
(continued)
Min.
Val ue
Typ .
Value
Max.
Value
CC D 0.5 ns
Ter min atio n
13 Trans. Line (differential Zo) CC D 95 100 105 Ω
14 Temperature CC D –40 150 °C
1. These are typical values that are estimated from simulation.

4.10 Oscillator and PLLMRFM electrical characteristics

Table 30. PLLMRFM electrical specifications
(V
=1.14 V to 1.32 V, VSS = V
DDPLL
Symbol C Parameter Conditions
(1)
= 0 V, TA = TL to TH)
SSPLL
Val ue
min max
Unit
Unit
f
ref_crystal
f
ref_ext
f
pll_in
f
vco
f
sys
D
CC
PLL reference frequency range
C External reference 4 80
CC P
Phase detector input frequency range (after pre-divider)
CC P VCO frequency range
CC C On-chip PLL frequency
T
f
t
CYC
f
LORL
f
LORH
f
SCM
C
JITTER
t
sys
cst
CC
System frequency in bypass mode
P External reference 0 80
CC D System clock period 1 / f
D
CC
Loss of reference frequency window
D Upper limit 24 56
CC P Self-clocked mode frequency
CLKOUT
T
T
period
(8),(9),(10),
jitter
(11)
CC
CC T Crystal start-up time
T
V
IHEXT
CC
EXTAL input high voltage
T
(2)
(3)
(2)
(4)
(5)
(6),(7)
Peak-to-peak (clock edge to clock edge)
Long-term jitter (avg. over 2 ms interval)
(12), (13)
Crystal reference 4 20
MHz
—416MHz
—256512MHz
—1680MHz
Crystal reference 4 20
MHz
sys
ns
Lower limit 1.6 3.7
MHz
—1.275MHz
%f
CLK
OUT
f
SYS
–5 5
maximum
–6 6 ns
——10ms
Crystal Mode
0.8 Vxtal 1.5V
(14)
,
Vxtal +
0.4
V
V
External Reference
(14), (15)
RC33
+ 0.4
/2
V
RC33
Doc ID 14642 Rev 9 97/142
Electrical characteristics SPC563M64L5, SPC563M64L7
Table 30. PLLMRFM electrical specifications
(V
=1.14 V to 1.32 V, VSS = V
DDPLL
(1)
= 0 V, TA = TL to TH) (continued)
SSPLL
Val ue
Symbol C Parameter Conditions
Unit
min max
(14)
(14), (15)
,
Vxtal –
0.4
/2
V
0
RC33
– 0.4
V
ILEXT
CC
T
EXTAL input low voltage
T
Crystal Mode
0.65Vxtal1.25V
External Reference
4MHz 5 30
8MHz 5 26
CC T XTAL load capacitance
(12)
12 MHz 5 23
16 MHz 5 19
20 MHz 5 16
t
lpll
t
dc
f
LCK
f
UL
f
CS
f
DS
f
MOD
1. All values given are initial design targets and subject to change.
2. Considering operation with PLL not bypassed.
3. f
VCO
— In Legacy Mode f — In Enhanced Mode fvco = (f
4. All internal registers retain data at 0 Hz.
5. “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked mode.
6. Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the f window.
7. f
VCO
mode.
8. This value is determined by the crystal manufacturer and board design.
9. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via V percentage for a given interval.
10. Proper PC board layout procedures must be followed to achieve specifications.
11. Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C fCS or f
12. This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this PLL, load capacitors should not exceed these limits. For a 20 MHz crystal the maximum load should be 17 pF.
13. Proper PC board layout procedures must be followed to achieve specifications.
14. This parameter is guaranteed by design rather than 100% tested.
15. V
IHEXT
16. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR).
CC P PLL lock time
CC T Duty cycle of reference
CC T Frequency LOCK range –6 6 % f
CC T Frequency un-LOCK range –18 18 % f
D
CC
Modulation Depth
D Down Spread –0.5 –8.0
CC D Modulation frequency
is calculated as follows:
self clock range is 20–150 MHz. f
(depending on whether center spread or down spread modulation is enabled).
DS
cannot exceed V
=(f
VCO
crystal
crystal
in external reference mode.
RC33
(12), (16)
(17)
/ (PREDIV + 1)) * (4 * (MFD + 4))
/ (EPREDIV + 1)) * (EMFD + 4)
DDPLL
represents f
SCM
and V
SSPLL
after PLL output divider (ERFD) of 2 through 16 in enhanced
SYS
and variation in crystal oscillator frequency increase the C
——200μs
—4060%
Center spread ±0.25 ±4.0
——100kHz
and either
JITTER
SYS
JITTER
%f
LOR
.
V
pF
sys
sys
sys
98/142 Doc ID 14642 Rev 9
SPC563M64L5, SPC563M64L7 Electrical characteristics
17. Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50kHz.

4.11 Temperature sensor electrical characteristics

Table 31. Temperature sensor electrical characteristics
Value
Symbol C Parameter Conditions
Unit
min typical max
—CCC
Temperature monitoring range
–40 150 °C
CC C Sensitivity 6.3 mV/°C
CC P Accuracy T
= –40 to 150 °C –10 10 °C
J

4.12 eQADC electrical characteristics

Note: ADC performance is affected by several environmental elements, such as quality of the
input signal source, presence of noise sources and quality of the PCB layout.
The DC or Static parameters (DNL, INL, OFFSET, GAIN, and TUE) are measured using methods that provide a very accurate evaluation using averaging.
The AC or Dynamic parameters (SNR, THD, SFDR, SINAD) are determined using a full scale peak-peak sinewave of 1kHz frequency at the input of the ADC.
Table 32. eQADC conversion specifications (operating)
Symbol C Parameter
Val ue
Unit
min max
f
ADCLK
CC CC D Conversion cycles 2 + 13 128 + 14
T
SR
CC D Resolution
SR — ADC clock (ADCLK) frequency 2 16 MHz
ADCLK
cycles
CC C Stop mode recovery time
(2)
(1)
—10 μs
1.25 mV
OFFNC CC C Offset error without calibration 0 160 Counts
OFFWC CC C Offset error with calibration –4 4 Counts
GAINNC CC C Full scale gain error without calibration –160 0 Counts
GAINWC CC C Full scale gain error with calibration –4 4 Counts
I
INJ
E
INJ
CC T Disruptive input injection current
CC T Incremental error due to injection current
TUE8 CC C Total unadjusted error (TUE) at 8 MHz
TUE16 CC C Total unadjusted error at 16 MHz
SNR CC T Signal to Noise Ratio
(11)
(3), (4), (5), (6)
(6),(7),(8)
(9)
(10)
–3 3 mA
–4 4 Counts
–4 4 Counts
–8 8 Counts
55.2 dB
THD CC T Total Harmonic Distorsion 70.0 dB
Doc ID 14642 Rev 9 99/142
Electrical characteristics SPC563M64L5, SPC563M64L7
Table 32. eQADC conversion specifications (operating) (continued)
Val ue
Symbol C Parameter
min max
SFDR CC T Spurious Free Dynamic Range 65.0 dB
SINAD CC T Signal to Noise and Distorsion 55.0 dB
ENOB CC T Effective Number of Bits 8.8 Counts
CC – Variable gain amplifier accuracy (gain=1)
CC C
(12)
8 MHz ADC –4 4 Counts
INL
GAINVGA1
CC C 16 MHz ADC –8 8 Counts
CC C
8MHz ADC –3
DNL
CC C 16 MHz ADC –3
CC – Variable gain amplifier accuracy (gain=2)
(12)
(14)
(14)
(14)
3
(14)
3
Unit
(13)
Counts
Counts
CC D
8 MHz ADC –5 5 Counts
INL
GAINVGA2
CC D 16 MHz ADC –8 8 Counts
CC D
8 MHz ADC –3 3 Counts
DNL
CC D 16 MHz ADC –3 3 Counts
CC – Variable gain amplifier accuracy (gain=4)
CC D
(12)
8 MHz ADC –7 7 Counts
INL
GAINVGA4
CC D 16 MHz ADC –8 8 Counts
CC D
8 MHz ADC –4 4 Counts
DNL
CC D 16 MHz ADC –4 4 Counts
DIFF
max
CC C
Maximum differential voltage
DIFF
max2
CC C
(DANx+ - DANx-) or (DANx- ­DANx+)
DIFF
max4
DIFF
cmv
1. Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time that the ADC is ready to perform conversions.Delay from power up to full accuracy = 8 ms.
2. At V
RH
3. Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs greater then V
4. Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do not affect device reliability or cause permanent damage.
5. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values using V
6. Condition applies to two adjacent pins at injection limits.
7. Performance expected with production silicon.
8. All channels have same 10 kΩ <Rs<100kΩ; Channel under test has Rs=10 kΩ; I
CC C
CC C
– VRL = 5.12 V, one count = 1.25 mV. Without using pregain.
and 0x0 for values less then VRL. Other channels are not affected by non-disruptive conditions.
RH
Differential input Common mode voltage (DANx- + DANx+)/2
= V
POSCLAMP
+ 0.5 V and V
DDA
(15)
NEGCLAMP
PREGAIN set
to 1X setting
PREGAIN set
to 2X setting
PREGAIN set
to 4X setting
(VRH -
VRL)/2 -
5%
= – 0.3 V, then use the larger of the calculated values.
INJ=IINJMAX,IINJMIN.
(VRH ­VRL)/2
(VRH ­VRL)/4
(VRH ­VRL)/8
(VRH -
VRL)/2 +
5%
V
V
V
V
100/142 Doc ID 14642 Rev 9
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