This document provides an overview and describes the features of the SPC563Mxx series
of microcontroller units (MCUs). For functional characteristics, refer to the device reference
manual. Electrical specifications and package mechanical drawings are included in this
device data sheet. Pin assignments can be found in both the reference manual and data
sheet.
1.2 Description
These 32-bit automotive microcontrollers are a family of system-on-chip (SoC) devices that
contain many new features coupled with high performance 90 nm CMOS technology to
provide substantial reduction of cost per feature and significant performance improvement.
The advanced and cost-efficient host processor core of this automotive controller family is
built on Power Architecture
the architecture’s fit in embedded applications, includes additional instruction support for
digital signal processing (DSP), integrates technologies—such as an enhanced time
processor unit, enhanced queued analog-to-digital converter, Controller Area Network, and
an enhanced modular input-output system—that are important for today’s lower-end
powertrain applications. The device has a single level of memory hierarchy consisting of up
to 94 KB on-chip SRAM and up to 1.5 MB of internal flash memory. The device also has an
external bus interface (EBI) for ‘calibration’.
®
technology. This family contains enhancements that improve
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2 Overview
This document provides electrical specifications, pin assignments, and package diagrams
for the SPC563Mxx series of microcontroller units (MCUs). For functional characteristics,
refer to the SPC563Mxx Microcontroller Reference Manual.
The SPC563Mxx series microcontrollers are system-on-chip devices that are built on Power
Architecture
●Are 100% user-mode compatible with the Power Architecture instruction set
●Contain enhancements that improve the architecture’s fit in embedded applications
●Include additional instruction support for digital signal processing (DSP)
●Integrate technologies such as an enhanced time processor unit, enhanced queued
®
technology and:
analog-to-digital converter, Controller Area Network, and an enhanced modular inputoutput system
●Operating Parameters
–Fully static operation, 0 MHz – 80 MHz (plus 2% frequency modulation - 82 MHz)
––40 °C – 150 °C junction temperature operating range
–Low power design
Less than 400 mW power dissipation (nominal)
Designed for dynamic power management of core and peripherals
Software controlled clock gating of peripherals
Low power stop mode, with all clocks stopped
–Fabricated in 90 nm process
–1.2 V internal logic
●High performance e200z335 core processor
●Advanced microcontroller bus architecture (AMBA) crossbar switch (XBAR)
●Enhanced direct memory access (eDMA) controller
●Interrupt controller (INTC)
–191 peripheral interrupt request sources, plus 165 reserved positions
–Low latency—three clocks from receipt of interrupt request from peripheral to
interrupt request to processor
●Frequency Modulating Phase-locked loop (FMPLL)
●Calibration bus interface (EBI) (available only in the calibration package)
●System integration unit (SIU) centralizes control of pads, GPIO pins and external
interrupts.
●Error correction status module (ECSM) provides configurable error-correcting codes
(ECC) reporting
●Up to 1.5 MB on-chip flash memory
●Up to 94 KB on-chip static RAM
●Boot assist module (BAM) enables and manages the transition of MCU from reset to
user code execution from internal flash memory, external memory on the calibration
bus or download and execution of code via FlexCAN or eSCI.
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●Periodic interrupt timer (PIT)
–32-bit wide down counter with automatic reload
–4 channels clocked by system clock
–1 channel clocked by crystal clock
●System timer module (STM)
–32-bit up counter with 8-bit prescaler
–Clocked from system clock
–4 channel timer compare hardware
●Software watchdog timer (SWT) 32-bit timer
●Enhanced modular I/O system (eMIOS)
–16 standard timer channels (up to 14 channels connected to pins in LQFP144)
–24-bit timer resolution
●Second-generation enhanced time processor unit (eTPU2)
–High level assembler/compiler
–Enhancements to make ‘C’ compiler more efficient
–New ‘engine relative’ addressing mode
●Enhanced queued A/D converter (eQADC)
–2 independent on-chip RSD Cyclic ADCs
–Up to 34 input channels available to the two on-chip ADCs
–4 pairs of differential analog input channels
●2 deserial serial peripheral interface modules (DSPI)
–SPI provides full duplex communication ports with interrupt and DMA request
support
–Deserial serial interface (DSI) achieves pin reduction by hardware serialization
and deserialization of eTPU, eMIOS channels and GPIO
●2 enhanced serial communication interface (eSCI) modules
●2 FlexCAN modules
●Nexus port controller (NPC) per IEEE-ISTO 5001-2003 standard
NDI (Nexus development interface) levelClass 2+Class 2+Class 2+
Non-maskable interrupt and critical interruptYesYesYes
PIT (periodic interrupt timers)555
Task monitor timer4 channels4 channels4 channels
Temperature sensorYesYesYes
Windowing software watchdogYesYesYes
Packages
1. Calibration package only.
2. The 176-pin and 208-pin packages have 34 input channels; 144-pin package has 32; 100-pin package has 23.
3. One FlexCAN module has 64 message buffers; the other has 32 message buffers.
LQFP144
LQFP176
LQFP100
LQFP144
LQFP176
LQFP100
LQFP144
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4. 165 interrupt channels are reserved for compatibility with future devices. This device has 191 peripheral interrupt sources
plus 8 software interrupts available to the user.
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2.2 SPC563Mxx features
●Operating Parameters
–Fully static operation, 0 MHz – 80 MHz (plus 2% frequency modulation - 82 MHz)
––40 °C to 150 °C junction temperature operating range
–Low power design
Less than 400 mW power dissipation (nominal)
Designed for dynamic power management of core and peripherals
Software controlled clock gating of peripherals
Low power stop mode, with all clocks stopped
–Fabricated in 90 nm process
–1.2 V internal logic
–Single power supply with 5.0 V −10% / +5% (4.5 V to 5.25 V) with internal
regulator to provide 3.3 V and 1.2 V for the core
–Input and output pins with 5.0 V −10% / +5% (4.5 V to 5.25 V) range
35%/65% V
Selectable hysteresis
Selectable slew rate control
–Nexus pins powered by 3.3 V supply
–Designed with EMI reduction techniques
Phase-locked loop
Frequency modulation of system clock frequency
On-chip bypass capacitance
Selectable slew rate and drive strength
●High performance e200z335 core processor
–32-bit Power Architecture Book E programmer’s model
–Variable Length Encoding Enhancements
Allows Power Architecture instruction set to be optionally encoded in a mixed 16
and 32-bit instructions
Results in smaller code size
–Single issue, 32-bit Power Architecture technology compliant CPU
–In-order execution and retirement
–Precise exception handling
–Branch processing unit
Dedicated branch address calculation adder
Branch acceleration using Branch Lookahead Instruction Buffer
–Load/store unit
One-cycle load latency
Fully pipelined
Big and Little Endian support
Misaligned access support
Zero load-to-use pipeline bubbles
–Thirty-two 64-bit general purpose registers (GPRs)
CMOS switch levels (with hysteresis)
DDE
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–Memory management unit (MMU) with 16-entry fully-associative translation look-
aside buffer (TLB)
–Separate instruction bus and load/store bus
–Vectored interrupt support
–Interrupt latency < 120 ns @ 80 MHz (measured from interrupt request to
execution of first instruction of interrupt exception handler)
–Non-maskable interrupt (NMI) input for handling external events that must produce
an immediate response, e.g., power down detection. On this device, the NMI input
is connected to the Critical Interrupt Input. (May not be recoverable)
–Critical Interrupt input. For external interrupt sources that are higher priority than
provided by the Interrupt Controller. (Always recoverable)
–New ‘Wait for Interrupt’ instruction, to be used with new low power modes
–Reservation instructions for implementing read-modify-write accesses
–Signal processing extension (SPE) APU
Operating on all 32 GPRs that are all extended to 64 bits wide
Provides a full compliment of vector and scalar integer and floating point arithmetic
operations (including integer vector MAC and MUL operations) (SIMD)
Provides rich array of extended 64-bit loads and stores to/from extended GPRs
Fully code compatible with e200z6 core
–Floating point (FPU)
IEEE 754 compatible with software wrapper
Scalar single precision in hardware, double precision with software library
Conversion instructions between single precision floating point and fixed point
Fully code compatible with e200z6 core
–Long cycle time instructions, except for guarded loads, do not increase interrupt
latency
–Extensive system development support through Nexus debug port
●Advanced microcontroller bus architecture (AMBA) crossbar switch (XBAR)
–Three master ports, four slave ports
Masters: CPU Instruction bus; CPU Load/store bus (Nexus); eDMA
–32-bit internal address bus, 64-bit internal data bus
●Enhanced direct memory access (eDMA) controller
–32 channels support independent 8-bit, 16-bit, or 32-bit single value or block
transfers
–Supports variable sized queues and circular queues
–Source and destination address registers are independently configured to post-
increment or remain constant
–Each transfer is initiated by a peripheral, CPU, or eDMA channel request
–Each eDMA channel can optionally send an interrupt request to the CPU on
completion of a single value or block transfer
●Interrupt controller (INTC)
–191 peripheral interrupt request sources
–8 software setable interrupt request sources
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–9-bit vector
Unique vector for each interrupt request source
Provided by hardware connection to processor or read from register
–Each interrupt source can be programmed to one of 16 priorities
–Preemption
Preemptive prioritized interrupt requests to processor
ISR at a higher priority preempts ISRs or tasks at lower priorities
Automatic pushing or popping of preempted priority to or from a LIFO
Ability to modify the ISR or task priority. Modifying the priority can be used to
implement the Priority Ceiling Protocol for accessing shared resources.
–Low latency—three clocks from receipt of interrupt request from peripheral to
interrupt request to processor
●Frequency Modulating Phase-locked loop (FMPLL)
–Reference clock pre-divider (PREDIV) for finer frequency synthesis resolution
–Reduced frequency divider (RFD) for reducing the FMPLL output clock frequency
without forcing the FMPLL to re-lock
–System clock divider (SYSDIV) for reducing the system clock frequency in normal
or bypass mode
–Input clock frequency range from 4 MHz to 20 MHz before the pre-divider, and
from 4 MHz to 16 MHz at the FMPLL input
–Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz
–VCO free-running frequency range from 25 MHz to 125 MHz
–Four bypass modes: crystal or external reference with PLL on or off
–Two normal modes: crystal or external reference
–Programmable frequency modulation
Triangle wave modulation
Register programmable modulation frequency and depth
–Lock detect circuitry reports when the FMPLL has achieved frequency lock and
continuously monitors lock status to report loss of lock conditions
User-selectable ability to generate an interrupt request upon loss of lock
User-selectable ability to generate a system reset upon loss of lock
–Clock quality monitor (CQM) module provides loss-of-clock detection for the
FMPLL reference and output clocks
User-selectable ability to generate an interrupt request upon loss of clock
User-selectable ability to generate a system reset upon loss of clock
Backup clock (reference clock or FMPLL free-running) can be applied to the
system in case of loss of clock
●Calibration bus interface (EBI)
–Available only in the calibration package (496 CSP package)
–1.8 V to 3.3 V ± 10% I/O (1.6 V to 3.6 V)
–Memory controller with support for various memory types
–16-bit data bus, up to 22-bit address bus
–Selectable drive strength
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–Configurable bus speed modes
–Bus monitor
–Configurable wait states
●System integration unit (SIU)
–Centralized GPIO control of 80 I/O pins
–Centralized pad control on a per-pin basis
Pin function selection
Configurable weak pull-up or pull-down
Drive strength
Slew rate
Hysteresis
–System reset monitoring and generation
–External interrupt inputs, filtering and control
–Critical Interrupt control
–Non-Maskable Interrupt control
–Internal multiplexer subblock (IMUX)
Allows flexible selection of eQADC trigger inputs (eTPU, eMIOS and external
signals)
Allows selection of interrupt requests between external pins and DSPI
–For SPC563M64: 94 KB general purpose RAM of which 32 KB are on standby
power supply
–For SPC563M60P: 64 KB general purpose RAM of which 32 KB are on standby
power supply
–For SPC563M54P: 48 KB general purpose RAM of which 24 KB are on standby
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power supply
●Boot assist module (BAM)
–Enables and manages the transition of MCU from reset to user code execution in
the following configurations:
Execution from internal flash memory
Execution from external memory on the calibration bus
Download and execution of code via FlexCAN or eSCI
●Periodic interrupt timer (PIT)
–32-bit wide down counter with automatic reload
–Four channels clocked by system clock
–One channel clocked by crystal clock
–Each channel can produce periodic software interrupt
–Each channel can produce periodic triggers for eQADC queue triggering
–One channel out of the five can be used as wake-up timer to wake device from low
power stop mode
●System timer module (STM)
–32-bit up counter with 8-bit prescaler
–Clocked from system clock
–Four-channel timer compare hardware
–Each channel can generate a unique interrupt request
–Designed to address AUTOSAR task monitor function
●Software watchdog timer (SWT)
–32-bit timer
–Clock by system clock or crystal clock
–Can generate either system reset or non-maskable interrupt followed by system
reset
–Enabled out of reset
●Enhanced modular I/O system (eMIOS)
–16 timer channels (up to 14 channels in LQFP144)
–24-bit timer resolution
–3 selectable time bases plus shared time or angle counter bus from eTPU2
–DMA and interrupt request support
–Motor control capability
●Second-generation enhanced time processor unit (eTPU2)
–Object-code compatible with eTPU—no changes are required to hardware or
software if only eTPU features are used
–Intelligent co-processor designed for timing control
–High level tools, assembler and compiler available
–32 channels (each channel has dedicated I/O pin in all packages except
LQFP100)
–24-bit timer resolution
–14 KB code memory and 3 KB data memory
–Double match and capture on all channels
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–Angle clock hardware support
–Shared time or angle counter bus with eMIOS
–DMA and interrupt request support
–Nexus Class 1 debug support
–eTPU2 enhancements
Counters and channels can run at full system clock speed
Software watchdog
Real-time performance monitor
Instruction set enhancements for smaller more flexible code generation
Programmable channel mode for customization of channel operation
●Enhanced queued A/D converter (eQADC)
–Two independent on-chip redundant signed digit (RSD) cyclic ADCs
8-, 10-, and 12-bit resolution
Differential conversions
Targets up to 10-bit accuracy at 500 KSample/s (ADC_CLK = 7.5 MHz) and 8-bit
accuracy at 1 MSample/s (ADC_CLK = 15 MHz) for differential conversions
Differential channels include variable gain amplifier (VGA) for improved dynamic
range (×1; ×2; ×4)
Differential channels include programmable pull-up and pull-down resistors for
biasing and sensor diagnostics (200 kΩ; 100 kΩ; low value of 5 kΩ)
Single-ended signal range from 0 to 5 V
Sample times of 2 (default), 8, 64 or 128 ADC clock cycles
Provides time stamp information when requested
Parallel interface to eQADC command FIFOs (CFIFOs) and result FIFOs
(RFIFOs)
Supports both right-justified unsigned and signed formats for conversion results
Temperature sensor to enable measurement of die temperature
Ability to measure all power supply pins directly
–Automatic application of ADC calibration constants
Provision of reference voltages (25% VREF
and 75% VREF) for ADC calibration
purposes
–Up to 34
(b)
input channels available to the two on-chip ADCs
–Four pairs of differential analog input channels
–Full duplex synchronous serial interface to an external device
Has a free-running clock for use by the external device
Supports a 26-bit message length
Transmits a null message when there are no triggered CFIFOs with commands
bound for external CBuffers, or when there are triggered CFIFOs with commands
bound for external CBuffers but the external CBuffers are full
–Parallel Side Interface to communicate with an on-chip companion module
–Zero jitter triggering for queue 0. (Queue 0 trigger causes current conversion to be
b. 176-pin and 208-pin packages have 34 input channels; 144-pin package has 32; 100-pin package has 23.
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aborted and the queued conversions in the CBUFFER to be bypassed. Delay from
Trigger to start of conversion is 13 system clocks + 1 ADC clock.)
–eQADC Result Streaming. Generation of a continuous stream of ADC conversion
results from a single eQADC command word. Controlled by two different trigger
signals; one to define the rate at which results are generated and the other to
define the beginning and ending of the stream. Used to digitize waveforms during
specific time/angle windows, e.g., engine knock sensor sampling.
–Angular Decimation. The ability of the eQADC to sample an analog waveform in
the time domain, perform Finite Impulse Response (FIR) or Infinite Impulse
Response (IIR) filtering also in the time domain, but to down sample the results in
the angle domain. Resulting in a time domain filtered result at a given engine
angle.
–Priority Based CFIFOs
Supports six CFIFOs with fixed priority. The lower the CFIFO number, the higher
its priority. When commands of distinct CFIFOs are bound for the same CBuffer,
the higher priority CFIFO is always served first.
Supports software and several hardware trigger modes to arm a particular CFIFO
Generates interrupt when command coherency is not achieved
–External Hardware Triggers
Supports rising edge, falling edge, high level and low level triggers
Supports configurable digital filter
–Supports four external 8-to-1 muxes which can expand the input channel number
from 34
●Two deserial serial peripheral interface modules (DSPI)
(c)
to 59
–SPI
Full duplex communication ports with interrupt and DMA request support
Support for queues in RAM
6 chip selects, expandable to 64 with external demultiplexers
Programmable frame size, baud rate, clock delay and clock phase on a per frame
basis
Modified SPI mode for interfacing to peripherals with longer setup time
requirements
LVDS option for output clock and data to allow higher speed communication
–Deserial serial interface (DSI)
Pin reduction by hardware serialization and deserialization of eTPU, eMIOS
channels and GPIO
32 bits per DSPI module
Triggered transfer control and change in data transfer control (for reduced EMI)
Compatible with Microsecond Channel Version 1.0 downstream
c.176-pin and 208-ball packages.
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●Two enhanced serial communication interface (eSCI) modules
–UART mode provides NRZ format and half or full duplex interface
–eSCI bit rate up to 1 Mbps
–Advanced error detection, and optional parity generation and detection
–Word length programmable as 8, 9, 12 or 13 bits
–Separately enabled transmitter and receiver
–LIN support
–DMA support
–Interrupt request support
–Programmable clock source: system clock or oscillator clock
–Support Microsecond Channel (Timed Serial Bus - TSB) upstream Version 1.0
●Tw o F l e xC A N
–One with 32 message buffers; the second with 64 message buffers
–Full implementation of the CAN protocol specification, Version 2.0B
–Programmable acceptance filters
–Short latency time for high priority transmit messages
–Arbitration scheme according to message ID or message buffer number
–Listen only mode capabilities
–Programmable clock source: system clock or oscillator clock
–Message buffers may be configured as mailboxes or as FIFO
●Nexus port controller (NPC)
–Per IEEE-ISTO 5001-2003
–Real time development support for Power Architecture core and eTPU engine
through Nexus class 2/1
–Read and write access (Nexus class 3 feature that is supported on this device)
Run-time access of entire memory map
Calibration
–Support for data value breakpoints / watchpoints
Run-time access of entire memory map
Calibration
Table constants calibrated using MMU and internal and external RAM
Scalar constants calibrated using cache line locking
–Configured via the IEEE 1149.1 (JTAG) port
●IEEE 1149.1 JTAG controller (JTAGC)
–IEEE 1149.1-2001 Test Access Port (TAP) interface
–5-bit instruction register that supports IEEE 1149.1-2001 defined instructions
–5-bit instruction register that supports additional public instructions
–Three test data registers: a bypass register, a boundary scan register, and a
device identification register
–Censorship disable register. By writing the 64-bit serial boot password to this
register, Censorship may be disabled until the next reset
–TAP controller state machine that controls the operation of the data registers,
instruction register and associated circuitry
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●On-chip Voltage Regulator for single 5 V supply operation
–On-chip regulator 5 V to 3.3 V for internal supplies
–On-chip regulator controller 5 V to 1.2 V (with external bypass transistor) for core
logic
●Low-power modes
–SLOW Mode. Allows device to be run at very low speed (approximately 1 MHz),
with modules (including the PLL) selectively disabled in software
–STOP Mode. System clock stopped to all modules including the CPU. Wake-up
timer used to restart the system clock after a predetermined time
2.3 SPC563Mxx feature details
2.3.1 e200z335 core
The e200z335 processor utilizes a four stage pipeline for instruction execution. The
Instruction Fetch (stage 1), Instruction Decode/Register file Read/Effective Address
Calculation (stage 2), Execute/Memory Access (stage 3), and Register Writeback (stage 4)
stages operate in an overlapped fashion, allowing single clock instruction execution for most
instructions.
The integer execution unit consists of a 32-bit Arithmetic Unit (AU), a Logic Unit (LU), a 32bit Barrel shifter (Shifter), a Mask-Insertion Unit (MIU), a Condition Register manipulation
Unit (CRU), a Count-Leading-Zeros unit (CLZ), a 32×32 Hardware Multiplier array, result
feed-forward hardware, and support hardware for division.
Most arithmetic and logical operations are executed in a single cycle with the exception of
the divide instructions. A Count-Leading-Zeros unit operates in a single clock cycle. The
Instruction Unit contains a PC incrementer and a dedicated Branch Address adder to
minimize delays during change of flow operations. Sequential prefetching is performed to
ensure a supply of instructions into the execution pipeline. Branch target prefetching is
performed to accelerate taken branches. Prefetched instructions are placed into an
instruction buffer capable of holding six instructions.
Branches can also be decoded at the instruction buffer and branch target addresses
calculated prior to the branch reaching the instruction decode stage, allowing the branch
target to be prefetched early. When a branch is detected at the instruction buffer, a
prediction may be made on whether the branch is taken or not. If the branch is predicted to
be taken, a target fetch is initiated and its target instructions are placed in the instruction
buffer following the branch instruction. Many branches take zero cycle to execute by using
branch folding. Branches are folded out from the instruction execution pipe whenever
possible. These include unconditional branches and conditional branches with condition
codes that can be resolved early.
Conditional branches which are not taken and not folded execute in a single clock. Branches
with successful target prefetching which are not folded have an effective execution time of
one clock. All other taken branches have an execution time of two clocks. Memory load and
store operations are provided for byte, halfword, and word (32-bit) data with automatic zero
or sign extension of byte and halfword load data as well as optional byte reversal of data.
These instructions can be pipelined to allow effective single cycle throughput. Load and
store multiple word instructions allow low overhead context save and restore operations.
The load/store unit contains a dedicated effective address adder to allow effective address
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generation to be optimized. Also, a load-to-use dependency does not incur any pipeline
bubbles for most cases.
The Condition Register unit supports the condition register (CR) and condition register
operations defined by the Power Architecture. The condition register consists of eight 4-bit
fields that reflect the results of certain operations, such as move, integer and floating-point
compare, arithmetic, and logical instructions, and provide a mechanism for testing and
branching. Vectored and autovectored interrupts are supported by the CPU. Vectored
interrupt support is provided to allow multiple interrupt sources to have unique interrupt
handlers invoked with no software overhead.
The hardware floating-point unit utilizes the IEEE-754 single-precision floating-point format
and supports single-precision floating-point operations in a pipelined fashion. The general
purpose register file is used for source and destination operands, thus there is a unified
storage model for single-precision floating-point data types of 32 bits and the normal integer
type. Single-cycle floating-point add, subtract, multiply, compare, and conversion operations
are provided. Divide instructions are multi-cycle and are not pipelined.
The Signal Processing Extension (SPE) Auxiliary Processing Unit (APU) provides hardware
SIMD operations and supports a full complement of dual integer arithmetic operation
including Multiply Accumulate (MAC) and dual integer multiply (MUL) in a pipelined fashion.
The general purpose register file is enhanced such that all 32 of the GPRs are extended to
64 bits wide and are used for source and destination operands, thus there is a unified
storage model for 32×32 MAC operations which generate greater than 32-bit results.
The majority of both scalar and vector operations (including MAC and MUL) are executed in
a single clock cycle. Both scalar and vector divides take multiple clocks. The SPE APU also
provides extended load and store operations to support the transfer of data to and from the
extended 64-bit GPRs.
The CPU includes support for Variable Length Encoding (VLE) instruction enhancements.
This enables the classic Power Architecture instruction set to be represented by a modified
instruction set made up from a mixture of 16- and 32-bit instructions. This results in a
significantly smaller code size footprint without noticeably affecting performance. The Power
Architecture instruction set and VLE instruction set are available concurrently. Regions of
the memory map are designated as PPC or VLE using an additional configuration bit in
each of Table Look-aside Buffers (TLB) entries in the MMU.
The CPU core is enhanced by the addition of two additional interrupt sources; NonMaskable Interrupt and Critical Interrupt. These two sources are routed directly from
package pins, via edge detection logic in the SIU to the CPU, bypassing completely the
Interrupt Controller. Once the edge detection logic is programmed, it cannot be disabled,
except by reset. The non-maskable Interrupt is, as the name suggests, completely unmaskable and when asserted will always result in the immediate execution of the respective
interrupt service routine. The non-maskable interrupt is not guaranteed to be recoverable.
The Critical Interrupt is very similar to the non-maskable interrupt, but it can be masked by
other exceptional interrupts in the CPU and is guaranteed to be recoverable (code execution
may be resumed from where it stopped).
The CPU core has an additional ‘Wait for Interrupt’ instruction that is used in conjunction
with low power STOP mode. When Low Power Stop mode is selected, this instruction is
executed to allow the system clock to be stopped. An external interrupt source or the system
wake-up timer is used to restart the system clock and allow the CPU to service the interrupt.
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2.3.2 Crossbar
The XBAR multi-port crossbar switch supports simultaneous connections between three
master ports and four slave ports. The crossbar supports a 32-bit address bus width and a
64-bit data bus width.
The crossbar allows three concurrent transactions to occur from the master ports to any
slave port; but each master must access a different slave. If a slave port is simultaneously
requested by more than one master port, arbitration logic selects the higher priority master
and grants it ownership of the slave port. All other masters requesting that slave port are
stalled until the higher priority master completes its transactions. Requesting masters are
treated with equal priority and are granted access to a slave port in round-robin fashion,
based upon the ID of the last master to be granted access. The crossbar provides the
following features:
●32-bit internal address, 64-bit internal data paths
2.3.3 eDMA
The enhanced direct memory access (eDMA) controller is a second-generation module
capable of performing complex data movements via 32 programmable channels, with
minimal intervention from the host processor. The hardware micro architecture includes a
DMA engine which performs source and destination address calculations, and the actual
data movement operations, along with an SRAM-based memory containing the transfer
control descriptors (TCD) for the channels. This implementation is utilized to minimize the
overall block size. The eDMA module provides the following features:
●All data movement via dual-address transfers: read from source, write to destination
●Programmable source and destination addresses, transfer size, plus support for
enhanced addressing modes
●Transfer control descriptor organized to support two-deep, nested transfer operations
●An inner data transfer loop defined by a “minor” byte transfer count
●An outer data transfer loop defined by a “major” iteration count
●Channel activation via one of three methods:
–Explicit software initiation
–Initiation via a channel-to-channel linking mechanism for continuous transfers
–Peripheral-paced hardware requests (one per channel)
●Support for fixed-priority and round-robin channel arbitration
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●Channel completion reported via optional interrupt requests
●1 interrupt per channel, optionally asserted at completion of major iteration count
●Error termination interrupts are optionally enabled
●Support for scatter/gather DMA processing
●Channel transfers can be suspended by a higher priority channel
2.3.4 Interrupt controller
The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt
requests, suitable for statically scheduled hard real-time systems. The INTC allows interrupt
request servicing from up to 191 peripheral interrupt request sources, plus 165 sources
reserved for compatibility with other family members).
For high priority interrupt requests, the time from the assertion of the interrupt request from
the peripheral to when the processor is executing the interrupt service routine (ISR) has
been minimized. The INTC provides a unique vector for each interrupt request source for
quick determination of which ISR needs to be executed. It also provides an ample number of
priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To
allow the appropriate priorities for each source of interrupt request, the priority of each
interrupt request is software configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be
supported. The INTC supports the priority ceiling protocol for coherent accesses. By
providing a modifiable priority mask, the priority can be raised temporarily so that all tasks
which share the resource can not preempt each other.
Multiple processors can assert interrupt requests to each other through software setable
interrupt requests. These same software setable interrupt requests also can be used to
break the work involved in servicing an interrupt request into a high priority portion and a low
priority portion. The high priority portion is initiated by a peripheral interrupt request, but
then the ISR asserts a software setable interrupt request to finish the servicing in a lower
priority ISR. Therefore these software setable interrupt requests can be used instead of the
peripheral ISR scheduling a task through the RTOS.
The INTC provides the following features:
●356 peripheral interrupt request sources
●8 software setable interrupt request sources
●9-bit vector addresses
●Unique vector for each interrupt request source
●Hardware connection to processor or read from register
●Each interrupt source can be programmed to one of 16 priorities
●Preemptive prioritized interrupt requests to processor
●ISR at a higher priority preempts executing ISRs or tasks at lower priorities
●Automatic pushing or popping of preempted priority to or from a LIFO
●Ability to modify the ISR or task priority to implement the priority ceiling protocol for
accessing shared resources
●Low latency—three clocks from receipt of interrupt request from peripheral to interrupt
request to processor
This device also includes a non-maskable interrupt (NMI) pin that bypasses the INTC and
multiplexing logic.
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2.3.5 FMPLL
The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 20 MHz
crystal oscillator or external clock generator. Further, the FMPLL supports programmable
frequency modulation of the system clock. The PLL multiplication factor, output clock divider
ratio are all software configurable. The PLL has the following major features:
●Input clock frequency from 4 MHz to 20 MHz
●Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz, resulting in
system clock frequencies from 16 MHz to 80 MHz with granularity of 4 MHz or better
●Reduced frequency divider (RFD) for reduced frequency operation without forcing the
PLL to relock
●3 modes of operation
–Bypass mode with PLL off
–Bypass mode with PLL running (default mode out of reset)
–PLL normal mode
●Each of the three modes may be run with a crystal oscillator or an external clock
reference
●Programmable frequency modulation
–Modulation enabled/disabled through software
–Triangle wave modulation up to 100 kHz modulation frequency
–Programmable modulation depth (0% to 2% modulation depth)
–Programmable modulation frequency dependent on reference frequency
●Lock detect circuitry reports when the PLL has achieved frequency lock and
continuously monitors lock status to report loss of lock conditions
●Clock Quality Module
–detects the quality of the crystal clock and cause interrupt request or system reset
if error is detected
–detects the quality of the PLL output clock. If an error is detected, causes a system
reset or switches the system clock to the crystal clock and causes an interrupt
request
●Programmable interrupt request or system reset on loss of lock
2.3.6 Calibration EBI
The Calibration EBI controls data transfer across the crossbar switch to/from memories or
peripherals attached to the calibration tool connector in the calibration address space. The
Calibration EBI is only available in the calibration tool. The Calibration EBI includes a
memory controller that generates interface signals to support a variety of external
memories. The Calibration EBI memory controller supports legacy flash, SRAM, and
asynchronous memories. In addition, the calibration EBI supports up to three regions via
chip selects (two chip selects are multiplexed with two address bits), along with programmed
region-specific attributes. The calibration EBI supports the following features:
●22-bit address bus (two most significant signals multiplexed with two chip selects)
●16-bit data bus
●Multiplexed mode with addresses and data signals present on the data lines
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Note:The calibration EBI must be configured in multiplexed mode when the extended Nexus trace
is used on the calibration tool. This is because Nexus signals and address lines of the
calibration bus share the same balls in the calibration package.
●Memory controller with support for various memory types:
–Asynchronous/legacy flash and SRAM
●Bus monitor
–User selectable
–Programmable timeout period (with 8 external bus clock resolution)
●Configurable wait states (via chip selects)
●3 chip-select (Cal_CS[0], Cal_CS[2:3]) signals (Multiplexed with 2 most significant
address signals)
●2 write/byte enable (WE[0:1]/BE[0:1]) signals
●Configurable bus speed modes
–system frequency
–1/2 of system frequency
–1/4 of system frequency
●Optional automatic CLKOUT gating to save power and reduce EMI
The SPC563Mxx SIU controls MCU reset configuration, pad configuration, external
interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and the system reset
operation. The reset configuration block contains the external pin boot configuration logic.
The pad configuration block controls the static electrical characteristics of I/O pins. The
GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU.
The reset controller performs reset monitoring of internal and external reset sources, and
drives the RSTOUT
via the crossbar switch. The SIU provides the following features:
●System configuration
–MCU reset configuration via external pins
–Pad configuration control for each pad
–Pad configuration control for virtual I/O via DSPI serialization
●System reset monitoring and generation
–Power-on reset support
–Reset status register provides last reset source to software
–Glitch detection on reset input
–Software controlled reset assertion
●External interrupt
–11 interrupt requests
–Rising or falling edge event detection
–Programmable digital filter for glitch rejection
–Critical Interrupt request
–Non-Maskable Interrupt request
pin. Communication between the SIU and the e200z335 CPU core is
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●GPIO
–GPIO function on 80 I/O pins
–Virtual GPIO on 64 I/O pins via DSPI serialization (requires external
deserialization device)
–Dedicated input and output registers for setting each GPIO and Virtual GPIO pin
●Internal multiplexing
–Allows serial and parallel chaining of DSPIs
–Allows flexible selection of eQADC trigger inputs
–Allows selection of interrupt requests between external pins and DSPI
2.3.8 ECSM
The error correction status module provides status information regarding platform memory
errors reported by error-correcting codes.
2.3.9 Flash
Devices in the SPC563Mxx family provide up to 1.5 MB of programmable, non-volatile, flash
memory. The non-volatile memory (NVM) can be used for instruction and/or data storage.
The flash module includes a Fetch Accelerator, that optimizes the performance of the flash
array to match the CPU architecture and provides single cycle random access to the flash
@ 80 MHz. The flash module interfaces the system bus to a dedicated flash memory array
controller. For CPU ‘loads’, DMA transfers and CPU instruction fetch, it supports a 64-bit
data bus width at the system bus port, and a 128-bit read data interface to flash memory.
The module contains a four-entry, 128-bit prefetch buffer and a prefetch controller which
prefetches sequential lines of data from the flash array into the buffer. Prefetch buffer hits
allow no-wait responses. Normal flash array accesses are registered and are forwarded to
the system bus on the following cycle, incurring three wait-states. Prefetch operations may
be automatically controlled, and are restricted to instruction fetch.
The flash memory provides the following features:
●Supports a 64-bit data bus for instruction fetch, CPU loads and DMA access. Byte,
halfword, word and doubleword reads are supported. Only aligned word and
doubleword writes are supported.
●Fetch Accelerator
–Architected to optimize the performance of the flash with the CPU to provide single
cycle random access to the flash up to 80 MHz system clock speed
–Configurable read buffering and line prefetch support
–Four line read buffers (128 bits wide) and a prefetch controller
●Hardware and software configurable read and write access protections on a per-master
basis
●Interface to the flash array controller is pipelined with a depth of one, allowing
overlapped accesses to proceed in parallel for interleaved or pipelined flash array
designs
●Configurable access timing allowing use in a wide range of system frequencies
●Multiple-mapping support and mapping-based block access timing (0-31 additional
cycles) allowing use for emulation of other memory types
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●Software programmable block program/erase restriction control
●Erase of selected block(s)
●Read page size of 128 bits (four words)
●ECC with single-bit correction, double-bit detection
●Program page size of 64 bits (two words)
●ECC single-bit error corrections are visible to software
●Minimum program size is two consecutive 32-bit words, aligned on a 0-modulo-8 byte
address, due to ECC
●Embedded hardware program and erase algorithm
●Erase suspend
●Shadow information stored in non-volatile shadow block
●Independent program/erase of the shadow block
2.3.10 SRAM
The SPC563Mxx SRAM module provides a general-purpose up to 94 KB memory block.
The SRAM controller includes these features:
●Supports read/write accesses mapped to the SRAM memory from any master
●32 KB or 24 KB block powered by separate supply for standby operation
●Byte, halfword, word and doubleword addressable
●ECC performs single-bit correction, double-bit detection on 32-bit data element
2.3.11 BAM
The BAM (Boot Assist Module) is a block of read-only memory that is programmed once by
ST and is identical for all SPC563Mxx MCUs. The BAM program is executed every time the
MCU is powered-on or reset in normal mode. The BAM supports different modes of booting.
They are:
●Booting from internal flash memory
●Serial boot loading (A program is downloaded into RAM via eSCI or the FlexCAN and
then executed)
●Booting from external memory on calibration bus
The BAM also reads the reset configuration half word (RCHW) from internal flash memory
and configures the SPC563Mxx hardware accordingly. The BAM provides the following
features:
●Sets up MMU to cover all resources and mapping all physical address to logical
addresses with minimum address translation
●Sets up the MMU to allow user boot code to execute as either Power Architecture code
(default) or as VLE code
●Detection of user boot code
●Automatic switch to serial boot mode if internal flash is blank or invalid
●Supports user programmable 64-bit password protection for serial boot mode
●Supports serial bootloading via FlexCAN bus and eSCI using fixed baudrate protocol
●Supports serial bootloading via FlexCAN bus and eSCI with auto baud rate sensing
●Supports serial bootloading of either Power Architecture code (default) or VLE code
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●Supports booting from calibration bus interface
●Supports censorship protection for internal flash memory
●Provides an option to enable the core watchdog timer
●Provides an option to disable the software watchdog timer
2.3.12 eMIOS
The eMIOS (Enhanced Modular Input Output System) module provides the functionality to
generate or measuretime events. The channels on this module provide a range of operating
modes including the capability to perform dual input capture or dual output compare as well
as PWM output.
The eMIOS provides the following features:
●16 channels (24-bit timer resolution)
●For compatibility with other family members selected channels and timebases are
implemented:
–Channels 0 to 6, 8 to 15, and 23
–Timebases A, B and C
●Channels 1, 3, 5 and 6 support modes:
–General Purpose Input/Output (GPIO)
–Single Action Input Capture (SAIC)
–Single Action Output Compare (SAOC)
●Channels 2, 4, 11 and 13 support all the modes above plus:
–Output Pulse Width Modulation Buffered (OPWMB)
●Channels 0, 8, 9, 10, 12, 14, 15, 23 support all the modes above plus:
–Input Period Measurement (IPM)
–Input Pulse Width Measurement (IPWM)
–Double Action Output Compare (set flag on both matches) (DAOC)
–Modulus Counter Buffered (MCB)
–Output Pulse Width and Frequency Modulation Buffered (OPWFMB)
●Three 24-bit wide counter buses
–Counter bus A can be driven by channel 23 or by the eTPU2 and all channels can
use it as a reference
–Counter bus B is driven by channel 0 and channels 0 to 6 can use it as a reference
–Counter bus C is driven by channel 8 and channels 8 to 15 can use it as a
reference
●Shared time bases with the eTPU2 through the counter buses
●Synchronization among internal and external time bases
2.3.13 eTPU2
The eTPU2 is an enhanced co-processor designed for timing control. Operating in parallel
with the host CPU, eTPU2 processes instructions and real-time input events, performs
output waveform generation, and accesses shared data without host intervention.
Consequently, for each timer event, the host CPU setup and service times are minimized or
eliminated. A powerful timer subsystem is formed by combining the eTPU2 with its own
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instruction and data RAM. High-level assembler/compiler and documentation allows
customers to develop their own functions on the eTPU2.
The eTPU2 includes these distinctive features:
●The Timer Counter (TCR1), channel logic and digital filters (both channel and the
external timer clock input [TCRCLK]) now have an option to run at full system clock
speed or system clock / 2.
●Channels support unordered transitions: transition 2 can now be detected before
transition 1. Related to this enhancement, the transition detection latches (TDL1 and
TDL2) can now be independently negated by microcode.
●A new User Programmable Channel Mode has been added: the blocking, enabling,
service request and capture characteristics of this channel mode can be programmed
via microcode.
●Microinstructions now provide an option to issue Interrupt and Data Transfer requests
selected by channel. They can also be requested simultaneously at the same
instruction.
●Channel Flags 0 and 1 can now be tested for branching, in addition to selecting the
entry point.
●Channel digital filters can be bypassed.
●The Timer Counter (TCR1), channel logic and digital filters (both channel and the
external timer clock input [TCRCLK]) now have an option to run at full system clock
speed or system clock / 2.
●Channels support unordered transitions: transition 2 can now be detected before
transition 1. Related to this enhancement, the transition detection latches (TDL1 and
TDL2) can now be independently negated by microcode.
●A new User Programmable Channel Mode has been added: the blocking, enabling,
service request and capture characteristics of this channel mode can be programmed
via microcode.
●Microinstructions now provide an option to issue Interrupt and Data Transfer requests
selected by channel. They can also be requested simultaneously at the same
instruction.
●Channel Flags 0 and 1 can now be tested for branching, in addition to selecting the
entry point.
●Channel digital filters can be bypassed.
●32 channels, each channel is associated with one input and one output signal
–Enhanced input digital filters on the input pins for improved noise immunity.
–Identical, orthogonal channels: each channel can perform any time function. Each
time function can be assigned to more than one channel at a given time, so each
signal can have any functionality.
–Each channel has an event mechanism which supports single and double action
functionality in various combinations. It includes two 24-bit capture registers, two
24-bit match registers, 24-bit greater-equal and equal-only comparators
–Input and output signal states visible from the host
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●2 independent 24-bit time bases for channel synchronization:
–First time base clocked by system clock with programmable prescale division from
2 to 512 (in steps of 2), or by output of second time base prescaler
–Second time base counter can work as a continuous angle counter, enabling
angle based applications to match angle instead of time
–Both time bases can be exported to the eMIOS timer module
–Both time bases visible from the host
●Event-triggered microengine:
–Fixed-length instruction execution in two-system-clock microcycle
–14 KB of code memory (SCM)
–3 KB of parameter (data) RAM (SPRAM)
–Parallel execution of data memory, ALU, channel control and flow control sub-
instructions in selected combinations
–32-bit microengine registers and 24-bit wide ALU, with 1 microcycle addition and
subtraction, absolute value, bitwise logical operations on 24-bit, 16-bit, or byte
operands, single-bit manipulation, shift operations, sign extension and conditional
execution
–Additional 24-bit Multiply/MAC/Divide unit which supports all signed/unsigned
Multiply/MAC combinations, and unsigned 24-bit divide. The MAC/Divide unit
works in parallel with the regular microcode commands
●Resource sharing features support channel use of common channel registers, memory
and microengine time:
–Hardware scheduler works as a “task management” unit, dispatching event
service routines by predefined, host-configured priority
–Automatic channel context switch when a “task switch” occurs, i.e., one function
thread ends and another begins to service a request from other channel: channelspecific registers, flags and parameter base address are automatically loaded for
the next serviced channel
–SPRAM shared between host CPU and eTPU2, supporting communication either
between channels and host or inter-channel
–Dual-parameter coherency hardware support allows atomic access to two
parameters by host
●Test and development support features:
–Nexus Class 1 debug, supporting single-step execution, arbitrary microinstruction
execution, hardware breakpoints and watchpoints on several conditions
–Software breakpoints
–SCM continuous signature-check built-in self test (MISC — multiple input
signature calculator), runs concurrently with eTPU2 normal operation
●System enhancements
–Software watchdog with programmable timeout
–Real-time performance information
●Channel enhancements
–Channels 1 and 2 can optionally drive angle clock hardware
●Programming enhancements
–Engine relative addressing mode
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2.3.14 eQADC
The enhanced queued analog to digital converter (eQADC) block provides accurate and fast
conversions for a wide range of applications. The eQADC provides a parallel interface to two
on-chip analog to digital converters (ADC), and a single master to single slave serial
interface to an off-chip external device. Both on-chip ADCs have access to all the analog
channels.
The eQADC prioritizes and transfers commands from six command conversion command
‘queues’ to the on-chip ADCs or to the external device. The block can also receive data from
the on-chip ADCs or from an off-chip external device into the six result queues, in parallel,
independently of the command queues. The six command queues are prioritized with
Queue_0 having the highest priority and Queue_5 the lowest. Queue_0 also has the added
ability to bypass all buffering and queuing and abort a currently running conversion on either
ADC and start a Queue_0 conversion. This means that Queue_0 will always have a
deterministic time from trigger to start of conversion, irrespective of what tasks the ADCs
were performing when the trigger occurred. The eQADC supports software and external
hardware triggers from other blocks to initiate transfers of commands from the queues to the
on-chip ADCs or to the external device. It also monitors the fullness of command queues
and result queues, and accordingly generates DMA or interrupt requests to control data
movement between the queues and the system memory, which is external to the eQADC.
The ADCs also support features designed to allow the direct connection of high impedance
acoustic sensors that might be used in a system for detecting engine knock. These features
include differential inputs; integrated variable gain amplifiers for increasing the dynamic
range; programmable pull-up and pull-down resistors for biasing and sensor diagnostics.
The eQADC also integrates a programmable decimation filter capable of taking in ADC
conversion results at a high rate, passing them through a hardware low pass filter, then
down-sampling the output of the filter and feeding the lower sample rate results to the result
FIFOs. This allows the ADCs to sample the sensor at a rate high enough to avoid aliasing of
out-of-band noise; while providing a reduced sample rate output to minimize the amount
DSP processing bandwidth required to fully process the digitized waveform.
–Pre-fill mode to pre-condition the filter before the sample window opens
●Full duplex synchronous serial interface to an external device
–Free-running clock for use by an external device
–Supports a 26-bit message length
●Priority based Queues
–Supports six Queues with fixed priority. When commands of distinct Queues are
bound for the same ADC, the higher priority Queue is always served first
–Queue_0 can bypass all prioritization, buffering and abort current conversions to
start a Queue_0 conversion a deterministic time after the queue trigger
–Streaming mode operation of Queue_0 to execute some commands several times
–Supports software and hardware trigger modes to arm a particular Queue
–Generates interrupt when command coherency is not achieved
●External hardware triggers
–Supports rising edge, falling edge, high level and low level triggers
–Supports configurable digital filter
●Supports four external 8-to-1 muxes which can expand the input channels to 56
channels total
2.3.15 DSPI
The deserial serial peripheral interface (DSPI) block provides a synchronous serial interface
for communication between the SPC563Mxx MCU and external devices. The DSPI supports
d. 176-pin and 208-pin packages have 34 input channels; 144-pin package has 32; 100-pin package has 23.
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pin count reduction through serialization and deserialization of eTPU and eMIOS channels
and memory-mapped registers. The channels and register content are transmitted using a
SPI-like protocol. This SPI-like protocol is completely configurable for baud rate, polarity and
phase, frame length, chip select assertion, etc. Each bit in the frame may be configured to
serialize either eTPU channels, eMIOS channels or GPIO signals. The DSPI can be
configured to serialize data to an external device that supports the Microsecond Channel
protocol. There are two identical DSPI blocks on the SPC563Mxx MCU. The DSPI output
pins support 5 V logic levels or Low Voltage Differential Signalling (LVDS) according to the
Microsecond Channel specification.
The DSPIs have three configurations:
●Serial peripheral interface (SPI) configuration where the DSPI operates as an up to 16-
bit SPI with support for queues
●Enhanced deserial serial interface (DSI) configuration where DSPI serializes up to 32
bits with three possible sources per bit
–eTPU, eMIOS, new virtual GPIO registers as possible bit source
–Programmable inter-frame gap in continuous mode
–Bit source selection allows microsecond channel downstream with command or
data frames up to 32 bits
–Microsecond channel dual receiver mode
●Combined serial interface (CSI) configuration where the DSPI operates in both SPI and
DSI configurations interleaving DSI frames with SPI frames, giving priority to SPI
frames
For queued operations, the SPI queues reside in system memory external to the DSPI. Data
transfers between the memory and the DSPI FIFOs are accomplished through the use of
the eDMA controller or through host software.
The DSPI supports these SPI features:
●Full-duplex, synchronous transfers
●Selectable LVDS Pads working at 40 MHz for SOUT and SCK pins
●Master and Slave Mode
●Buffered transmit operation using the TX FIFO with parameterized depth of 4 entries
●Buffered receive operation using the RX FIFO with parameterized depth of 4 entries
●TX and RX FIFOs can be disabled individually for low-latency updates to SPI queues
●Visibility into the TX and RX FIFOs for ease of debugging
●FIFO Bypass Mode for low-latency updates to SPI queues
●Programmable transfer attributes on a per-frame basis:
–Parameterized number of transfer attribute registers (from two to eight)
–Serial clock with programmable polarity and phase
–Various programmable delays:
PCS to SCK delay
SCK to PCS delay
Delay between frames
–Programmable serial frame size of 4 to 16 bits, expandable with software control
–Continuously held chip select capability
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●6 Peripheral Chip Selects, expandable to 64 with external demultiplexer
●Deglitching support for up to 32 Peripheral Chip Selects with external demultiplexer
●DMA support for adding entries to TX FIFO and removing entries from RX FIFO:
–TX FIFO is not full (TFFF)
–RX FIFO is not empty (RFDF)
●6 Interrupt conditions:
–End of queue reached (EOQF)
–TX FIFO is not full (TFFF)
–Transfer of current frame complete (TCF)
–Attempt to transmit with an empty Transmit FIFO (TFUF)
–RX FIFO is not empty (RFDF)
–FIFO Underrun (slave only and SPI mode, the slave is asked to transfer data when
the TxFIFO is empty)
–FIFO Overrun (serial frame received while RX FIFO is full)
●Modified transfer formats for communication with slower peripheral devices
●Continuous Serial Communications Clock (SCK)
●Power savings via support for Stop Mode
●Enhanced DSI logic to implement a 32-bit Timed Serial Bus (TSB) configuration,
supporting the Microsecond Channel downstream frame format
The DSPIs also support these features unique to the DSI and CSI configurations:
●2 sources of the serialized data:
–eTPU_A and eMIOS output channels
–Memory-mapped register in the DSPI
●Destinations for the deserialized data:
–eTPU_A and eMIOS input channels
–SIU External Interrupt Request inputs
–Memory-mapped register in the DSPI
●Deserialized data is provided as Parallel Output signals and as bits in a memory-
mapped register
●Transfer initiation conditions:
–Continuous
–Edge sensitive hardware trigger
–Change in data
●Pin serialization/deserialization with interleaved SPI frames for control and diagnostics
●Continuous serial communications clock
●Support for parallel and serial chaining of up to four DSPI blocks
2.3.16 eSCI
The enhanced serial communications interface (eSCI) allows asynchronous serial
communications with peripheral devices and other MCUs. It includes special support to
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interface to Local Interconnect Network (LIN) slave devices. The eSCI block provides the
following features:
●Full-duplex operation
●Standard mark/space non-return-to-zero (NRZ) format
●13-bit baud rate selection
●Programmable 8-bit or 9-bit, data format
●Programmable 12-bit or 13-bit data format for Timed Serial Bus (TSB) configuration to
support the Microsecond Channel upstream
●Automatic parity generation
●LIN support
–Autonomous transmission of entire frames
–Configurable to support all revisions of the LIN standard
–Automatic parity bit generation
–Double stop bit after bit error
–10- or 13-bit break support
●Separately enabled transmitter and receiver
●Programmable transmitter output parity
●2 receiver wake up methods:
–Idle line wake-up
–Address mark wake-up
●Interrupt-driven operation with flags
●Receiver framing error detection
●Hardware parity checking
●1/16 bit-time noise detection
●DMA support for both transmit and receive data
–Global error bit stored with receive data in system RAM to allow post processing of
errors
2.3.17 FlexCAN
The SPC563Mxx MCU contains two controller area network (FlexCAN) blocks. The
FlexCAN module is a communication controller implementing the CAN protocol according to
Bosch Specification version 2.0B. The CAN protocol was designed to be used primarily as a
vehicle serial data bus, meeting the specific requirements of this field: real-time processing,
reliable operation in the EMI environment of a vehicle, cost-effectiveness and required
bandwidth. FlexCAN module ‘A’ contains 64 message buffers (MB); FlexCAN module ‘C’
contains 32 message buffers.
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The FlexCAN module provides the following features:
●Full Implementation of the CAN protocol specification, Version 2.0B
–Standard data and remote frames
–Extended data and remote frames
–Zero to eight bytes data length
–Programmable bit rate up to 1 Mbit/s
●Content-related addressing
●64 / 32 message buffers of zero to eight bytes data length
●Individual Rx Mask Register per message buffer
●Each message buffer configurable as Rx or Tx, all supporting standard and extended
messages
●Includes 1056 / 544 bytes of embedded memory for message buffer storage
●Includes a 256-byte and a 128-byte memories for storing individual Rx mask registers
●Full featured Rx FIFO with storage capacity for six frames and internal pointer handling
●Powerful Rx FIFO ID filtering, capable of matching incoming IDs against 8 extended, 16
standard or 32 partial (8 bits) IDs, with individual masking capability
●Selectable backwards compatibility with previous FlexCAN versions
●Programmable clock source to the CAN Protocol Interface, either system clock or
●Programmable transmit-first scheme: lowest ID, lowest buffer number or highest priority
●Time Stamp based on 16-bit free-running timer
●Global network time, synchronized by a specific message
●Maskable interrupts
●Warning interrupts when the Rx and Tx Error Counters reach 96
●Independent of the transmission medium (an external transceiver is assumed)
●Multi master concept
●High immunity to EMI
●Short latency time due to an arbitration scheme for high-priority messages
●Low power mode, with programmable wake-up on bus activity
2.3.18 System timers
The system timers provide two distinct types of system timer:
●Periodic interrupts/triggers using the Periodic Interrupt Timer (PIT)
●Operating system task monitors using the System Timer Module (STM)
Periodic Interrupt Timer (PIT)
The PIT provides five independent timer channels, capable of producing periodic interrupts
and periodic triggers. The PIT has no external input or output pins and is intended to be
used to provide system ‘tick’ signals to the operating system, as well as periodic triggers for
eQADC queues. Of the five channels in the PIT, four are clocked by the system clock, one is
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clocked by the crystal clock. This one channel is also referred to as Real Time Interrupt
(RTI) and is used to wakeup the device from low power stop mode.
The following features are implemented in the PIT:
●5 independent timer channels
●Each channel includes 32-bit wide down counter with automatic reload
●4 channels clocked from system clock
●1 channel clocked from crystal clock (wake-up timer)
●Wake-up timer remains active when System STOP mode is entered. Used to restart
system clock after predefined timeout period
●Each channel can optionally generate an interrupt request or a trigger event (to trigger
eQADC queues) when the timer reaches zero
System Timer Module (STM)
The System Timer Module (STM) is designed to implement the software task monitor as
defined by AUTOSAR (see http://www.autosar.org). It consists of a single 32-bit counter,
clocked by the system clock, and four independent timer comparators. These comparators
produce a CPU interrupt when the timer exceeds the programmed value.
The following features are implemented in the STM:
●One 32-bit up counter with 8-bit prescaler
●Four 32-bit compare channels
●Independent interrupt source for each channel
●Counter can be stopped in debug mode
2.3.19 Software Watchdog Timer (SWT)
The Software Watchdog Timer (SWT) is a second watchdog module to complement the
standard Power Architecture watchdog integrated in the CPU core. The SWT is a 32-bit
modulus counter, clocked by the system clock or the crystal clock, that can provide a system
reset or interrupt request when the correct software key is not written within the required
time window.
The following features are implemented:
●32-bit modulus counter
●Clocked by system clock or crystal clock
●Optional programmable watchdog window mode
●Can optionally cause system reset or interrupt request on timeout
●Reset by writing a software key to memory mapped register
●Enabled out of reset
●Configuration is protected by a software key or a write-once register
2.3.20 Debug features
Nexus port controller
The NPC (Nexus Port Controller) block provides real-time development support capabilities
for the SPC563Mxx Power Architecture-based MCU in compliance with the IEEE-ISTO
5001-2003 standard. This development support is supplied for MCUs without requiring
Doc ID 14642 Rev 937/142
OverviewSPC563M64L5, SPC563M64L7
external address and data pins for internal visibility. The NPC block is an integration of
several individual Nexus blocks that are selected to provide the development support
interface for SPC563Mxx. The NPC block interfaces to the host processor (e200z335),
eTPU, and internal buses to provide development support as per the IEEE-ISTO 5001-2003
standard. The development support provided includes program trace and run-time access to
the MCUs internal memory map and access to the Power Architecture and eTPU internal
registers during halt. The Nexus interface also supports a JTAG only mode using only the
JTAG pins. SPC563Mxx in the production LQFP144 supports a 3.3 V reduced (4-bit wide)
Auxiliary port. These Nexus port pins can also be used as 5 V I/O signals to increase usable
I/O count of the device. When using this Nexus port as IO, Nexus trace is still possible using
calibration tool calibration. In the calibration tool calibration package, the full 12-bit Auxiliary
port is available.
Note:In the calibration tool package, the full Nexus Auxiliary port shares balls with the addresses
of the calibration bus. Therefore multiplexed address/data bus mode must be used for the
calibration bus when using full width Nexus trace in calibration tool assembly.
The following features are implemented:
●5-pin JTAG port (JCOMP, TDI, TDO, TMS, and TCK)
–Always available in production package
–Supports both JTAG Boundary Scan and debug modes
–3.3V interface
–Supports Nexus class 1 features
–Supports Nexus class 3 read/write feature
●9-pin Reduced Port interface in LQFP144 production package
–Alternate function as IO
–5 V (in GPIO or alternate function mode), 3.3 V (in Nexus mode) interface
–Auxiliary Output port
1 MCKO (message clock out) pin
4 MDO (message data out) pins
2 MSEO
1 EVTO
(message start/end out) pins
(event out) pin
–Auxiliary input port
1 EVTI
●17-pin Full Port interface in calibration package used on calibration tool boards
(event in) pin
–3.3V interface
–Auxiliary Output port
1 MCKO (message clock out) pin
4 (reduced port mode) or 12 (full port mode) MDO (message data out) pins; 8
extra full port pins shared with calibration bus
2 MSEO
1 EVTO
(message start/end out) pins
(event out) pin
–Auxiliary input port
1 EVTI
(event in) pin
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SPC563M64L5, SPC563M64L7Overview
●Host processor (e200) development support features
–IEEE-ISTO 5001-2003 standard class 2 compliant
–Program trace via branch trace messaging (BTM). Branch trace messaging
displays program flow discontinuities (direct branches, indirect branches,
exceptions, etc.), allowing the development tool to interpolate what transpires
between the discontinuities. Thus, static code may be traced.
–Watchpoint trigger enable of program trace messaging
–Data Value Breakpoints (JTAG feature of the e200z335 core): allows CPU to be
halted when the CPU writes a specific value to a memory location
4 data value breakpoints
CPU only
Detects ‘equal’ and ‘not equal’
Byte, half word, word (naturally aligned)
Note:This feature is imprecise due to CPU pipelining.
–Subset of Power Architecture software debug facilities with OnCE block (Nexus
class 1 features)
●eTPU development support features
–IEEE-ISTO 5001-2003 standard class 1 compliant for the eTPU
–Nexus based breakpoint configuration and single step support (JTAG feature of
the eTPU)
●Run-time access to the on-chip memory map via the Nexus read/write access protocol.
This feature supports accesses for run-time internal visibility, calibration variable
acquisition, calibration constant tuning, and external rapid prototyping for powertrain
automotive development systems.
●All features are independently configurable and controllable via the IEEE 1149.1 I/O
port
●Power-on-reset status indication during reset via MDO[0] in disabled and reset modes
JTAG
The JTAGC (JTAG Controller) block provides the means to test chip functionality and
connectivity while remaining transparent to system logic when not in test mode. Testing is
performed via a boundary scan technique, as defined in the IEEE 1149.1-2001 standard. All
data input to and output from the JTAGC block is communicated in serial format. The JTAGC
block is compliant with the IEEE 1149.1-2001 standard and supports the following features:
●IEEE 1149.1-2001 Test Access Port (TAP) interface 4 pins (TDI, TMS, TCK, and TDO)
●A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined
(see signal details, pin 21)
(see signal details, pin 22)
(see signal details, pin 23)
(see signal details, pin 24)
(see signal details, pin 25)
(see signal details, pin 26)
(see signal details, pin 27)
(see signal details, pin 28)
(see signal details, pin 21)
(see signal details, pin 22)
(see signal details, pin 23)
(see signal details, pin 24)
(see signal details, pin 25)
(see signal details, pin 26)
(see signal details, pin 27)
(see signal details, pin 28)
2. Pins marked “NC” are not functional pins but may be connected to internal circuitry. Connections to external circuits or other
pins on this device can result in unpredictable system behavior or damage.
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48/142Doc ID 14642 Rev 9
3.5 LBGA208 ballmap (SPC563M64)
Figure 6 shows the 208-pin LBGA ballmap for the SPC563M64 (1536 KB flash memory) as viewed from above.
Figure 6.208-pin LBGA ballmap (SPC563M64; top view)
12345678910111213141516
Pinout and signal descriptionSPC563M64L5, SPC563M64L7
1. For each pin in the table, each line in the Function column is a separate function of the pin. For all I/O pins the selection of primary pin function or secondary function or
GPIO is done in the SIU except where explicitly noted.
Pin No.
LQFP
176
33, 62,
103,
149
15, 29,
43, 57,
72, 90,
96,
108,
115
127,
133,
140
31, 41
55
95,
110,
74
125,
138
16,
119
C2, D3, E4,
H7, H8, H9,
H10, J7, J8,
7
J9, J10, K7,
,
(7)
Pinout and signal descriptionSPC563M64L5, SPC563M64L7
LBGA208
B1, B16,
N5, P4,
P13, R3,
R14, T2,
T15
A1, A16,
B2, B15,
C3, C14,
D4, D13,
G7, G8,
G9, G10,
K8, K9,
K10, N4,
N13, P3,
P14, R2,
R15, T1,
T16
K4
—
D12
E13, P6
2. Values in this column refer to registers in the System Integration Unit (SIU). The actual register name is “SIU_PCR” suffixed by the PCR number. For example, PCR[190]
refers to the SIU register named SIU_PCR190.
3. The Pad Configuration Register (PCR) PA field is used by software to select pin function.
4. The VDDE and VDDEH supply inputs are broken into segments. Each segment of slow I/O pins (VDDEH) may have a separate supply in the 3.3 V to 5.0 V range (–
10%/+5%). Each segment of fast I/O (VDDE) may have a separate supply in the 1.8 V to 3.3 V range (+/– 10%).
5. Terminology is O — output, I — input, Up — weak pull up enabled, Down — weak pull down enabled, Low — output driven low, High — output driven high. A dash for the
function in this column denotes that both the input and output buffer are turned off.
6. Function after reset of GPI is general purpose input. A dash for the function in this column denotes that both the input and output buffer are turned off.
7. Not available on 1 MB version of 176-pin package.
8. The GPIO functions on GPIO[206] and GPIO[207] can be selected as trigger functions in the SIU for the ADC by making the proper selections in the SIU_ETISR and
SIU_ISEL3 registers in the SIU.
9. Some signals in this section are available only on calibration package.
10. These pins are only available in the 496 CSP/MAPBGA calibration/development package.
11. On the calibration package, the Nexus function on this pin is enabled when the NEXUSCFG pin is high and Nexus is configured to full port mode. On the 176-pin and 208pin packages, the Nexus function on this pin is enabled permanently. Do not connect the Nexus MDO or MSEO pins directly to a power supply or ground.
12. In the calibration package, the I/O segment containing this pin is called VDDE12.
Doc ID 14642 Rev 965/142
13. 208-ball BGA package only
14. When configured as Nexus (208-pin package or calibration package with NEXUSCFG=1), and JCOMP is asserted during reset, MDO[0] is driven high until the crystal
oscillator becomes stable, at which time it is then negated.
15. The function of this pin is Nexus when NEXUSCFG is high.
16. High when the pin is configured to Nexus, low otherwise.
17. O/Low for the calibration with NEXUSCFG=0; I/Up otherwise.
18. ALT_ADDR/Low for the calibration package with NEXUSCFG=0; EVTI
19. In 176-pin and 208-pin packages, the Nexus function is disabled and the pin/ball has the secondary function
20. This signal is not available in the 176-pin and 208-pin packages.
21. The primary function is not selected via the PA field when the pin is a Nexus signal. Instead, it is activated by the Nexus controller.
22. TDI and TDO are required for JTAG operation.
23. The primary function is not selected via the PA field when the pin is a JTAG signal. Instead, it is activated by the JTAG controller.
24. The function and state of the CAN_A and eSCI_A pins after execution of the BAM program is determined by the BOOTCFG1 pin.
25. Connect an external 10K pull-up resistor to the SCI_A_RX pin to ensure that the pin is driven high during CAN serial boot.
26. For pins AN[0:7], during and just after POR negates, internal pull resistors can be enabled, resulting in as much as 4 mA of current draw. The pull resistors are disabled
when the system clock propagates through the device.
27. ETPUA[24:29] are input and output. The input muxing is controlled by SIU_ISEL8 register.
28. eTPU_A[25] is an output only function.
29. Only the output channels of eTPU[8:9] are connected to pins.
30. The function after reset of the XTAL pin is determined by the value of the signal on the PLLCFG[1] pin. When bypass mode is chosen XTAL has no function and should be
grounded.
/Up otherwise.
SPC563M64L5, SPC563M64L7Pinout and signal description
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31. The function after reset of the EXTAL_EXTCLK pin is determined by the value of the signal on the PLLCFG[1] pin. If the EXTCLK function is chosen, the valid operating
voltage for the pin is 1.62 V to 3.6 V. If the EXTAL function is chosen, the valid operating voltage is 3.3 V.
32. VSSPLL and VSSREG are connected to the same pin.
33. This pin is shared by two pads: VDDA_AN, using pad_vdde_hv, and VDDA_DIG, using pad_vdde_int_hv.
34. This pin is shared by two pads: VSSA_AN, using pad_vsse_hv, and VSSA_DIG, using pad_vsse_int_hv.
35. VDDEH1A, VDDEH1B, and VDDEH1AB are shorted together in all production packages. The separation of the signal names is present to support legacy naming, however
they should be considered as the same signal in this document.
36. LVDS pins will not work at 3.3 V.
37. The VDDEH6 segment may be powered from 3.0 V to 5.0 V for mux address or SSI functions, but must meet the VDDA specifications of 4.5 V to 5.25 V for analog input
function.
38. VDDEH6A and VDDEH6B are shorted together in all production packages. The separation of the signal names is present to support legacy naming, however they should
be considered as the same signal in this document.
39. If using JTAG or Nexus, the I/O segment that contains the JTAG and Nexus pins must be powered by a 5 V supply. The 3.3 V Nexus/JTAG signals are derived from the 5
volt power supply.
40. In the calibration package this signal is named VDDE12.
Pinout and signal descriptionSPC563M64L5, SPC563M64L7
SPC563M64L5, SPC563M64L7Pinout and signal description
Table 5.Pad types
Pad TypeNameSupply Voltage
Slowpad_ssr_hv3.0 V – 5.25 V
Mediumpad_msr_hv3.0 V – 5.25 V
Fastpad_fc3.0 V – 3.6 V
MultiVpad_multv_hv
3.0 V – 5.25 V (high swing mode)
4.5 V – 5.25 V (low swing mode)
Analogpad_ae_hv0.0 – 5.25 V
LVDSpad_lo_lv —
3.7 Signal details
Ta bl e 6 contains details on the multiplexed signals that appear in Tab l e 4 .
Table 6.Signal details
SignalModule or FunctionDescription
CLKOUTClock Generation
EXTALClock Generation
SPC563Mxx clock output for the external/calibration bus
interface
Input pin for an external crystal oscillator or an external clock
source based on the value driven on the PLLREF pin at reset.
EXTCLKClock GenerationExternal clock input
PLLREF is used to select whether the oscillator operates in xtal
PLLREFClock Generation
mode or external reference mode from reset. PLLREF=0
selects external reference mode.
XTALClock GenerationCrystal oscillator input
SCK_B_LVDS–
SCK_B_LVDS+
SOUT_B_LVDS–
SOUT_B_LVDS+
SCK_C_LVDS–
SCK_C_LVDS+
SOUT_C_LVDS–
SOUT_C_LVDS+
PCS_B[0]
PCS_C[0]
PCS_B[1:5]
PCS_C[1:5]
SCK_B
SCK_C
SIN_B
SIN_C
DSPILVDS pair used for DSPI_B TSB mode transmission
DSPILVDS pair used for DSPI_B TSB mode transmission
DSPILVDS pair used for DSPI_C TSB mode transmission
DSPI LVDS pair used for DSPI_C TSB mode transmission
DSPI_B – DSPI_C
DSPI_B – DSPI_C
DSPI_B – DSPI_C
Peripheral chip select when device is in master mode—slave
select when used in slave mode
Peripheral chip select when device is in master mode—not
used in slave mode
DSPI clock—output when device is in master mode; input when
in slave mode
DSPI_B – DSPI_CDSPI data in
Doc ID 14642 Rev 967/142
Pinout and signal descriptionSPC563M64L5, SPC563M64L7
Table 6.Signal details (continued)
SignalModule or FunctionDescription
SOUT_B
SOUT_C
CAL_ADDR[12:30]Calibration Bus
CAL_CS
CAL_DATA[0:15]Calibration Bus
CAL_OE
CAL_RD_WR
CAL_TS_ALECalibration Bus
CAL_EVTOCalibration BusNexus Event Out
CAL_MCKOCalibration BusNexus Message Clock Out
NEXUSCFGNexus/Calibration Bus Nexus/Calibration Bus selector
eMIOS[0:23]eMIOSeMIOS I/O channels
[0:3]Calibration Bus
DSPI_B – DSPI_CDSPI data out
The CAL_ADDR[12:30] signals specify the physical address of
the bus transaction.
CSx is asserted by the master to indicate that this transaction
is targeted for a particular memory bank on the Primary
external bus.
The CAL_DATA[0:15] signals contain the data to be transferred
for the current transaction.
is used to indicate when an external memory is permitted to
OE
Calibration Bus
Calibration Bus
drive back read data. External memories must have their data
output buffers off when OE is negated. OE is only asserted for
chip-select accesses.
RD_WR
access or a write access.
The Transfer Start signal (TS
to indicate the start of a transfer.
The Address Latch Enable (ALE) signal is used to demultiplex
the address from the data bus.
indicates whether the current transaction is a read
) is asserted by the SPC563Mxx
AN[0:39]eQADCSingle-ended analog inputs for analog-to-digital converter
FCKeQADCeQADC free running clock for eQADC SSI.
MA[0:2]eQADC
REFBYPCeQADCBypass capacitor input
SDIeQADCSerial data in
SDOeQADCSerial data out
SDSeQADCSerial data select
VRHeQADCVoltage reference high input
VRLeQADCVoltage reference low input
SCI_A_RX
SCI_B_RX
SCI_A_TX
SCI_B_TX
ETPU_A[0:31]eTPUeTPU I/O channel
68/142Doc ID 14642 Rev 9
eSCI_A – eSCI_BeSCI receive
eSCI_A – eSCI_BeSCI transmit
These three control bits are output to enable the selection for
an external Analog Mux for expansion channels.
SPC563M64L5, SPC563M64L7Pinout and signal description
Table 6.Signal details (continued)
SignalModule or FunctionDescription
CAN_A_TX
CAN_C_TX
CAN_A_RX
CAN_C_RX
JCOMPJTAGEnables the JTAG TAP controller.
TCKJTAGClock input for the on-chip test and debug logic.
TDIJTAG
TDOJTAGSerial test data output for the on-chip test logic.
TMSJTAG
EVTI
EVTO
MCKONexus
MDO[3:0]Nexus
[1:0]Nexus
MSEO
FlexCan_A –
FlexCAN_C
FlexCAN_A –
FlexCAN_C
Nexus
Nexus
FlexCAN transmit
FlexCAN receive
Serial test instruction and data input for the on-chip test and
debug logic.
Controls test mode operations for the on-chip test and debug
logic.
is an input that is read on the negation of RESET to
EVTI
enable or disable the Nexus Debug port. After reset, the EVTI
pin is used to initiate program synchronization messages or
generate a breakpoint.
Output that provides timing to a development tool for a single
watchpoint or breakpoint occurrence.
MCKO is a free running clock output to the development tools
which is used for timing of the MDO and MSEO
Trace message output to development tools. This pin also
indicates the status of the crystal oscillator clock following a
power-on reset, when MDO[0] is driven high until the crystal
oscillator clock achieves stability and is then negated.
Output pin—Indicates the start or end of the variable length
message on the MDO pins
signals.
BOOTCFG[1]SIU – Configuration
The BOOTCFG1 pin is sampled during the assertion of the
RSTOUT signal, and the value is used to update the RSR and
the BAM boot mode
The following values are for BOOTCFG[0:1}:
0 Boot from internal flash memory
1 FlexCAN/eSCI boot
Doc ID 14642 Rev 969/142
Pinout and signal descriptionSPC563M64L5, SPC563M64L7
Table 6.Signal details (continued)
SignalModule or FunctionDescription
The WKPCFG pin is applied at the assertion of the internal
reset signal (assertion of RSTOUT
cycles before the negation of the RSTOUT pin.
The value is used to configure whether the eTPU and eMIOS
pins are connected to internal weak pull up or weak pull down
WKPCFGSIU – Configuration
devices after reset. The value latched on the WKPCFG pin at
reset is stored in the Reset Status Register (RSR), and is
updated for all reset sources except the Debug Port Reset and
Software External Reset.
0:Weak pulldown applied to eTPU and eMIOS pins at reset
1:Weak pullup applied to eTPU and eMIOS pins at reset.
ETRIG[2:3]SIU – eQADC Triggers External signal eTRIGx triggers eQADC CFIFOx
), and is sampled 4 clock
IRQ[0:15]
NMI
SIU – External
Interrupts
SIU – External
Interrupts
GPIO[n]SIU – GPIO
RESET
RSTOUT
SIU – Reset
SIU – Reset
The IRQ[0:15] pins connect to the SIU IRQ inputs. IMUX Select
Register 1 is used to select the IRQ[0:15] pins as inputs to the
IRQs.
Non-Maskable Interrupt
Configurable general purpose I/O pins. Each GPIO input and
output is separately controlled by an 8-bit input (GPDI) or
output (GPDO) register. Additionally, each GPIO pins is
configured using a dedicated SIU_PCR register.
The GPIO pins are generally multiplexed with other I/O pin
functions.
The RESET
pin is an active low input. The RESET pin is
asserted by an external device during a power-on or external
reset. The internal reset signal asserts only if the RESET pin
asserts for 10 clock cycles. Assertion of the RESET
pin while
the device is in reset causes the reset cycle to start over.
The RESET
pin has a glitch detector which detects spikes
greater than two clock cycles in duration that fall below the
switch point of the input buffer logic of the VDDEH input pins.
The switch point lies between the maximum VIL and minimum
VIH specifications for the VDDEH input pins.
The RSTOUT
pin is an active low output that uses a push/pull
configuration. The RSTOUT pin is driven to the low state by the
MCU for all internal and external reset sources. There is a
delay between initiation of the reset and the assertion of the
RSTOUT pin.
Ta bl e 7 gives the power/ground segmentation of the SPC563Mx MCU. Each segment
provides the power and ground for the given set of I/O pins, and can be powered by any of
the allowed voltages regardless of the power on the other segments.
70/142Doc ID 14642 Rev 9
SPC563M64L5, SPC563M64L7Pinout and signal description
.
Table 7.SPC563Mx Power/Ground Segmentation
Power
Segment
100-LQFP
Pin
Number
144-LQFP
Pin
Number
176-LQFP
Pin
Number
208-BGA
Pin
Number
Voltage
Range
VDDA0366B115.0 V
VDDE5———T13
VDDEH1
(a,b)
VDDEH6
(a,b)
20, 2324, 3431, 41K4
56, 6678, 9395, 110F13
1.8 V –
3.3 V
3.3 V –
5.0 V
3.3 V –
5.0 V
I/O Pins Powered
(1)
by Segment
AN[0:7], AN[9], AN[11],
AN[16:18], AN[21:25],
AN[27:28], AN[30:37],
AN38, AN39, VRL,
REFBYPC,
CLKOUT
PCKCFG[2],
eTPU_A[0:31],
eMIOS[0:2]
RESET
WKPCFG, BOOTCFG1,
PLLREF, SCK_B,
PCKCFG[0],
CAN_A_TX, CAN_A_RX,
CAN_C_TX, CAN_C_RX,
SCI_A_TX, SCI_A_RX,
SCI_B_TX, SCI_B_RX,
SCK_B, SIN_B, SOUT_B,
DSPI_B_PCS_B[0:5],
eMIOS[4],
eMIOS[8:15], eMIOS[23],
XTAL, EXTAL
VRH
, RSTOUT,
PCKCFG[1],
VDDEH7
(2)
71, 76 102, 113125, 138D12
3.3 V –
5.0 V
MDO[0:3], EVTI
MCKO, MSEO
TDI, TMS, TCK, JCOMP,
AN[12:15]
, EVTO,
[0:1], TDO,
(GPIO[98:99],
GPIO[206:207])
CAL_ADDR[12:30],
CAL_DATA[0:15],
VDDE12
(3)
VDDE7
——16, 119E13, P6
1.8 V –
3.3 V
CAL_CS
CAL_CS[2:3],
CAL_RD_WR,
CAL_WE
[0],
[0:1], CAL_OE,
CAL_TS, ALT_MCKO,
ALT_EVTO, NEXUSCFG
1. These are nominal voltages. All VDDE and VDDEH voltages are –5%, +10% (VDDE 1.62 V to 3.6 V,
VDDEH 3.0 V to 5.5 V). VDDA is +5%, –10%.
2. The VDDEH7 segment may be powered from 3.0 V to 5.0 V for mux address or SSI functions, but must
meet the VDDA specifications of 4.5 V to 5.25 V for analog input function.
3. In the calibration package this signal is named VDDE12; it is named VDDE7 in all other packages.
This section contains detailed information on power considerations, DC/AC electrical
characteristics, and AC timing specifications for the SPC563Mxx series of MCUs.In the
tables where the device logic provides signals with their respective timing characteristics,
the symbol “CC” for Controller Characteristics is included in the Symbol column.
In the tables where the external system must provide signals with their respective timing
characteristics to the device, the symbol “SR” for System Requirement is included in the
Symbol column.
4.1 Parameter classification
The electrical parameters shown in this document are guaranteed by various methods. To
provide a better understanding, the classifications listed in Tab le 8 are used and the
parameters are tagged accordingly in the tables. Note that only controller characteristics
(“CC”) are classified. System requirements (“SR”) are operating conditions that must be
provided to ensure normal device operation.
Table 8.Parameter classifications
Classification tagTag description
PThose parameters are guaranteed during production testing on each individual device.
C
T
DThose parameters are derived mainly from simulations.
Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical
column are within this category.
Note:The classification is shown in the column labeled “C” in the parameter tables where
1. Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings
only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device
reliability or cause permanent damage to the device.
2. Allowed 2 V for 10 hours cumulative time, remaining time at 1.2 V +10%.
3. The V
4. Allowed 6.8 V for 10 hours cumulative time, remaining time at 5 V +10%.
5. The pin named as V
6. All functional non-supply I/O pins are clamped to V
7. AC signal overshoot and undershoot of up to 2.0 V of the input voltages is permitted for an accumulative duration of 60
8. Internal structures hold the voltage greater than –1.0 V if the injection current limit of 2 mA is met.
FLASH
apply when the internal regulator is disabled and V
hours over the complete lifetime of the device (injection current not limited for this duration).
9. Internal structures hold the input voltage less than the maximum voltage on all pads powered by V
maximum injection current specification is met (2 mA for all pins) and V
10. Internal structures hold the input voltage less than the maximum voltage on all pads powered by V
maximum injection current specification is met (2 mA for all pins) and V
11. Total injection current for all pins (including both digital and analog) must not exceed 25 mA.
12. Total injection current for all analog input pins must not exceed 15 mA.
13. Lifetime operation at these specification limits is not guaranteed.
14. Solder profile per CDF-AEC-Q100.
15. Moisture sensitivity per JEDEC test method A112.
is within the operating voltage specifications.
DDEH
is within the operating voltage specifications.
DDE
supplies, if the
DDEH
supplies, if the
DDE
4.3 Thermal characteristics
Table 10.Thermal characteristics for 100-pin LQFP
SymbolCParameterConditionsValueUnit
R
θJA
R
θJA
R
θJMA
R
θJMA
R
θJB
R
θJCtop
Ψ
JT
1. Thermal characteristics are targets based on simulation that are subject to change per device characterization.
2. Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package.
3. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification
for the specified package.
4. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
5. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JT.
1. Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package.
2. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification
for the specified package.
3. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
4. Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JT.
Table 12.Thermal characteristics for 176-pin LQFP
SymbolCParameterConditionsValueUnit
R
θJA
R
θJA
R
θJMA
R
θJMA
R
θJB
R
θJCtop
Ψ
JT
1. Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package.
2. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification
for the specified package.
3. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
4. Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JT.
CCD Junction-to-Ambient, Natural Convection
CCD Junction-to-Ambient, Natural Convection
CCD Junction-to-Moving-Air, Ambient
CCD Junction-to-Moving-Air, Ambient
CCD Junction-to-Board
CCD Junction-to-Case
CCD
Junction-to-Package Top, Natural
Convection
(2)
(3)
(4)
(2)
(2)
(1)
Single layer board - 1s38°C/W
(2)
Four layer board - 2s2p31°C/W
@200 ft./min., single
layer board - 1s
@200 ft./min., four layer
board - 2s2p
30°C/W
25°C/W
20°C/W
5°C/W
2°C/W
Table 13.Thermal characteristics for 208-pin LBGA
(1)
SymbolCParameterConditionsValueUnit
R
θJA
R
θJMA
R
θJA
R
θJMA
R
θJB
R
θJC
Ψ
JT
1. Thermal characteristics are targets based on simulation that are subject to change per device characterization.
2. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
3. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
4. Per JEDEC JESD51-6 with the board horizontal.
5. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
6. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method
(MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.
7. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JT.
4.3.1 General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, TJ, can be obtained from the equation:
Equation 1 T
= TA + (R
J
θJA
* PD)
where:
T
= ambient temperature for the package (oC)
A
R
= junction-to-ambient thermal resistance (oC/W)
θJA
P
= power dissipation in the package (W)
D
The thermal resistance values used are based on the JEDEC JESD51 series of standards
to provide consistent values for estimations and comparisons. The difference between the
values determined for the single-layer (1s) board compared to a four-layer board that has
two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal
resistance is not a constant. The thermal resistance depends on the:
●Construction of the application board (number of planes)
●Effective size of the board which cools the component
●Quality of the thermal and electrical connections to the planes
●Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using
fewer vias to connect the package to the planes reduces the thermal performance. Thinner
planes also reduce the thermal performance. When the clearance between the vias leave
the planes virtually disconnected, the thermal performance is also greatly reduced.
As a general rule, the value obtained on a single-layer board is within the normal range for
the tightly packed printed circuit board. The value obtained on a board with the internal
planes is usually within the normal range if the application board has:
●One oz. (35 micron nominal thickness) internal planes
●Components are well separated
●Overall power dissipation on the board is less than 0.02 W/cm2
The thermal performance of any component depends on the power dissipation of the
surrounding components. In addition, the ambient temperature varies widely within the
application. For many natural convection and especially closed box applications, the board
temperature at the perimeter (edge) of the package is approximately the same as the local
air temperature near the device. Specifying the local ambient conditions explicitly as the
board temperature provides a more precise description of the local ambient conditions that
determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following
equation:
Equation 2 T
= TB + (R
J
θJB
* PD)
where:
T
= board temperature for the package perimeter (oC)
B
R
= junction-to-board thermal resistance (oC/W) per JESD51-8S
θJB
P
= power dissipation in the package (W)
D
When the heat loss from the package case to the air does not factor into the calculation, an
acceptable value for the junction temperature is predictable. Ensure the application board is
similar to the thermal test condition, with the component soldered to a board with internal
planes.
The thermal resistance is expressed as the sum of a junction-to-case thermal resistance
plus a case-to-ambient thermal resistance:
Equation 3 R
θJA
= R
θJC
+ R
θCA
where:
R
= junction-to-ambient thermal resistance (oC/W)
θJA
R
= junction-to-case thermal resistance (oC/W)
θJC
R
= case to ambient thermal resistance (oC/W)
θCA
R
is device related and is not affected by other factors. The thermal environment can be
θJC
controlled to change the case-to-ambient thermal resistance, R
. For example, change
θCA
the air flow around the device, add a heat sink, change the mounting arrangement on the
printed circuit board, or change the thermal dissipation on the printed circuit board
surrounding the device. This description is most useful for packages with heat sinks where
90% of the heat flow is through the case to heat sink to ambient. For most packages, a
better model is required.
A more accurate two-resistor thermal model can be constructed from the junction-to-board
thermal resistance and the junction-to-case thermal resistance. The junction-to-case
thermal resistance describes when using a heat sink or where a substantial amount of heat
is dissipated from the top of the package. The junction-to-board thermal resistance
describes the thermal performance when most of the heat is conducted to the printed circuit
board. This model can be used to generate simple estimations and for computational fluid
dynamics (CFD) thermal models.
To determine the junction temperature of the device in the application on a prototype board,
use the thermal characterization parameter (Ψ
) to determine the junction temperature by
JT
measuring the temperature at the top center of the package case using the following
equation:
Equation 4 T
= TT + (ΨJT x PD)
J
where:
T
Ψ
P
= thermocouple temperature on top of the package (oC)
The thermal characterization parameter is measured in compliance with the JESD51-2
specification using a 40-gauge type T thermocouple epoxied to the top center of the
package case. Position the thermocouple so that the thermocouple junction rests on the
package. Place a small amount of epoxy on the thermocouple junction and approximately 1
mm of wire extending from the junction. Place the thermocouple wire flat against the
package case to avoid measurement errors caused by the cooling effects of the
thermocouple wire.
References:
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134
USA
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering
Documents at 800-854-7179 or 303-397-7956.
JEDEC specifications are available on the web at http://www.jedec.org.
●C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an
Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998,
pp. 47-54.
●G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled
Applications”, Electronic Packaging and Production, pp. 53-58, March 1998.
●B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal
Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San
Diego, 1999, pp. 212-220.
1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2. Device failure is defined as: “If after exposure to ESD pulses, the device does not meet the device specification
requirements, which includes the complete DC parametric and functional testing at room temperature and hot
temperature.”
1. The limits will be reviewed after data collection from 3 different lots in a full production environment.
2. Using external ballast transistor.
3. Min range is extended to 10% since Lvi1p2 is reprogrammed from 1.2 V to 1.16 V after power-on reset.
4. LVI for falling supply is calculated as LVI rising - LVI hysteresis.
5. The internal voltage regulator can be disabled by tying the VDDREG pin to ground. When the internal voltage regulator is
disabled, the LVI specifications are not applicable because all LVI monitors are disabled. POR specifications remain valid
when the internal voltage regulator is disabled as long as VDDEH and VDD33 supplies are within the required ranges.
6. This parameter is the “inrush” current of the internal 3.3V regulator when it is turned on. This spec. is the current at which
the regulator will go into current limit mode.
7. Lvi3p3 tracks DC target variation of internal Vdd33 regulator. Minimum and maximum Lvi3p3 correspond to minimum and
maximum Vdd33 DC target respectively.
Figure 7.Core voltage regulator controller external components preferred
configuration
There are three options for the bypassing and compensation networks for the 1.2V regulator
controller. The component values in the following table are the same for all PMC network
requirements.
Table 18.Required external PMC component values
ComponentSymbolMinimumTypicalMaximumUnitsComment
Pass TransistorT1
VDDREG capacitorC
Pass transistor Collector
bypass capacitor
Collector resistor
1. The collector resistor may not be required. It depends on the allowable power dissipation of the pass transistor (T1).
(1)
C
R
REG
C
C
1.1
10µFX7R, -50%/+35%
13.3µFX7R, -50%/+35%
—
5.6
NJD2873 or
BCP68
Ω
Ta bl e 1 9 , Ta bl e 2 0 and Tab l e 2 1 show the required component values for the three different
The following component configuration is acceptable when using the BCP68 transistor,
however, is not recommended for new designs. Either option 1 or option 2 should be used
for new designs. This option should not be used with the NJD2873 transistor.
The following NPN transistors are recommended for use with the on-chip voltage regulator
controller: ON Semiconductor
BCP68. The collector of the external transistor is preferably connected to the same voltage
supply source as the output stage of the regulator.
Table 22.Recommended operating characteristics
SymbolParameterValueUnit
h
(β)DC current gain (Beta)60 – 550—
FE
P
I
CMaxDC
VCE
V
1. Adjust resistor at bipolar transistor collector for 3.3 V/5.0 V to avoid VCE < VCE
Absolute minimum power dissipation
D
Minimum peak collector current1.0A
Collector-to-emitter saturation voltage200–600
SAT
Base-to-emitter voltage0.4–1.0V
BE
TM
BCP68T1 or NJD2873 as well as Philips SemiconductorTM
Ω
Ω
>1.0
(1.5 preferred)
(1)
SAT
Not required
(short)
W
mV
4.7 Power up/down sequencing
There is no power sequencing required among power sources during power up and power
down, in order to operate within specification but use of the following sequence is strongly
recommended when the internal regulator is bypassed:
5V → 3.3 V and 1.2 V
This is also the normal sequence when the internal regulator is enabled.
Although there are no power up/down sequencing requirements to prevent issues like latchup, excessive current spikes, etc., the state of the I/O pins during power up/down varies
according to table Tab le 2 3 for all pins with fast pads and Ta bl e 2 4 for all pins with medium,
slow and multi-voltage pads.
Table 23.Power sequence pin states for fast pads
V
DDE
LOWXXLOW
V
DDE
e. If an external 3.3V external regulator is used to supply current to the 1.2V pass transistor and this supply also
supplies current for the other 3.3V supplies, then the 5V supply must always be greater than or equal to the
external 3.3V supply.
1. These specifications are design targets and subject to change per device characterization.
2. TBD: To Be Defined.
3. V
4. These specifications apply when V
5. ADC is functional with 4 V ≤ V
6. Internal structures hold the input voltage less than V
7. The V
8. V
9. Regulator is functional, with derated performance, with supply voltage down to 4.0 V.
10. Multi-voltage pads (type pad_multv_hv) must be supplied with a power supply between 4.75 V and 5.25 V.
11. The slew rate (SRC) setting must be 0b11 when in low-swing mode.
12. While in low-swing mode there are no restrictions in transitioning to high-swing mode.
13. Pin in low-swing mode can accept a 5 V input.
14. Pin in low-swing mode can accept a 5 V input.
15. Characterization based capability:
16. Characterization based capability:
17. All VOL/VOH values 100% tested with ± 2 mA load.
must be lower than V
DDE
speed with no bad behavior, but the accuracy will be degraded.
injection current specification is met (3 mA for all pins) and V
supply is connected to VDD in the package substrate. This specification applies to calibration package devices
DDF
only.
is only available in the calibration package.
FLASH
IOH_S = {6, 11.6} mA and IOL_S = {9.2, 17.7} mA for {slow, medium} I/O with VDDEH=4.5 V;
IOH_S = {2.8, 5.4} mA and IOL_S = {4.2, 8.1} mA for {slow, medium} I/O with VDDEH=3.0 V
IOH_F = {12, 20, 30, 40} mA and IOL_F = {24, 40, 50, 65} mA for {00, 01,10, 11} drive mode with VDDE=3.0 V;
IOH_F = {7, 13, 18, 25} mA and IOL_F = {18, 30, 35, 50} mA for {00, 01, 10, 11} drive mode with VDDE=2.25 V;
IOH_F = {3, 7, 10, 15} mA and IOL_F = {12, 20, 27, 35} mA for {00, 01, 10, 11} drive mode with VDDE=1.62 V
Slew rate on power
supply pins
, otherwise there is additional leakage on pins supplied by V
RC33
is supplied externally, after disabling the internal regulator (V
RC33
≤ 4.75 V but with derated accuracy. This means the ADC will continue to function at full
System clock = 40/60/80 MHz + FM 2%
Code executed from flash memory
ADC0 at 16 MHz with DMA enabled
ADC1 at 8 MHz
eMIOS pads toggle in PWM mode with a rate between 100 kHz and 500 kHz
eTPU pads toggle in PWM mode with a rate between 10 kHz and 500 kHz
CAN configured for a bit rate of 500 kHz
DSPI configured in master mode with a bit rate of 2 MHz
eSCI transmission configured with a bit rate of 100 kHz
19. Bypass mode, system clock at 1 MHz (using system clock divider), PLL shut down, CPU running simple executive code,
4 x ADC conversion every 10 ms, 2 × PWM channels at 1 kHz, all other modules stopped.
20. Bypass mode, system clock at 1 MHz (using system clock divider), CPU stopped, PIT running, all other modules stopped.
21. When using the internal regulator only, a bypass capacitor should be connected to this pin. External circuits should not be
powered by the internal regulator. The internal regulator can be used as a reference for an external debugger.
22. Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a
particular I/O segment, and the voltage of the I/O segment. See Table 26 for values to calculate power dissipation for
specific operation. The total power consumption of an I/O segment is the sum of the individual power consumptions for
each pin on the segment.
23. Absolute value of current, measured at V
24. Weak pull up/down inactive. Measured at V
25. Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for
each 8 to 12
o
C, in the ambient temperature range of 50 to 125 oC. Applies to pad types: pad_a and pad_ae.
26. Applies to CLKOUT, external bus pins, and Nexus pins.
27. Applies to the FCK, SDI, SDO, and SDS
28. This programmable option applies only to eQADC differential input channels and is used for biasing and sensor
diagnostics.
29. When the pull-up and pull-down of the same nominal 200 KΩ or 100 KΩ value are both enabled, assuming no interference
from external devices, the resulting pad voltage will be 0.5*V
Note:SPC563Mxx devices use two sets of I/O pads (5 V and 3.3 V). See Tab l e 4 and Tab l e 5 in
Section 3.6, Signal summary, for the pad type associated with each signal.
The power consumption of an I/O segment depends on the usage of the pins on a particular
segment. The power consumption is the sum of all output pin currents for a particular
segment. The output pin current can be calculated from Ta bl e 2 6 based on the voltage,
frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage,
frequency, and load parameters that fall outside the values given in Tab le 2 6 .
Table 26.I/O pad average I
DDE
Pad TypeSymbolC
CCD37505.25119—
CCD130505.25012.5—
SlowI
DRV_SSR_HV
CCD650505.25000.5—
CCD8402005.25001.5—
CCD24505.251114—
CCD62505.25015.3—
MediumI
DRV_MSR_HV
CCD317505.25001.1—
specifications
Period
(ns)
(1)
Load
(pF)
(2)
V
DDE
(V)
Drive/Slew
Rate Select
I
DDE
(mA)
Avg
(3)
I
DDE
RMS
(mA)
CCD4252005.25003—
CCD10503.61122.768.3
CCD10303.61012.141.1
CCD10203.6018.327.7
CCD10103.6004.4414.3
FastI
DRV_FC
CCD10501.981112.531
CCD10301.98107.318.6
CCD10201.98015.4212.6
CCD10101.98002.846.4
CCD15505.251121.2
MultiV
(High
Swing
Mode)
I
DRV_MULTV_HV
CCD30505.2510—
CCD50505.25016.2
CCD300505.25001.1
CCD3002005.25004.0
MultiV
(Low
Swing
I
DRV_MULTV_HV
CCD15305.251120.2
CCD30305.2511NA—
Mode)
1. Numbers from simulations at best case process, 150 °C.
2. All loads are lumped.
3. Average current is for pad configured as output only.
4. Ratio from 5.5 V pad spec to 5.25 V data sheet.
5. Not specified.
6. Low swing mode is not a strong function of V
DDE
.
4.9.1 I/O pad VRC33 current specifications
The power consumption of the VRC33 supply is dependent on the usage of the pins on all
I/O segments. The power consumption is the sum of all output pin V
segments. The output pin V
voltage, frequency, and load on all medium, slow, and multv_hv pins. The output pin VRC33
current can be calculated from Tab le 2 8 based on the voltage, frequency, and load on all fast
pins. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters
that fall outside the values given in Ta bl e 2 7 and Ta bl e 2 8.
Table 27.I/O pad V
Pad TypeSymbolC
SlowI
RC33
DRV_SSR_HV
average I
CCD10050110.8235.7
CCD20050010.0487.4
CCD80050000.0647.4
current can be calculated from Tab l e 2 7 based on the
RC33
specifications
DDE
Period
(ns)
Load
(pF)
(1)
(2)
Slew Rate
Select
currents for all I/O
RC33
I
Avg
DD33
(µA)
I
DD33
RMS
(µA)
CCD800200000.00947
CCD4050112.75258
CCD10050010.1176.5
MediumI
DRV_MSR_HV
CCD50050000.0256.2
CCD500200000.0156.2
CCD4050112.75258
(3)
MultiV
(High
Swing Mode)
I
DRV_MULTV_HV
CCD10050010.1176.5
CCD50050000.0256.2
CCD500200000.0156.2
CCD4030112.75258
(4)
MultiV
(Low
Swing Mode)
I
DRV_MULTV_HV
CCD10030110.1176.5
CCD50030110.0256.2
CCD50030110.0156.2
1. These are typical values that are estimated from simulation and not tested. Currents apply to output pins only.
2. All loads are lumped.
3. Average current is for pad configured as output only.
4. In low swing mode, multi-voltage pads (pad_multv_hv) must operate in highest slew rate setting.
1. These are typical values that are estimated from simulation and not tested. Currents apply to output pins
only.
2. All loads are lumped.
4.9.2 LVDS pad specifications
LVDS pads are implemented to support the MSC (Microsecond Channel) protocol which is
an enhanced feature of the DSPI module. The LVDS pads are compliant with LVDS
specifications and support data rates up to 50 MHz.
1. All values given are initial design targets and subject to change.
2. Considering operation with PLL not bypassed.
3. f
VCO
— In Legacy Mode f
— In Enhanced Mode fvco = (f
4. All internal registers retain data at 0 Hz.
5. “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked mode.
6. Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the f
window.
7. f
VCO
mode.
8. This value is determined by the crystal manufacturer and board design.
9. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via V
percentage for a given interval.
10. Proper PC board layout procedures must be followed to achieve specifications.
11. Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C
fCS or f
12. This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this
PLL, load capacitors should not exceed these limits. For a 20 MHz crystal the maximum load should be 17 pF.
13. Proper PC board layout procedures must be followed to achieve specifications.
14. This parameter is guaranteed by design rather than 100% tested.
15. V
IHEXT
16. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR).
CCP PLL lock time
CCT Duty cycle of reference
CCT Frequency LOCK range—–66% f
CCT Frequency un-LOCK range—–1818% f
D
CC
Modulation Depth
DDown Spread–0.5–8.0
CCD Modulation frequency
is calculated as follows:
self clock range is 20–150 MHz. f
(depending on whether center spread or down spread modulation is enabled).
DS
cannot exceed V
=(f
VCO
crystal
crystal
in external reference mode.
RC33
(12), (16)
(17)
/ (PREDIV + 1)) * (4 * (MFD + 4))
/ (EPREDIV + 1)) * (EMFD + 4)
DDPLL
represents f
SCM
and V
SSPLL
after PLL output divider (ERFD) of 2 through 16 in enhanced
SYS
and variation in crystal oscillator frequency increase the C
1. Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time that
the ADC is ready to perform conversions.Delay from power up to full accuracy = 8 ms.
2. At V
RH
3. Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs greater
then V
4. Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit
do not affect device reliability or cause permanent damage.
5. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values using V
6. Condition applies to two adjacent pins at injection limits.
7. Performance expected with production silicon.
8. All channels have same 10 kΩ <Rs<100kΩ; Channel under test has Rs=10 kΩ; I
CCC
CCC
– VRL = 5.12 V, one count = 1.25 mV. Without using pregain.
and 0x0 for values less then VRL. Other channels are not affected by non-disruptive conditions.
RH
Differential input Common mode
voltage (DANx- + DANx+)/2
= V
POSCLAMP
+ 0.5 V and V
DDA
(15)
NEGCLAMP
PREGAIN set
to 1X setting
PREGAIN set
to 2X setting
PREGAIN set
to 4X setting
–
–
–
(VRH -
VRL)/2 -
5%
= – 0.3 V, then use the larger of the calculated values.
INJ=IINJMAX,IINJMIN.
(VRH VRL)/2
(VRH VRL)/4
(VRH VRL)/8
(VRH -
VRL)/2 +
5%
V
V
V
V
100/142Doc ID 14642 Rev 9
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1 point = 1 manual.
You can buy points or you can get point for every manual you upload.