ST PC560B60L7, SPC560B64L7, SPC560B54L5, SPC560B60L5, SPC560B64L5 User Manual

Features

SPC560B54x

SPC560B60x, SPC560B64x

32-bit MCU family built on the Power Architecture

for automotive body electronics applications

®

■ High performance 64 MHz e200z0h CPU

– 32-bit Power A rc hitecture

®

technology CPU
– Up to 60 DMIPs operation
– Variable length encoding (VLE)

■ Memory

– Up to 1.5 MB on-chip Code Flash with ECC
– 64 KB on-chip Data Flash with ECC
– Up to 96 KB on-chip SRAM with ECC
–8-entry MPU

■ Interrupts

– 16 priority levels
– Non-maskable interrupt (NMI)
– Up to 51 external interrupts lines including

27 wake-up lines

■ 16-channel eDMA (linked to PITs, DSPI,

ADCs, eMIOS, LINFlex and I

■ GPIOs: 77 (LQFP100), 121 (LQFP144) and

2

C)

149 (LQFP176)

■ Timer units

– 8-channel 32-bit periodic interrupt timer
– 4-channel 32-bit system timer
– System watchdog timer
– Real-time clock timer

■ eMIOS, 16-bit counter timed I/O units

– Up to 64 channels with PWM/MC/IC/OC
– Up to 10 counter basis
– ADC diagnostic trigger via CTU

■ One 10-bit and one 12-bit ADC with up to 53

channels
– Extendable to 81 channels
– Individual conversion registers
– Cross triggering unit (CTU)

■ Dedicated diagnostic module for lighting

– Advanced PWM generation
– Time-triggered diagnostics
– PWM-synchronized ADC measurements

■ On-chip CAN/UART bootstrap loader

■ Communications interfaces

LQFP144LQFP100 LQFP176

(20 x 20 x 1.4 mm) (24 x 24 x 1.4 mm)(14 x 14 x 1.4 mm)

– Up to 6 FlexCAN (2.0B active) with 64

message buffers each
– Up to 10 LINFlex/UART channels
– Up to 6 buffered DSPI channels

2

–I

C interface

■ Clock generation

– 4 to 16 MHz fast external crystal oscillator
– 32 kHz slow external crystal oscillator
– 16 MHz fast internal RC oscillator
– 128 kHz slow internal RC oscillator for low-

power modes
– Software-controlled FMPLL
– Clock monitoring unit

■ Low-power capabilities

– Several low-power mode configurations
– Ultra-low-power standby with RTC and

communication
– Fast wakeup schemes

■ Exhaustive debugging capability

– Nexus 2+ interface on LBGA208 package
– Nexus 1 on all packages

■ Voltage supply

– Single 5 V or 3.3 V supply
– On-chip voltage regulator
– External ballast resistor support

■ LQFP100, LQFP144, and LQFP176 packages;

LBGA208 package for Nexus2+

■ Operating temperature range -40 to 125 °C

Table 1. Device summary

Package

LQFP176 — SPC560B60L7 SPC560B64L7
LQFP144 SPC560B54L5 SPC560B60L5 SPC560B64L5
LQFP100 SPC560B54L3 SPC560B60L3 —

768 KByte

Code Flash

1 MByte

Code Flash

1.5 MByte

Code Flash

September 2011 Doc ID 15131 Rev 6 1/134

www.st.com

1

Contents SPC560B54/6x

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 13

3.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2 Pad configuration during reset phases . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3 Pad configuration during standby mode exit . . . . . . . . . . . . . . . . . . . . . . 17

3.4 Voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.5 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.6 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.7 Functi onal port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.8 Nexus 2+ pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.1 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.2 NVUSR O register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.2.1 NVUSRO[PAD3V5V] field description . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.2.2 NVUSRO[OSCILLATOR_MARGIN] field description . . . . . . . . . . . . . . . 58

4.2.3 NVUSRO[WATCHDOG_EN] field description . . . . . . . . . . . . . . . . . . . . 58

4.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.4 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4.5.1 External ballast resistor recommendations . . . . . . . . . . . . . . . . . . . . . . 61

4.5.2 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

4.5.3 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

4.6 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.6.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.6.2 I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.6.3 I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4.6.4 Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

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SPC560B54/6x Contents

4.6.5 I/O pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

4.7 RESET electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

4.8 Power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 80

4.8.1 V oltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 80

4.8.2 Low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . . 83

4.9 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

4.10 Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 86

4.10.1 Program/erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

4.10.2 Flash power supply DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.10.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

4.11 Electromagnetic compatibilit y (EM C ) characteristics . . . . . . . . . . . . . . . . 88

4.11.1 Designing hardened software to avoid noise problems . . . . . . . . . . . . . 88

4.11.2 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

4.11.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 89

4.12 Fast external crystal oscillator (4 to 16 MHz) electrical characteristics . . 90

4.13 Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . 93

4.14 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4.15 Fast internal RC oscilla tor (16 MHz) electrical characteristics . . . . . . . . . 96

4.16 Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . 97

4.17 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

4.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

4.17.2 Input impedance and ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

4.17.3 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

4.18 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

4.18.1 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

4.18.2 DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

4.18.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

4.18.4 JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

5 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

5.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

5.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

5.2.1 LQFP176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

5.2.2 LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

5.2.3 LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

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Contents SPC560B54/6x

5.2.4 LBGA208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Appendix A Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

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SPC560B54/6x List of tables

List of tables

Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. SPC560B54/6 family comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 3. SPC560B54/6 series block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 4. Voltage supply pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 5. System pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 6. Functional port pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 7. Nexus 2+ pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 8. Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 9. PAD3V5V field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 10. OSCILLATOR_MARGIN field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 11. WATCHDOG_EN field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 12. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 13. Recommended operating conditions (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 14. Recommended operating conditions (5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 15. LQFP thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 16. I/O input DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 17. I/O pull-up/pull-down DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 18. SLOW configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 19. MEDIUM configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 67

Table 20. FAST configuration output buffer electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 21. Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 22. I/O supply segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 23. I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 24. I/O weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 25. Reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 26. Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 27. Low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 28. Power consumption on VDD_BV and VDD_HV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 29. Program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 30. Flash module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 31. Flash read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 32. Flash power supply DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 33. Start-up time/Switch-off time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 34. EMI radiated emission measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 35. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 36. Latch-up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 37. Crystal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 38. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics. . . . . . . . . . . . . . . . 92

Table 39. Crystal motional characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 40. Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . 95

Table 41. FMPLL electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 42. Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 96

Table 43. Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . 97

Table 44. ADC input leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 45. ADC_0 conversion characteristics (10-bit ADC_0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 46. ADC_1 conversion characteristics (12-bit ADC_1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 47. On-chip peripherals current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 48. DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

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List of tables SPC560B54/6x

Table 49. Nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 50. JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 51. LQFP176 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 52. LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 53. LQFP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 54. LBGA208 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 55. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 56. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

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SPC560B54/6x List of figures

List of figures

Figure 1. SPC560B54/6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 2. LQFP176 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 3. LQFP144 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 4. LQFP100 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 5. LBGA208 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 6. I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 7. Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 8. Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 9. Voltage regulator capacitance connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 10. Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 11. Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 12. Fast external crystal oscillator (4 to 16 MHz) timing diagram. . . . . . . . . . . . . . . . . . . . . . . 92

Figure 13. Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 14. lEquivalent circuit of a quartz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 15. Slow external crystal oscillator (32 kHz) timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 16. ADC_0 characteristic and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 17. Input equivalent circuit (precise channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 18. Input equivalent circuit (extended channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 19. Transient behavior during sampling phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 20. Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 21. ADC_1 characteristic and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 22. DSPI classic SPI timing — master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 23. DSPI classic SPI timing — master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 24. DSPI classic SPI timing — slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 25. DSPI classic SPI timing — slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 26. DSPI modified transfer format timing — master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 27. DSPI modified transfer format timing — master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 28. DSPI modified transfer format timing — slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 29. DSPI modified transfer format timing — slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 30. DSPI PCS strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 31. Nexus TDI, TMS, TDO timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 32. Timing diagram — JTAG boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 33. LQFP176 package mechanical drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 34. LQFP144 package mechanical drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 35. LQFP100 package mechanical drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 36. LBGA208 package mechanical drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 37. Commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Doc ID 15131 Rev 6 7/134

Introduction SPC560B54/6x

1 Introduction

1.1 Document overview

This document describes the features of the family and options available within the family
members, and highlights important electrical and physical characteristics of the device.

1.2 Description

This family of 32-bit system-on-chip (SoC) microcontrollers is the latest achievement in
integrated automotive application controllers. It belongs to an expanding family of
automotive-focused products designed to address the next wave of body electronics
applications within the vehicle.

The advanced and cost-efficient e200z0h host processor core of this automotive controller
family complies with the Power Architecture technology and only implements the VLE
(variable-length encoding) APU (Auxiliary Processor Unit), providing improved code density.
It operates at speeds of up to 64 MHz and offers high performance processing optimized for
low power consumption. It capitalizes on the available development infrastructure of current
Power Architecture devices and is supported with software drivers, operating systems and
configuration code to assist with users implementations.

Table 2. SPC560B54/6 family comparison

(1)

Feature SPC560B54 SPC560B60 SPC560B64

CPU e200z0h
Execution speed
Code flash memory 768 KB 1 MB 1.5 MB
Data flash memory 64 (4
SRAM 64 KB 80 KB 96 KB
MPU 8-entry
eDMA 16 ch
10-bit ADC Yes

shared with 12-bit ADC 19 ch

12-bit ADC Yes

shared with 10-bit ADC 19 ch

Total timer I/O

Counter / OPWM /

(2)

dedicated

dedicated

(5)

eMIOS

ICOC

Up to 64 MHz

× 16) KB

(3)

7 ch 15 ch 7 ch 15 ch 29 ch 15 ch 29 ch 29 ch

(4)

(6)

37 ch,

16-bit

64 ch,

16-bit

37 ch,

16-bit

64 ch,

16-bit

5 ch

10 ch

64 ch,

16-bit

64 ch,

16-bit

64 ch,

16-bit

64 ch,

16-bit

O(I)PWM / OPWFMB /

OPWMCB / ICOC

8/134 Doc ID 15131 Rev 6

(7)

7ch

SPC560B54/6x Introduction

Table 2. SPC560B54/6 family comparison

(1)

(continued)

Feature SPC560B54 SPC560B60 SPC560B64

O(I)PWM / ICOC

OPWM / ICOC

(8)

7 ch 14 ch 7 ch 14 ch 14 ch 14 ch 14 ch 14 ch

(9)

13 ch 33 ch 13 ch 33 ch 33 ch 33 ch 33 ch 33 ch
SCI (LINFlex) 48481081010
SPI (DSPI) 3535656 6
CAN (FlexCAN) 6

2

I

C1

32 KHz oscillator Yes

(10)

GPIO

77 121 77 121 149 121 149 149

Debug JTAG N2+

Package LQFP100 LQFP144 LQFP100 LQFP144 LQFP176 LQFP144 LQFP176

1. Feature set dependent on selected peripheral multiplexing; table shows example

2. Based on 125 °C ambient operating temperature

3. Not shared with 12-bit ADC, but possibly shared with other alternate functions

4. Not shared with 10-bit ADC, but possibly shared with other alternate functions

5. See the eMIOS section of the chip reference manual for information on the channel configuration and functions.

6. Each channel supports a range of modes including Modulus counters, PWM generation, Input Capture, Output Compare.

7. Each channel supports a range of modes including PWM generation with dead time, Input Capture, Output Compare.

8. Each channel supports a range of modes including PWM generation, Input Capture, Output Compare, Period and Pulse
width measurement.

9. Each channel supports a range of modes including PWM generation, Input Capture, and Output Compare.

10. Maximum I/O count based on multiplexing with peripherals

11. LBGA208 available only as development package for Nexus2+

LBGA208

(11)

Doc ID 15131 Rev 6 9/134

Block diagram SPC560B54/6x

2 Block diagram

Figure 1

shows a top-level block diagram of the SPC560B54/6.

Figure 1. SPC560B54/6 block diagram

JTAG

JTAG Port

Nexus Port

NMI

Clocks

Interrupt
Request

Nexus

Voltage

Regulator

FMPLL

RTC

SIUL

Reset Control

External
Interrupt
Request

IMUX

GPIO &

Pad Control

NMI

SIUL

Interrupt requests

from peripheral

blocks

CMU

SWT

19 ch 10-bit/12-bit

ADC

5 ch 12-bit

ECSM

ADC

e200z0h

Nexus 2+

PITSTM

29 ch 10-bit

ADC

INTC

Instructions

(Master)

Data

(Master)

MPU

Registers

Peripheral Bridge

CTU

(Master)

64 ch

eMIOS

eDMA

64-bit 2 x 3 Crossbar Switch

MPU

10 x

LINFlex

SRAM
96 KB

SRAM

Controller

(Slave)

(Slave)

MC_PCUMC_MEMC_CGMMC_RGM

DSPI

Code Flash

6 x

1.5 MB

WKPU

BAM

I2C

Data Flash

Flash

Controller

(Slave)

request with

functionality

SSCM

FlexCAN

64 KB

Interrupt

wakeup

6 x

I/O

Legend:
ADC Analog-to-Digital Converter

BAM Boot Assist Module
CMU Clock Monitor Unit
CTU Cross Triggering Unit
DSPI Deserial Serial Peripheral Interface
ECSM Error Correction Status Module
eDMA Enhanced Direct Memory Access
eMIOS Enhanced Modular Input Output System
Flash Flash memory
FlexCAN Controller Area Network
FMPLL Frequency-Modulated Phase-Locked Loop
GPIO General-purpose input/output

2

C Inter-Integrated Circuit bus

I
IMUX Internal Multiplexer
INTC Interrupt Controller
JTAG JTAG controller
LINFlex Serial Communication Interface (LIN support)

. . .

. . .

10/134 Doc ID 15131 Rev 6

. . .

MC_CGM Clock Generation Module
MC_ME Mode Entry Module
MC_PCU Power Control Unit
MC_RGM Reset Generation Module
MPU Memory Protection Unit
NMI Non-Maskable Interrupt
PIT Periodic Interrupt Timer
RTC Real-Time Clock
SIUL System Integration Unit Lite
SRAM Stati c Rand om -A cce ss Memory
SSCM System Status Configuration Module
STM System Timer Module
SWT Software Watchdog Timer
VREG Voltage regulator
WKPU Wakeup Unit
XBAR Crossbar switch

. . .

. . .

SPC560B54/6x Block diagram

Table 3

Table 3. SPC560B54/6 series block summary

summarizes the functions of the blocks present on the SPC560B54/6.

Block Function

Analog-to-digital converter (ADC) Converts analog voltages to digital values

Boot assist module (BAM)

Clock gener ati on mo dul e
(MC_CGM)

A block of read-only memory containing VL E c ode w hi ch is executed according
to the boot mode of the device

Provides logic and control requi red for the generation of system and peripheral
clocks

Clock monitor unit (CMU) Monitors clock source (internal and external) integrity

Cross triggering unit (CTU)

Enables synchro nization of ADC c onve rsions with a timer ev ent from th e eMIOS
or from the PIT

Supports simultaneous connections between two master ports and three slave

Crossbar switch (XBAR)

ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width.

Deserial serial peripheral
interface (DSPI)

Enhanced Dir ect Me mory Access
(eDMA)

Enhanced modular input output
system (eMIOS)

Provides a synchronous serial interface for communication with external
devices

Performs complex data transfers with minimal intervention from a host

n

processor via “

” programmable channels

Provides the functionality to generate or measure events

Provides a myriad of miscellaneous control functions for the device including
Error Correction Status Module
(ECSM)

program-visible information about configuration and revision levels, a reset

status register, wakeup control for exiting sleep modes, and optional features

such as information on memory errors reported by error-correcting codes
Flash memory Provides non-volatile storage for program code, constants and variables
FlexCAN (controller area

network)
Frequency-modulated phase-

locked loop (FMPLL)

Inter-integrated circuit (I2C™) bus

Internal multiplexer (IMUX) SIU
subblock

Supports the standard CAN communications protocol

Generates high-speed system clocks and supports programmable frequency

modulation

A two wire bidirectional se rial bus t hat provide s a simple and efficient me thod of

data exchange between devices

Allows flexible mapping of peripheral in terface on the different p ins of the devi ce

Interrupt controller (INTC) Provides priority-based preemptive scheduling of interrupt requests

JTAG controller (JTAGC)

LINFlex co ntr ol ler

Memory protection unit (MPU)

Provides the means to test chip functionality and connectivity while remaining

transparent to system logic when not in test mode

Manages a high number of LIN (Local Interconnect Network protocol)

messages efficiently with a minimum of CPU load

Provides hardware access control for all memory references generated in a

device

Provides a mechanism for controlling the device operational mode and
Mode entry module (MC_ME)

modetransition sequences in all functional states; also manages the power

control unit, reset generation module and clock generation module, and holds

the configuration, control and status registers accessible for applications

Doc ID 15131 Rev 6 11/134

Block diagram SPC560B54/6x

Table 3. SPC560B54/6 series block summary (continued)

Block Function

Non-Maskable Interrupt (NMI)

Handles external events that must produce an immediate response, such as

power down detection
Periodic interrupt timer (PIT) Produces periodic interrupts and triggers

Reduces the overall power consumption by disconnecting parts of the device
Power control unit (MC_PCU)

from the power supply via a power switching device; device components are

grouped into sections called “power domains” which are controlled by the PCU

A free running counter used for time keeping applications, the RTC can be
Real-time counter (RTC)

configured to generate an interrupt at a predefined interval independent of the

mode of operation (run mode or low-power mode)
Reset generation module

(MC_RGM)
Static random-access memory

(SRAM)

Centralizes reset sources and manages the device reset sequence of the

device

Provides storage for program code, constants, and variables

Provides control over all the electrical pad controls and up 32 ports with 16 bits
System integrati on uni t lite (SIUL)

of bidirectional, ge neral-pu rpose input and o utput sign als and supports up to 32

external interrupts with trigger event configuration

System status and configuration
module (SSCM)

System timer module (STM)

Provides system configuration and status data (such as memory size and

status, device mode and security status), device identification data, debug

status port enable and selection, and bus and peripheral abort enable/disable

Provides a set of output compare events to support AUTOSAR (AUTomotive

Open System ARchitecture) and operating system tasks
System watchdog timer (SWT) Provides protection from runaway code

WKPU (wakeup unit)

The wakeup unit supports up to 27 external sources that can generate

interrupts or wakeup events, of which 1 can cause non-maskable interrupt

requests or wakeup events.

12/134 Doc ID 15131 Rev 6

SPC560B54/6x Package pinouts and signal descriptions

3 Package pinouts and signal descriptions

3.1 Package pinouts

The available LQFP pinouts and the ballmap are provided in the following figures. For pin
signal descriptions, please see

Figure 2

shows the SPC560B54/6 in the LQFP176 package.

Figure 2. LQFP176 pin configuration

PB[2]

PC[8]

PC[13]

PC[12]

PI[0]

PI[1]

PI[2]

PI[3]

PE[7]

PE[6]

PH[8]

PH[7]

PH[6]

PH[5]

176

175

174

173

172

171

170

169

168

167

166

165

164

PB[3]

PC[9]
PC[14]
PC[15]

PJ[4]

VDD_HV

VSS_HV

PH[15]
PH[13]
PH[14]

PI[6]

PI[7]
PG[5]
PG[4]
PG[3]
PG[2]

PA[2]

PE[0]

PA[1]
PE[1]
PE[8]
PE[9]

PE[10]

PA[0]

PE[11]

VSS_HV

VDD_HV

VSS_HV

RESET

VSS_LV

VDD_LV

VDD_BV

PG[9]

PG[8]
PC[11]
PC[10]

PG[7]

PG[6]

PB[0]
PB[1]
PF[9]
PF[8]

PF[12]

PC[6]

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

45464748495051525354555657585960616263646566676869707172737475767778798081828384858687

163

Table 6

PH[4]

PE[5]

PE[4]

PC[4]

162

161

160

159

PC[5]

PE[3]

PE[2]

158

157

156

155

LQFP176

Top view

.

PH[9]

PC[0]

VSS_LV

VDD_LV

VDD_HV

VSS_HV

PC[1]

PH[10]

PA[6]

PA[5]

PC[2]

PC[3]

PI[4]

PI[5]

PH[12]

PH[11]

PG[11]

PG[10]

PE[15]

PE[14]

PG[15]

PG[14]

PE[12]

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

PA[11]

132

PA[10]

131

PA[9]

130

PA[8]

129

PA[7]

128

PE[13]

127

PF[14]

126

PF[15]

125

VDD_HV

124

VSS_HV

123

PG[0]

122

PG[1]

121

PH[3]

120

PH[2]

119

PH[1]

118

PH[0]

117

PG[12]

116

PG[13]

115

PA[3]

114

PI[13]

113

PI[12]

112

PI[11]

111

PI[10]

110

PI[9]

109

PI[8]

108

PB[15]

107

PD[15]

106

PB[14]

105

PD[14]

104

PB[13]

103

PD[13]

102

PB[12]

101

PD[12]

100

VDD_HV_ADC1

99

VSS_HV_ADC1

98

PB[11]

97
96

PD[11]

95

PD[10]

94

PD[9]

93

PB[7]

92

PB[6]

91

PB[5]

90

VDD_HV_ADC0

89

VSS_HV_ADC0

88

PJ[3]

PJ[2]

PJ[1]

PC[7]

PF[10]

PA[4]

PA[15]

PA[14]

PF[11]

PF[13]

XTAL

PA[13]

PA[12]

EXTAL

VSS_LV

VDD_LV

VSS_HV

PF[0]

PF[1]

PF[2]

PF[3]

PF[4]

PF[5]

PB[9]

PB[8]

PB[10]

VDD_HV

PF[6]

PJ[0]

PF[7]

PD[0]

PD[1]

PD[2]

PD[3]

PD[4]

PD[5]

PI[15]

PI[14]

PD[6]

PB[4]

PD[7]

PD[8]

VSS_HV

VDD_HV

Doc ID 15131 Rev 6 13/134

Package pinouts and signal descriptions SPC560B54/6x

Figure 3

shows the SPC560B54/6 in the LQFP144 package.

Figure 3. LQFP144 pin configuration

PB[2]

PC[8]

PC[13]

PC[12]

PE[7]

PE[6]

PH[8]

PH[7]

PH[6]

PH[5]

PH[4]

PE[5]

PE[4]

PC[4]

PC[5]

PE[3]

PE[2]

PH[9]

PC[0]

VSS_LV

VDD_LV

VDD_HV

VSS_HV

PC[1]

PH[10]

PA[6]

PA[5]

PC[2]

PC[3]

PG[11]

PG[10]

PE[15]

PE[14]

PG[15]

PG[14]

PE[12]

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

72

107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73

PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
PE[13]
PF[14]
PF[15]
VDD_HV
VSS_HV
PG[0]
PG[1]
PH[3]
PH[2]
PH[1]
PH[0]
PG[12]
PG[13]
PA[3]
PB[15]
PD[15]
PB[14]
PD[14]
PB[13]
PD[13]
PB[12]
VDD_HV_ADC1
VSS_HV_ADC1
PD[11]
PD[10]
PD[9]
PB[7]
PB[6]
PB[5]
VDD_HV_ADC0
VSS_HV_ADC0

PB[3]

PC[9]
PC[14]
PC[15]

PG[5]
PG[4]
PG[3]
PG[2]

PA[2]

PE[0]

PA[1]
PE[1]
PE[8]
PE[9]

PE[10]

PA[0]

PE[11]

VSS_HV

VDD_HV

VSS_HV

RESET

VSS_LV

VDD_LV

VDD_BV

PG[9]

PG[8]
PC[11]
PC[10]

PG[7]

PG[6]

PB[0]
PB[1]

PF[9]
PF[8]

PF[12]

PC[6]

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

3738394041424344454647484950515253545556575859606162636465666768697071

LQFP144

Top view

PC[7]

Figure 4

PA[4]

PA[15]

PA[14]

PF[10]

PF[11]

PA[13]

PF[13]

XTAL

PA[12]

VDD_LV

EXTAL

VSS_LV

VSS_HV

VDD_HV

shows the SPC560B54/6 in the LQFP100 package.

PF[0]

PF[1]

PF[2]

PF[3]

PF[4]

PB[9]

PB[8]

PB[10]

PF[5]

14/134 Doc ID 15131 Rev 6

PF[6]

PF[7]

PD[0]

PD[1]

PD[2]

PD[3]

PD[4]

PD[5]

PB[4]

PD[6]

PD[7]

PD[8]

SPC560B54/6x Package pinouts and signal descriptions

Figure 4. LQFP100 pin configuration

PB[2]

PC[8]

PC[13]

PC[12]

PE[7]

PE[6]

PE[5]

PE[4]

PC[4]

PC[5]

PE[3]

PE[2]

PH[9]

PC[0]

VSS_LV

VDD_LV

VDD_HV

VSS_HV

PC[1]

PH[10]

PA[6]

PA[5]

PC[2]

PC[3]

PE[12]

PB[3]

PC[9]
PC[14]
PC[15]

PA[2]

PE[0]

PA[1]
PE[1]
PE[8]
PE[9]

PE[10]

PA[0]

PE[11]

VSS_HV

VDD_HV

VSS_HV

RESET

VSS_LV

VDD_LV

VDD_BV

PC[11]
PC[10]

PB[0]
PB[1]
PC[6]

9998979695949392919089888786858483828180797877

100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

26272829303132333435363738394041424344454647484950

PA[4]

PC[7]

PA[15]

PA[14]

PA[13]

PA[12]

VSS_LV

VDD_LV

LQFP100

Top view

XTAL

EXTAL

VSS_HV

VDD_HV

PB[9]

PB[8]

PD[0]

PD[1]

PD[2]

PD[3]

PB[10]

PD[4]

76

PA[11]

75

PA[10]

74

PA[9]

73

PA[8]

72

PA[7]

71

VDD_HV

70

VSS_HV

69

PA[3]

68

PB[15]

67

PD[15]

66

PB[14]

65

PD[14]

64

PB[13]

63

PD[13]

62

PB[12]

61

VDD_HV_ADC1

60

VSS_HV_ADC1

59

PD[11]

58

PD[10]

57

PD[9]

56

PB[7]

55

PB[6]

54

PB[5]

53

VDD_HV_ADC0

52

VSS_HV_ADC0

51

PD[5]

PB[4]

PD[6]

PD[7]

PD[8]

Figure 5

shows the SPC560B54/6 in the LBGA208 package.

Doc ID 15131 Rev 6 15/134

Package pinouts and signal descriptions SPC560B54/6x

Figure 5. LBGA208 configuration

1 2345678910111213141516

PC[8] PC[13] PH[15] PJ[4] PH[8] PH[4] PC[5] PC[0] PI[0] PI[1] PC[2] PI[4] PE[15] PH[11] NC NC

A

A

PC[9] PB[2] PH[13] PC[12] PE[6] PH[5] PC[4] PH[9] PH[10] PI[2] PC[3] PG[11] PG[15] PG[14] PA[11] PA[10]

B

VDD_H

PC[14]

C

PH[14] PI[6] PC[15] PI[7] PH[6] PE[4] PE[2] VDD_LV

D

PG[4] PG[5] PG[3] PG[2] PG[1] PG[0] PF[15]

E

PE[0] PA[2] PA[1] PE[1] PH[0] PH[1] PH[3] PH[2]

F

PE[9] PE[8] PE[10] PA[0]

G

VSS_HV PE[11]

H

RESET VSS_LV NC NC

J

EVTI NC

K

PG[9] PG[8] NC EVTO PB[15] PD[15] PD[14] PB[14]

L

PG[7] PG[6] PC[10] PC[11] PB[13] PD[13] PD[12] PB[12]

M

PB[1] PF[9] PB[0]

N

PF[8] PJ[3] PC[7] PJ[2] PJ[1] PA[14] VDD_LV XTAL PB[10] PF[1] PF[5] PD[0] PD[3]

P

PB[3] PE[7] PH[7] PE[5] PE[3] VSS_LV PC[1] PI[3] PA[5] PI[5] PE[14] PE[12] PA[9] PA[8]

V

VDD_H

V

VDD_B

V

NC

VDD_LV

VDD_H

V

VSS_HVVSS_HVVSS_HVVSS_H

VSS_HVVSS_HVVSS_HVVSS_H

VSS_HVVSS_HVVSS_HVVSS_H

VSS_HVVSS_HVVSS_HVVSS_H

PJ[0] PA[4] VSS_LV EXTAL

VDD_H

VDD_H

NC PA[6] PH[12] PG[10] PF[14] PE[13] PA[7]

V

VDD_H

PI[12] PI[13] MSEO

V

MDO3 MDO2 MDO0 MDO1

PI[8] PI[9] PI[10] PI[11]

VDD_H
V_ADC1PG[12] PA[3] PG[13]

VDD_H
V_ADC0PB[6] PB[7]

V

V

V

V

V

PF[0] PF[4]

VSS_H
V_ADC1PB[11] PD[10] PD[9] PD[11]

VDD_H

V

B

C

D

E

F

G

H

J

K

L

M

N

P

PF[12] PC[6] PF[10] PF[11]

R

NC NC NC MCKO NC PF[13] PA[12] PI[15]

T

VDD_H

PA[15] PA[13] PI[14] XTAL32 PF[3] PF[7] PD[2] PD[4] PD[7]

V

EXTAL

PF[2] PF[6] PD[1] PD[5] PD[6] PD[8] PB[4]

32

VSS_H
V_ADC0PB[5]

1 2345678910111213141516

NOTE: The LBGA208 is available only as dev elopment package for Nexus 2+.

= Not connected

NC

3.2 Pad configuration during reset phases

All pads have a fixed configuration under reset.
During the power-up phase, all pads are forced to tristate.
After power-up phase, all pads are tristate with the following exceptions:

● PA[9] (FAB) is pull-down. Without external strong pull-up the device starts fetching from

flash.

● PA[8], PC[0] and PH[9:10] are in input weak pull-up when out of reset.

● RESET pad is driven low by the device till 40 FIRC clock cycles after phase2

completion. Minimum phase3 duration is 40 FIRC cycles.

● Nexus output pads (MDO[n], MCKO, EVTO, MSEO) are forced to output.

R

T

16/134 Doc ID 15131 Rev 6

SPC560B54/6x Package pinouts and signal descriptions

3.3 Pad configuration during standby mode exit

Pad configuration (input buffer enable, pull enable) for low-power wakeup pads is controlled
by both the SIUL and WKPU modules. During standby exit, all low power pads
PA[0,1,2,4,15], PB[1,3,8,9,10]
PG[3,5,7,9]

b

, PI[1,3]

(c)

are configured according to their respective configuration done in the

(a)

, PC[7,9,11], PD[0,1], PE[0,9,11], PF[9,11,13]

(b)

,

WKPU module. All other pads will have the same configuration as expected after a reset.
The TDO pad has been moved into the STANDBY domain in order to allow low-power

debug handshaking in STANDBY mode. However, no pull-resistor is active on the TDO pad
while in STANDBY mode. At this time the pad is configured as an input. When no debugger
is connected the TDO pad is floating causing additional current consumption.

To avoid the extra consumption TDO must be connected. An external pull-up resistor in the
range of 47–100 kOhms should be added between the TDO pin and VDD. Only if the TDO
pin is used as an application pin and a pull-up cannot be used should a pull-down resistor
with the same value be used instead between the TDO pin and GND.

3.4 Voltage supply pins

Voltage supply pins are used to provide power to the device. Three dedicated
VDD_LV/VSS_LV supply pairs are used for 1.2 V regulator stabilization.

Table 4. Voltage supply pin descriptions

Pin number

Port pin Function

LQFP100 LQFP144 LQFP176 LBGA208

15, 37, 70, 84 19, 51, 100,

VDD_HV Digital supply voltage

14, 16, 35,

69, 83

VSS_HV Digital ground

1.2 V decoupling pins. Decoupling

VDD_LV

VSS_LV

VDD_BV Internal regulator supply voltage 20 24 32 K3

capacitor must be connected
between these pins and the
nearest V

1.2 V decoupling pins. Decoupling
capacitor must be connected
between these pins and the
nearest V

SS_LV

DD_LV

pin.

pin.

(1)

1

19, 32, 85 23, 46, 124

18, 33, 86 22, 47, 125

123

18, 20, 49,

99, 122

6, 27, 59, 85,

124, 151

7, 26, 28, 57,

86, 123, 150

31, 54, 152

30, 55, 153

C2, D9, E16,
G13, H3, N4,

N9, R5

G7, G8, G9,

G10, H7, H8,

H9, H10, J7,

J8, J9, J10,
K7, K8, K9,

K10

D8, K4, P7

C8, J2, N7

a. PB[8, 9] ports have wakeup functionality in all modes except STANDBY.
b. PF[9,11,13], PG[3,5,7,9], PI[1,3] are not available in the 100-pin LQFP.
c. PI[1,3] are not available in the 144-pin LQFP.

Doc ID 15131 Rev 6 17/134

Package pinouts and signal descriptions SPC560B54/6x

Table 4. Voltage supply pin descriptions (continued)

Pin number

Port pin Function

LQFP100 LQFP144 LQFP176 LBGA208

Reference ground and analog

VSS_HV_ADC0

VDD_HV_ADC0

VSS_HV_ADC1

VDD_HV_ADC1

1. A decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage
(see the recommended operating conditions in the device datasheet).

ground for the A/D converter 0 (10­bit)

Reference voltage and analog
supply for the A/D converter 0 (10­bit)

Reference ground and analog
ground for the A/D converter 1 (12­bit)

Reference voltage and analog
supply for the A/D converter 1 (12­bit)

51 73

52 74

59 81

60 82

R15

89

P14

90

N12

98

K13

99

3.5 Pad types

In the device the following types of pads are available for system pins and functional port
pins:

S = Slow
M = Mediumd
F = Fastd
I = Input only with analog feature
J = Input/Output (‘S’ pad) with analog feature
X = Oscillator

(d)

(e)

e

d

3.6 System pins

The system pins are listed in

d. See the I/O pad electrical characteristics in the chip datasheet for details.
e. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium.

The only exception is PC[1] which is in medium configuration by default (see the PCR.SRC description in the
chip reference manual, Pad Configuration Registers (PCR0–PCR148)).

18/134 Doc ID 15131 Rev 6

Table 5

.

SPC560B54/6x Package pinouts and signal descriptions

Table 5. System pin descriptions

Pin number

Port pin Functi on

I/O direction

Bidirectional reset with Schmitt-

RESET

Trigger characteristics and noise

I/O M

filter.

Analog output of the oscillator
amplifier circuit, when the oscillator is

EXTAL

not in bypass mode.
Analog input for the clock generator

I/O X Tristate 36 50 58 N8

when the oscillator is in bypass
mode.

Analog input of the o scillator ampl ifier

XTAL

circuit. Needs to be grounded if

I X Tristate 34 48 56 P8

oscillator bypass mode is used.

1. LBGA208 available only as development package for Nexus2+

RESET

configuration

Pad type

Input weak

pull-up after

RGM PHASE2

and 40 FIRC

cycles

LQFP

100

LQFP

144

LQFP

176

17 21 29 J1

LBGA

(1)

208

Doc ID 15131 Rev 6 19/134

20/134 Doc ID 15131 Rev 6

3.7 Functional port pins

Package pinouts and signal descriptions SPC560B54/6x

The funct ional port pins are listed in

Table 6. Functional port pin descriptions

(1)

Port pin PCR

Table 6

.

Function Peripheral

Alternate function

PA[0] PCR[0]

PA[1] PCR[1]

PA[2] PCR[2]

AF0
AF1
AF2
AF3

—

AF0
AF1
AF2
AF3

—

AF0
AF1
AF2
AF3

—

GPIO[0]

E0UC[0]

CLKOUT

E0UC[13]

WKPU[19]

GPIO[1]

E0UC[1]

(6)

NMI

—

WKPU[2]

GPIO[2]

E0UC[2]

—

MA[2]

WKPU[3]

(5)

5

5

SIUL

eMIOS_0

MC_CGM

eMIOS_0

WKPU

SIUL

eMIOS_0

WKPU

—

WKPU

SIUL

eMIOS_0

—

ADC_0

WKPU

Port A

I/O
I/O

I/O

I/O
I/O

I/O
I/O

(2)

Pad type

I/O direction

O

MTristate121624G4

(3)

RESET

configuration

LQFP

100

LQFP

144

LQFP

176

I

Pin number

I

S Tristate 7 11 19 F3

—

I

—

STristate 5917F2

O

I

LBGA

(4)

208

PA[3] PCR[3]

AF0
AF1
AF2
AF3

—
—

GPIO[3]

E0UC[3]

LIN5TX

CS4_1

EIRQ[0]

ADC1_S[0]

SIUL

eMIOS_0

LINFlex_5

DSPI_1

SIUL

ADC_1

I/O
I/O

O
O

JTristate6890114K15

I
I

Table 6. Functional port pin descriptions (continued)

(1)

SPC560B54/6x Package pinouts and signal descriptions

(2)

(3)

Pin number

Doc ID 15131 Rev 6 21/134

Port pin PCR

PA[4] PCR[4]

PA[5] PCR[5]

PA[6] PCR[6]

PA[7] PCR[7]

AF0
AF1
AF2
AF3

—
—

AF0
AF1
AF2
AF3

AF0
AF1
AF2
AF3

—
—

AF0
AF1
AF2
AF3

—
—

Function Peripheral

I/O direction

Pad type

RESET

configuration

LQFP

100

LQFP

144

LQFP

176

LBGA

(4)

208

Alternate function

GPIO[4]

E0UC[4]

—

CS0_1

LIN5RX

WKPU[9]

GPIO[5]

E0UC[5]

LIN4TX

—

GPIO[6]

E0UC[6]

—

CS1_1
EIRQ[1]
LIN4RX

GPIO[7]

E0UC[7]

LIN3TX

—

EIRQ[2]

ADC1_S[1]

SIUL

eMIOS_0

—

DSPI_1

LINFlex_5

5

WKPU

SIUL

eMIOS_0

LINFlex_4

—

SIUL

eMIOS_0

—

DSPI_1

SIUL

LINFlex_4

SIUL

eMIOS_0

LINFlex_3

—

SIUL

ADC_1

I/O
I/O

—

STristate294351N6

I/O

I
I

I/O
I/O

M Tristate 79 118 146 C11

O

—

I/O
I/O

—

S Tristate 80 119 147 D11

O

I
I

I/O
I/O

O

J Tristate 71 104 128 D16

—

I
I

22/134 Doc ID 15131 Rev 6

Table 6. Functional port pin descriptions (continued)

(1)

(2)

(3)

Pin number

Package pinouts and signal descriptions SPC560B54/6x

Port pin PCR

PA[8] PCR[8]

PA[9] PCR[9]

PA[10] PCR[10]

PA[11] PCR[11]

AF0
AF1
AF2
AF3

N/A

AF0
AF1
AF2
AF3

N/A

AF0
AF1
AF2
AF3

AF0
AF1
AF2
AF3

—

—

—

—
—
—

Alternate function

(7)

Function Peripheral

Pad type

I/O direction

GPIO[8]

E0UC[8]

E0UC[14]

—

EIRQ[3]

ABS[0]
LIN3RX

GPIO[9]

E0UC[9]

—

CS2_1

7

FAB

GPIO[10]

E0UC[10]

SDA

LIN2TX

ADC1_S[2]

GPIO[11]

E0UC[11]

SCL

—

EIRQ[16]

LIN2RX

ADC1_S[3]

SIUL
eMIOS_0
eMIOS_0

—
SIUL
BAM

LINFlex_3

SIUL

eMIOS_0

—

DSPI_1

BAM
SIUL

eMIOS_0

2

I

C_0

LINFlex_2

ADC_1

SIUL

eMIOS_0

2

I

C_0

—
SIUL

LINFlex_2

ADC_1

I/O
I/O
I/O

—

S Input, weak pull-up 72 105 129 C16
I
I
I

I/O
I/O

—

S

O

I

I/O
I/O
I/O

J Tristate 74 107 131 B16

O

I

I/O
I/O
I/O

—

J Tristate 75 108 132 B15
I
I
I

RESET

configuration

Pull-

down

LQFP

100

LQFP

144

LQFP

176

73 106 130 C15

LBGA

(4)

208

Table 6. Functional port pin descriptions (continued)

(1)

SPC560B54/6x Package pinouts and signal descriptions

(2)

(3)

Pin number

Doc ID 15131 Rev 6 23/134

Port pin PCR

PA[12] PCR[12]

PA[13] PCR[13]

PA[14] PCR[14]

PA[15] PCR[15]

AF0
AF1
AF2
AF3

—
—

AF0
AF1
AF2
AF3

AF0
AF1
AF2
AF3

—

AF0
AF1
AF2
AF3

—

Function Peripheral

I/O direction

Pad type

RESET

configuration

LQFP

100

LQFP

144

LQFP

176

LBGA

(4)

208

Alternate function

GPIO[12]

—

E0UC[28]

CS3_1

EIRQ[17]

SIN_0

GPIO[13]

SOUT_0

E0UC[29]

—

GPIO[14]

SCK_0
CS0_0

E0UC[0]

EIRQ[4]

GPIO[15]

CS0_0
SCK_0

E0UC[1]

WKPU[10]

5

SIUL

—

eMIOS_0

DSPI_1

SIUL

DSPI_0

SIUL

DSPI_0

eMIOS_0

—

SIUL
DSPI_0
DSPI_0

eMIOS_0

SIUL

SIUL
DSPI_0
DSPI_0

eMIOS_0

WKPU

I/O

—

I/O

STristate314553T7

O

I
I

I/O

O

MTristate304452R7

I/O

—

I/O
I/O
I/O

MTristate284250P6

I/O

I

I/O
I/O
I/O

MTristate274048R6

I/O

I

PB[0] PCR[16]

AF0
AF1
AF2
AF3

GPIO[16]

CAN0TX

E0UC[30]

LIN0TX

SIUL

FlexCAN_0

eMIOS_0

LINFlex_0

Port B

I/O

I/O

O

MTristate233139N3

O

24/134 Doc ID 15131 Rev 6

Table 6. Functional port pin descriptions (continued)

(1)

(2)

(3)

Pin number

Package pinouts and signal descriptions SPC560B54/6x

Port pin PCR

PB[1] PCR[17]

PB[2] PCR[18]

PB[3] PCR[19]

PB[4] PCR[20]

AF0
AF1
AF2
AF3

—
—
—

AF0
AF1
AF2
AF3

AF0
AF1
AF2
AF3

—
—

AF0
AF1
AF2
AF3

—
—
—

Function Peripheral

I/O direction

Pad type

RESET

configuration

LQFP

100

LQFP

144

LQFP

176

LBGA

(4)

208

Alternate function

GPIO[17]

—

E0UC[31]

—

WKPU[4]

CAN0RX

LIN0RX

GPIO[18]

LIN0TX

SDA

E0UC[30]

GPIO[19]

E0UC[31]

SCL

—

WKPU[11]

LIN0RX

—
—
—

—
ADC0_P[0]
ADC1_P[0]

GPIO[20]

SIUL

—

eMIOS_0

—

5

WKPU

FlexCAN_0

LINFlex_0

SIUL

LINFlex_0

2

I

C_0

eMIOS_0

SIUL

eMIOS_0

2

I

C_0
—

5

WKPU

LINFlex_0

—
—
—

—
ADC_0
ADC_1

SIUL

I/O

—

I/O

—

STristate243240N1
I
I
I

I/O

O

M Tristate 100 144 176 B2

I/O
I/O

I/O
I/O
I/O

STristate 111C3

—

I
I

—
—
—
—

I Tristate 50 72 88 T16
I
I
I

Table 6. Functional port pin descriptions (continued)

(1)

SPC560B54/6x Package pinouts and signal descriptions

(2)

(3)

Pin number

Doc ID 15131 Rev 6 25/134

Port pin PCR

PB[5] PCR[21]

PB[6] PCR[22]

PB[7] PCR[23]

AF0
AF1
AF2
AF3

—
—
—

AF0
AF1
AF2
AF3

—
—
—

AF0
AF1
AF2
AF3

—
—
—

Function Peripheral

I/O direction

Pad type

RESET

configuration

LQFP

100

LQFP

144

LQFP

176

LBGA

(4)

208

Alternate function

—
—
—

—
ADC0_P[1]
ADC1_P[1]

GPIO[21]

—

—

—

—
ADC0_P[2]
ADC1_P[2]

GPIO[22]

—

—

—

—
ADC0_P[3]
ADC1_P[3]

GPIO[23]

—
—
—

—
ADC_0
ADC_1

SIUL

—

—

—

—
ADC_0
ADC_1

SIUL

—

—

—

—
ADC_0
ADC_1

SIUL

—
—
—
—

I Tristate 53 75 91 R16
I
I
I

—
—
—
—

I Tristate 54 76 92 P15
I
I
I

—
—
—
—

I Tristate 55 77 93 P16
I
I
I

26/134 Doc ID 15131 Rev 6

Table 6. Functional port pin descriptions (continued)

(1)

(2)

(3)

Pin number

Package pinouts and signal descriptions SPC560B54/6x

Port pin PCR

PB[8] PCR[24]

PB[9] PCR[25]

PB[10] PCR[26]

AF0
AF1
AF2
AF3

—
—
—
—

AF0
AF1
AF2
AF3

—
—
—
—

AF0
AF1
AF2
AF3

—
—
—

Alternate function

OSC32K_XTAL

WKPU[25]
ADC0_S[0]
ADC1_S[4]

OSC32K_EXTAL

WKPU[26]
ADC0_S[1]
ADC1_S[5]

ADC0_S[2]
ADC1_S[6]

Function Peripheral

GPIO[24]

—
—
—

(8)

5

SIUL

—
—
—

OSC32K

WKPU
ADC_0
ADC_1

GPIO[25]

—
—
—

8

5

SIUL

—
—
—

OSC32K

WKPU
ADC_0
ADC_1

GPIO[26]

—
—
—

WKPU[8]

5

SIUL

—
—
—

WKPU
ADC_0
ADC_1

—
—
—
—

(9)

I

—
—
—
—

I

I/O

—
—
—

I/O direction

Pad type

RESET

LQFP

100

configuration

LQFP

144

LQFP

176

LBGA

208

I

I — 39 53 61 R9

I
I

I

I — 38 52 60 T9

9

I
I

JTristate405462P9
I
I
I

(4)

Table 6. Functional port pin descriptions (continued)

(1)

SPC560B54/6x Package pinouts and signal descriptions

(2)

(3)

Pin number

Doc ID 15131 Rev 6 27/134

Port pin PCR

PB[11] PCR[27]

PB[12] PCR[28]

PB[13] PCR[29]

PB[14] PCR[30]

AF0
AF1
AF2
AF3

—

AF0
AF1
AF2
AF3

—

AF0
AF1
AF2
AF3

—

AF0
AF1
AF2
AF3

—

Function Peripheral

I/O direction

Pad type

RESET

configuration

LQFP

100

LQFP

144

LQFP

176

LBGA

(4)

208

Alternate function

GPIO[27]

E0UC[3]

—

CS0_0

ADC0_S[3]

GPIO[28]

E0UC[4]

—

CS1_0

ADC0_X[0]

GPIO[29]

E0UC[5]

—

CS2_0

ADC0_X[1]

GPIO[30]

E0UC[6]

—

CS3_0

ADC0_X[2]

SIUL

eMIOS_0

—
DSPI_0
ADC_0

SIUL

eMIOS_0

—
DSPI_0
ADC_0

SIUL

eMIOS_0

—
DSPI_0
ADC_0

SIUL

eMIOS_0

—
DSPI_0
ADC_0

I/O
I/O

—

I/O

I/O
I/O

—

O

I/O
I/O

—

O

I/O
I/O

—

O

J Tristate — — 97 N13

I

JTristate6183101M16

I

JTristate6385103M13

I

J Tristate 65 87 105 L16

I

PB[15] PCR[31]

AF0
AF1
AF2
AF3

—

GPIO[31]

E0UC[7]

—

CS4_0

ADC0_X[3]

SIUL

eMIOS_0

—
DSPI_0
ADC_0

I/O
I/O

—

O

J Tristate 67 89 107 L13

I

28/134 Doc ID 15131 Rev 6

Table 6. Functional port pin descriptions (continued)

(1)

(2)

(3)

Pin number

Package pinouts and signal descriptions SPC560B54/6x

Port pin PCR

(10)

PC[0]

PC[1]

PCR[32]

10

PCR[33]

PC[2] PCR[34]

PC[3] PCR[35]

AF0
AF1
AF2
AF3

AF0
AF1
AF2
AF3

AF0
AF1
AF2
AF3

—

AF0
AF1
AF2
AF3

—
—
—

Function Peripheral

I/O direction

Pad type

RESET

configuration

LQFP

100

LQFP

144

LQFP

176

LBGA

(4)

208

Alternate function

Port C

GPIO[32]

—

TDI

—

GPIO[33]

—

TDO

—

GPIO[34]

SCK_1

CAN4TX

DEBUG[0]

EIRQ[5]

GPIO[35]

CS0_1

MA[0]

DEBUG[1]

EIRQ[6]
CAN1RX
CAN4RX

SIUL

—

JTAGC

—

SIUL

—

JTAGC

—

SIUL

DSPI_1

FlexCAN_4

SSCM

SIUL

SIUL
DSPI_1
ADC_0

SSCM

SIUL

FlexCAN_1
FlexCAN_4

I/O

—

M Input, weak pull-up 87 126 154 A8

I

—

I/O

—

(11)

F

O

Tristate 82 121 149 C9

—

I/O
I/O

O

M Tristate 78 117 145 A11

O

I

I/O
I/O

O
O

S Tristate 77 116 144 B11
I
I
I

Table 6. Functional port pin descriptions (continued)

(1)

SPC560B54/6x Package pinouts and signal descriptions

(2)

(3)

Pin number

Doc ID 15131 Rev 6 29/134

Port pin PCR

PC[4] PCR[36]

PC[5] PCR[37]

PC[6] PCR[38]

PC[7] PCR[39]

AF0
AF1
AF2
AF3

—
—
—

AF0
AF1
AF2
AF3

—

AF0
AF1
AF2
AF3

AF0
AF1
AF2
AF3

—
—

Function Peripheral

I/O direction

Pad type

RESET

configuration

LQFP

100

LQFP

144

LQFP

176

LBGA

(4)

208

Alternate function

GPIO[36]

E1UC[31]

—

DEBUG[2]

EIRQ[18]

SIN_1

CAN3RX
GPIO[37]

SOUT_1
CAN3TX

DEBUG[3]

EIRQ[7]

GPIO[38]

LIN1TX

E1UC[28]

DEBUG[4]

GPIO[39]

—

E1UC[29]

DEBUG[5]

LIN1RX

WKPU[12]

SIUL

eMIOS_1

—

SSCM

SIUL

DSPI_1

FlexCAN_3

SIUL

DSPI_1

FlexCAN_3

SSCM

SIUL
SIUL

LINFlex_1

eMIOS_1

SSCM

SIUL

—

eMIOS_1

SSCM

LINFlex_1

5

WKPU

I/O
I/O

—

O

M Tristate 92 131 159 B7
I
I
I

I/O

O
O

M Tristate 91 130 158 A7

O

I

I/O

O

STristate253644R2

I/O

O

I/O

—

I/O

STristate263745P3

O

I
I

30/134 Doc ID 15131 Rev 6

Table 6. Functional port pin descriptions (continued)

(1)

(2)

(3)

Pin number

Package pinouts and signal descriptions SPC560B54/6x

Port pin PCR

PC[8] PCR[40]

PC[9] PCR[41]

PC[10] PCR[42]

PC[11] PCR[43]

AF0
AF1
AF2
AF3

AF0
AF1
AF2
AF3

—
—

AF0
AF1
AF2
AF3

AF0
AF1
AF2
AF3

—
—
—

Function Peripheral

I/O direction

Pad type

RESET

configuration

LQFP

100

LQFP

144

LQFP

176

LBGA

(4)

208

Alternate function

GPIO[40]

LIN2TX

E0UC[3]

DEBUG[6]

GPIO[41]

—

E0UC[7]

DEBUG[7]

WKPU[13]

LIN2RX

GPIO[42]

CAN1TX
CAN4TX

MA[1]

GPIO[43]

—
—

MA[2]

WKPU[5]

CAN1RX
CAN4RX

5

5

SIUL

LINFlex_2

eMIOS_0

SSCM

SIUL

—

eMIOS_0

SSCM

WKPU

LINFlex_2

SIUL
FlexCAN_1
FlexCAN_4

ADC_0

SIUL

—
—

ADC_0

WKPU
FlexCAN_1
FlexCAN_4

I/O

O

S Tristate 99 143 175 A1

I/O

O

I/O

—

I/O

STristate 222B1

O

I
I

I/O

O

MTristate222836M3

O
O

I/O

—
—

O

STristate212735M4
I
I
I