Features
SPC560B54x
SPC560B60x, SPC560B64x
32-bit MCU family built on the Power Architecture
for automotive body electronics applications
®
■ High performance 64 MHz e200z0h CPU
– 32-bit Power A rc hitecture
®
technology CPU
– Up to 60 DMIPs operation
– Variable length encoding (VLE)
■ Memory
– Up to 1.5 MB on-chip Code Flash with ECC
– 64 KB on-chip Data Flash with ECC
– Up to 96 KB on-chip SRAM with ECC
–8-entry MPU
■ Interrupts
– 16 priority levels
– Non-maskable interrupt (NMI)
– Up to 51 external interrupts lines including
27 wake-up lines
■ 16-channel eDMA (linked to PITs, DSPI,
ADCs, eMIOS, LINFlex and I
■ GPIOs: 77 (LQFP100), 121 (LQFP144) and
2
C)
149 (LQFP176)
■ Timer units
– 8-channel 32-bit periodic interrupt timer
– 4-channel 32-bit system timer
– System watchdog timer
– Real-time clock timer
■ eMIOS, 16-bit counter timed I/O units
– Up to 64 channels with PWM/MC/IC/OC
– Up to 10 counter basis
– ADC diagnostic trigger via CTU
■ One 10-bit and one 12-bit ADC with up to 53
channels
– Extendable to 81 channels
– Individual conversion registers
– Cross triggering unit (CTU)
■ Dedicated diagnostic module for lighting
– Advanced PWM generation
– Time-triggered diagnostics
– PWM-synchronized ADC measurements
■ On-chip CAN/UART bootstrap loader
■ Communications interfaces
LQFP144LQFP100 LQFP176
(20 x 20 x 1.4 mm) (24 x 24 x 1.4 mm)(14 x 14 x 1.4 mm)
– Up to 6 FlexCAN (2.0B active) with 64
message buffers each
– Up to 10 LINFlex/UART channels
– Up to 6 buffered DSPI channels
2
–I
C interface
■ Clock generation
– 4 to 16 MHz fast external crystal oscillator
– 32 kHz slow external crystal oscillator
– 16 MHz fast internal RC oscillator
– 128 kHz slow internal RC oscillator for low-
power modes
– Software-controlled FMPLL
– Clock monitoring unit
■ Low-power capabilities
– Several low-power mode configurations
– Ultra-low-power standby with RTC and
communication
– Fast wakeup schemes
■ Exhaustive debugging capability
– Nexus 2+ interface on LBGA208 package
– Nexus 1 on all packages
■ Voltage supply
– Single 5 V or 3.3 V supply
– On-chip voltage regulator
– External ballast resistor support
■ LQFP100, LQFP144, and LQFP176 packages;
LBGA208 package for Nexus2+
■ Operating temperature range -40 to 125 °C
Table 1. Device summary
Package
LQFP176 — SPC560B60L7 SPC560B64L7
LQFP144 SPC560B54L5 SPC560B60L5 SPC560B64L5
LQFP100 SPC560B54L3 SPC560B60L3 —
768 KByte
Code Flash
1 MByte
Code Flash
1.5 MByte
Code Flash
September 2011 Doc ID 15131 Rev 6 1/134
www.st.com
1
Contents SPC560B54/6x
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Pad configuration during reset phases . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Pad configuration during standby mode exit . . . . . . . . . . . . . . . . . . . . . . 17
3.4 Voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.7 Functi onal port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.8 Nexus 2+ pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.1 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.2 NVUSR O register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.2.1 NVUSRO[PAD3V5V] field description . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.2.2 NVUSRO[OSCILLATOR_MARGIN] field description . . . . . . . . . . . . . . . 58
4.2.3 NVUSRO[WATCHDOG_EN] field description . . . . . . . . . . . . . . . . . . . . 58
4.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.4 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.5.1 External ballast resistor recommendations . . . . . . . . . . . . . . . . . . . . . . 61
4.5.2 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.5.3 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.6 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.6.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.6.2 I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.6.3 I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.6.4 Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2/134 Doc ID 15131 Rev 6
SPC560B54/6x Contents
4.6.5 I/O pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.7 RESET electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.8 Power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 80
4.8.1 V oltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 80
4.8.2 Low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . . 83
4.9 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.10 Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.10.1 Program/erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.10.2 Flash power supply DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.10.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.11 Electromagnetic compatibilit y (EM C ) characteristics . . . . . . . . . . . . . . . . 88
4.11.1 Designing hardened software to avoid noise problems . . . . . . . . . . . . . 88
4.11.2 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.11.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 89
4.12 Fast external crystal oscillator (4 to 16 MHz) electrical characteristics . . 90
4.13 Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . 93
4.14 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.15 Fast internal RC oscilla tor (16 MHz) electrical characteristics . . . . . . . . . 96
4.16 Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . 97
4.17 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.17.2 Input impedance and ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.17.3 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.18 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.18.1 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.18.2 DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.18.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.18.4 JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.2.1 LQFP176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.2.2 LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.2.3 LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Doc ID 15131 Rev 6 3/134
Contents SPC560B54/6x
5.2.4 LBGA208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Appendix A Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
4/134 Doc ID 15131 Rev 6
SPC560B54/6x List of tables
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. SPC560B54/6 family comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. SPC560B54/6 series block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Voltage supply pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. System pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Functional port pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Nexus 2+ pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 8. Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 9. PAD3V5V field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 10. OSCILLATOR_MARGIN field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 11. WATCHDOG_EN field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 12. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 13. Recommended operating conditions (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 14. Recommended operating conditions (5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 15. LQFP thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 16. I/O input DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 17. I/O pull-up/pull-down DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 18. SLOW configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 19. MEDIUM configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 67
Table 20. FAST configuration output buffer electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 21. Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 22. I/O supply segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 23. I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 24. I/O weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 25. Reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 26. Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 27. Low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 28. Power consumption on VDD_BV and VDD_HV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 29. Program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 30. Flash module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 31. Flash read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 32. Flash power supply DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 33. Start-up time/Switch-off time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 34. EMI radiated emission measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 35. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 36. Latch-up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 37. Crystal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 38. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics. . . . . . . . . . . . . . . . 92
Table 39. Crystal motional characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 40. Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . 95
Table 41. FMPLL electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 42. Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 96
Table 43. Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . 97
Table 44. ADC input leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 45. ADC_0 conversion characteristics (10-bit ADC_0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 46. ADC_1 conversion characteristics (12-bit ADC_1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 47. On-chip peripherals current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 48. DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Doc ID 15131 Rev 6 5/134
List of tables SPC560B54/6x
Table 49. Nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 50. JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 51. LQFP176 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 52. LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 53. LQFP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 54. LBGA208 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 55. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 56. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
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SPC560B54/6x List of figures
List of figures
Figure 1. SPC560B54/6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 2. LQFP176 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3. LQFP144 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. LQFP100 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5. LBGA208 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6. I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 7. Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 8. Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 9. Voltage regulator capacitance connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 10. Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 11. Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 12. Fast external crystal oscillator (4 to 16 MHz) timing diagram. . . . . . . . . . . . . . . . . . . . . . . 92
Figure 13. Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 14. lEquivalent circuit of a quartz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 15. Slow external crystal oscillator (32 kHz) timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 16. ADC_0 characteristic and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 17. Input equivalent circuit (precise channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 18. Input equivalent circuit (extended channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 19. Transient behavior during sampling phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 20. Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 21. ADC_1 characteristic and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 22. DSPI classic SPI timing — master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 23. DSPI classic SPI timing — master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 24. DSPI classic SPI timing — slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 25. DSPI classic SPI timing — slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 26. DSPI modified transfer format timing — master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 27. DSPI modified transfer format timing — master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 28. DSPI modified transfer format timing — slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 29. DSPI modified transfer format timing — slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 30. DSPI PCS strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 31. Nexus TDI, TMS, TDO timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 32. Timing diagram — JTAG boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 33. LQFP176 package mechanical drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 34. LQFP144 package mechanical drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 35. LQFP100 package mechanical drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 36. LBGA208 package mechanical drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 37. Commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Doc ID 15131 Rev 6 7/134
Introduction SPC560B54/6x
1 Introduction
1.1 Document overview
This document describes the features of the family and options available within the family
members, and highlights important electrical and physical characteristics of the device.
1.2 Description
This family of 32-bit system-on-chip (SoC) microcontrollers is the latest achievement in
integrated automotive application controllers. It belongs to an expanding family of
automotive-focused products designed to address the next wave of body electronics
applications within the vehicle.
The advanced and cost-efficient e200z0h host processor core of this automotive controller
family complies with the Power Architecture technology and only implements the VLE
(variable-length encoding) APU (Auxiliary Processor Unit), providing improved code density.
It operates at speeds of up to 64 MHz and offers high performance processing optimized for
low power consumption. It capitalizes on the available development infrastructure of current
Power Architecture devices and is supported with software drivers, operating systems and
configuration code to assist with users implementations.
Table 2. SPC560B54/6 family comparison
(1)
Feature SPC560B54 SPC560B60 SPC560B64
CPU e200z0h
Execution speed
Code flash memory 768 KB 1 MB 1.5 MB
Data flash memory 64 (4
SRAM 64 KB 80 KB 96 KB
MPU 8-entry
eDMA 16 ch
10-bit ADC Yes
shared with 12-bit ADC 19 ch
12-bit ADC Yes
shared with 10-bit ADC 19 ch
Total timer I/O
Counter / OPWM /
(2)
dedicated
dedicated
(5)
eMIOS
ICOC
Up to 64 MHz
× 16) KB
(3)
7 ch 15 ch 7 ch 15 ch 29 ch 15 ch 29 ch 29 ch
(4)
(6)
37 ch,
16-bit
64 ch,
16-bit
37 ch,
16-bit
64 ch,
16-bit
5 ch
10 ch
64 ch,
16-bit
64 ch,
16-bit
64 ch,
16-bit
64 ch,
16-bit
O(I)PWM / OPWFMB /
OPWMCB / ICOC
8/134 Doc ID 15131 Rev 6
(7)
7ch
SPC560B54/6x Introduction
Table 2. SPC560B54/6 family comparison
(1)
(continued)
Feature SPC560B54 SPC560B60 SPC560B64
O(I)PWM / ICOC
OPWM / ICOC
(8)
7 ch 14 ch 7 ch 14 ch 14 ch 14 ch 14 ch 14 ch
(9)
13 ch 33 ch 13 ch 33 ch 33 ch 33 ch 33 ch 33 ch
SCI (LINFlex) 48481081010
SPI (DSPI) 3535656 6
CAN (FlexCAN) 6
2
I
C1
32 KHz oscillator Yes
(10)
GPIO
77 121 77 121 149 121 149 149
Debug JTAG N2+
Package LQFP100 LQFP144 LQFP100 LQFP144 LQFP176 LQFP144 LQFP176
1. Feature set dependent on selected peripheral multiplexing; table shows example
2. Based on 125 °C ambient operating temperature
3. Not shared with 12-bit ADC, but possibly shared with other alternate functions
4. Not shared with 10-bit ADC, but possibly shared with other alternate functions
5. See the eMIOS section of the chip reference manual for information on the channel configuration and functions.
6. Each channel supports a range of modes including Modulus counters, PWM generation, Input Capture, Output Compare.
7. Each channel supports a range of modes including PWM generation with dead time, Input Capture, Output Compare.
8. Each channel supports a range of modes including PWM generation, Input Capture, Output Compare, Period and Pulse
width measurement.
9. Each channel supports a range of modes including PWM generation, Input Capture, and Output Compare.
10. Maximum I/O count based on multiplexing with peripherals
11. LBGA208 available only as development package for Nexus2+
LBGA208
(11)
Doc ID 15131 Rev 6 9/134
Block diagram SPC560B54/6x
2 Block diagram
Figure 1
shows a top-level block diagram of the SPC560B54/6.
Figure 1. SPC560B54/6 block diagram
JTAG
JTAG Port
Nexus Port
NMI
Clocks
Interrupt
Request
Nexus
Voltage
Regulator
FMPLL
RTC
SIUL
Reset Control
External
Interrupt
Request
IMUX
GPIO &
Pad Control
NMI
SIUL
Interrupt requests
from peripheral
blocks
CMU
SWT
19 ch 10-bit/12-bit
ADC
5 ch 12-bit
ECSM
ADC
e200z0h
Nexus 2+
PITSTM
29 ch 10-bit
ADC
INTC
Instructions
(Master)
Data
(Master)
MPU
Registers
Peripheral Bridge
CTU
(Master)
64 ch
eMIOS
eDMA
64-bit 2 x 3 Crossbar Switch
MPU
10 x
LINFlex
SRAM
96 KB
SRAM
Controller
(Slave)
(Slave)
MC_PCUMC_MEMC_CGMMC_RGM
DSPI
Code Flash
6 x
1.5 MB
WKPU
BAM
I2C
Data Flash
Flash
Controller
(Slave)
request with
functionality
SSCM
FlexCAN
64 KB
Interrupt
wakeup
6 x
I/O
Legend:
ADC Analog-to-Digital Converter
BAM Boot Assist Module
CMU Clock Monitor Unit
CTU Cross Triggering Unit
DSPI Deserial Serial Peripheral Interface
ECSM Error Correction Status Module
eDMA Enhanced Direct Memory Access
eMIOS Enhanced Modular Input Output System
Flash Flash memory
FlexCAN Controller Area Network
FMPLL Frequency-Modulated Phase-Locked Loop
GPIO General-purpose input/output
2
C Inter-Integrated Circuit bus
I
IMUX Internal Multiplexer
INTC Interrupt Controller
JTAG JTAG controller
LINFlex Serial Communication Interface (LIN support)
. . .
. . .
10/134 Doc ID 15131 Rev 6
. . .
MC_CGM Clock Generation Module
MC_ME Mode Entry Module
MC_PCU Power Control Unit
MC_RGM Reset Generation Module
MPU Memory Protection Unit
NMI Non-Maskable Interrupt
PIT Periodic Interrupt Timer
RTC Real-Time Clock
SIUL System Integration Unit Lite
SRAM Stati c Rand om -A cce ss Memory
SSCM System Status Configuration Module
STM System Timer Module
SWT Software Watchdog Timer
VREG Voltage regulator
WKPU Wakeup Unit
XBAR Crossbar switch
. . .
. . .
SPC560B54/6x Block diagram
Table 3
Table 3. SPC560B54/6 series block summary
summarizes the functions of the blocks present on the SPC560B54/6.
Block Function
Analog-to-digital converter (ADC) Converts analog voltages to digital values
Boot assist module (BAM)
Clock gener ati on mo dul e
(MC_CGM)
A block of read-only memory containing VL E c ode w hi ch is executed according
to the boot mode of the device
Provides logic and control requi red for the generation of system and peripheral
clocks
Clock monitor unit (CMU) Monitors clock source (internal and external) integrity
Cross triggering unit (CTU)
Enables synchro nization of ADC c onve rsions with a timer ev ent from th e eMIOS
or from the PIT
Supports simultaneous connections between two master ports and three slave
Crossbar switch (XBAR)
ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width.
Deserial serial peripheral
interface (DSPI)
Enhanced Dir ect Me mory Access
(eDMA)
Enhanced modular input output
system (eMIOS)
Provides a synchronous serial interface for communication with external
devices
Performs complex data transfers with minimal intervention from a host
n
processor via “
” programmable channels
Provides the functionality to generate or measure events
Provides a myriad of miscellaneous control functions for the device including
Error Correction Status Module
(ECSM)
program-visible information about configuration and revision levels, a reset
status register, wakeup control for exiting sleep modes, and optional features
such as information on memory errors reported by error-correcting codes
Flash memory Provides non-volatile storage for program code, constants and variables
FlexCAN (controller area
network)
Frequency-modulated phase-
locked loop (FMPLL)
Inter-integrated circuit (I2C™) bus
Internal multiplexer (IMUX) SIU
subblock
Supports the standard CAN communications protocol
Generates high-speed system clocks and supports programmable frequency
modulation
A two wire bidirectional se rial bus t hat provide s a simple and efficient me thod of
data exchange between devices
Allows flexible mapping of peripheral in terface on the different p ins of the devi ce
Interrupt controller (INTC) Provides priority-based preemptive scheduling of interrupt requests
JTAG controller (JTAGC)
LINFlex co ntr ol ler
Memory protection unit (MPU)
Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
Manages a high number of LIN (Local Interconnect Network protocol)
messages efficiently with a minimum of CPU load
Provides hardware access control for all memory references generated in a
device
Provides a mechanism for controlling the device operational mode and
Mode entry module (MC_ME)
modetransition sequences in all functional states; also manages the power
control unit, reset generation module and clock generation module, and holds
the configuration, control and status registers accessible for applications
Doc ID 15131 Rev 6 11/134
Block diagram SPC560B54/6x
Table 3. SPC560B54/6 series block summary (continued)
Block Function
Non-Maskable Interrupt (NMI)
Handles external events that must produce an immediate response, such as
power down detection
Periodic interrupt timer (PIT) Produces periodic interrupts and triggers
Reduces the overall power consumption by disconnecting parts of the device
Power control unit (MC_PCU)
from the power supply via a power switching device; device components are
grouped into sections called “power domains” which are controlled by the PCU
A free running counter used for time keeping applications, the RTC can be
Real-time counter (RTC)
configured to generate an interrupt at a predefined interval independent of the
mode of operation (run mode or low-power mode)
Reset generation module
(MC_RGM)
Static random-access memory
(SRAM)
Centralizes reset sources and manages the device reset sequence of the
device
Provides storage for program code, constants, and variables
Provides control over all the electrical pad controls and up 32 ports with 16 bits
System integrati on uni t lite (SIUL)
of bidirectional, ge neral-pu rpose input and o utput sign als and supports up to 32
external interrupts with trigger event configuration
System status and configuration
module (SSCM)
System timer module (STM)
Provides system configuration and status data (such as memory size and
status, device mode and security status), device identification data, debug
status port enable and selection, and bus and peripheral abort enable/disable
Provides a set of output compare events to support AUTOSAR (AUTomotive
Open System ARchitecture) and operating system tasks
System watchdog timer (SWT) Provides protection from runaway code
WKPU (wakeup unit)
The wakeup unit supports up to 27 external sources that can generate
interrupts or wakeup events, of which 1 can cause non-maskable interrupt
requests or wakeup events.
12/134 Doc ID 15131 Rev 6
SPC560B54/6x Package pinouts and signal descriptions
3 Package pinouts and signal descriptions
3.1 Package pinouts
The available LQFP pinouts and the ballmap are provided in the following figures. For pin
signal descriptions, please see
Figure 2
shows the SPC560B54/6 in the LQFP176 package.
Figure 2. LQFP176 pin configuration
PB[2]
PC[8]
PC[13]
PC[12]
PI[0]
PI[1]
PI[2]
PI[3]
PE[7]
PE[6]
PH[8]
PH[7]
PH[6]
PH[5]
176
175
174
173
172
171
170
169
168
167
166
165
164
PB[3]
PC[9]
PC[14]
PC[15]
PJ[4]
VDD_HV
VSS_HV
PH[15]
PH[13]
PH[14]
PI[6]
PI[7]
PG[5]
PG[4]
PG[3]
PG[2]
PA[2]
PE[0]
PA[1]
PE[1]
PE[8]
PE[9]
PE[10]
PA[0]
PE[11]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PG[9]
PG[8]
PC[11]
PC[10]
PG[7]
PG[6]
PB[0]
PB[1]
PF[9]
PF[8]
PF[12]
PC[6]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45464748495051525354555657585960616263646566676869707172737475767778798081828384858687
163
Table 6
PH[4]
PE[5]
PE[4]
PC[4]
162
161
160
159
PC[5]
PE[3]
PE[2]
158
157
156
155
LQFP176
Top view
.
PH[9]
PC[0]
VSS_LV
VDD_LV
VDD_HV
VSS_HV
PC[1]
PH[10]
PA[6]
PA[5]
PC[2]
PC[3]
PI[4]
PI[5]
PH[12]
PH[11]
PG[11]
PG[10]
PE[15]
PE[14]
PG[15]
PG[14]
PE[12]
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PA[11]
132
PA[10]
131
PA[9]
130
PA[8]
129
PA[7]
128
PE[13]
127
PF[14]
126
PF[15]
125
VDD_HV
124
VSS_HV
123
PG[0]
122
PG[1]
121
PH[3]
120
PH[2]
119
PH[1]
118
PH[0]
117
PG[12]
116
PG[13]
115
PA[3]
114
PI[13]
113
PI[12]
112
PI[11]
111
PI[10]
110
PI[9]
109
PI[8]
108
PB[15]
107
PD[15]
106
PB[14]
105
PD[14]
104
PB[13]
103
PD[13]
102
PB[12]
101
PD[12]
100
VDD_HV_ADC1
99
VSS_HV_ADC1
98
PB[11]
97
96
PD[11]
95
PD[10]
94
PD[9]
93
PB[7]
92
PB[6]
91
PB[5]
90
VDD_HV_ADC0
89
VSS_HV_ADC0
88
PJ[3]
PJ[2]
PJ[1]
PC[7]
PF[10]
PA[4]
PA[15]
PA[14]
PF[11]
PF[13]
XTAL
PA[13]
PA[12]
EXTAL
VSS_LV
VDD_LV
VSS_HV
PF[0]
PF[1]
PF[2]
PF[3]
PF[4]
PF[5]
PB[9]
PB[8]
PB[10]
VDD_HV
PF[6]
PJ[0]
PF[7]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PI[15]
PI[14]
PD[6]
PB[4]
PD[7]
PD[8]
VSS_HV
VDD_HV
Doc ID 15131 Rev 6 13/134
Package pinouts and signal descriptions SPC560B54/6x
Figure 3
shows the SPC560B54/6 in the LQFP144 package.
Figure 3. LQFP144 pin configuration
PB[2]
PC[8]
PC[13]
PC[12]
PE[7]
PE[6]
PH[8]
PH[7]
PH[6]
PH[5]
PH[4]
PE[5]
PE[4]
PC[4]
PC[5]
PE[3]
PE[2]
PH[9]
PC[0]
VSS_LV
VDD_LV
VDD_HV
VSS_HV
PC[1]
PH[10]
PA[6]
PA[5]
PC[2]
PC[3]
PG[11]
PG[10]
PE[15]
PE[14]
PG[15]
PG[14]
PE[12]
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
72
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
PE[13]
PF[14]
PF[15]
VDD_HV
VSS_HV
PG[0]
PG[1]
PH[3]
PH[2]
PH[1]
PH[0]
PG[12]
PG[13]
PA[3]
PB[15]
PD[15]
PB[14]
PD[14]
PB[13]
PD[13]
PB[12]
VDD_HV_ADC1
VSS_HV_ADC1
PD[11]
PD[10]
PD[9]
PB[7]
PB[6]
PB[5]
VDD_HV_ADC0
VSS_HV_ADC0
PB[3]
PC[9]
PC[14]
PC[15]
PG[5]
PG[4]
PG[3]
PG[2]
PA[2]
PE[0]
PA[1]
PE[1]
PE[8]
PE[9]
PE[10]
PA[0]
PE[11]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PG[9]
PG[8]
PC[11]
PC[10]
PG[7]
PG[6]
PB[0]
PB[1]
PF[9]
PF[8]
PF[12]
PC[6]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
3738394041424344454647484950515253545556575859606162636465666768697071
LQFP144
Top view
PC[7]
Figure 4
PA[4]
PA[15]
PA[14]
PF[10]
PF[11]
PA[13]
PF[13]
XTAL
PA[12]
VDD_LV
EXTAL
VSS_LV
VSS_HV
VDD_HV
shows the SPC560B54/6 in the LQFP100 package.
PF[0]
PF[1]
PF[2]
PF[3]
PF[4]
PB[9]
PB[8]
PB[10]
PF[5]
14/134 Doc ID 15131 Rev 6
PF[6]
PF[7]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PB[4]
PD[6]
PD[7]
PD[8]
SPC560B54/6x Package pinouts and signal descriptions
Figure 4. LQFP100 pin configuration
PB[2]
PC[8]
PC[13]
PC[12]
PE[7]
PE[6]
PE[5]
PE[4]
PC[4]
PC[5]
PE[3]
PE[2]
PH[9]
PC[0]
VSS_LV
VDD_LV
VDD_HV
VSS_HV
PC[1]
PH[10]
PA[6]
PA[5]
PC[2]
PC[3]
PE[12]
PB[3]
PC[9]
PC[14]
PC[15]
PA[2]
PE[0]
PA[1]
PE[1]
PE[8]
PE[9]
PE[10]
PA[0]
PE[11]
VSS_HV
VDD_HV
VSS_HV
RESET
VSS_LV
VDD_LV
VDD_BV
PC[11]
PC[10]
PB[0]
PB[1]
PC[6]
9998979695949392919089888786858483828180797877
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26272829303132333435363738394041424344454647484950
PA[4]
PC[7]
PA[15]
PA[14]
PA[13]
PA[12]
VSS_LV
VDD_LV
LQFP100
Top view
XTAL
EXTAL
VSS_HV
VDD_HV
PB[9]
PB[8]
PD[0]
PD[1]
PD[2]
PD[3]
PB[10]
PD[4]
76
PA[11]
75
PA[10]
74
PA[9]
73
PA[8]
72
PA[7]
71
VDD_HV
70
VSS_HV
69
PA[3]
68
PB[15]
67
PD[15]
66
PB[14]
65
PD[14]
64
PB[13]
63
PD[13]
62
PB[12]
61
VDD_HV_ADC1
60
VSS_HV_ADC1
59
PD[11]
58
PD[10]
57
PD[9]
56
PB[7]
55
PB[6]
54
PB[5]
53
VDD_HV_ADC0
52
VSS_HV_ADC0
51
PD[5]
PB[4]
PD[6]
PD[7]
PD[8]
Figure 5
shows the SPC560B54/6 in the LBGA208 package.
Doc ID 15131 Rev 6 15/134
Package pinouts and signal descriptions SPC560B54/6x
Figure 5. LBGA208 configuration
1 2345678910111213141516
PC[8] PC[13] PH[15] PJ[4] PH[8] PH[4] PC[5] PC[0] PI[0] PI[1] PC[2] PI[4] PE[15] PH[11] NC NC
A
A
PC[9] PB[2] PH[13] PC[12] PE[6] PH[5] PC[4] PH[9] PH[10] PI[2] PC[3] PG[11] PG[15] PG[14] PA[11] PA[10]
B
VDD_H
PC[14]
C
PH[14] PI[6] PC[15] PI[7] PH[6] PE[4] PE[2] VDD_LV
D
PG[4] PG[5] PG[3] PG[2] PG[1] PG[0] PF[15]
E
PE[0] PA[2] PA[1] PE[1] PH[0] PH[1] PH[3] PH[2]
F
PE[9] PE[8] PE[10] PA[0]
G
VSS_HV PE[11]
H
RESET VSS_LV NC NC
J
EVTI NC
K
PG[9] PG[8] NC EVTO PB[15] PD[15] PD[14] PB[14]
L
PG[7] PG[6] PC[10] PC[11] PB[13] PD[13] PD[12] PB[12]
M
PB[1] PF[9] PB[0]
N
PF[8] PJ[3] PC[7] PJ[2] PJ[1] PA[14] VDD_LV XTAL PB[10] PF[1] PF[5] PD[0] PD[3]
P
PB[3] PE[7] PH[7] PE[5] PE[3] VSS_LV PC[1] PI[3] PA[5] PI[5] PE[14] PE[12] PA[9] PA[8]
V
VDD_H
V
VDD_B
V
NC
VDD_LV
VDD_H
V
VSS_HVVSS_HVVSS_HVVSS_H
VSS_HVVSS_HVVSS_HVVSS_H
VSS_HVVSS_HVVSS_HVVSS_H
VSS_HVVSS_HVVSS_HVVSS_H
PJ[0] PA[4] VSS_LV EXTAL
VDD_H
VDD_H
NC PA[6] PH[12] PG[10] PF[14] PE[13] PA[7]
V
VDD_H
PI[12] PI[13] MSEO
V
MDO3 MDO2 MDO0 MDO1
PI[8] PI[9] PI[10] PI[11]
VDD_H
V_ADC1PG[12] PA[3] PG[13]
VDD_H
V_ADC0PB[6] PB[7]
V
V
V
V
V
PF[0] PF[4]
VSS_H
V_ADC1PB[11] PD[10] PD[9] PD[11]
VDD_H
V
B
C
D
E
F
G
H
J
K
L
M
N
P
PF[12] PC[6] PF[10] PF[11]
R
NC NC NC MCKO NC PF[13] PA[12] PI[15]
T
VDD_H
PA[15] PA[13] PI[14] XTAL32 PF[3] PF[7] PD[2] PD[4] PD[7]
V
EXTAL
PF[2] PF[6] PD[1] PD[5] PD[6] PD[8] PB[4]
32
VSS_H
V_ADC0PB[5]
1 2345678910111213141516
NOTE: The LBGA208 is available only as dev elopment package for Nexus 2+.
= Not connected
NC
3.2 Pad configuration during reset phases
All pads have a fixed configuration under reset.
During the power-up phase, all pads are forced to tristate.
After power-up phase, all pads are tristate with the following exceptions:
● PA[9] (FAB) is pull-down. Without external strong pull-up the device starts fetching from
flash.
● PA[8], PC[0] and PH[9:10] are in input weak pull-up when out of reset.
● RESET pad is driven low by the device till 40 FIRC clock cycles after phase2
completion. Minimum phase3 duration is 40 FIRC cycles.
● Nexus output pads (MDO[n], MCKO, EVTO, MSEO) are forced to output.
R
T
16/134 Doc ID 15131 Rev 6
SPC560B54/6x Package pinouts and signal descriptions
3.3 Pad configuration during standby mode exit
Pad configuration (input buffer enable, pull enable) for low-power wakeup pads is controlled
by both the SIUL and WKPU modules. During standby exit, all low power pads
PA[0,1,2,4,15], PB[1,3,8,9,10]
PG[3,5,7,9]
b
, PI[1,3]
(c)
are configured according to their respective configuration done in the
(a)
, PC[7,9,11], PD[0,1], PE[0,9,11], PF[9,11,13]
(b)
,
WKPU module. All other pads will have the same configuration as expected after a reset.
The TDO pad has been moved into the STANDBY domain in order to allow low-power
debug handshaking in STANDBY mode. However, no pull-resistor is active on the TDO pad
while in STANDBY mode. At this time the pad is configured as an input. When no debugger
is connected the TDO pad is floating causing additional current consumption.
To avoid the extra consumption TDO must be connected. An external pull-up resistor in the
range of 47–100 kOhms should be added between the TDO pin and VDD. Only if the TDO
pin is used as an application pin and a pull-up cannot be used should a pull-down resistor
with the same value be used instead between the TDO pin and GND.
3.4 Voltage supply pins
Voltage supply pins are used to provide power to the device. Three dedicated
VDD_LV/VSS_LV supply pairs are used for 1.2 V regulator stabilization.
Table 4. Voltage supply pin descriptions
Pin number
Port pin Function
LQFP100 LQFP144 LQFP176 LBGA208
15, 37, 70, 84 19, 51, 100,
VDD_HV Digital supply voltage
14, 16, 35,
69, 83
VSS_HV Digital ground
1.2 V decoupling pins. Decoupling
VDD_LV
VSS_LV
VDD_BV Internal regulator supply voltage 20 24 32 K3
capacitor must be connected
between these pins and the
nearest V
1.2 V decoupling pins. Decoupling
capacitor must be connected
between these pins and the
nearest V
SS_LV
DD_LV
pin.
pin.
(1)
1
19, 32, 85 23, 46, 124
18, 33, 86 22, 47, 125
123
18, 20, 49,
99, 122
6, 27, 59, 85,
124, 151
7, 26, 28, 57,
86, 123, 150
31, 54, 152
30, 55, 153
C2, D9, E16,
G13, H3, N4,
N9, R5
G7, G8, G9,
G10, H7, H8,
H9, H10, J7,
J8, J9, J10,
K7, K8, K9,
K10
D8, K4, P7
C8, J2, N7
a. PB[8, 9] ports have wakeup functionality in all modes except STANDBY.
b. PF[9,11,13], PG[3,5,7,9], PI[1,3] are not available in the 100-pin LQFP.
c. PI[1,3] are not available in the 144-pin LQFP.
Doc ID 15131 Rev 6 17/134
Package pinouts and signal descriptions SPC560B54/6x
Table 4. Voltage supply pin descriptions (continued)
Pin number
Port pin Function
LQFP100 LQFP144 LQFP176 LBGA208
Reference ground and analog
VSS_HV_ADC0
VDD_HV_ADC0
VSS_HV_ADC1
VDD_HV_ADC1
1. A decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage
(see the recommended operating conditions in the device datasheet).
ground for the A/D converter 0 (10bit)
Reference voltage and analog
supply for the A/D converter 0 (10bit)
Reference ground and analog
ground for the A/D converter 1 (12bit)
Reference voltage and analog
supply for the A/D converter 1 (12bit)
51 73
52 74
59 81
60 82
R15
89
P14
90
N12
98
K13
99
3.5 Pad types
In the device the following types of pads are available for system pins and functional port
pins:
S = Slow
M = Mediumd
F = Fastd
I = Input only with analog feature
J = Input/Output (‘S’ pad) with analog feature
X = Oscillator
(d)
(e)
e
d
3.6 System pins
The system pins are listed in
d. See the I/O pad electrical characteristics in the chip datasheet for details.
e. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium.
The only exception is PC[1] which is in medium configuration by default (see the PCR.SRC description in the
chip reference manual, Pad Configuration Registers (PCR0–PCR148)).
18/134 Doc ID 15131 Rev 6
Table 5
.
SPC560B54/6x Package pinouts and signal descriptions
Table 5. System pin descriptions
Pin number
Port pin Functi on
I/O direction
Bidirectional reset with Schmitt-
RESET
Trigger characteristics and noise
I/O M
filter.
Analog output of the oscillator
amplifier circuit, when the oscillator is
EXTAL
not in bypass mode.
Analog input for the clock generator
I/O X Tristate 36 50 58 N8
when the oscillator is in bypass
mode.
Analog input of the o scillator ampl ifier
XTAL
circuit. Needs to be grounded if
I X Tristate 34 48 56 P8
oscillator bypass mode is used.
1. LBGA208 available only as development package for Nexus2+
RESET
configuration
Pad type
Input weak
pull-up after
RGM PHASE2
and 40 FIRC
cycles
LQFP
100
LQFP
144
LQFP
176
17 21 29 J1
LBGA
(1)
208
Doc ID 15131 Rev 6 19/134
20/134 Doc ID 15131 Rev 6
3.7 Functional port pins
Package pinouts and signal descriptions SPC560B54/6x
The funct ional port pins are listed in
Table 6. Functional port pin descriptions
(1)
Port pin PCR
Table 6
.
Function Peripheral
Alternate function
PA[0] PCR[0]
PA[1] PCR[1]
PA[2] PCR[2]
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
—
GPIO[0]
E0UC[0]
CLKOUT
E0UC[13]
WKPU[19]
GPIO[1]
E0UC[1]
(6)
NMI
—
WKPU[2]
GPIO[2]
E0UC[2]
—
MA[2]
WKPU[3]
(5)
5
5
SIUL
eMIOS_0
MC_CGM
eMIOS_0
WKPU
SIUL
eMIOS_0
WKPU
—
WKPU
SIUL
eMIOS_0
—
ADC_0
WKPU
Port A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
(2)
Pad type
I/O direction
O
MTristate121624G4
(3)
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
I
Pin number
I
S Tristate 7 11 19 F3
—
I
—
STristate 5917F2
O
I
LBGA
(4)
208
PA[3] PCR[3]
AF0
AF1
AF2
AF3
—
—
GPIO[3]
E0UC[3]
LIN5TX
CS4_1
EIRQ[0]
ADC1_S[0]
SIUL
eMIOS_0
LINFlex_5
DSPI_1
SIUL
ADC_1
I/O
I/O
O
O
JTristate6890114K15
I
I
Table 6. Functional port pin descriptions (continued)
(1)
SPC560B54/6x Package pinouts and signal descriptions
(2)
(3)
Pin number
Doc ID 15131 Rev 6 21/134
Port pin PCR
PA[4] PCR[4]
PA[5] PCR[5]
PA[6] PCR[6]
PA[7] PCR[7]
AF0
AF1
AF2
AF3
—
—
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
—
—
AF0
AF1
AF2
AF3
—
—
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
GPIO[4]
E0UC[4]
—
CS0_1
LIN5RX
WKPU[9]
GPIO[5]
E0UC[5]
LIN4TX
—
GPIO[6]
E0UC[6]
—
CS1_1
EIRQ[1]
LIN4RX
GPIO[7]
E0UC[7]
LIN3TX
—
EIRQ[2]
ADC1_S[1]
SIUL
eMIOS_0
—
DSPI_1
LINFlex_5
5
WKPU
SIUL
eMIOS_0
LINFlex_4
—
SIUL
eMIOS_0
—
DSPI_1
SIUL
LINFlex_4
SIUL
eMIOS_0
LINFlex_3
—
SIUL
ADC_1
I/O
I/O
—
STristate294351N6
I/O
I
I
I/O
I/O
M Tristate 79 118 146 C11
O
—
I/O
I/O
—
S Tristate 80 119 147 D11
O
I
I
I/O
I/O
O
J Tristate 71 104 128 D16
—
I
I
22/134 Doc ID 15131 Rev 6
Table 6. Functional port pin descriptions (continued)
(1)
(2)
(3)
Pin number
Package pinouts and signal descriptions SPC560B54/6x
Port pin PCR
PA[8] PCR[8]
PA[9] PCR[9]
PA[10] PCR[10]
PA[11] PCR[11]
AF0
AF1
AF2
AF3
N/A
AF0
AF1
AF2
AF3
N/A
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
—
—
—
—
—
—
Alternate function
(7)
Function Peripheral
Pad type
I/O direction
GPIO[8]
E0UC[8]
E0UC[14]
—
EIRQ[3]
ABS[0]
LIN3RX
GPIO[9]
E0UC[9]
—
CS2_1
7
FAB
GPIO[10]
E0UC[10]
SDA
LIN2TX
ADC1_S[2]
GPIO[11]
E0UC[11]
SCL
—
EIRQ[16]
LIN2RX
ADC1_S[3]
SIUL
eMIOS_0
eMIOS_0
—
SIUL
BAM
LINFlex_3
SIUL
eMIOS_0
—
DSPI_1
BAM
SIUL
eMIOS_0
2
I
C_0
LINFlex_2
ADC_1
SIUL
eMIOS_0
2
I
C_0
—
SIUL
LINFlex_2
ADC_1
I/O
I/O
I/O
—
S Input, weak pull-up 72 105 129 C16
I
I
I
I/O
I/O
—
S
O
I
I/O
I/O
I/O
J Tristate 74 107 131 B16
O
I
I/O
I/O
I/O
—
J Tristate 75 108 132 B15
I
I
I
RESET
configuration
Pull-
down
LQFP
100
LQFP
144
LQFP
176
73 106 130 C15
LBGA
(4)
208
Table 6. Functional port pin descriptions (continued)
(1)
SPC560B54/6x Package pinouts and signal descriptions
(2)
(3)
Pin number
Doc ID 15131 Rev 6 23/134
Port pin PCR
PA[12] PCR[12]
PA[13] PCR[13]
PA[14] PCR[14]
PA[15] PCR[15]
AF0
AF1
AF2
AF3
—
—
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
—
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
GPIO[12]
—
E0UC[28]
CS3_1
EIRQ[17]
SIN_0
GPIO[13]
SOUT_0
E0UC[29]
—
GPIO[14]
SCK_0
CS0_0
E0UC[0]
EIRQ[4]
GPIO[15]
CS0_0
SCK_0
E0UC[1]
WKPU[10]
5
SIUL
—
eMIOS_0
DSPI_1
SIUL
DSPI_0
SIUL
DSPI_0
eMIOS_0
—
SIUL
DSPI_0
DSPI_0
eMIOS_0
SIUL
SIUL
DSPI_0
DSPI_0
eMIOS_0
WKPU
I/O
—
I/O
STristate314553T7
O
I
I
I/O
O
MTristate304452R7
I/O
—
I/O
I/O
I/O
MTristate284250P6
I/O
I
I/O
I/O
I/O
MTristate274048R6
I/O
I
PB[0] PCR[16]
AF0
AF1
AF2
AF3
GPIO[16]
CAN0TX
E0UC[30]
LIN0TX
SIUL
FlexCAN_0
eMIOS_0
LINFlex_0
Port B
I/O
I/O
O
MTristate233139N3
O
24/134 Doc ID 15131 Rev 6
Table 6. Functional port pin descriptions (continued)
(1)
(2)
(3)
Pin number
Package pinouts and signal descriptions SPC560B54/6x
Port pin PCR
PB[1] PCR[17]
PB[2] PCR[18]
PB[3] PCR[19]
PB[4] PCR[20]
AF0
AF1
AF2
AF3
—
—
—
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
—
—
AF0
AF1
AF2
AF3
—
—
—
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
GPIO[17]
—
E0UC[31]
—
WKPU[4]
CAN0RX
LIN0RX
GPIO[18]
LIN0TX
SDA
E0UC[30]
GPIO[19]
E0UC[31]
SCL
—
WKPU[11]
LIN0RX
—
—
—
—
ADC0_P[0]
ADC1_P[0]
GPIO[20]
SIUL
—
eMIOS_0
—
5
WKPU
FlexCAN_0
LINFlex_0
SIUL
LINFlex_0
2
I
C_0
eMIOS_0
SIUL
eMIOS_0
2
I
C_0
—
5
WKPU
LINFlex_0
—
—
—
—
ADC_0
ADC_1
SIUL
I/O
—
I/O
—
STristate243240N1
I
I
I
I/O
O
M Tristate 100 144 176 B2
I/O
I/O
I/O
I/O
I/O
STristate 111C3
—
I
I
—
—
—
—
I Tristate 50 72 88 T16
I
I
I
Table 6. Functional port pin descriptions (continued)
(1)
SPC560B54/6x Package pinouts and signal descriptions
(2)
(3)
Pin number
Doc ID 15131 Rev 6 25/134
Port pin PCR
PB[5] PCR[21]
PB[6] PCR[22]
PB[7] PCR[23]
AF0
AF1
AF2
AF3
—
—
—
AF0
AF1
AF2
AF3
—
—
—
AF0
AF1
AF2
AF3
—
—
—
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
—
—
—
—
ADC0_P[1]
ADC1_P[1]
GPIO[21]
—
—
—
—
ADC0_P[2]
ADC1_P[2]
GPIO[22]
—
—
—
—
ADC0_P[3]
ADC1_P[3]
GPIO[23]
—
—
—
—
ADC_0
ADC_1
SIUL
—
—
—
—
ADC_0
ADC_1
SIUL
—
—
—
—
ADC_0
ADC_1
SIUL
—
—
—
—
I Tristate 53 75 91 R16
I
I
I
—
—
—
—
I Tristate 54 76 92 P15
I
I
I
—
—
—
—
I Tristate 55 77 93 P16
I
I
I
26/134 Doc ID 15131 Rev 6
Table 6. Functional port pin descriptions (continued)
(1)
(2)
(3)
Pin number
Package pinouts and signal descriptions SPC560B54/6x
Port pin PCR
PB[8] PCR[24]
PB[9] PCR[25]
PB[10] PCR[26]
AF0
AF1
AF2
AF3
—
—
—
—
AF0
AF1
AF2
AF3
—
—
—
—
AF0
AF1
AF2
AF3
—
—
—
Alternate function
OSC32K_XTAL
WKPU[25]
ADC0_S[0]
ADC1_S[4]
OSC32K_EXTAL
WKPU[26]
ADC0_S[1]
ADC1_S[5]
ADC0_S[2]
ADC1_S[6]
Function Peripheral
GPIO[24]
—
—
—
(8)
5
SIUL
—
—
—
OSC32K
WKPU
ADC_0
ADC_1
GPIO[25]
—
—
—
8
5
SIUL
—
—
—
OSC32K
WKPU
ADC_0
ADC_1
GPIO[26]
—
—
—
WKPU[8]
5
SIUL
—
—
—
WKPU
ADC_0
ADC_1
—
—
—
—
(9)
I
—
—
—
—
I
I/O
—
—
—
I/O direction
Pad type
RESET
LQFP
100
configuration
LQFP
144
LQFP
176
LBGA
208
I
I — 39 53 61 R9
I
I
I
I — 38 52 60 T9
9
I
I
JTristate405462P9
I
I
I
(4)
Table 6. Functional port pin descriptions (continued)
(1)
SPC560B54/6x Package pinouts and signal descriptions
(2)
(3)
Pin number
Doc ID 15131 Rev 6 27/134
Port pin PCR
PB[11] PCR[27]
PB[12] PCR[28]
PB[13] PCR[29]
PB[14] PCR[30]
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
—
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
GPIO[27]
E0UC[3]
—
CS0_0
ADC0_S[3]
GPIO[28]
E0UC[4]
—
CS1_0
ADC0_X[0]
GPIO[29]
E0UC[5]
—
CS2_0
ADC0_X[1]
GPIO[30]
E0UC[6]
—
CS3_0
ADC0_X[2]
SIUL
eMIOS_0
—
DSPI_0
ADC_0
SIUL
eMIOS_0
—
DSPI_0
ADC_0
SIUL
eMIOS_0
—
DSPI_0
ADC_0
SIUL
eMIOS_0
—
DSPI_0
ADC_0
I/O
I/O
—
I/O
I/O
I/O
—
O
I/O
I/O
—
O
I/O
I/O
—
O
J Tristate — — 97 N13
I
JTristate6183101M16
I
JTristate6385103M13
I
J Tristate 65 87 105 L16
I
PB[15] PCR[31]
AF0
AF1
AF2
AF3
—
GPIO[31]
E0UC[7]
—
CS4_0
ADC0_X[3]
SIUL
eMIOS_0
—
DSPI_0
ADC_0
I/O
I/O
—
O
J Tristate 67 89 107 L13
I
28/134 Doc ID 15131 Rev 6
Table 6. Functional port pin descriptions (continued)
(1)
(2)
(3)
Pin number
Package pinouts and signal descriptions SPC560B54/6x
Port pin PCR
(10)
PC[0]
PC[1]
PCR[32]
10
PCR[33]
PC[2] PCR[34]
PC[3] PCR[35]
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
—
—
—
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
Port C
GPIO[32]
—
TDI
—
GPIO[33]
—
TDO
—
GPIO[34]
SCK_1
CAN4TX
DEBUG[0]
EIRQ[5]
GPIO[35]
CS0_1
MA[0]
DEBUG[1]
EIRQ[6]
CAN1RX
CAN4RX
SIUL
—
JTAGC
—
SIUL
—
JTAGC
—
SIUL
DSPI_1
FlexCAN_4
SSCM
SIUL
SIUL
DSPI_1
ADC_0
SSCM
SIUL
FlexCAN_1
FlexCAN_4
I/O
—
M Input, weak pull-up 87 126 154 A8
I
—
I/O
—
(11)
F
O
Tristate 82 121 149 C9
—
I/O
I/O
O
M Tristate 78 117 145 A11
O
I
I/O
I/O
O
O
S Tristate 77 116 144 B11
I
I
I
Table 6. Functional port pin descriptions (continued)
(1)
SPC560B54/6x Package pinouts and signal descriptions
(2)
(3)
Pin number
Doc ID 15131 Rev 6 29/134
Port pin PCR
PC[4] PCR[36]
PC[5] PCR[37]
PC[6] PCR[38]
PC[7] PCR[39]
AF0
AF1
AF2
AF3
—
—
—
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
—
—
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
GPIO[36]
E1UC[31]
—
DEBUG[2]
EIRQ[18]
SIN_1
CAN3RX
GPIO[37]
SOUT_1
CAN3TX
DEBUG[3]
EIRQ[7]
GPIO[38]
LIN1TX
E1UC[28]
DEBUG[4]
GPIO[39]
—
E1UC[29]
DEBUG[5]
LIN1RX
WKPU[12]
SIUL
eMIOS_1
—
SSCM
SIUL
DSPI_1
FlexCAN_3
SIUL
DSPI_1
FlexCAN_3
SSCM
SIUL
SIUL
LINFlex_1
eMIOS_1
SSCM
SIUL
—
eMIOS_1
SSCM
LINFlex_1
5
WKPU
I/O
I/O
—
O
M Tristate 92 131 159 B7
I
I
I
I/O
O
O
M Tristate 91 130 158 A7
O
I
I/O
O
STristate253644R2
I/O
O
I/O
—
I/O
STristate263745P3
O
I
I
30/134 Doc ID 15131 Rev 6
Table 6. Functional port pin descriptions (continued)
(1)
(2)
(3)
Pin number
Package pinouts and signal descriptions SPC560B54/6x
Port pin PCR
PC[8] PCR[40]
PC[9] PCR[41]
PC[10] PCR[42]
PC[11] PCR[43]
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
—
—
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
—
—
—
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
GPIO[40]
LIN2TX
E0UC[3]
DEBUG[6]
GPIO[41]
—
E0UC[7]
DEBUG[7]
WKPU[13]
LIN2RX
GPIO[42]
CAN1TX
CAN4TX
MA[1]
GPIO[43]
—
—
MA[2]
WKPU[5]
CAN1RX
CAN4RX
5
5
SIUL
LINFlex_2
eMIOS_0
SSCM
SIUL
—
eMIOS_0
SSCM
WKPU
LINFlex_2
SIUL
FlexCAN_1
FlexCAN_4
ADC_0
SIUL
—
—
ADC_0
WKPU
FlexCAN_1
FlexCAN_4
I/O
O
S Tristate 99 143 175 A1
I/O
O
I/O
—
I/O
STristate 222B1
O
I
I
I/O
O
MTristate222836M3
O
O
I/O
—
—
O
STristate212735M4
I
I
I
Table 6. Functional port pin descriptions (continued)
(1)
SPC560B54/6x Package pinouts and signal descriptions
(2)
(3)
Pin number
Doc ID 15131 Rev 6 31/134
Port pin PCR
PC[12] PCR[44]
PC[13] PCR[45]
PC[14] PCR[46]
PC[15] PCR[47]
AF0
AF1
AF2
AF3
—
—
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
—
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
GPIO[44]
E0UC[12]
—
—
EIRQ[19]
SIN_2
GPIO[45]
E0UC[13]
SOUT_2
—
GPIO[46]
E0UC[14]
SCK_2
—
EIRQ[8]
GPIO[47]
E0UC[15]
CS0_2
—
EIRQ[20]
SIUL
eMIOS_0
—
—
SIUL
DSPI_2
SIUL
eMIOS_0
DSPI_2
—
SIUL
eMIOS_0
DSPI_2
—
SIUL
SIUL
eMIOS_0
DSPI_2
—
SIUL
I/O
I/O
—
M Tristate 97 141 173 B4
—
I
I
I/O
I/O
S Tristate 98 142 174 A2
O
—
I/O
I/O
I/O
STristate 333C1
—
I
I/O
I/O
I/O
MTristate 444D3
—
I
32/134 Doc ID 15131 Rev 6
Table 6. Functional port pin descriptions (continued)
(1)
(2)
(3)
Pin number
Package pinouts and signal descriptions SPC560B54/6x
Port pin PCR
PD[0] PCR[48]
PD[1] PCR[49]
PD[2] PCR[50]
AF0
AF1
AF2
AF3
—
—
—
AF0
AF1
AF2
AF3
—
—
—
AF0
AF1
AF2
AF3
—
—
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
Port D
GPIO[48]
—
—
—
WKPU[27]
ADC0_P[4]
ADC1_P[4]
GPIO[49]
—
—
—
WKPU[28]
ADC0_P[5]
ADC1_P[5]
GPIO[50]
—
—
—
ADC0_P[6]
ADC1_P[6]
SIUL
—
—
—
5
WKPU
ADC_0
ADC_1
SIUL
—
—
—
5
WKPU
ADC_0
ADC_1
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
—
I Tristate 41 63 77 P12
I
I
I
I
—
—
—
I Tristate 42 64 78 T12
I
I
I
I
—
—
I Tristate 43 65 79 R12
—
I
I
Table 6. Functional port pin descriptions (continued)
(1)
SPC560B54/6x Package pinouts and signal descriptions
(2)
(3)
Pin number
Doc ID 15131 Rev 6 33/134
Port pin PCR
PD[3] PCR[51]
PD[4] PCR[52]
PD[5] PCR[53]
AF0
AF1
AF2
AF3
—
—
AF0
AF1
AF2
AF3
—
—
AF0
AF1
AF2
AF3
—
—
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
GPIO[51]
—
—
—
ADC0_P[7]
ADC1_P[7]
GPIO[52]
—
—
—
ADC0_P[8]
ADC1_P[8]
GPIO[53]
—
—
—
ADC0_P[9]
ADC1_P[9]
SIUL
—
—
—
ADC_0
ADC_1
SIUL
—
—
—
ADC_0
ADC_1
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
I Tristate 44 66 80 P13
—
I
I
I
—
—
I Tristate 45 67 81 R13
—
I
I
I
—
—
I Tristate 46 68 82 T13
—
I
I
PD[6] PCR[54]
AF0
AF1
AF2
AF3
—
—
GPIO[54]
—
—
—
ADC0_P[10]
ADC1_P[10]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
I Tristate 47 69 83 T14
—
I
I
34/134 Doc ID 15131 Rev 6
Table 6. Functional port pin descriptions (continued)
(1)
(2)
(3)
Pin number
Package pinouts and signal descriptions SPC560B54/6x
Port pin PCR
PD[7] PCR[55]
PD[8] PCR[56]
PD[9] PCR[57]
AF0
AF1
AF2
AF3
—
—
AF0
AF1
AF2
AF3
—
—
AF0
AF1
AF2
AF3
—
—
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
GPIO[55]
—
—
—
ADC0_P[11]
ADC1_P[11]
GPIO[56]
—
—
—
ADC0_P[12]
ADC1_P[12]
GPIO[57]
—
—
—
ADC0_P[13]
ADC1_P[13]
SIUL
—
—
—
ADC_0
ADC_1
SIUL
—
—
—
ADC_0
ADC_1
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
I Tristate 48 70 84 R14
—
I
I
I
—
—
I Tristate 49 71 87 T15
—
I
I
I
—
—
I Tristate 56 78 94 N15
—
I
I
PD[10] PCR[58]
AF0
AF1
AF2
AF3
—
—
GPIO[58]
—
—
—
ADC0_P[14]
ADC1_P[14]
SIUL
—
—
—
ADC_0
ADC_1
I
—
—
I Tristate 57 79 95 N14
—
I
I
Table 6. Functional port pin descriptions (continued)
(1)
SPC560B54/6x Package pinouts and signal descriptions
(2)
(3)
Pin number
Doc ID 15131 Rev 6 35/134
Port pin PCR
PD[11] PCR[59]
PD[12] PCR[60]
PD[13] PCR[61]
PD[14] PCR[62]
AF0
AF1
AF2
AF3
—
—
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
—
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
GPIO[59]
—
—
—
ADC0_P[15]
ADC1_P[15]
GPIO[60]
CS5_0
E0UC[24]
—
ADC0_S[4]
GPIO[61]
CS0_1
E0UC[25]
—
ADC0_S[5]
GPIO[62]
CS1_1
E0UC[26]
—
ADC0_S[6]
SIUL
—
—
—
ADC_0
ADC_1
SIUL
DSPI_0
eMIOS_0
—
ADC_0
SIUL
DSPI_1
eMIOS_0
—
ADC_0
SIUL
DSPI_1
eMIOS_0
—
ADC_0
—
—
—
I/O
O
I/O
—
I/O
I/O
I/O
—
I/O
O
I/O
—
I
I Tristate 58 80 96 N16
I
I
JTristate——100M15
I
JTristate6284102M14
I
J Tristate 64 86 104 L15
I
36/134 Doc ID 15131 Rev 6
Table 6. Functional port pin descriptions (continued)
(1)
(2)
(3)
Pin number
Package pinouts and signal descriptions SPC560B54/6x
Port pin PCR
PD[15] PCR[63]
PE[0] PCR[64]
PE[1] PCR[65]
PE[2] PCR[66]
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
—
—
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
—
—
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
GPIO[63]
CS2_1
E0UC[27]
—
ADC0_S[7]
SIUL
DSPI_1
eMIOS_0
—
ADC_0
I/O
O
I/O
—
J Tristate 66 88 106 L14
I
Port E
GPIO[64]
E0UC[16]
—
—
WKPU[6]
CAN5RX
GPIO[65]
E0UC[17]
CAN5TX
—
GPIO[66]
E0UC[18]
—
—
EIRQ[21]
SIN_1
SIUL
eMIOS_0
—
—
5
WKPU
FlexCAN_5
SIUL
eMIOS_0
FlexCAN_5
—
SIUL
eMIOS_0
—
—
SIUL
DSPI_1
I/O
I/O
—
S Tristate 6 10 18 F1
—
I
I
I/O
I/O
M Tristate 8 12 20 F4
O
—
I/O
I/O
—
M Tristate 89 128 156 D7
—
I
I
Table 6. Functional port pin descriptions (continued)
(1)
SPC560B54/6x Package pinouts and signal descriptions
(2)
(3)
Pin number
Doc ID 15131 Rev 6 37/134
Port pin PCR
PE[3] PCR[67]
PE[4] PCR[68]
PE[5] PCR[69]
PE[6] PCR[70]
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
—
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
GPIO[67]
E0UC[19]
SOUT_1
—
GPIO[68]
E0UC[20]
SCK_1
—
EIRQ[9]
GPIO[69]
E0UC[21]
CS0_1
MA[2]
GPIO[70]
E0UC[22]
CS3_0
MA[1]
EIRQ[22]
SIUL
eMIOS_0
DSPI_1
—
SIUL
eMIOS_0
DSPI_1
—
SIUL
SIUL
eMIOS_0
DSPI_1
ADC_0
SIUL
eMIOS_0
DSPI_0
ADC_0
SIUL
I/O
I/O
M Tristate 90 129 157 C7
O
—
I/O
I/O
I/O
M Tristate 93 132 160 D6
—
I
I/O
I/O
M Tristate 94 133 161 C6
I/O
O
I/O
I/O
O
M Tristate 95 139 167 B5
O
I
PE[7] PCR[71]
AF0
AF1
AF2
AF3
—
GPIO[71]
E0UC[23]
CS2_0
MA[0]
EIRQ[23]
SIUL
eMIOS_0
DSPI_0
ADC_0
SIUL
I/O
I/O
O
M Tristate 96 140 168 C4
O
I
38/134 Doc ID 15131 Rev 6
Table 6. Functional port pin descriptions (continued)
(1)
(2)
(3)
Pin number
Package pinouts and signal descriptions SPC560B54/6x
Port pin PCR
PE[8] PCR[72]
PE[9] PCR[73]
PE[10] PCR[74]
PE[11] PCR[75]
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
—
—
—
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
—
—
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
GPIO[72]
CAN2TX
E0UC[22]
CAN3TX
GPIO[73]
—
E0UC[23]
—
WKPU[7]
CAN2RX
CAN3RX
GPIO[74]
LIN3TX
CS3_1
E1UC[30]
EIRQ[10]
GPIO[75]
E0UC[24]
CS4_1
—
LIN3RX
WKPU[14]
5
5
SIUL
FlexCAN_2
eMIOS_0
FlexCAN_3
SIUL
—
eMIOS_0
—
WKPU
FlexCAN_2
FlexCAN_3
SIUL
LINFlex_3
DSPI_1
eMIOS_1
SIUL
SIUL
eMIOS_0
DSPI_1
—
LINFlex_3
WKPU
I/O
O
M Tristate 9 13 21 G2
I/O
O
I/O
—
I/O
—
STristate101422G1
I
I
I
I/O
O
O
STristate111523G3
I/O
I
I/O
I/O
O
STristate131725H2
—
I
I
Table 6. Functional port pin descriptions (continued)
(1)
SPC560B54/6x Package pinouts and signal descriptions
(2)
(3)
Pin number
Doc ID 15131 Rev 6 39/134
Port pin PCR
PE[12] PCR[76]
PE[13] PCR[77]
PE[14] PCR[78]
PE[15] PCR[79]
AF0
AF1
AF2
AF3
—
—
—
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
GPIO[76]
—
E1UC[19]
—
EIRQ[11]
SIN_2
ADC1_S[7]
GPIO[77]
SOUT_2
E1UC[20]
—
GPIO[78]
SCK_2
E1UC[21]
—
EIRQ[12]
GPIO[79]
CS0_2
E1UC[22]
—
(12)
SIUL
—
eMIOS_1
—
SIUL
DSPI_2
ADC_1
SIUL
DSPI_2
eMIOS_1
—
SIUL
DSPI_2
eMIOS_1
—
SIUL
SIUL
DSPI_2
eMIOS_1
—
I/O
—
I/O
—
J Tristate 76 109 133 C14
I
I
I
I/O
O
S Tristate — 103 127 D15
I/O
—
I/O
I/O
I/O
S Tristate — 112 136 C13
—
I
I/O
I/O
M Tristate — 113 137 A13
I/O
—
40/134 Doc ID 15131 Rev 6
Table 6. Functional port pin descriptions (continued)
(1)
(2)
(3)
Pin number
Package pinouts and signal descriptions SPC560B54/6x
Port pin PCR
PF[0] PCR[80]
PF[1] PCR[81]
PF[2] PCR[82]
PF[3] PCR[83]
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
—
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
Port F
GPIO[80]
E0UC[10]
CS3_1
—
ADC0_S[8]
GPIO[81]
E0UC[11]
CS4_1
—
ADC0_S[9]
GPIO[82]
E0UC[12]
CS0_2
—
ADC0_S[10]
GPIO[83]
E0UC[13]
CS1_2
—
ADC0_S[11]
SIUL
eMIOS_0
DSPI_1
—
ADC_0
SIUL
eMIOS_0
DSPI_1
—
ADC_0
SIUL
eMIOS_0
DSPI_2
—
ADC_0
SIUL
eMIOS_0
DSPI_2
—
ADC_0
I/O
I/O
O
—
I/O
I/O
O
—
I/O
I/O
I/O
—
I/O
I/O
O
—
J Tristate — 55 63 N10
I
J Tri state — 56 64 P10
I
J Tristate — 57 65 T10
I
J Tristate — 58 66 R10
I
Table 6. Functional port pin descriptions (continued)
(1)
SPC560B54/6x Package pinouts and signal descriptions
(2)
(3)
Pin number
Doc ID 15131 Rev 6 41/134
Port pin PCR
PF[4] PCR[84]
PF[5] PCR[85]
PF[6] PCR[86]
PF[7] PCR[87]
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
—
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
GPIO[84]
E0UC[14]
CS2_2
—
ADC0_S[12]
GPIO[85]
E0UC[22]
CS3_2
—
ADC0_S[13]
GPIO[86]
E0UC[23]
CS1_1
—
ADC0_S[14]
GPIO[87]
—
CS2_1
—
ADC0_S[15]
SIUL
eMIOS_0
DSPI_2
—
ADC_0
SIUL
eMIOS_0
DSPI_2
—
ADC_0
SIUL
eMIOS_0
DSPI_1
—
ADC_0
SIUL
—
DSPI_1
—
ADC_0
I/O
I/O
O
—
I/O
I/O
O
—
I/O
I/O
O
—
I/O
—
O
—
J Tristate — 59 67 N11
I
J Tri state — 60 68 P11
I
J Tristate — 61 69 T11
I
J Tristate — 62 70 R11
I
PF[8] PCR[88]
AF0
AF1
AF2
AF3
GPIO[88]
CAN3TX
CS4_0
CAN2TX
SIUL
FlexCAN_3
DSPI_0
FlexCAN_2
I/O
O
M Tristate — 34 42 P1
O
O
42/134 Doc ID 15131 Rev 6
Table 6. Functional port pin descriptions (continued)
(1)
(2)
(3)
Pin number
Package pinouts and signal descriptions SPC560B54/6x
Port pin PCR
PF[9] PCR[89]
PF[10] PCR[90]
PF[11] PCR[91]
PF[12] PCR[92]
AF0
AF1
AF2
AF3
—
—
—
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
—
—
AF0
AF1
AF2
AF3
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
GPIO[89]
E1UC[1]
CS5_0
—
WKPU[22]
CAN2RX
CAN3RX
GPIO[90]
CS1_0
LIN4TX
E1UC[2]
GPIO[91]
CS2_0
E1UC[3]
—
WKPU[15]
LIN4RX
GPIO[92]
E1UC[25]
LIN5TX
—
SIUL
eMIOS_1
DSPI_0
—
5
WKPU
FlexCAN_2
FlexCAN_3
SIUL
DSPI_0
LINFlex_4
eMIOS_1
SIUL
DSPI_0
eMIOS_1
—
5
WKPU
LINFlex_4
SIUL
eMIOS_1
LINFlex_5
—
I/O
I/O
O
—
S Tristate — 33 41 N2
I
I
I
I/O
O
M Tristate — 38 46 R3
O
I/O
I/O
O
I/O
S Tristate — 39 47 R4
—
I
I
I/O
I/O
M Tristate — 35 43 R1
O
—
Table 6. Functional port pin descriptions (continued)
(1)
SPC560B54/6x Package pinouts and signal descriptions
(2)
(3)
Pin number
Doc ID 15131 Rev 6 43/134
Port pin PCR
PF[13] PCR[93]
PF[14] PCR[94]
PF[15] PCR[95]
AF0
AF1
AF2
AF3
—
—
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
—
—
—
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
GPIO[93]
E1UC[26]
—
—
WKPU[16]
LIN5RX
GPIO[94]
CAN4TX
E1UC[27]
CAN1TX
GPIO[95]
E1UC[4]
—
—
EIRQ[13]
CAN1RX
CAN4RX
5
SIUL
eMIOS_1
—
—
WKPU
LINFlex_5
SIUL
FlexCAN_4
eMIOS_1
FlexCAN_1
SIUL
eMIOS_1
—
—
SIUL
FlexCAN_1
FlexCAN_4
I/O
I/O
—
S Tristate — 41 49 T6
—
I
I
I/O
O
M Tristate — 102 126 D14
I/O
O
I/O
I/O
—
—
S Tristate — 101 125 E15
I
I
I
Port G
PG[0] PCR[96]
AF0
AF1
AF2
AF3
GPIO[96]
CAN5TX
E1UC[23]
—
SIUL
FlexCAN_5
eMIOS_1
—
I/O
O
M Tristate — 98 122 E14
I/O
—
44/134 Doc ID 15131 Rev 6
Table 6. Functional port pin descriptions (continued)
(1)
(2)
(3)
Pin number
Package pinouts and signal descriptions SPC560B54/6x
Port pin PCR
PG[1] PCR[97]
PG[2] PCR[98]
PG[3] PCR[99]
PG[4] PCR[100]
PG[5] PCR[101]
AF0
AF1
AF2
AF3
—
—
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
—
—
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
GPIO[97]
—
E1UC[24]
—
EIRQ[14]
CAN5RX
GPIO[98]
E1UC[11]
SOUT_3
—
GPIO[99]
E1UC[12]
CS0_3
—
WKPU[17]
GPIO[100]
E1UC[13]
SCK_3
—
GPIO[101]
E1UC[14]
—
—
WKPU[18]
SIN_3
5
5
SIUL
—
eMIOS_1
—
SIUL
FlexCAN_5
SIUL
eMIOS_1
DSPI_3
—
SIUL
eMIOS_1
DSPI_3
—
WKPU
SIUL
eMIOS_1
DSPI_3
—
SIUL
eMIOS_1
—
—
WKPU
DSPI_3
I/O
—
I/O
S Tristate — 97 121 E13
—
I
I
I/O
I/O
MTristate —816E4
O
—
I/O
I/O
I/O
STristate—715E3
—
I
I/O
I/O
MTristate —614E1
I/O
—
I/O
I/O
—
STristate—513E2
—
I
I
Table 6. Functional port pin descriptions (continued)
(1)
SPC560B54/6x Package pinouts and signal descriptions
(2)
(3)
Pin number
Doc ID 15131 Rev 6 45/134
Port pin PCR
PG[6] PCR[102]
PG[7] PCR[103]
PG[8] PCR[104]
PG[9] PCR[105]
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
—
—
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
—
—
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
GPIO[102]
E1UC[15]
LIN6TX
—
GPIO[103]
E1UC[16]
E1UC[30]
—
WKPU[20]
LIN6RX
GPIO[104]
E1UC[17]
LIN7TX
CS0_2
EIRQ[15]
GPIO[105]
E1UC[18]
—
SCK_2
WKPU[21]
LIN7RX
5
5
SIUL
eMIOS_1
LINFlex_6
—
SIUL
eMIOS_1
eMIOS_1
—
WKPU
LINFlex_6
SIUL
eMIOS_1
LINFlex_7
DSPI_2
SIUL
SIUL
eMIOS_1
—
DSPI_2
WKPU
LINFlex_7
I/O
I/O
M Tristate — 30 38 M2
O
—
I/O
I/O
I/O
S Tristate — 29 37 M1
—
I
I
I/O
I/O
O
S Tristate — 26 34 L2
I/O
I
I/O
I/O
—
S Tristate — 25 33 L1
I/O
I
I
46/134 Doc ID 15131 Rev 6
Table 6. Functional port pin descriptions (continued)
(1)
(2)
(3)
Pin number
Package pinouts and signal descriptions SPC560B54/6x
Port pin PCR
PG[10] PCR[106]
PG[11] PCR[107]
PG[12] PCR[108]
PG[13] PCR[109]
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
GPIO[106]
E0UC[24]
E1UC[31]
—
SIN_4
GPIO[107]
E0UC[25]
CS0_4
—
GPIO[108]
E0UC[26]
SOUT_4
—
GPIO[109]
E0UC[27]
SCK_4
—
SIUL
eMIOS_0
eMIOS_1
—
DSPI_4
SIUL
eMIOS_0
DSPI_4
—
SIUL
eMIOS_0
DSPI_4
—
SIUL
eMIOS_0
DSPI_4
—
I/O
I/O
I/O
S Tristate — 114 138 D13
—
I
I/O
I/O
M Tristate — 115 139 B12
I/O
—
I/O
I/O
M Tristate — 92 116 K14
O
—
I/O
I/O
M Tristate — 91 115 K16
I/O
—
PG[14] PCR[110]
AF0
AF1
AF2
AF3
GPIO[110]
E1UC[0]
LIN8TX
—
SIUL
eMIOS_1
LINFlex_8
—
I/O
I/O
S Tristate — 110 134 B14
O
—
Table 6. Functional port pin descriptions (continued)
(1)
SPC560B54/6x Package pinouts and signal descriptions
(2)
(3)
Pin number
Doc ID 15131 Rev 6 47/134
Port pin PCR
PG[15] PCR[111]
PH[0] PCR[112]
PH[1] PCR[113]
PH[2] PCR[114]
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
GPIO[111]
E1UC[1]
—
—
LIN8RX
SIUL
eMIOS_1
—
—
LINFlex_8
I/O
I/O
—
M Tristate — 111 135 B13
—
I
Port H
GPIO[112]
E1UC[2]
—
—
SIN_1
GPIO[113]
E1UC[3]
SOUT_1
—
GPIO[114]
E1UC[4]
SCK_1
—
SIUL
eMIOS_1
—
—
DSPI_1
SIUL
eMIOS_1
DSPI_1
—
SIUL
eMIOS_1
DSPI_1
—
I/O
I/O
—
M Tristate — 93 117 F13
—
I
I/O
I/O
M Tristate — 94 118 F14
O
—
I/O
I/O
M Tristate — 95 119 F16
I/O
—
PH[3] PCR[115]
AF0
AF1
AF2
AF3
GPIO[115]
E1UC[5]
CS0_1
—
SIUL
eMIOS_1
DSPI_1
—
I/O
I/O
M Tristate — 96 120 F15
I/O
—
48/134 Doc ID 15131 Rev 6
Table 6. Functional port pin descriptions (continued)
(1)
(2)
(3)
Pin number
Package pinouts and signal descriptions SPC560B54/6x
Port pin PCR
PH[4] PCR[116]
PH[5] PCR[117]
PH[6] PCR[118]
PH[7] PCR[119]
PH[8] PCR[120]
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
GPIO[116]
E1UC[6]
—
—
GPIO[117]
E1UC[7]
—
—
GPIO[118]
E1UC[8]
—
MA[2]
GPIO[119]
E1UC[9]
CS3_2
MA[1]
GPIO[120]
E1UC[10]
CS2_2
MA[0]
SIUL
eMIOS_1
—
—
SIUL
eMIOS_1
—
—
SIUL
eMIOS_1
—
ADC_0
SIUL
eMIOS_1
DSPI_2
ADC_0
SIUL
eMIOS_1
DSPI_2
ADC_0
I/O
I/O
M Tristate — 134 162 A6
—
—
I/O
I/O
S Tristate — 135 163 B6
—
—
I/O
I/O
M Tristate — 136 164 D5
—
O
I/O
I/O
M Tristate — 137 165 C5
O
O
I/O
I/O
M Tristate — 138 166 A5
O
O
PH[9]
10
PCR[121]
AF0
AF1
AF2
AF3
GPIO[121]
—
TCK
—
SIUL
—
JTAGC
—
I/O
—
S Input, weak pull-up 88 127 155 B8
I
—
Table 6. Functional port pin descriptions (continued)
(1)
SPC560B54/6x Package pinouts and signal descriptions
(2)
(3)
Pin number
Doc ID 15131 Rev 6 49/134
Port pin PCR
10
PH[10]
PCR[122]
PH[11] PCR[123]
PH[12] PCR[124]
PH[13] PCR[125]
PH[14] PCR[126]
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
GPIO[122]
—
TMS
—
GPIO[123]
SOUT_3
CS0_4
E1UC[5]
GPIO[124]
SCK_3
CS1_4
E1UC[25]
GPIO[125]
SOUT_4
CS0_3
E1UC[26]
GPIO[126]
SCK_4
CS1_3
E1UC[27]
SIUL
—
JTAGC
—
SIUL
DSPI_3
DSPI_4
eMIOS_1
SIUL
DSPI_3
DSPI_4
eMIOS_1
SIUL
DSPI_4
DSPI_3
eMIOS_1
SIUL
DSPI_4
DSPI_3
eMIOS_1
I/O
—
M Input, weak pull-up 81 120 148 B9
I
—
I/O
O
MTristate ——140A14
I/O
I/O
I/O
I/O
MTristate ——141D12
O
I/O
I/O
O
MTristate ——9B3
I/O
I/O
I/O
I/O
MTristate ——10D1
O
I/O
PH[15] PCR[127]
AF0
AF1
AF2
AF3
GPIO[127]
SOUT_5
—
E1UC[17]
SIUL
DSPI_5
—
eMIOS_1
I/O
O
MTristate ——8A3
—
I/O
50/134 Doc ID 15131 Rev 6
Table 6. Functional port pin descriptions (continued)
(1)
(2)
(3)
Pin number
Package pinouts and signal descriptions SPC560B54/6x
Port pin PCR
PI[0] PCR[128]
PI[1] PCR[129]
PI[2] PCR[130]
PI[3] PCR[131]
PI[4] PCR[132]
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
—
—
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
—
—
AF0
AF1
AF2
AF3
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
Port I
GPIO[128]
E0UC[28]
LIN8TX
—
GPIO[129]
E0UC[29]
—
—
WKPU[24]
LIN8RX
GPIO[130]
E0UC[30]
LIN9TX
—
GPIO[131]
E0UC[31]
—
—
WKPU[23]
LIN9RX
GPIO[132]
E1UC[28]
SOUT_4
—
5
5
SIUL
eMIOS_0
LINFlex_8
—
SIUL
eMIOS_0
—
—
WKPU
LINFlex_8
SIUL
eMIOS_0
LINFlex_9
—
SIUL
eMIOS_0
—
—
WKPU
LINFlex_9
SIUL
eMIOS_1
DSPI_4
—
I/O
I/O
STristate——172A9
O
—
I/O
I/O
—
STristate——171A10
—
I
I
I/O
I/O
STristate——170B10
O
—
I/O
I/O
—
STristate——169C10
—
I
I
I/O
I/O
STristate——143A12
O
—
Table 6. Functional port pin descriptions (continued)
(1)
SPC560B54/6x Package pinouts and signal descriptions
(2)
(3)
Pin number
Doc ID 15131 Rev 6 51/134
Port pin PCR
PI[5] PCR[133]
PI[6] PCR[134]
PI[7] PCR[135]
PI[8] PCR[136]
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
AF0
AF1
AF2
AF3
—
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
GPIO[133]
E1UC[29]
SCK_4
—
GPIO[134]
E1UC[30]
CS0_4
—
GPIO[135]
E1UC[31]
CS1_4
—
GPIO[136]
—
—
—
ADC0_S[16]
SIUL
eMIOS_1
DSPI_4
—
SIUL
eMIOS_1
DSPI_4
—
SIUL
eMIOS_1
DSPI_4
—
SIUL
—
—
—
ADC_0
I/O
I/O
STristate——142C12
I/O
—
I/O
I/O
STristate——11D2
I/O
—
I/O
I/O
STristate——12D3
O
—
I/O
—
—
JTristate——108J13
—
I
PI[9] PCR[137]
AF0
AF1
AF2
AF3
—
GPIO[137]
—
—
—
ADC0_S[17]
SIUL
—
—
—
ADC_0
I/O
—
—
—
JTristate——109J14
I
52/134 Doc ID 15131 Rev 6
Table 6. Functional port pin descriptions (continued)
(1)
(2)
(3)
Pin number
Package pinouts and signal descriptions SPC560B54/6x
Port pin PCR
PI[10] PCR[138]
PI[11] PCR[139]
PI[12] PCR[140]
PI[13] PCR[141]
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
—
—
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
—
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
GPIO[138]
—
—
—
ADC0_S[18]
GPIO[139]
—
—
—
ADC0_S[19]
SIN_3
GPIO[140]
CS0_3
—
—
ADC0_S[20]
GPIO[141]
CS1_3
—
—
ADC0_S[21]
SIUL
—
—
—
ADC_0
SIUL
—
—
—
ADC_0
DSPI_3
SIUL
DSPI_3
—
—
ADC_0
SIUL
DSPI_3
—
—
ADC_0
I/O
—
—
—
I/O
—
—
—
I/O
I/O
—
—
I/O
O
—
—
JTristate——110J15
I
JTristate——111J16
I
I
JTristate——112G14
I
JTristate——113G15
I
Table 6. Functional port pin descriptions (continued)
(1)
SPC560B54/6x Package pinouts and signal descriptions
(2)
(3)
Pin number
Doc ID 15131 Rev 6 53/134
Port pin PCR
PI[14] PCR[142]
PI[15] PCR[143]
PJ[0] PCR[144]
AF0
AF1
AF2
AF3
—
—
AF0
AF1
AF2
AF3
—
AF0
AF1
AF2
AF3
—
Function Peripheral
I/O direction
Pad type
RESET
configuration
LQFP
100
LQFP
144
LQFP
176
LBGA
(4)
208
Alternate function
GPIO[142]
—
—
—
ADC0_S[22]
SIN_4
GPIO[143]
CS0_4
—
—
ADC0_S[23]
SIUL
—
—
—
ADC_0
DSPI_4
SIUL
DSPI_4
—
—
ADC_0
I/O
—
—
—
I/O
I/O
—
—
JTristate——76R8
I
I
JTristate——75T8
I
Port J
GPIO[144]
CS1_4
—
—
ADC0_S[24]
SIUL
DSPI_4
—
—
ADC_0
I/O
O
—
—
JTristate——74N5
I
PJ[1] PCR[145]
AF0
AF1
AF2
AF3
—
—
GPIO[145]
—
—
—
ADC0_S[25]
SIN_5
SIUL
—
—
——
ADC_0
DSPI_5
I/O
—
—
—
JTristate——73P5
I
I
54/134 Doc ID 15131 Rev 6
Table 6. Functional port pin descriptions (continued)
(1)
(2)
(3)
Pin number
Package pinouts and signal descriptions SPC560B54/6x
Port pin PCR
Function Peripheral
I/O direction
Pad type
RESET
LQFP
100
LQFP
144
LQFP
176
LBGA
208
configuration
Alternate function
AF0
AF1
PJ[2] PCR[146]
AF2
AF3
—
AF0
AF1
PJ[3] PCR[147]
AF2
AF3
—
AF0
PJ[4] PCR[148]
AF1
AF2
AF3
1. Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module. PCR.PA = 00 → AF0; PCR.PA = 01 → AF1;
PCR.PA = 10
written to ‘1’, regardless of the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is reported as “—”.
2. Multiple i nputs are routed to all respective modules internally. The input of some modules must be configured by setting the values of the PSMIO.PADSELx
bitfields inside the SIUL module.
3. The RESET configuration applies during and after reset.
4. LBGA208 available only as development package for Nexus2+
5. All WKPU pins also support external interrupt capability. See the WKPU chapter for further details.
6. NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored.
7. “Not applicable” because these functions are available only while the device is booting. Refer to the BAM information for details.
8. Value of PCR.IBE bit must be 0
9. This wakeup input cannot be used to exit STANDBY mode.
→ AF2; PCR.PA= 11 → AF2. This is intended to select the output functions; to use one of the input functions, the PCR.IBE bit must be
GPIO[146]
CS0_5
—
—
ADC0_S[26]
GPIO[147]
CS1_5
—
—
ADC0_S[27]
GPIO[148]
SCK_5
E1UC[18]
—
SIUL
DSPI_5
—
—
ADC_0
SIUL
DSPI_5
—
—
ADC_0
SIUL
DSPI_5
eMIOS_1
—
I/O
I/O
—
JTristate——72P4
—
I
I/O
O
—
JTristate——71P2
—
I
I/O
I/O
MTristate ——5A4
I/O
—
(4)
Doc ID 15131 Rev 6 55/134
10. Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO.
PC[0:1] are available as JTAG pins (TDI and TDO respectively).
PH[9:10] are available as JTAG pins (TCK and TMS respectively) .
It is up to the user to configure these pins as GPIO when needed.
11. PC[1] is a fast/medium pad but is in medium configuration by default.
This pad is in Alternate Function 2 mode after reset which has TDO
functionality. The reset value of PCR.OBE is ‘1’, but this setting has no impact as long as this pad stays in AF2 mode. After configuring
this pad as GPIO (PCR.PA = 0), output buffer is enabled as reset value of PCR.OBE = 1.
12. Not available in LQFP100 package
SPC560B54/6x Package pinouts and signal descriptions
Package pinouts and signal descriptions SPC560B54/6x
3.8 Nexus 2+ pins
In the LBGA208 package, eight additional debug pins are available (see
Table 7. Nexus 2+ pin descriptions
Table 7
).
Pin number
Port pin Function
I/O
direction
Pad type
Function
after reset
LQFP
100
LQFP
144
MCKO Message clock out O F — — — T4
MDO0 Message data out 0 O M — — — H15
MDO1 Message data out 1 O M — — — H16
MDO2 Message data out 2 O M — — — H14
MDO3 Message data out 3 O M — — — H13
EVTI Event in I M Pull-up — — K1
EVTO Event out O M — — — L4
MSEO Message start/end out O M — — — G16
1. LBGA208 available only as development package for Nexus2+
LBGA
(1)
208
56/134 Doc ID 15131 Rev 6
SPC560B54/6x Electrical characterist ics
4 Electrical characteristics
This section contains electrical characteristics of the device as well as temperature and
power considerations.
This product contains devices to protect the inputs against damage due to high static
voltages. However, it is advisable to take precautions to avoid application of any voltage
higher than the specified maximum rated voltages.
To enhance reliability , unused inputs can be driven to an appropriate logic voltage level (V
or V
). This could be done by the internal pull-up and pull-down, which is provided by the
SS
product for most general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and
its demands on the system.
In the tables where the device logic provides signals with their respective timing
characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol
column.
In the tables where the external system must provide signals with their respective timing
characteristics to the device, the symbol “SR” for System Requirement is included in the
Symbol column.
4.1 Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To
give the customer a better understanding, the classifications listed in
the parameters are tagged accordingly in the tables where appropriate.
Table 8. Parameter classifications
Classification tag Tag description
P Those parameters are guaranteed during production testing on each individual device.
Table 8
DD
are used and
C
T
D Those parameters are derived mainly from simulations.
Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
Those parame ters are a chie v ed b y de sign ch aracteriza tion on a small sample siz e from typi cal
devices under typical conditions unless otherwise noted. All values shown in the typical
column are within this category.
Note: The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
4.2 NVUSRO register
Bit values in the Non-Volatile User Options (NVUSRO) Register control portions of the
device configuration, namely electrical parameters such as high voltage supply and
oscillator margin, as well as digital functionality (watchdog enable/disable after reset).
Doc ID 15131 Rev 6 57/134
Electrical characteristics SPC560B54/6x
For a detailed description of the NVUSRO register, please refer to the device reference
manual.
4.2.1 NVUSRO[PAD3V5V] field descript ion
The DC electrical characteristics are dependent on the PAD3V5V bit value.
how NVUSRO[PAD3V5V] controls the device configuration.
Table 9. PAD3V5V field description
(2)
Value
0 High voltage supply is 5.0 V
1 High voltage supply is 3.3 V
1. See the device reference manual for more information on the NVUSRO register.
2. Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.
(1)
Description
4.2.2 NVUSRO[OSCILLATOR_MARGIN] field description
The fast external crystal oscillator consumption is dependent on the
OSCILLATOR_MARGIN bit value.
controls the device configuration.
Table 10. OSCILLATOR_MARGIN field description
1. See the device reference manual for more information on the NVUSRO register.
2. Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.
(2)
Value
0 Low consumption config uration (4 MHz/8 MHz)
1 High margin configuration (4 MHz/16 MHz)
Table 10
shows how NVUSRO[OSCILLATOR_MARGIN]
(1)
Description
Table 9
shows
4.2.3 NVUSRO[WATCHDOG_EN] field description
The watchdog enable/disable configuration after reset is dependent on the
WATCHDOG_EN bit value.
device configuration.
Table 11. WATCHDOG_EN field description
1. Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.
58/134 Doc ID 15131 Rev 6
(1)
Value
0 Disable after reset
1 Enable after reset
Table 11
shows how NVUSRO[WATCHDOG_EN] controls the
Description
SPC560B54/6x Electrical characterist ics
4.3 Absolute maximum ratings
Table 12. Absolute maximum ratings
Symbol Parameter Conditions
V
V
V
SS_LV
V
DD_BV
DD
SS
SR Digital ground on VSS_HV pins — 0 0 V
Voltage on VDD_HV pins with respect to
SR
ground (V
Voltage on VSS_LV (low voltage digital
SR
supply) pins with respect to ground (V
Voltage on VDD_BV (regulator supply) pin
SR
with respect to ground (V
SS
)
)
SS
)
SS
Relative to V
Voltage on VSS_HV_ADC0,
V
SS_ADC
SR
VSS_HV_ADC1 (ADC reference) pins with
respect to ground (V
SS
)
Voltage on VDD_HV_ADC0,
V
DD_ADC
V
I
INJPAD
I
INJSUM
SR
VDD_HV_ADC1 (ADC reference) pins with
respect to ground (V
Voltage on any GPIO pin with respect to
SR
IN
ground (V
Injected input current on any pin during
SR
overload condi t ion
Absolute su m of all injected input currents
SR
during overload condition
SS
)
SS
)
Relative to V
Relative to V
Value
Unit
Min Max
—–0.36.0V
—V
–0.1 VSS+0.1 V
SS
—–0.36.0
V
DD
—V
–0.3 VDD+0.3
–0.1 VSS+0.1 V
SS
—–0.36.0
V
DD
VDD− 0.3 VDD+0.3
—–0.36.0
V
DD
—VDD+0.3
— –10 10
mA
— –50 50
= 5.0 V ± 10%,
V
I
AVGSEG
T
STORAGE
DD
Sum of all the static I/O current within a
SR
supply segment
PAD3V5V = 0
= 3.3 V ± 10%,
V
DD
PAD3V5V = 1
SR Storage temperature — –55 150 °C
—70
mA
—64
Note: Stresses exceeding the recommended absolute maximum ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification are not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. During overload conditions (V
the voltage on pins with respect to ground (V
) must not exceed the recommended values.
SS
IN>VDD
or VIN<VSS),
Doc ID 15131 Rev 6 59/134
Electrical characteristics SPC560B54/6x
4.4 Recommended operating conditions
Table 13. Recommended operating conditions (3.3 V)
Value
Symbol Parameter Conditions
Min Max
V
V
SS_LV
V
DD_BV
V
DD
SS
(1)
SR Digital ground on VSS_HV pins — 0 0 V
Voltage on VDD_HV pins with respect to
(2)
(3)
SR
ground (V
Voltage on VSS_LV (low voltage digital
SR
supply) pins with respect to ground (V
V oltage on VDD _BV pin (regulator supply)
SR
with respect to ground (V
SS
)
)
SS
SS
)
Relative to V
—3.03.6V
—V
− 0.1 VSS+0.1 V
SS
—3.03.6
VDD− 0.1 VDD+0.1
DD
Voltage on VSS_HV_ADC0,
V
SS_ADC
V
DD_ADC
V
IN
I
INJPAD
I
INJSUM
TV
DD
1. 100nF capacitance needs to be provided between each VDD/VSS pair.
2. 330nF capacitance needs to be provided between each V
3. 470nF capacitance needs to be provided between V
depending on external regulator characteristics). Supply ramp slope on VDD_BV should always be faster or equal to slope
of VDD_HV. Otherwise, device may enter regulator bypass mode if slope on VDD_BV is slower.
4. 100nF capacitance needs to be provided between V
5. Ful l electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical
characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below V
reset.
6. Guaranteed by device validation
SR
VSS_HV_ADC1 (ADC reference) pin with
(4)
respect to ground (V
Voltage on VDD_HV_ADC0,
SR
VDD_HV_ADC1 (ADC reference) with
respect to ground (V
Voltage on any GPIO pin with respect to
SR
ground (V
Injected input current on any pin during
SR
overload condition
Absolute sum of all inject ed in put curre nts
SR
during overload condition
SS
)
SS
SS
)
)
SR VDD slope to ensure correct power up
(6)
DD_LV/VSS_LV
and the nearest V
DD_BV
DD_ADC/VSS_ADC
Relative to V
Relative to V
supply pair.
SS_LV
pair.
—V
—3.0
DD
—V
DD
− 0.1 VSS+0.1 V
SS
(5)
3.6
VDD− 0.1 VDD+0.1
− 0.1 —
SS
—VDD+0.1
— −55
— −50 50
— — 0.25 V/µs
(higher value may be needed
LVDHVL,
Unit
V
V
V
mA
device is
Table 14. Recommended operating conditions (5.0 V)
Symbol Parameter Conditions
V
SS
V
DD
60/134 Doc ID 15131 Rev 6
SR Digital ground on VSS_HV pins — 0 0 V
(1)
Voltage on VDD_HV pins with respect to
SR
ground (V
SS
)
Voltage drop
Value
Unit
Min Max
—4.55.5
(2)
3.0 5.5
V
SPC560B54/6x Electrical characterist ics
Table 14. Recommended operating conditions (5.0 V) (continued)
Value
Symbol Parameter Conditions
Min Max
Unit
V
SS_LV
(3)
Voltage on VSS_LV (low voltage digital
SR
supply) pins with respect to ground (V
SS
)
—V
− 0.1 VSS+0.1 V
SS
—4.55.5
V
DD_BV
(4)
Voltage on VDD_BV pin (regulator supply)
SR
with respect to ground (V
SS
)
Relative to V
(2)
DD
3.0 5.5
3.0 VDD+0.1
Voltage on VSS_HV_ADC0, VSS_HV_ADC1
V
SS_ADC
SR
(ADC reference) pin with respect to ground
)
(V
SS
—V
− 0.1 VSS+0.1 V
SS
—4.55.5
V
1. 100nF capacitance needs to be provided between each VDD/VSS pair.
2. Ful l devi ce operation is guaranteed by design when the voltage drops below 4.5 V down to 3.0 V. However, certain analog
3. 330nF capacitance needs to be provided between each V
4. 470nF capacitance needs to be provided between V
5. 100nF capacitance needs to be provided between V
6. Guaranteed by device validation. Please refer to
(5)
DD_ADC
V
IN
I
INJPAD
I
INJSUM
TV
DD
electrical characteristics will not be guaranteed to stay within the stated limits.
depending on external regulator characteristics). While the supply voltage ramps up, the slope on V
than 0.9V
V
DD_HV
slope to be guaranteed to ensure correct power up in case of external resistor usage.
DD
V oltage on VDD_HV_ADC0, VDD_HV_ADC1
SR
(ADC reference) with respect to ground (V
SS
)
Relative to V
Voltage on any GPIO pin with respect to
SR
ground (V
Injected input current on any pin during
SR
overload cond ition
Absolute sum of all injected input currents
SR
during overload condition
SR VDD slope to ensure correct power up
in order to ensure the device does not enter regulator bypass mode.
SS
)
(6)
DD_LV/VSS_LV
and the nearest V
DD_BV
DD_ADC/VSS_ADC
Section 4.5.1: External ballast resistor recommendations
Relative to V
supply pair.
SS_LV
pair.
(2)
DDVDD
—V
DD
3.0 5.5
− 0.1 VDD+0.1
− 0.1 —
SS
—VDD+0.1
— −55
— −50 50
— — 0.25 V/µs
(higher value may be needed
should be less
DD_BV
for minimum
VVoltage drop
VVoltage drop
V
mA
Note: RAM data retention is guaranteed with V
not below 1.08 V.
DD_LV
4.5 Thermal characteristics
4.5.1 External ballast resistor recommendations
External ballast resistor on V
the device. This resistor is required only when maximum power consumption exceeds the
limit imposed by package thermal characteristics.
As stated in
Table 15
LQFP thermal characteristics, considering a thermal resistance of
LQFP144 as 48.3 °C/W, at ambient temperature T
will cross 150 °C if the total power dissipation is greater than
pin helps in reducing the overall power dissipation inside
DD_BV
= 125 °C, the junction temperature T
A
Doc ID 15131 Rev 6 61/134
j
Electrical characteristics SPC560B54/6x
(150 – 125)/48.3 = 517 mW . Therefore, the total device current I
not exceed 94.1 mA (i.e., PD/VDD). Assuming an average I
consumption typically during device RUN mode, the L V domain consumption I
thus limited to I
DDMAX–IDD(VDD_HV
), i.e., 80 mA.
Therefore, respecting the maximum power allowed as explained in
thermal characteristics
, it is recommended to use this resistor only in the 125 °C/5.5 V
operating corner as per the following guidelines:
● If I
● If 80 mA < I
● If I
DD(VDD_BV
DD(VDD_BV
) < 80 mA, then no resistor is required.
DD(VDD_BV
) < 90 mA, then 4 Ω resistor can be used.
) > 90 mA, then 8 Ω resistor can be used.
Using resistance in the range of 4–8 Ω, the gain will be around 10–20% of total consumption
on V
. For example, if 8 Ω resistor is used, then power consumption when IDD(V
DD_BV
is 110 mA is equivalent to power consumption when I
when resistor not used.
In order to ensure correct power up, the minimum V
the supply ramp is slower than this value, then LVDHV3B monitoring ballast supply V
pin gets triggered leading to device reset. Until the supply reaches certain threshold, this
low voltage detector (LVD) generates destructive reset event in the system. This threshold
depends on the maximum I
DD(VDD_BV
) possible across the external resistor.
4.5.2 Package thermal characteristics
Table 15. LQFP thermal charact er istics
(1)
at 125 °C/5.5 V must
DDMAX
DD(VDD_HV
) of 15–20 mA
Section 4.5.2: Package
DD(VDD_BV
DD_BV
) is 90 mA (approximately)
to be guaranteed is 30 ms/V. If
DD(VDD_BV
DD_BV
DD_BV
) is
)
Symbol C Parameter Conditions
Single-layer board — 1s
Thermal resistance, junction-
R
CC D
θJA
R
CC
θJB
to-ambient natural
convection
Thermal resistance, junctionto-board
(3)
(4)
Four-layer board — 2s2p
Single-layer board — 1s
Four-layer board — 2s2p
(2)
Value
Pin count
Min Typ Max
100 — — 64
144 — — 64
176 — — 64
100 — — 49.7
144 — — 48.3
176 — — 47.3
100 — — 36
144 — — 38
176 — — 38
100 — — 33.6
144 — — 33.4
176 — — 33.4
Unit
°C/W
°C/W
62/134 Doc ID 15131 Rev 6
SPC560B54/6x Electrical characterist ics
Table 15. LQFP thermal charact er istics
Symbol C Parameter Conditions
(1)
(continued)
(2)
Pin count
Value
Unit
Min Typ Max
100 — — 23
Single-layer board — 1s
R
CC
θJC
Thermal resistance, junction-
(5)
to-case
Four-layer board — 2s2p
144 — — 23
176 — — 23
°C/W
100 — — 19.8
144 — — 19.2
176 — — 18.8
1. Thermal characteristics are targets based on simulation.
= 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C.
2. V
DD
3. Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package. When Greek letters are not available, the symbols are typed as R
4. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for
the specified package. When Greek letters are not available, the symbols are typed as R
5. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer. When Greek letters
are not available, the symbols are typed as R
thJC
.
thJB
.
thJA
and R
thJMA
.
4.5.3 Power considerations
The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using
<Cross Refs>Equation 1:
Equation 1: T
Where:
Most of the time for the applications, P
P
may be significant, if the device is configured to continuously drive external modules
I/O
and/or memories.
An approximate relationship between P
Equation 2: P
Therefore, solving equations <Cross Refs>1 and <Cross Refs>2:
Equation 3: K = P
Where:
= TA + (PD x R
J
T
is the ambient temperature in °C.
A
R
is the package junction-to-ambient thermal resistance, in °C/W.
θJA
is the sum of P
P
D
P
is the product of I
INT
power.
P
represents the power dissipation on input and output pins; user determined.
I/O
= K / (TJ + 273 °C)
D
x (TA + 273 °C) + R
D
K is a constant for the particular part, which may be determined from <Cross
Refs>Equation 3 by measuring P
INT
)
θJA
and P
and VDD, expressed in watts. This is the chip internal
DD
= P
I/O (PD
I/O< PINT
and TJ (if P
D
x P
θJA
(at equilibrium) for a known TA. Using this value
D
+ P
INT
I/O
).
and may be neglected. On the other hand,
is neglected) is given by:
I/O
2
D
Doc ID 15131 Rev 6 63/134
Electrical characteristics SPC560B54/6x
of K, the values of PD and TJ may be obtained by solving equations <Cross
Refs>1 and <Cross Refs>2 iteratively for any value of T
.
A
4.6 I/O pad electrical characteristics
4.6.1 I/O pad types
The device provides four main I/O pad types depending on the associated alternate
functions:
● Slow pads—are the most common pads, providing a good compromise between
transition time and low electromagnetic emission.
● Medium pads—provide transition fast enough for the serial communication channels
with controlled current to reduce electromagnetic emission.
● Fast pads—provide maximum speed. These are used for improved Nexus debugging
capability.
● Input only pads—are associated with ADC channels and 32 kHz low power external
crystal oscillator providing low input leakage.
Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at
the cost of reducing AC performance.
4.6.2 I/O input DC characteristics
Table 16
Figure 6. I/O input DC electrical characteristics definition
PDIx = ‘1
(GPDI register of SIUL)
PDIx = ‘0’
provides input DC electrical characteristics as described in
V
IN
V
DD
V
IH
V
IL
Figure 6
V
HYS
.
64/134 Doc ID 15131 Rev 6
SPC560B54/6x Electrical characterist ics
Table 16. I/O input DC electrical characteristics
Symbol C Parameter Conditions
(1)
Value
Min Typ Max
V
V
I
W
W
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
2. In the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and voltage.
SR P
IH
SR P
IL
CC C
HYS
CC
LKG
(2)
SR P Wakeup input filtered pulse — — — 40 ns
FI
(2)
SR P W a k eup in put no t filtere d pul se — 1000 — — ns
NFI
Input high level CMOS
(Schmitt Trigger)
Input low lev el CMOS (Schmi tt
Trigger)
Input hysteres is CMOS
(Schmitt Trigger)
D
DT
DT
Digital input leakage
DT
No injection
on adjacent
pin
PT
—0.65V
—VDD+0.4
DD
— −0.4 — 0.35V
—0.1V
= −40 °C — 2 200
T
A
= 25 °C — 2 200
A
= 85 °C — 5 300
A
= 105 °C — 12 500
A
= 125 °C — 70 1000
A
——
DD
DD
Unit
VV
nA
4.6.3 I/O output DC characteristics
The following tables provide DC characteristics for bidirectional pads:
●
Table 17
supported.
●
Table 18
configuration.
●
Table 19
configuration.
●
Table 20
Table 17. I/O pull-up/pull-down DC electrical characteristics
Symbol C Parameter Conditions
|I
|CC
WPU
|I
|CC
WPD
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
P
Weak pull-up current
absolute value
PV
P
Weak pull-do w n
current absolute value
PV
provides weak pull figures. Both pull-up and pull-down resistances are
provides output driver characteristics for I/O pads when in SLOW
provides output driver characteristics for I/O pads when in MEDIUM
provides output driver characteristics for I/O pads when in FAST configuration.
(1)
= VIL, VDD = 5.0 V ± 10%
V
IN
= VIL, VDD = 3.3 V ± 10% PAD3V5V = 1 10 — 150
IN
= VIH, VDD = 5.0 V ± 10%
V
IN
= VIH, VDD = 3.3 V ± 10% PAD3V5V = 1 10 — 150
IN
PAD3V5V = 0 10 — 150
PAD3V5V = 0 10 — 150
Value
Min Typ Max
(2)
10 — 250
Unit
µACPAD3V5V = 1
µAC PAD3V5V = 1 10 — 250
Doc ID 15131 Rev 6 65/134
Electrical characteristics SPC560B54/6x
2. The configuration PAD3V5 = 1 when VDD= 5 V is only a transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Table 18. SLOW configuration output buffer electrical characteristics
Symbol C Parameter Conditions
(1)
= −2mA,
I
OH
= 5.0 V ± 10%,
V
P
DD
PAD3V5V = 0
0.8V
(recommended)
= −2mA,
I
V
CC
OH
Output high level
SLOW configuration
Push Pull
C
OH
V
= 5.0 V ± 10%,
DD
PAD3V5V = 1
I
= −1mA,
OH
V
= 3.3 V ± 10%,
DD
PAD3V5V = 1
(2)
0.8V
V
DD
(recommended)
I
= 2 mA,
OL
= 5.0 V ± 10%,
V
P
DD
PAD3V5V = 0
(recommended)
I
= 2 mA,
CC
V
OL
Output low level
SLOW configuration
Push Pull
OL
= 5.0 V ± 10%,
V
DD
PAD3V5V = 1
(2)
Value
Min T yp Max
DD
DD
——
——
− 0.8 — —
——0.1V
——0.1V
DD
DD
Unit
VC
VC
I
= 1 mA,
OL
= 3.3 V ± 10%,
V
C
DD
PAD3V5V = 1
(recommended)
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
2. The configuration PAD3V5 = 1 when V
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
= 5 V is only a transient configuration during power-up. All pads but RESET and
DD
——0.5
66/134 Doc ID 15131 Rev 6
SPC560B54/6x Electrical characterist ics
Table 19. MEDIUM configuration output buffer electrical characteristics
Symbol C Parameter Conditions
(1)
= −3.8 mA,
I
C
P
OH
V
= 5.0 V ± 10%, PAD3V5V = 0
DD
I
= −2mA,
OH
= 5.0 V ± 10%, PAD3V5V = 0
V
DD
0.8V
0.8V
(recommended)
Output high level
V
CC
C
OH
MEDIUM
configuration
Push
Pull
C
= −1mA,
I
OH
= 5.0 V ± 10%, PAD3V5V = 1
V
DD
I
= −1mA,
OH
= 3.3 V ± 10%, PAD3V5V = 1
V
DD
(2)
0.8V
V
(recommended)
= −100 µA,
I
C
C
P
OH
= 5.0 V ± 10%, PAD3V5V = 0
V
DD
= 3.8 mA,
I
OL
V
= 5.0 V ± 10%, PAD3V5V = 0
DD
I
= 2 mA,
OL
= 5.0 V ± 10%, PAD3V5V = 0
V
DD
0.8V
(recommended)
VOLCC
Output low level
MEDIUM
C
configuration
C
Push
Pull
= 1 mA,
I
OL
= 5.0 V ± 10%, PAD3V5V = 1
V
DD
I
= 1 mA,
OL
= 3.3 V ± 10%, PAD3V5V = 1
V
DD
(2)
(recommended)
= 100 µA,
I
C
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
2. The configuration PAD3V5 = 1 when V
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
DD
OL
= 5.0 V ± 10%, PAD3V5V = 0
V
DD
= 5 V is only a transient configuration during power-up. All pads but RESET and
Value
Min Typ Max
——
DD
——
DD
——
DD
−
DD
0.8
——0.2V
——0.1V
——0.1V
——
——
DD
DD
DD
DD
——0.5
——0.1V
DD
Unit
V
V
CC
P
Output high
level
FAST
configuration
C
Push
Pull
(1)
= −14 mA,
I
OH
= 5.0 V ± 10%, P AD3V5V = 0
V
DD
(recommended)
= −7mA,
I
OH
= 5.0 V ± 10%, PAD3V5V = 1
V
DD
= −11 mA,
I
OH
V
= 3.3 V ± 10%, P AD3V5V = 1
DD
(2)
Table 20. FAST configuration output buffer electrical characteristics
Symbol C Parameter Conditions
V
OH
(recommended)
Doc ID 15131 Rev 6 67/134
Value
Min Typ Max
0.8V
0.8V
DD
DD
——
——
VDD− 0.8 — —
Unit
VC
Electrical characteristics SPC560B54/6x
Table 20. FAST configuration output buffer electrical characteristics (continued)
Symbol C Parameter Conditions
I
= 14 mA,
P
OL
= 5.0 V ± 10%, PAD3V5V = 0
V
DD
(1)
(recommended)
Output low level
V
OL
CC
FAST
configuration
C
Push
Pull
= 7 mA,
I
OL
= 5.0 V ± 10%, PAD3V5V = 1
V
DD
I
= 11 mA,
OL
= 3.3 V ± 10%, PAD3V5V = 1
V
DD
(recommended)
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
2. The configuration PAD3V5 = 1 when V
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
= 5 V is only a transient configuration during power-up. All pads but RESET and
DD
4.6.4 Output pin transition times
Table 21. Output pin transition times
Symbol C Parameter Conditions
TtrCC
T
tr
T
tr
D
TC
DC
Output transition time output pin
SLOW configur ati on
DC
TC
DC
D
TC
DC
CC
Output transition time output pin
MEDIUM configuration
DC
TC
DC
CC D
Output transition time output pin
FAST configuration
= 25 pF
C
L
= 50 pF — — 100
L
(2)
= 100 pF — — 125
L
= 25 pF
L
= 50 pF — — 100
L
= 100 pF — — 125
L
= 25 pF
C
L
= 50 pF — — 20
L
(2)
= 100 pF — — 40
L
= 25 pF
L
= 50 pF — — 25
L
= 100 pF — — 40
L
= 25 pF
C
L
C
= 50 pF — — 6
L
(2)
CL = 100 pF — — 12
C
= 25 pF
L
C
= 50 pF — — 7
L
V
= 5.0 V ± 10%,
DD
PAD3V5V = 0
V
= 3.3 V ± 10%,
DD
PAD3V5V = 1
= 5.0 V ± 10%,
V
DD
PAD3V5V = 0
SIUL.PCRx.SRC = 1
= 3.3 V ± 10%,
V
DD
PAD3V5V = 1
SIUL.PCRx.SRC = 1
V
= 5.0 V ± 10%,
DD
PAD3V5V = 0
V
= 3.3 V ± 10%,
DD
PAD3V5V = 1
CL = 100 pF — — 12
(1)
Min Typ Max
——0.1V
(2)
——0.1V
——0.5
Value
DD
DD
Value
Min Typ Max
——50
——50
——10
——12
—— 4
—— 4
Unit
VC
Unit
ns
ns
ns
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
includes device and package capacitances (C
2. C
L
PKG
< 5 pF).
68/134 Doc ID 15131 Rev 6
SPC560B54/6x Electrical characterist ics
4.6.5 I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is
associated to a V
Table 23
provides I/O consumption figures.
DD/VSS
In order to ensure device reliability, the average current of the I/O on a single segment
should remain below the I
Table 22. I/O supply segments
Package
12345678
supply pair as described in
AVGSEG
maximum value.
Supply segment
Table 22
.
LBGA208
(1)
LQFP176
LQFP144
LQFP100
1. LBGA208 available only as development package for Nexus2+
Table 23. I/O consumption
pin7 –
pin27
pin20 –
pin49
pin16 –
pin35
Equivalent to LQFP176 segment pad distribution MCKO
pin28 –
pin57
pin51 –
pin99
pin37 –
pin69
pin59 –
pin85
pin100 –
pin122
pin70 –
pin83
pin86 –
pin123
pin 123 –
pin19
pin84 –
pin15
Symbol C Parameter Conditions
I
SWTSLW
I
SWTMED
I
SWTFST
(2)
(2)
(2)
CC D
CC D
CC D
Dynamic I/O current for
SLOW configuration
Dynamic I/O current for
MEDIUM configuration
Dynamic I/O current for
FAST configuration
CL = 25 pF
= 25 pF
C
L
= 25 pF
C
L
pin124 –
pin150
pin151 –
pin6
— —
— — — —
— — — —
(1)
Value
Min Typ Max
V
= 5.0 V ± 10%,
DD
PAD3V5V = 0
= 3.3 V ± 10%,
V
DD
PAD3V5V = 1
V
= 5.0 V ± 10%,
DD
PAD3V5V = 0
= 3.3 V ± 10%,
V
DD
PAD3V5V = 1
= 5.0 V ± 10%,
V
DD
PAD3V5V = 0
= 3.3 V ± 10%,
V
DD
PAD3V5V = 1
——20
——16
——29
——17
— — 110
——50
MDOn
/MSEO
Unit
mA
mA
mA
Doc ID 15131 Rev 6 69/134
Electrical characteristics SPC560B54/6x
Table 23. I/O consumption (continued)
Symbol C Parameter Conditions
CL = 25 pF, 2 MHz
C
= 25 pF, 4 MHz — — 3.2
L
I
RMSSLW
CC D
Root mean square I/O
current for SLO W
configuration
CL = 100 pF, 2 MHz — — 6.6
C
= 25 pF, 2 MHz
L
C
= 25 pF, 4 MHz — — 2.3
L
CL = 100 pF, 2 MHz — — 4.7
CL = 25 pF, 13 MHz
C
= 25 pF, 40 MHz — — 13.4
L
I
RMSMED
CC D
Root mean square I/O
current for MEDIUM
configuration
CL = 100 pF, 13 MHz — — 18.3
C
= 25 pF, 13 MHz
L
C
= 25 pF, 40 MHz — — 8.5
L
CL = 100 pF, 13 MHz — — 11
CL = 25 pF, 40 MHz
C
= 25 pF, 64 MHz — — 33
L
I
RMSFST
CC D
Root mean square I/O
current for FAST
configuration
CL = 100 pF, 40 MHz — — 56
C
= 25 pF, 40 MHz
L
C
= 25 pF, 64 MHz — — 20
L
CL = 100 pF, 40 MHz — — 35
(1)
V
= 5.0 V ± 10%,
DD
PAD3V5V = 0
V
= 3.3 V ± 10%,
DD
PAD3V5V = 1
V
= 5.0 V ± 10%,
DD
PAD3V5V = 0
V
= 3.3 V ± 10%,
DD
PAD3V5V = 1
V
= 5.0 V ± 10%,
DD
PAD3V5V = 0
V
= 3.3 V ± 10%,
DD
PAD3V5V = 1
Value
Unit
Min Typ Max
——2.3
mA
——1.6
——6.6
mA
—— 5
——22
mA
——14
Sum of all the static I/O
I
AVGSEG
SR D
current within a supply
segment
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to125 °C, unless otherwise specified
2. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.
Table 24
provides the weight of concurrent switching I/Os.
V
= 5.0 V ± 10%, PAD3V5V = 0 — — 70
DD
= 3.3 V ± 10%, PAD3V5V = 1 — — 65
V
DD
Due to the dynamic current limitations, the sum of the weight of concurrent switching I/Os on
a single segment must not exceed 100% to ensure device functionality.
70/134 Doc ID 15131 Rev 6
mA
SPC560B54/6x Electrical characterist ics
Table 24. I/O weight
Supply segment
LQFP
LQFP
176
144
LQFP
100
44
6
PC[14] 4% — 4% — 13% — 15% —
PC[15] 3% 4% 4% 4% 12% 18% 15% 16%
——PJ[4] 3% 4% 3% 3% — — — —
— — PH[15] 2% 3% 3% 3% — — — —
— — PH[13] 3% 4% 3% 4% — — — —
— — PH[14] 3% 4% 4% 4% — — — —
——PI[6]4% —4%—————
——PI[7]4% —4%—————
— PG[5] 4% — 5% — 10% — 12% —
— PG[4] 4% 6% 5% 5% 9% 13% 11% 12%
— PG[3] 4% — 5% — 9% — 11% —
(1)
LQFP176 LQFP144/100
Pad
Weight 5 V Weight 3.3 V Weight 5 V Weight 3.3 V
(2)
SRC
=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1
PB[3] 5% — 6% — 13% — 15% —
PC[9]4% — 5% —13%—15%—
1
— PG[2] 4% 6% 5% 5% 9% 12% 10% 11%
PA[2] 4% — 5% — 8% — 10% —
PE[0] 4% — 5% — 8% — 9% —
4
PA[1] 4% — 5% — 8% — 9% —
PE[1] 4% 6% 5% 6% 7% 10% 9% 9%
PE[8] 4% 6% 5% 6% 7% 10% 8% 9%
4
PE[9] 4% — 5% — 6% — 8% —
PE[10] 4% — 5% — 6% — 7% —
PA[0]4% 6%5%5%6%8%7%7%
PE[11] 4% — 5% — 5% — 6% —
Doc ID 15131 Rev 6 71/134
Electrical characteristics SPC560B54/6x
Table 24. I/O weight
Supply segment
LQFP
LQFP
176
21
144
LQFP
100
— PG[9] 9% — 10% — 9% — 10% —
— PG[8] 9% — 11% — 9% — 11% —
PC[11] 9% — 11% — 9% — 11% —
1
PC[10] 9% 13% 11% 12% 9% 13% 11% 12%
— PG[7] 9% — 11% — 9% — 11% —
— PG[6] 10% 14% 11% 12% 10% 14% 11% 12%
1
— PF[9] 10% — 12% — 10% — 12% —
— PF[8] 10% 14% 12% 13% 10% 14% 12% 13%
— PF[12] 10% 15% 12% 13% 10% 15% 12% 13%
1
— PF[10] 10% 14% 11% 12% 10% 14% 11% 12%
(1)
(continued)
LQFP176 LQFP144/100
Pad
PB[0] 10% 14% 12% 12% 10% 14% 12% 12%
PB[1] 10% — 12% — 10% — 12% —
PC[6] 10% — 12% — 10% — 12% —
PC[7] 10% — 12% — 10% — 12% —
Weight 5 V Weight 3.3 V Weight 5 V Weight 3.3 V
(2)
SRC
=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1
— PF[11] 9% — 11% — 9% — 11% —
1 PA[15] 8% 12% 10% 10% 8% 12% 10% 10%
— PF[13] 8% — 10% — 8% — 10% —
PA[14] 8% 11% 9% 10% 8% 11% 9% 10%
PA[4] 7% — 9% — 7% — 9% —
1
PA[13] 7% 10% 8% 9% 7% 10% 8% 9%
PA[12] 7% — 8% — 7% — 8% —
72/134 Doc ID 15131 Rev 6
SPC560B54/6x Electrical characterist ics
Table 24. I/O weight
Supply segment
LQFP
LQFP
176
LQFP
144
100
2
PB[10] 5% — 6% — 6% — 7% —
— PF[0] 5% — 6% — 6% — 8% —
— PF[1] 5% — 6% — 7% — 8% —
— PF[2] 6% — 7% — 7% — 9% —
2
— PF[3] 6% — 7% — 8% — 9% —
— PF[4] 6% — 7% — 8% — 10% —
— PF[5] 6% — 7% — 9% — 10% —
— PF[6] 6% — 7% — 9% — 11% —
— PF[7] 6% — 7% — 9% — 11% —
——PJ[3]6% —7%—————
(1)
(continued)
LQFP176 LQFP144/100
Pad
PB[9] 1% — 1% — 1% — 1% —
PB[8] 1% — 1% — 1% — 1% —
Weight 5 V Weight 3.3 V Weight 5 V Weight 3.3 V
(2)
SRC
=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1
——PJ[2]6% —7%—————
3
——PJ[1]6% —7%—————
——PJ[0]6% —7%—————
— — PI[15] 6% — 7% — — — — —
— — PI[14] 6% — 7% — — — — —
PD[0] 1% — 1% — 1% — 1% —
PD[1] 1% — 1% — 1% — 1% —
PD[2] 1% — 1% — 1% — 1% —
22
PD[3] 1% — 1% — 1% — 1% —
PD[4] 1% — 1% — 1% — 1% —
PD[5] 1% — 1% — 1% — 1% —
PD[6] 1% — 1% — 1% — 2% —
PD[7] 1% — 1% — 1% — 2% —
Doc ID 15131 Rev 6 73/134
Electrical characteristics SPC560B54/6x
Table 24. I/O weight
Supply segment
LQFP
LQFP
176
422
144
LQFP
100
PD[10] 1% — 1% — 1% — 2% —
PD[11] 1% — 1% — 1% — 2% —
(1)
(continued)
LQFP176 LQFP144/100
Pad
PD[8] 1% — 1% — 1% — 2% —
PB[4] 1% — 1% — 1% — 2% —
PB[5] 1% — 1% — 1% — 2% —
PB[6] 1% — 1% — 1% — 2% —
PB[7] 1% — 1% — 1% — 2% —
PD[9] 1% — 1% — 1% — 2% —
Weight 5 V Weight 3.3 V Weight 5 V Weight 3.3 V
(2)
SRC
=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1
74/134 Doc ID 15131 Rev 6
SPC560B54/6x Electrical characterist ics
Table 24. I/O weight
Supply segment
LQFP
LQFP
176
4
LQFP
144
100
——PB[11]1% —1%—————
— — PD[12] 11% — 13% — — — — —
PB[12] 11% — 13% — 15% — 17% —
PD[13] 11% — 13% — 14% — 17% —
PB[13] 11% — 13% — 14% — 17% —
22
— — PI[8] 10% — 12% — — — — —
— — PI[9] 10% — 12% — — — — —
— — PI[10] 10% — 12% — — — — —
— — PI[11] 10% — 12% — — — — —
— — PI[12] 10% — 12% — — — — —
PD[14] 11% — 13% — 14% — 17% —
PB[14] 11% — 13% — 14% — 16% —
PD[15] 11% — 13% — 13% — 16% —
PB[15] 11% — 13% — 13% — 15% —
(1)
(continued)
Pad
SRC
LQFP176 LQFP144/100
Weight 5 V Weight 3.3 V Weight 5 V Weight 3.3 V
(2)
=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1
— — PI[13] 10% — 11% — — — — —
2 PA[3] 9% — 11% — 11% — 13% —
— PG[13] 9% 13% 11% 11% 10% 14% 12% 13%
— PG[12] 9% 13% 10% 11% 10% 14% 12% 12%
— PH[0] 6% 8% 7% 7% 6% 9% 7% 8%
— PH[1] 6% 8% 7% 7% 6% 8% 7% 7%
2
— PH[2] 5% 7% 6% 6% 5% 7% 6% 7%
— PH[3] 5% 7% 5% 6% 5% 7% 6% 6%
— PG[1] 4% — 5% — 4% — 5% —
— PG[0] 4% 5% 4% 5% 4% 5% 4% 5%
Doc ID 15131 Rev 6 75/134
Electrical characteristics SPC560B54/6x
Table 24. I/O weight
Supply segment
LQFP
LQFP
176
144
3
LQFP
100
— PF[15] 4% — 4% — 4% — 4% —
—PF[14]4% 6%5%5%4%6%5%5%
— PE[13] 4% — 5% — 4% — 5% —
3
PA[10] 6% — 8% — 6% — 8% —
PA[11] 8% — 9% — 8% — 9% —
PE[12] 8% — 9% — 8% — 9% —
— PG[14] 8% — 9% — 8% — 9% —
— PG[15] 8% 11% 9% 10% 8% 11% 9% 10%
— PE[14] 8% — 9% — 8% — 9% —
(1)
(continued)
LQFP176 LQFP144/100
Pad
PA[7] 5% — 6% — 5% — 6% —
PA[8] 5% — 6% — 5% — 6% —
PA[9] 6% — 7% — 6% — 7% —
Weight 5 V Weight 3.3 V Weight 5 V Weight 3.3 V
(2)
SRC
=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1
5
— PE[15] 8% 11% 9% 10% 8% 11% 9% 10%
— PG[10] 8% — 9% — 8% — 9% —
— PG[11] 7% 11% 9% 9% 7% 11% 9% 9%
— — PH[11] 7% 10% 9% 9% — — — —
— — PH[12] 7% 10% 8% 9% — — — —
——PI[5]7% —8%—————
——PI[4]7% —8%—————
PC[3] 6% — 8% — 6% — 8% —
PC[2]6% 8%7%7%6%8%7%7%
PA[5]6% 8%7%7%6%8%7%7%
33
PA[6] 5% — 6% — 5% — 6% —
PH[10] 5% 7% 6% 6% 5% 7% 6% 6%
PC[1] 5% 19% 5% 13% 5% 19% 5% 13%
76/134 Doc ID 15131 Rev 6
SPC560B54/6x Electrical characterist ics
Table 24. I/O weight
Supply segment
LQFP
LQFP
176
6
144
4
LQFP
100
4
— PH[4] 8% 12% 10% 10% 10% 14% 12% 12%
— PH[5] 8% — 10% — 10% — 12% —
— PH[6] 8% 12% 10% 11% 10% 15% 12% 13%
— PH[7] 9% 12% 10% 11% 11% 15% 13% 13%
(1)
(continued)
LQFP176 LQFP144/100
Pad
Weight 5 V Weight 3.3 V Weight 5 V Weight 3.3 V
(2)
SRC
=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1 SRC=0 SRC=1
PC[0] 6% 9% 7% 8% 7% 10% 8% 8%
PH[9] 7% — 8% — 7% — 9% —
PE[2] 7% 10% 8% 9% 8% 11% 9% 10%
PE[3] 7% 10% 9% 9% 8% 12% 10% 10%
PC[5] 7% 11% 9% 9% 8% 12% 10% 11%
PC[4] 8% 11% 9% 10% 9% 13% 10% 11%
PE[4] 8% 11% 9% 10% 9% 13% 11% 12%
PE[5] 8% 11% 10% 10% 9% 14% 11% 12%
— PH[8] 9% 12% 10% 11% 11% 16% 13% 14%
PE[6] 9% 12% 10% 11% 11% 16% 13% 14%
4
PE[7] 9% 12% 10% 11% 11% 16% 14% 14%
——PI[3]9% —10%—————
——PI[2]9% —10%—————
——PI[1]9% —10%—————
——PI[0]9% —10%—————
PC[12] 8% 12% 10% 11% 12% 18% 15% 16%
PC[13] 8% — 10% — 13% — 15% —
44
PC[8] 8% — 10% — 13% — 15% —
PB[2] 8% 11% 9% 10% 13% 18% 15% 16%
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
2. SRC: “Slew Rate Control” bit in SIU_PCRx
Doc ID 15131 Rev 6 77/134
Electrical characteristics SPC560B54/6x
4.7 RESET electrical characteristics
The device implements a dedicated bidirectional RESET pin.
Figure 7. Start-up reset requirements
V
DD
V
DDMIN
RESET
V
IH
V
IL
device reset forced by RESET
Figure 8. Noise filtering on reset signal
V
RESET
V
DD
V
IH
V
IL
filtered by
hysteresis
filtered by
lowpass filter
W
FRST
filtered by
lowpass filter
W
device start-up phase
FRST
unknown reset
state
W
NFRST
hw_rst
‘1’
‘0’
device under hardware reset
78/134 Doc ID 15131 Rev 6
SPC560B54/6x Electrical characterist ics
Table 25. Reset electrical characteristics
Symbol C Parameter Conditions
Input High Lev e l
V
SR P
IH
CMOS
(Schmitt Trigger)
V
SR P
IL
Input low Level CMOS
(Schmitt Trigger)
Input hysteres is
V
HYS
CC C
CMOS
(Schmitt Trigger)
Push Pull, I
V
DD
OL
= 5.0 V ± 10%, PAD3V5V = 0
(recommended)
Push Pull, I
V
CC P Output low level
OL
V
DD
(2)
1
Push Pull, I
V
DD
OL
= 5.0 V ± 10%, PAD3V5V =
OL
= 3.3 V ± 10%, PAD3V5V = 1
(recommended)
= 25 pF,
C
L
= 5.0 V ± 10%, PAD3V5V = 0
V
DD
CL = 50 pF,
= 5.0 V ± 10%, PAD3V5V = 0
V
DD
= 100 pF,
C
L
V
= 5.0 V ± 10%, PAD3V5V = 0
DD
C
= 25 pF,
L
= 3.3 V ± 10%, PAD3V5V = 1
V
DD
= 50 pF,
C
L
= 3.3 V ± 10%, PAD3V5V = 1
V
DD
= 100 pF,
C
L
V
= 3.3 V ± 10%, PAD3V5V = 1
DD
W
W
T
tr
FRST
NFRST
CC D
SR P
SR P
Output transition time
output pin
(3)
MEDIUM
configuration
RESET
input filtered
pulse
RESET
input not
filtered pulse
(1)
Value
Unit
Min Typ Max
—0.65V
— −0.4 — 0.35V
—0.1V
—VDD+0.4 V
DD
DD
—— V
DD
V
= 2 mA,
— — 0.1V
DD
= 1 mA,
— — 0.1V
DD
V
= 1 mA,
—— 0.5
—— 10
—— 20
—— 40
ns
—— 12
—— 25
—— 40
———40ns
— 1000 — — ns
P
DV
|I
WPU
|CC
Weak pull-up current
absolute value
P
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
2. This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of the
device reference manual).
includes device and package capacitance (C
3. C
L
= 3.3 V ± 10%, PAD3V5V = 1 10 — 150
V
DD
= 5.0 V ± 10%, PAD3V5V = 0 10 — 150
DD
= 5.0 V ± 10%, PAD3V5V =
V
1
DD
(4)
PKG
<5pF).
10 — 250
Doc ID 15131 Rev 6 79/134
µA
Electrical characteristics SPC560B54/6x
4. The configuration PAD3V5 = 1 when VDD= 5 V is only transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
4.8 Power management electrical characteristics
4.8.1 Voltage regulator electrical characteristics
The device implements an internal voltage regulator to generate the low voltage core supply
V
common I/O supply V
● HV: High voltage external power supply for voltage regulator module. This must be
● BV: High voltage external power supply for internal ballast module. This must be
● LV: Low voltage internal power supply for core, FMPLL and Flash digital logic. This is
from the high voltage ballast supply V
DD_LV
. The following supplies are involved:
DD
provided externally through V
provided externally through V
V
.
DD
power pin.
DD
power pin. Voltage values should be aligned with
DD_BV
. The regulator itself is supplied by the
DD_BV
generated by the internal voltage regulator but provided outside to connect stability
capacitor. It is further split into four main domains to ensure noise isolation between
critical LV modules within the device:
– LV_COR: Low voltage supply for the core. It is also used to provide supply for
FMPLL through double bonding.
– LV_CFLA: Low voltage supply for code flash module. It is supplied with dedicated
ballast and shorted to LV_COR through double bonding.
– LV_DFLA: Low voltage supply for data flash module. It is supplied with dedicated
ballast and shorted to LV_COR through double bonding.
– LV_PLL: Low voltage supply for FMPLL. It is shorted to LV_COR through double
bonding.
80/134 Doc ID 15131 Rev 6
SPC560B54/6x Electrical characterist ics
Figure 9. Voltage regulator capacitance connection
C
(LV_COR/LV_CFLA)
REG2
V
DD
V
DD_BV
V
DD_LVn
V
SS_LVn
V
SS_LV
V
REF
Voltage Regulator
I
(Ballast decoupling)
C
(LV_COR/LV_DFLA)
DEC1
REG1
C
DEVICE
V
DD_BV
V
V
V
DD_LV
SS_LV
SS_LV
C
V
REG3
The internal voltage regulator requires external capacitance (C
DD_LV
REGn
V
DD_LV
DEVICE
C
DEC2
V
DD
V
SS
(supply/IO decoupling)(LV_COR/LV_PLL)
) to be connected to the
device in order to provide a stable low voltage digital supply to the device. Capacitances
should be placed on the board as near as possible to the associated pins. Care should also
be taken to limit the serial inductance of the board to less than 5 nH.
Each decoupling capacitor must be placed between each of the three V
pairs to ensure stable voltage (see
Table 26. Voltage regulator electrical characteristics
Symbol C Parameter Conditions
C
REGn
R
REG
C
DEC1
C
DEC2
SR —
SR —
Internal voltage regulator external
capacitance
Stability capacitor equivalent serial
resistance
SR — Decoupling capacitance
SR —
Decoupling capacitance regulator
supply
Section 4.4: Recommended operating conditions
Range:
10 kHz to 20 MHz
V
DD_BV/VSS_LV
V
(2)
ballast
Doc ID 15131 Rev 6 81/134
DD_BV
V
DD_BV/VSS_LV
V
DD_BV
V
DD/VSS
DD_LV/VSS_LV
supply
).
(1)
— 200 — 500 nF
pair:
= 4.5 V to 5.5 V
100
pair:
= 3V to 3.6V
pair 10 100 — nF
Value
Min Typ Max
——0.2W
(3)
470
—
(4)
400 —
Unit
nF
Electrical characteristics SPC560B54/6x
Table 26. Voltage regulator electrical characteristics (continued)
Symbol C Parameter Conditions
Before exiting from
V
MREG
CCTMain regulator output voltage
reset
P After trimming 1.16 1.28 —
I
MREG
I
MREGINT
V
LPREG
I
LPREG
I
LPREGINT
V
ULPREG
I
ULPREG
I
ULPREGINT
I
DD_BV
SR —
CC D
CC P Low-power regulator output voltage After trimming 1.16 1.28 — V
SR —
CC
CC P
SR —
CC D
CC D
Main regulator current provided to
domain
V
DD_LV
Main regulator module current
consumption
Low-power regulator current
provided to V
DD_LV
domain
D
Low-power regulator module current
consumption
—
Ultra low power regulator output
voltage
Ultra low power regulator current
provided to V
DD_LV
domain
Ultra low power regulator module
current consumptio n
In-rush average current on V
during power-up
(5)
DD_BV
I
= 200 mA — — 2
MREG
I
= 0 mA — — 1
MREG
I
LPREG
T
= 55 °C
A
I
LPREG
= 55 °C
T
A
After trimming 1.16 1.28 — V
I
ULPREG
= 55 °C
T
A
I
ULPREG
= 55 °C
T
A
(1)
Value
Min Typ Max
1.32 —
—
———150 mA
———15 mA
= 15 mA;
= 0 mA;
——
—
600
5—
———5 mA
= 5 mA;
= 0 mA;
——
—
———
100
2—
300
(6)
Unit
V
mA
µA
µA
mA
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
2. This capacitance value is driven by the constraints of the external voltage regulator supplying the V
value is in the range of 470 nF.
3. This value is acceptable to guarantee operation from 4.5 V to 5.5 V
4. External regulator and capacitance circuitry must be capable of providing I
operating range.
5. In-rush average current is seen only for short time during power-up and on standby exit (maximum 20 µs, depending on
external capacitances to be loaded).
6. The duration of the in-rush current depends on the capacitance placed on LV pins. BV decoupling capacitors must be sized
accordingly. Refer to I
value for minimum amount of current to be provided in cc.
MREG
while maintaining supply V
DD_BV
voltage. A typical
DD_BV
DD_BV
in
82/134 Doc ID 15131 Rev 6
SPC560B54/6x Electrical characterist ics
4.8.2 Low voltage dete ctor electrical characteristics
The device implements a power-on reset (POR) module to ensure correct power-up
initialization, as well as five low voltage detectors (L VDs) to monitor the V
voltage while device is supplied:
● POR monitors V
during the power-up phase to ensure device is maintained in a safe
DD
reset state (refer to RGM Destructive Event Status (RGM_DES) Register flag F_POR
in device reference manual)
● LVDHV3 monitors V
to ensure device reset below minimum functional supply (refer
DD
to RGM Destructive Event Status (RGM_DES) Register flag F_LVD27 in device
reference manu al)
● LVDHV3B monitors V
to ensure device reset below minimum functional supply
DD_BV
(refer to RGM Destructive Event Status (RGM_DES) Register flag F_LVD27_VREG in
device reference manual)
● LVDHV5 monitors V
when application uses device in the 5.0 V ± 10% range (refer to
DD
RGM Functional Event Status (RGM_FES) Register flag F_LVD45 in device reference
manual)
● LVDLVCOR monitors power domain No. 1 (refer to RGM Destructive Event Status
(RGM_DES) Register flag F_LVD12_PD1 in device reference manual)
● LVDLVBKP monitors power domain No. 0 (refer to RGM Destructive Event Status
(RGM_DES) Register flag F_LVD12_PD0 in device reference manual)
and the V
DD
DD_LV
Note: When enabled, power domain No. 2 is monitored through LVDLVBKP.
Figure 10. Low voltage detector vs reset
V
DD
V
LVDHVxH
V
LVDHVxL
RESET
Doc ID 15131 Rev 6 83/134
Electrical characteristics SPC560B54/6x
Table 27. Low voltage detector electrical characteristics
Symbol C Parameter Conditions
V
PORUP
V
PORH
V
LVDHV3H
V
LVDHV3L
V
LVDHV3BH
V
LVDHV3BL
V
LVDHV5H
V
LVDHV5L
V
LVDLVCORL
V
LVDLVBKPL
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
SR P Supply for functional POR module
CC P Power-on reset threshold 1.5 — 2.6
CC T LVDHV3 low voltage detector h i gh threshold — — 2.95
CC P LVDHV3 low voltage detector low threshold 2.7 — 2.9
CC P LVDHV3B low voltage detector high threshold — — 2.95
CC P LVDHV3B low voltage detector low threshold 2.7 — 2.9
CC T LVDHV5 low voltage detector h i gh threshold — — 4.5
CC P LVDHV5 low voltage detector low threshold 3.8 — 4.4
CC P LVDLVCOR low voltage detector low threshold 1.08 — 1.16
CC P LVDLVBKP low voltage detector low threshold 1.08 — 1.16
4.9 Power consumption
(1)
T
= 25 °C,
A
after trimming
Value
Unit
Min Typ Max
1.0 — 5.5
V
Table 28
provides DC electrical characteristics for significant application modes. These
values are indicative values; actual consumption depends on the application.
(2)
(4)
CC D
CC
CC
RUN mode maximum
average current
f
T
Tf
RUN mode typic al average
Tf
current
(5)
Pf
Pf
C
HALT mode current
(6)
PT
= 8 MHz — 12 —
CPU
= 16 MHz — 27 —
CPU
= 32 MHz — 43 —
CPU
= 48 MHz — 56 100
CPU
= 64 MHz — 70 125
CPU
Slow internal RC
oscillator (128 kHz)
running
P
DT
CC
STOP mode current
DT
(7)
Slow internal RC
oscillator (128 kHz)
running
PT
Table 28. Power consumption on VDD_BV and VDD_HV
Symbol C Parameter Conditions
I
DDMAX
I
DDRUN
I
DDHALT
I
DDSTOP
(1)
Value
Min Typ Max
— — 115
=25°C — 10 18
T
A
= 125 °C — 17 28
A
TA= 25 °C — 350
= 55 °C — 750 —
A
=85°C — 2 7
A
=105°C — 4 10
A
=125°C — 7 14
A
Unit
140
mA
(3)
mA
mA
900
(8)
µA
mADT
84/134 Doc ID 15131 Rev 6
SPC560B54/6x Electrical characterist ics
Table 28. Power consumption on VDD_BV and VDD_HV (continued)
Value
Symbol C Parameter Conditions
(1)
Min Typ Max
P
I
DDSTDBY2
DT
CC
STANDBY2 mode current
DT
DT
Slow internal RC
(9)
oscillator (128 kHz)
running
PT
T
I
DDSTDBY1
DT
DT
CC
STANDBY1 mode current
DT
Slow internal RC
(10)
oscillator (128 kHz)
running
DT
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
2. Running consumption does not include I/Os toggling which is highly dependent on the application. The given value is
thought to be a worst case value with all peripherals running, and code fetched from code flash while modify operation
ongoing on data flash. Notice that this value can be significantly reduced by application: switch off not used peripherals
(default), reduce peripheral frequency through internal prescaler, fetch from RAM most used functions, use low power
mode when possible.
3. Higher current may be sunk by device during power-up and standby exit. Please refer to in-rush average current in
Table 26
4. RUN current measured with typical application with accesses on both Flash and RAM.
5. Only for the “P” classification: Data and Code Flash in Normal Power. Code fetched from RAM: Serial IPs CAN and LIN in
loop back mode, DSPI as Master, PLL as system clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and running at
max frequency, periodic SW/WDG timer reset enabled.
6. Data Flash Power Down. Code Flash in Low Power. SIRC 128 kHz and FIRC 16 MHz on. 10 MHz XTAL clock. FlexCAN:
instances: 0, 1, 2 ON (clocked but not reception or transmission), instances: 4, 5, 6 clocks gated. LINFlex: instances: 0, 1,
2 ON (clocked but not reception or transmission), instance: 3 to 9 clocks gated. eMIOS: instance: 0 ON (16 channels on
PA[0]–PA[11] and PC[12]–PC[15]) with PWM 20 kHz, instance: 1 clock gated. DSPI: instance: 0 (clocked but no
communication), instance: 1 to 5 clocks gated. RTC/API ON. PIT ON. STM ON. ADC1 OFF. ADC0 ON but no conversion
except two analog watchdogs.
7. Only for the “P” classification: No clock, FIRC 16 MHz off, SIRC 128 kHz on, PLL off, HPvreg off, ULPVreg/LPVreg on. All
possible peripherals off and clock gated. Flash in power down mode.
8. When going from RUN to STOP mode and the core consumption is > 6 mA, it is normal operation for the main regulator
module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction temperatures
exceeding 125 °C and under these circumstances, it is possible for the current to initially exceed the maximum STOP
specification by up to 2 mA. After entering stop, the application junction temperature will reduce to the ambient level and
the main regulator will be automatically switched off when the load current is below 6 mA.
9. Only for the “P” classification: ULPreg on, HP/LPVreg off, 32 KB RAM on, device configured for minimum consumption, all
possible modules switched off.
10. ULPreg on, HP/LPVreg off, 8 KB RAM on, device configured for minimum consumption, all possible modules switched off.
.
TA= 25 °C — 30 100
=55°C — 75 —
A
= 85 °C — 180 700
A
= 105 °C — 315 1000
A
= 125 °C — 560 1700
A
TA=25°C — 20 60
=55°C — 45 —
A
= 85 °C — 100 350
A
= 105 °C — 165 500
A
= 125 °C — 280 900
A
Unit
µA
µA
Doc ID 15131 Rev 6 85/134
Electrical characteristics SPC560B54/6x
4.10 Flash memory electrical characteristics
4.10.1 Program/erase characteristics
Table 29
Table 29. Program and erase specifications
shows the program and erase characteristics.
Symbol C Parameter Conditions
t
dwprogram
t
16Kpperase
Double word (64 bits) program time
16 KB block preprogram and erase time
(4)
C
t
32Kpperase
t
128Kpperase
t
esus
t
ESRT
CC
32 KB block preprogram and erase time
128 KB block preprogram and erase time
D Erase Suspend Latency — — — 30 30 µs
C Erase Suspend Request Rate
Value
Code Flash
Min
—
Typ
(1)
18
Initial
Max
max
(2)
(3)
50 500 µs
Data Flash 22
Code Flash
—
200
500 5000 ms
Data Flash 300
Code Flash
—
300
600 5000 ms
Data Flash 400
Code Flash
—
600
1300 7500 ms
Data Flash 800
Code Flash 20 — — —
Data Flash 10 — — —
Unit
ms
1. Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change
pending device characterization.
2. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values
are characterized but not guaranteed.
4. Actual hardware programming times. This does not include software overhead.
Table 30. Flash module life
Value
Symbol C Parameter Conditions
Unit
Min Typ Max
Number of p rogram/erase
P/E CC C
cycles per block for 16 KB
blocks over the operating
temperature range (T
)
J
— 100000 — — cycles
Number of p rogram/erase
P/E CC C
cycles per block for 32 KB
blocks over the operating
temperature range (T
)
J
— 10000 100000 — cycles
86/134 Doc ID 15131 Rev 6
SPC560B54/6x Electrical characterist ics
Table 30. Flash module life
Value
Symbol C Parameter Conditions
Number of p rogram/erase
P/E CC C
cycles per block for 128 KB
blocks over the operating
— 1000 100000 — cycles
temperature range (TJ)
Min Typ Max
Unit
Retention CC C
Minimum data retention at
85 °C average ambient
temperature
(1)
Blocks with
0–1000 P/E cycles
Blocks with
1001–10000 P/E
cycles
20 — — years
10 — — years
Blocks with
10001–100000 P/E
5——years
cycles
1. Ambient temperature averaged over duration of application, not to exceed recom mended produc t operating temperature
range.
ECC circuitry provides correction of single bit faults and is used to improve further
automotive reliability results. Some units will experience single bit corrections throughout
the life of the product with no impact to product reliability.
Table 31. Flash read access timing
Symbol C Parameter Conditions
f
READ
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
CC
P
Maximum frequency for Flash reading
2 wait states 64
C 0 wait states 20
(1)
Max Unit
MHzC1 wait state40
4.10.2 Flash power supply DC characteristics
Table 32
Table 32. Flash power supply DC electrical characteristics
Symbol Parameter Conditions
I
CFREAD
I
DFREAD
I
CFMOD
I
DFMOD
Sum of the current consumption on
CC
V
Sum of the current consumption on
CC
V
modification (program/erase)
shows the power supply DC characteristics on external supply.
Flash module read
DD_HV
DD_HV
and V
and V
on read access
DD_BV
on matrix
DD_BV
= 64 MHz
f
CPU
Program/Erase
on-going while
reading
Flash registers
= 64 MHz
f
CPU
Doc ID 15131 Rev 6 87/134
(1)
Value
Min Typ Max
Code Flash — — 33
Data Flash — — 33
Code Flash — — 52
Data Flash — — 33
Unit
mA
mA
Electrical characteristics SPC560B54/6x
Table 32. Flash power supply DC electrical characteristics (continued)
Symbol Parameter Conditions
I
CFLPW
I
DFLPW
I
CFPWD
I
DFPWD
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified
Sum of the current consumption on
CC
V
DD_HV
and V
DD_BV
during Flash
low power mode
Sum of the current consumption on
CC
V
DD_HV
and V
DD_BV
during Flash
power down mode
—
—
4.10.3 Start-up/Switch-off timings
Table 33. Start-up time/Switch-off time
Symbol C Parameter Conditions
t
FLARSTEXIT
t
FLALPEXIT
t
FLAPDEXIT
t
FLALPENTRY
t
FLAPDENTRY
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
CC T Delay for Flash module to exit reset mode — — — 125
CC T Delay for Flash module to exit low-power mode — — — 0.5
CC T Delay for Flash module to exit power-down mode — — — 30
CC T Delay for Flash module to enter low-power mode — — — 0.5
CC T Delay for Flash module to enter power-down mode — — — 1.5
(1)
Value
Unit
Min Typ Max
Code Flash — — 1.1 mA
Data Flash — — 900 µA
Code Flash — — 150
Data Flash — — 150
(1)
Value
Unit
Min Typ Max
µA
µs
4.11 Electromagnetic compatibility (EMC) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
4.11.1 Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
88/134 Doc ID 15131 Rev 6
SPC560B54/6x Electrical characterist ics
Therefore it is recommended that the user apply EMC software optimization and
prequalification tests in relation with the EMC level requested for the application.
● Software recommendations − The softw are fl owchart must includ e t he ma na g eme nt of
runaway conditions such as:
– Corrupted program counter
– Unexpected reset
– Critical data corruption (control registers...)
● Prequalification trials − Most of the common failures (unexpected reset and program
counter corruption) can be reproduced by manually forcing a low state on the reset pin
or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device. When
unexpected behavior is detected, the software can be hardened to prevent
unrecoverable errors occurring (see application note
Improving Microcontroller EMC Performance
(AN1015)).
Software Techniques For
4.11.2 Electromagnetic interference (EMI)
The product is monitored in terms of emission based on a typical application. This emission
test conforms to the IEC61967-1 standard, which specifies the general conditions for EMI
measurements.
Table 34. EMI radiated emission measurement
(1)(2)
Value
Symbol C Parameter Conditions
Min Typ Max
— SR — Scan range — 0.150 1000 MHz
f
CPU
V
DD_LV
S
1. EMI testing and I/O port waveforms per IEC 61967-1, -2, -4
2. For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your local
SR — Operating frequency — — 64 — MHz
SR — LV operating voltages — — 1.28 — V
No PLL frequency
modulation
± 2% PLL
frequency
=
modulation
— — 18 dBµV
— — 14 dBµV
CC T Peak level
EMI
marketing representative.
VDD= 5V, TA=25°C,
LQFP144 package
Test conforming to IEC
61967-2,
f
=8 MHz/f
OSC
64 MHz
CPU
4.11.3 Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Unit
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts×( n + 1) suppl y p in ). This test
Doc ID 15131 Rev 6 89/134
Electrical characteristics SPC560B54/6x
conforms to the AEC-Q100-002/-003/-011 standard. For more details, refer to the
application note
Table 35. ESD absolute maximum ratings
Symbol Ratings Conditions Class Max value
Electrostatic Discharge Sensitivity Measurement
(1)(2)
(AN1181).
(3)
Unit
V
ESD(HBM)
V
ESD(MM)
V
ESD(CDM)
1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2. A device will be defined as a failure if aft er exposure to ESD pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at
room temperature followed by hot temperature, unless specified otherwise in the device specification.
3. Data based on characterization results, not tested in production
Electrostatic discharge voltage
(Human Body Model)
Electrostatic discharge voltage
(Machine Model)
Electrostatic discharge voltage
(Charged Device Model)
TA = 25 °C
conforming to AEC-Q100-002
TA = 25 °C
conforming to AEC-Q100-003
TA = 25 °C
conforming to AEC-Q100-011
H1C 2000
M2 200
500
C3A
750
(corners)
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up
performance:
● A supply overvoltage is applied to each power supply pin.
● A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 36. Latch-up results
V
Symbol Pa rameter Conditions Class
= 125 °C
T
LU Static latch-up class
A
conforming to JESD 78
II level A
4.12 Fast external crystal oscillator (4 to 16 MHz) electri cal
characteristics
The device provides an oscillator/resonator driver.
the internal oscillator driver and provides an example of a connection for an oscillator or a
resonator.
Table 37
provides the parameter description of 4 MHz to 16 MHz crystals used for the
design simulations.
90/134 Doc ID 15131 Rev 6
Figure 11
describes a simple model of
SPC560B54/6x Electrical characterist ics
Figure 11. Crystal oscillator and resonator connection scheme
EXTAL
C1
EXTAL
Crystal
XTAL
V
DD
I
R
DEVICE
C2
XTAL
EXTAL
DEVICE
Resonator
XTAL
DEVICE
Notes:
1. XTAL/EXTAL must not be directly used to drive external circuits
2. A series resistor may be required, according to crystal oscillator supplier recommendations.
Table 37. Crystal description
Nominal
frequency
(MHz)
NDK crystal
reference
Crystal
equivalent
series
resistance
ESR Ω
Crystal
motional
capacitance
) fF
(C
m
Crystal
motional
inductance
(Lm) mH
Load on
xtalin/xtalout
C1 = C2
(1)
(pF)
4 NX8045GB 300 2.68 591.0 21 2.93
8
300 2.46 160.7 17 3.01
10 150 2.93 86.6 15 2.91
NX5032GA
12 120 3.11 56.5 15 2.93
Shunt
capacitance
between
xtalout
and xtalin
(2)
(pF)
C0
16 120 3.90 25.3 10 3.00
1. The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing includes all
the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them.
2. The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads, package,
etc.).
Doc ID 15131 Rev 6 91/134
Electrical characteristics SPC560B54/6x
Figure 12. Fast external crystal oscillator (4 to 16 MHz) timing diagram
S_MTRANS bit (ME_GS register)
1
0
V
V
MXOSC
V
MXOSCOP
XTAL
T
MXOSCSU
90%
10%
valid internal clock
1/f
MXOSC
Table 38. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
Symbol C Parameter Conditions
(1)
Value
Min Typ Max
f
FXOSC
SR —
CC C
Fast external cr ystal
oscillator frequency
V
= 3.3 V ± 10%,
DD
PAD3V5V = 1
—4.0—16.0MHz
2.2 — 8.2
OSCILLATOR_MARGIN = 0
V
= 5.0 V ± 10%,
DD
PAD3V5V = 0
OSCILLATOR_MARGIN = 0
V
= 3.3 V ± 10%,
DD
PAD3V5V = 1
2.0 — 7.4
2.7 — 9.7
g
mFXOSC
CC P
Fast external cr ystal
oscillator
transconductance
CC C
OSCILLATOR_MARGIN = 1
V
= 5.0 V ± 10%,
CC C
DD
PAD3V5V = 0
2.5 — 9.2
OSCILLATOR_MARGIN = 1
=4MHz,
f
V
FXOSC
CC T
Oscillation amplitude at
EXTAL
OSC
OSCILLATOR_MARGIN = 0
=16MHz,
f
OSC
OSCILLATOR_MARGIN = 1
1.3 — —
1.3 — —
Unit
mA/V
V
V
FXOSCOP
I
FXOSC
(2)
CC C
CC T
Oscillation operating
point
Fast external cr ystal
oscillator consumption
— — 0.95 — V
——23mA
92/134 Doc ID 15131 Rev 6
SPC560B54/6x Electrical characterist ics
Table 38. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics (continued)
Value
Symbol C Parameter Conditions
(1)
Min Typ Max
f
= 4 MHz,
OSC
t
FXOSCSU
CC T
Fast external cr ystal
oscillator start-up time
OSCILLATOR_MARGIN = 0
= 16 MHz,
f
OSC
OSCILLATOR_MARGIN = 1
V
V
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.
2. Stated values take into account only analog module consumption but not the digital contributor (clock tree and enabled
peripherals).
SR P
IH
SR P
IL
Input high level CMOS
(Schmitt Trigger)
Input low level CMOS
(Schmitt Trigger)
Oscillator bypa ss mode 0.65V
Oscillator bypa ss mode −0.4 — 0.35V
—— 6
——1.8
—VDD+0.4 V
DD
DD
4.13 Slow external crystal oscillator (32 kHz) electr ical
characteristics
The device provides a low power oscillator/resonator driver.
Figure 13. Crystal oscillator and resonator connection scheme
Unit
ms
V
OSC32K_EXTAL
OSC32K_XTAL
DEVICE
Note: OSC32_XTAL/OSC32_EXTAL must not be directly used to drive external circuits
OSC32K_EXTAL
C1
R
Crystal
P
Resonator
OSC32K_XTAL
C2
DEVICE
Doc ID 15131 Rev 6 93/134
Electrical characteristics SPC560B54/6x
Figure 14. lEquivalent circuit of a quartz crystal
C0
Crystal
C2C1
C1
Table 39. Crystal motional characteristics
(1)
Symbol Parameter Conditions
L
Motional inductance — — 11.796 — KH
m
C
Motional capacitance — — 2 — fF
m
Load capacitance at O SC32K_XT AL a nd
C1/C2
OSC32K_EXTAL with respect to
(2)
ground
— 18 — 28 pF
AC coupled at C0 = 2.85 pF
(3)
R
Motional resistance
m
AC coupled at C0 = 4.9 pF
AC coupled at C0 = 7.0 pF
AC coupled at C0 = 9.0 pF
C
R
m
m
L
m
C2
Value
Unit
Min Typ Max
(4)
——65
(4)
(4)
(4)
——50
kW
——35
——30
1. The crystal used is Epson Toyocom MC306.
2. This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to ground. It
includes all the parasitics due to board traces, crystal and package.
3. Maximum ESR (R
4. C0 Includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins.
) of the crystal is 50 kΩ
m
94/134 Doc ID 15131 Rev 6
SPC560B54/6x Electrical characterist ics
Figure 15. Slow external crystal oscillator (32 kHz) timing diagram
OSCON bit (OSC_CTL register)
1
0
V
OSC32K_XTAL
V
LPXOSC32K
T
LPXOSC32KSU
Table 40. Slow external crystal oscillator (32 kHz) electrical characteristics
90%
10%
valid internal clock
1/f
LPXOSC32K
Value
Symbol C Parameter Conditions
(1)
Min Typ Max
f
SXOSC
V
SXOSC
I
SXOSCBIAS
I
SXOSC
t
SXOSCSU
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified. Values are specified for no neighbor
GPIO pin activity. If oscillator is enabled (OSC32K_XTAL and OSC32K_EXTAL pins), neighboring pins should not toggle.
2. Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal.
SR — Slow external crystal oscillator frequency — 32 32.768 40 kHz
CC T Oscillation amplitude — — 2.1 — V
CC T Oscillation bias current — 2.5 µA
CC T
CC T
Slow external crystal oscillator
consumption
Slow external crystal oscillator start-up
time
———8µA
———2
(2)
4.14 FMPLL electrical characteristics
The device provides a frequency modulated phase locked loop (FMPLL) module to generate
a fast system clock from the main oscillator driver.
Table 41. FMPLL electrical characteristics
Symbol C Parameter Conditions
f
PLLIN
Δ
PLLIN
SR — FMPLL reference clock
SR —
FMPLL reference clock duty
(2)
cycle
(2)
(1)
Value
Min Typ Max
—4—64MHz
—40—60%
Unit
s
Unit
Doc ID 15131 Rev 6 95/134
Electrical characteristics SPC560B54/6x
Table 41. FMPLL electrical characteristics (continued)
Value
Symbol C Parameter Conditions
(1)
Min Typ Max
f
PLLOUT
f
VCO
f
CPU
f
FREE
t
LOCK
Δt
STJIT
Δt
I
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
2. PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in functional
3. Frequency modulation is considered ± 4%.
4. f
5. Short term jitter is measured on the clock rising edge at cycle n and n+4.
CC P
(3)
CC
SR — System clock frequency — — — 64
CC P Free-running frequency — 20 — 150 MHz
CC P FMPLL lock time
CC — FMPLL short term jitter
CC — FMPLL long term jitter f
LTJIT
CC C FMPLL consumption TA = 25 °C — — 4 mA
PLL
mode. When bypass mode is used, oscillator input clock should verify f
64 MHz can be achieved only at up to 105 °C.
CPU
FMPLL output clock
frequency
VCO frequency without
P
frequency modulation
VCO frequency with
P
frequency modulation
(5)
—16—64MHz
— 256 — 512
— 245.76 — 532.48
Stable oscillator
=16MHz)
(f
PLLIN
f
maximum –4 — 4 %
sys
at 64 MHz, 4000 cycles — — 10 ns
PLLCLK
PLLIN
and Δ
PLLIN
.
40 100 µs
(4)
Unit
MHz
MHz
4.15 Fast internal RC oscillator (16 MHz) electrical characteri stics
The device provides a 16 MHz main internal RC oscillator. This is used as the default clock
at the power-up of the device.
Table 42. Fast internal RC oscillator (16 MHz) electrical characteristics
Symbol C Parameter Conditions
f
FIRC
I
FIRCRUN
I
FIRCPWD
(1)
Value
Min Typ Max
CC P
SR — — 12 20
(2)
CC T
Fast internal RC oscillator
high frequency
Fast internal RC oscillator
high frequency current in
TA = 25 °C, trimmed — 16 —
TA = 25 °C, trimmed — — 200 µA
running mode
Fast internal RC oscillator
CC D
high frequency current in
TA = 25 °C — — 10 µA
power down mode
Unit
MHz
96/134 Doc ID 15131 Rev 6
SPC560B54/6x Electrical characterist ics
Table 42. Fast internal RC oscillator (16 MHz) electrical characteristics (continued)
Value
Symbol C Parameter Conditions
(1)
Min Typ Max
sysclk = off — 500 —
sysclk = 2 MHz — 600 —
sysclk = 4 MHz — 700 —
sysclk = 8 MHz — 900 —
I
FIRCSTOP
CC T
Fast internal RC oscillator
high frequency and system
clock current in stop mode
TA = 25 °C
sysclk = 16 MHz — 1250 —
t
FIRCSU
CC C
Fast internal RC oscillator
start-up time
= 5.0 V ± 10% — 1.1 2.0 µs
V
DD
Fast internal RC oscillator
Δ
FIRCPRE
Δ
FIRCTRIM
CC C
CC C
precision after software
trimming of f
FIRC
Fast internal RC oscillator
trimming step
TA = 25 °C −1—1%
TA = 25 °C — 1.6 %
Fast internal RC oscillator
variation over temperature
Δ
FIRCVAR
CC C
and supply with respect to
at TA=25°C in high-
f
FIRC
— −5—5%
frequency configuration
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
2. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON.
Unit
µA
4.16 Slow internal RC oscillator (128 kHz) electrical
characteristics
The device provides a 128 kHz low power internal RC oscillator. This can be used as the
refer ence clock for the RTC module.
Table 43. Slow internal RC oscillator (128 kHz) electrical characteristics
Symbol C Parameter Conditions
f
SIRC
I
SIRC
t
SIRCSU
(1)
CC P
SR — — 100 — 150
(2)
CC C
CC P
Slow internal RC oscillator low
frequency
Slow internal RC oscillator low
frequency current
Slow internal RC oscillator start-up
time
TA = 25 °C, trimmed — 128 —
= 25 °C, trimmed — — 5 µA
T
A
TA = 25 °C, VDD = 5.0 V ±
10%
Value
Unit
Min Typ Max
kHz
—812µs
Doc ID 15131 Rev 6 97/134
Electrical characteristics SPC560B54/6x
Table 43. Slow internal RC oscillator (128 kHz) electrical characteristics (continued)
Value
Symbol C Parameter Conditions
(1)
Min Typ Max
Δ
SIRCPRE
Δ
SIRCTRIM
CC C
CC C
Slow internal RC oscillator precision
after software trimming of f
SIRC
Slow internal RC oscillator trimming
step
TA = 25 °C −2—2
——2.7—
Slow internal RC oscillato r variati on in
Δ
SIRCVAR
CC C
temperature and supply with respect
to f
at TA= 55 °C in high
SIRC
High frequency
configuration
−10 — 10 %
frequency configur ati on
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
2. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON.
4.17 ADC electrical characteristics
4.17.1 Introduction
The device provides two Successive Approximation Register (SAR) analog-to-digital
converters (10-bit and 12-bit).
Unit
%
98/134 Doc ID 15131 Rev 6
SPC560B54/6x Electrical characterist ics
Figure 16. ADC_0 characteristic and error definitions
code out
1023
1022
1021
1020
1019
1018
Offset Error (EO)
1 LSB ideal = V
(2)
7
(1)
6
5
(5)
4
3
2
(4)
(3)
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer curve
Gain Error (E
DD_ADC
/ 1024
)
G
1
0
1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023
Offset Error (E
O
)
1 LSB (ideal)
V
in(A)
4.17.2 Input impedance and ADC accuracy
In the following analysis, the input circuit corresponding to the precise channels is
considered.
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have
low AC impedance. Placing a capacitor with good high frequency characteristics at the input
pin of the device can be effective: the capacitor should be as large as possible, ideally
infinite. This capacitor contributes to attenuating the noise present on the input pin;
furthermore, it sources charge during the sampling phase, when the analog signal source is
a high-impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the
input pin (simple RC filter). The RC filtering may be limited according to the value of source
impedance of the transducer or circuit supplying the analog signal to be measured. The filter
Doc ID 15131 Rev 6 99/134
(LSB
ideal
)
Electrical characteristics SPC560B54/6x
at the input pins must be designed taking into account the dynamic characteristics of the
input signal (bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the
sampling capacitance: C
being substantially a switched capacitance, with a frequency
S
equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For
instance, assuming a conversion rate of 1 MHz, with C
kΩ is obtained (R
= 1 / (fc*CS), where fc represents the conversion rate at the considered
EQ
equal to 3 pF, a resistance of 330
S
channel). To minimize the error induced by the voltage partitioning between this resistance
(sampled voltage on C
) and the sum of RS + RF + RL + RSW + RAD, the external circuit
S
must be designed to respect the <Cross Refs>Equation 4:
Equation 4:
RSRFRLR
+++ +
-------------------------------------------------------------------------- -
V
•
A
R
EQ
SWRAD
<
1
-- -LSB
2
<Cross Refs>Equation 4 generates a constraint for external network design, in particular on
resistive path. Internal switch resistances (R
and RAD) can be neglected with respect to
SW
external resistances.
Figure 17. Input equivalent circuit (precise channels)
EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME
Source Filter Current Limiter
R
S
V
A
RS Source Impedance
RF Filter Resistance
CF Filter Capacitance
RL Current Limiter Resistance
RSW1 Channel Selection Switch Impedance
RADSampling Switch Impedance
CP Pin Capacitance (two contributions, CP1 and CP2)
CS Sampling Capacitance
R
F
C
F
V
DD
Channel
Selection
R
L
C
P1
R
SW1
Sampling
R
AD
C
P2
C
S
100/134 Doc ID 15131 Rev 6
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