ST M28W320EBT, M28W320EBB User Manual

FEATURES SUMMARY

■ SUPPLY VOLTAGE

= 2.7V to 3.6V Core Power Supply

–V

DD

–V
–V

■ ACCESS TIME: 70, 85, 90,100ns

■ PROGRAMMING TIME

= 1.65V to 3.6V for Input/Output

DDQ

= 12V for fast Program (optional)

PP

– 10µs typical
– Double Word Programming Option
– Quadruple Word Programming Option

■ COMMON FLASH INTERFACE

■ MEMORY BLOCKS

– Parameter Blocks (Top or Bottom location)
– Main Blocks

■ BLOCK PROTECTIO N o n TWO PARAMETER

BLOCKS
–WP

for Block Protection

■ AUTOMATIC STAND-BY MODE

■ PROGRAM and ERASE SUSPEND

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h
– Top Device Code, M28W320EBT: 88BCh
– Bottom Device Code, M28W320EBB: 88BDh

M28W320EBT

M28W320EBB

32 Mbit (2Mb x16, Boot Block)

3V Supply Flash Me m ory

PRELIMINARY DATA

Figure 1. Packages

FBGA

TFBGA47 (ZB)

6.39 x 6.37mm

TSOP48 (N)

12 x 20mm

October 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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M28W320EBT, M28W320EBB

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

V

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

DD

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

V

DDQ

V

Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

PP

V

Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SS

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Read.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0

Write.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read Memory Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Read Electronic Signature Comma nd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Clear Status Regist e r Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Program/Erase Suspend Comm and . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Program/Eras e Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 5. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

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M28W320EBT, M28W320EBB

Table 6. Memory Blocks Protection Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 7. Program, Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 15

STATUS REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Erase Status (Bit 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

V

Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

PP

Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 8. Status Re gister Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 9. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9

Table 10. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 7. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 11. Device Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 12. DC Characte r i stics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 8. Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 13. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 9. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 14. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 10. Write AC Wavefo rms, Chip Enable Control led. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 15. Write AC Chara cte ristics, Chip Enabl e Contro lled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 11. Power-Up and Reset AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 16. Power-Up and Res et AC Charac te r istics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 12. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . 27

Table 17. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 27
Figure 13. TFBGA47 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, Bottom View Package Outlin e28
Table 18. TFBGA47 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, Package Mecha nical Data . . . 28

Figure 14. TFBGA47 Daisy Chain - Package Connections (Top view through package) . . . . . . . . 29

Figure 15. TFBGA47 Daisy Chain - PCB Connections proposal (Top view through package). . . . 29

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 19. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 20. Daisy Chain Orde r ing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

APPENDIX A. BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

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M28W320EBT, M28W320EBB

Table 21. Top Boot Block Addresses, M28W320EBT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 22. Botto m Boo t Block Addresses, M28W320E BB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 23. Query Stru cture Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 24. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 25. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 26. Device Geome try Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 27. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 28. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6

APPENDIX C. FLOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 16. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 17. Double Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 19. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 40

Figure 20. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 21. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 42

APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE . . . . . . . 43

Table 29. Write State Machine Current/Next. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 30. Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

4/45

SUMMARY DESCRIPTION

The M28W320EB is a 32 M bit (2 Mbit x 16) non­volatile Flash memory that can b e erased electri­cally at the block level and programmed in-system
on a Word-by-Word basis. These operations can
be performed using a single low voltage (2.7 to

3.6V) supply. V
down to 1.65V. An optional 12V V

allows to drive the I/O pin

DDQ

power supply

PP

is provided to speed up customer programming.
The device features an asymmetrical blocked ar-

chitecture. The M28W320EB has an array of 71
blocks: 8 Parameter Blocks of 4 KWord and 63
Main Blocks of 32 KWord. M28W320EBT has the
Parameter Blocks at the top of the memory ad­dress space while the M28W320EBB locates the
Parameter Blocks starting from the bottom. The
memory maps are shown in Figure 5, Block Ad­dresses.

Parameter blocks 0 and 1 can be protected from
accidental programming or erasure. Each block
can be erased separately. Erase can be suspend­ed in order to perform either read or program in
any other block and then resumed . Program can
be suspended to read data in any other block and
then resumed. Each block can be programmed
and erased over 100,000 cycles.

Program and Erase command s are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller takes care of the tim­ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.

The memory is offered in TSOP48 (10 X 20mm),
and TFBGA47 (6.39 x 6.37mm, 0.75mm pitch)
packages and is supplied with all the bits erased
(set to ’1’).

M28W320EBT, M28W320EBB

Figure 2. Logic Diagram

V

V

DDQVPP

DD

21

A0-A20

W

E
G

RP

WP

Table 1. Signal Names

A0-A20 Address Inputs
DQ0-DQ15 Data Input/Output
E
G
W
RP

M28W320EBT
M28W320EBB

V

SS

Chip Enable
Output Enable
Write Enable
Reset

16

DQ0-DQ15

AI05514

WP
V

DD

V

DDQ

V

PP

V

SS

Write Protect
Core Power Supply
Power Supply for

Input/Output
Optional Supply Voltage for

Fast Program & Erase
Ground

5/45

M28W320EBT, M28W320EBB

Figure 3. TSOP Con necti on s

A15
A14
A13
A12
A11

1

48

A16
V

DDQ

V

SS

DQ15
DQ7

A10 DQ14

37
36

DQ6
DQ13
DQ5
DQ12
DQ4
V

DD

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
V

SS

E
A0

A9
A8

NC

A20

RP

V

PP

WP
A19
A18
A17

A7
A6
A5
A4
A3
A2
A1

W

12

M28W320EBT
M28W320EBB

13

24 25

6/45

AI05515

Figure 4. TFBGA Connections (Top view through package)

M28W320EBT, M28W320EBB

87654321

A

B

C

D

E

F

DDQ

SS

DQ7V

A8A11A13

DQ13

PP

RP A18

DQ11

DQ12

DQ4

WP A19

A20

DQ2

DD

A7V

A5A17WA10A14

DQ0DQ9DQ3DQ6DQ15V

DQ1DQ10V

A4

A2

A1A3A6A9A12A15

A0EDQ8DQ5DQ14A16

V

SS

G

AI03823

7/45

M28W320EBT, M28W320EBB

Figure 5. Block Addresses

M28W320EBT

Top Boot Block Addresses

1FFFFF

1FF000

1F8FFF

1F8000

1F7FFF

1F0000

00FFFF

008000

007FFF

000000

4 KWords

4 KWords

32 KWords

32 KWords

32 KWords

Total of 8

4 KWord Blocks

Total of 63

32 KWord Blocks

M28W320EBB

Bottom Boot Block Addresses

1FFFFF

1F8000

1F7FFF

1F0000

00FFFF

008000

007FFF

007000

000FFF

000000

32 KWords

32 KWords

32 KWords

4 KWords

4 KWords

Total of 63

32 KWord Blocks

Total of 8

4 KWord Blocks

AI05516

Note: Also see Appendix A, Tables 21 and 22 f or a full listing of the Block A ddresses.

8/45

SIGNAL DESCRIPTIONS

See Figure 2 Logic Diagram and T able 1,Signal
Names, for a brief overview of the signals connect­ed to this de vice.

Address Inputs (A0-A20). The Address Inputs
select the cell s in th e memory array to a ccess dur­ing Bus Read operations. During Bus Write opera­tions they control the commands sent to the
Command Interface of the internal state machine.

Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or data to be programmed during a Write Bus op­eration.

Chip Enable (E

). The Chip Enable input acti-

vates the memory control logic, input bu ffers, de­coders and sense amplifiers. When Chip Enable is

and Reset is at VIH the device is in active

at V

IL

mode. When Chi p E nable is at V

the memory is

IH

deselected, the outputs are high impedan ce and
the power consumption is reduced to the stand-by
level.

Output Enable (G

). The Output Enable controls

data outputs during the Bus Read operation of the
memory.

Write Enable (W

). The Write Enable controls the

Bus Write operation of the memory’s Command
Interface. The data and address inputs are latched
on the rising edge of Chip Enable, E, or Write En­able, W

Write Protect (WP

, whichever occurs first.

). Write Protect is an input to
protect or unprotect the two lockable parameter
blocks. When Write Protect is at V

, the lockable

IL

blocks are protected and Program or Erase oper­ations are not possible. When Wr ite Protect is at

, the lockable blocks are unprotected and can

V

IH

be programmed or erased (refer to Table 5, Mem­ory Blocks Protect ion Truth).

Reset (RP

ware reset of the memory. W hen Reset is at V

). The Reset input provides a hard-

IL

the memory is in reset mode: the outputs are high
impedance and the current consumption is mini­mized. When Reset is at V

, the device is in nor-

IH

M28W320EBT, M28W320EBB

mal operation. Exiting reset mode the device
enters read array mode, but a negative trans ition
of Chip Enable or a change of the address is re­quired to ensure valid data outputs.

V

Supply Voltage. VDD provides the power

DD

supply to the internal core of the memory device.
It is the main power supply for all operations
(Read, Program and Erase).

Su pp ly V olt ag e . V

V

DDQ

power supply to the I/O pins a nd ena bles all Out­puts to be powered independently from V
can be tied to VDD or can use a separate supply.

V

Program Supply Voltage. VPP is both a

PP

control input and a power supply pin. The two
functions are selected by the voltage range ap­plied to the pin. The Supply Voltage V
Program Supply Voltage V
any order.

If V

is kept in a low voltage range (0V to 3.6V)

PP

V

is seen as a control input. In this case a volt-

PP

age lower than V

gives an absolute protection

PPLK

against program or erase, whi le V
ables these functions (see Table 12, DC Charac­teristics for the relevant values). V
sampled at the beginning of a Program or Erase;
a change in its value after the operation has start­ed does not have any effect on Program or Erase,
however for Double or Q uadruple Word Program
the results are uncertain.

is in the range 11.4V to 12.6V it acts as a

If V

PP

power supply pin. In t his condition V
stable until the Program/Erase algorithm i s com­pleted (see Table 14 and 15).

Ground. VSS is the reference for all voltage

V

SS

measurements.

Note: Each device in a system should have
V

DD,VDDQ

and VPP decoupled with a 0.1µF ca-

pacitor close to the pin. See Figure 7, AC Mea-

,

surement Load Circu it. The PCB trace widths
should be sufficient to carry the required V
Program and Erase currents.

provides the

DDQ

can be applied in

PP

PP

DD

and the

DD

> V

is only

PP

must be

PP

. V

PP1

DDQ

en-

PP

9/45

M28W320EBT, M28W320EBB

BUS OPERATIONS

There are six standard bus operations that control
the device. These are Bus Read, Bus Wri te, Out­put Disable, Standby, Automatic Standby and Re­set. See Table 2, Bus Operations, for a summary.

Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.

Read. Read Bus operations are used to output
the contents of the Memory Array, the Electronic
Signature, the Status Register and the Common
Flash Interface. Both Chip Enable and Output En­able must be at V
eration. The Chip Enable input should be used t o
enable the device. Out put E nable shoul d be used
to gate data onto th e output. The data read de­pends on the previous command written to the
memory (see Command Interface section). See
Figure 8, Read Mode AC Wa veforms, and Table
13, Read AC Characteristics, for details of when
the output becomes valid.

Read mode is the default state of the device when
exiting Reset or after power-up.

Write. Bus Write operations write Comm ands to
the memory or latch Input Data to be programmed.
A write operation is initiated when Chip Enable
and Write Enable are at V
V

. Commands, Input Data and Addresses are

IH

latched on the rising edge of Write Enable or Chip
Enable, whichever occurs first.

in order to perform a read op-

IL

with Output Enable at

IL

See Figures 9 and 10, Write AC Waveforms, and
Tables 14 and 15, Write AC Characteristics, for
details of the timing requirements.

Output Disa bl e . The data outputs are high im­pedance when the Output Enable is at V

.

IH

Standby. Stan dby disables most of the inte rnal
circuitry allowing a substantial reduction of the cur­rent consumption. The memory is in stand-by
when Chip Enable is at V

and the device is in

IH

read mode. The power consumption is reduced to
the stand-by level and the o utputs are set to high
impedance, independently from the Output Enable
or Write Enable inputs. If Chip Enable switches to
V

during a program or erase operation, t he de-

IH

vice enters Standby mode when finished.
Automatic Standby. Automatic Standby pro-

vides a low power consumption state during Read
mode. Following a read operation, the device en­ters Automatic Standby after 150ns of bus inactiv­ity, even if Chip Enable is low, V
current is reduced to I

. The data I nputs/Out-

DD1

, and the supply

IL

puts will st ill ou t p ut d ata.
Reset. During Reset mode, when Output Enable

is low, V

, the memory is deselected and the out-

IL

puts are high impedance. The memory is in Reset
mode when Reset is at V

. The power consump-

IL

tion is reduced to the Standby level, independently
from the Chip Enable, Output Enable or Write En­able inputs. If Reset is pulled to V

during a Pro-

SS

gram or Erase, this operation is aborted and the
memory content is no longer valid.

Table 2. Bus Operations

Operation E G W RP WP

Read
Write
Output Disable
Standby
Reset X X X

Note: X = VIL or VIH, V

10/45

V
V
V
V

= 12V ± 5%.

PPH

IL

IL

IL

IH

V

IL

V

IH

V

IH

XX

V

IH

V

IL

V

IH

V

IH

V

IH

V

IH

V

IH

V

IL

V

PP

X Don’t Care Data Output

V

X
X Don’t Care Hi-Z
X Don’t Care Hi-Z
X Don’t Care Hi-Z

DD

or V

PPH

DQ0-DQ15

Data Input

COMMAND INTERFACE

All Bus Write operations t o the me mory are in ter­preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper­ations. An internal Program/Erase Controller han­dles all timings and verifies the correct execution
of the Program and Erase commands. The Pro­gram/Erase Controller provides a Status Regi ster
whose output may be read at any time, to monitor
the progress of an operation, or the Program/
Erase states. See T able 3, Command Codes , for
a summary of the commands and see Appendix D,
Table 29, Write State Machine Current/Next, for a
summary of the Command Interface.

The Command Interface is reset to Read mode
when power is first applied, when exiting from Re­set or whenever V

is lower than V

DD

LKO

. Com­mand sequences must be followed exactly. Any
invalid combination of commands will reset the de­vice to Read mode. Refer to Table 4, Commands,
in conjunction with the text descriptions below.

Read Memory Array command

The Read command returns the memory to its
Read mode. One Bus Write cycle is required to is­sue the Read Memory Array command and return
the memory to Read mode. Subsequ ent read op­erations will read the addressed location and out­put the data. When a device Reset occurs, the
memory defaults to Read mode.

Read Status Register Command

The Status Register indicates when a program or
erase operation is complete and the success or
failure of the operation itself. Issue a Read Status
Register command to rea d the Status Register’s
contents. Subsequent Bus Read op erations read
the Status Register, at any addres s, until anot her
command is issued. See Tab le 8, Status Register
Bits, for details on the definitions of the bits.

The Read Status Register command m ay be is­sued at any time, even during a Program/Erase
operation. Any Read attempt during a Program/
Erase operation will automatically output the con­tent of the Status Register.

Read Electronic Signature Command

The Read Electronic Signature command reads
the Manufacturer and Device Codes.

The Read Electronic Signature command consists
of one write cycle, a subsequent read will ou tput
the Manufacturer or the Device Code depending
on the levels of A0. The Manufacturer Code is out­put when the address line A0 is at V
Code is output when A 0 is at V
A7 must be kept to V

, other addresses are ig-

IL

, the Device

IL

. Addresses A1-

IH

nored. The codes are output on DQ0-DQ7 with
DQ8-DQ15 at 00h. (see Table 5)

M28W320EBT, M28W320EBB

Table 3. Command Codes

Hex Code Command

10h Program
20h Erase
30h
40h Program
50h Clear Status Register
55h Reserved
56h
70h Read Status Register
90h Read Electronic Signature
98h Read CFI Query
B0h Program/Erase Suspend

D0h Program/Erase Resume

FFh Read Memory Array

Read CFI Query Command

The Read Query Command is used to read dat a
from the Common Flash Interface (CFI) Me mory
Area, allowing programming equi pment or appli­cations to automatically match their interface to
the characteristics of the device.

One Bus Write cycle is required to issue the Read
Query Command. Once the command is issued
subsequent Bus Read operations read from the
Common Flash Interfac e Memory Area. See Ap­pendix B, Common Flash Interface, Tables 23, 24,
25, 26, 27 and 28 for details on the information
contained in the Common Flash Interface memory
area.

Block Erase Command

The Block Erase com mand can be used to erase
a block. It sets all the bits within the selected block
to ’1’. A ll previous data in t he block is lost. If the
block is protected then the Erase operation will
abort, the data in the block will not be changed and
the Status Register will output the error.

Two Bus Write cycles are required to issue the
command.

■ The first bus cycle sets up the Erase command.

■ The second latches the block address in the

internal state machine and starts the Program/
Erase Controller.

If the second bus cycle is not Write Erase Confirm
(D0h), Status Register bits b4 and b5 are set and
the command aborts.

Double Word Program

Quadruple Word Program

11/45

M28W320EBT, M28W320EBB

Erase aborts if Reset turns to VIL. As data integrity
cannot be guaranteed when the Erase operation is
aborted, the block must be erased again.

During Erase operations the memory will onl y ac­cept the Read Status Register command and the
Program/Erase Suspend command, all other com­mands will be ignored. Typical Erase times are
given in Table 7, Program, Erase Times and Pr o­gram/Erase Endurance Cycles.

See Appendix C , Figure 20, Erase Fl owchart and
Pseudo Code, for the flowchart for using the Erase
command.

Program Command

The memory array can be programmed word-by­word. Two bus write cycles are required to issue
the Program command.

■ The first bus cycle sets up the Program

command.

■ The second latches the Address and the Data to

be written and starts the Program/Erase
Controller.

During Program operations the memory will only
accept the Read Status Register command and
the Program/Erase Su spend command. All ot her
commands will be ignored. Typical Program times
are given in Table 7, Prog ram, Erase Times and
Program/Erase Endurance Cycles.

Programming aborts if Reset goe s to V

. As data

IL

integrity cannot be guaranteed when the program
operation is aborted, the block containing the
memory location must be erased and repro­grammed.

See Appendix C, Figure 16, Program Flowchart
and Pseudo Code, for the f lowchart for using the
Program command.

Double Word Program Command

This feature is offered to improve the programming
throughput, writing a page of two adjacent words
in parallel.The two words m ust differ only for the
address A0. Programm ing s hould not b e at t emp t­ed when V

is not at V

PP

PPH

.

Three bus write cycles are necessary to issue the
Double Word Program command.

■ The first bus cycle sets up the Double Word

Program command.

■ The second bus cycle latches the Address and

the Data of the first word to be written.

■ The third bus cycle latches the Address and the

Data of the second word to be written and starts
the Program/Erase Controller.

Read operations output the Status Register con­tent after the programming has s tarted. Program­ming aborts if Res et goes to V

. As data integrity

IL

cannot be guaranteed when the program opera-

tion is aborted, the block containing the memory
location must be erased and reprogrammed.

See Appendix C, Figure 17, Double Word Pro­gram Flowchart and Pseudo Code, for the flow­chart for using the Double Word Program
command.

Quadruple Word Program Command

This feature is offered to improve the programming
throughput, writing a page of four adjacent words
in parallel.The four words must differ only for the
addresses A0 and A1. Programming should not be
attempted when V

is not at V

PP

PPH

.

Five bus write cycles are necessary to issue the
Quadruple Word Program command.

■ The first bus cycle sets up the Quadruple Word

Program Command.

■ The second bus cycle latches the Address and

the Data of the first word to be written.

■ The third bus cycle latches the Address and the

Data of the second word to be written.

■ The fourth bus cycle latches the Address and

the Data of the third word to be written.

■ The fifth bus cycle latches the Ad dr es s and th e

Data of the fourth word to be written and starts
the Program/Erase Controller.

Read operations output the Status Register con­tent after the programming has s tarted. Program­ming aborts if Reset goes to V

. As data integrity

IL

cannot be guaranteed when the program opera­tion is aborted, the block containing the memory
location must be erased and reprogrammed.

See Appendix C, Figure 18, Quadruple Word Pro­gram Flowchart and Pseudo Code, for the flow­chart for using the Quadruple Word Program
command.

Clear Status Register Command

The Clear Status Register comm and can be used
to reset bits 1, 3, 4 and 5 in the Status Register to
‘0’. One bus write cycle is required to issue the
Clear Status Register command.

The bits in the Status Register do not automatical­ly return to ‘0’ when a new Program or Erase com­mand is issued. The error bits in the Status
Register should be cleared before attempting a
new Program or Erase command.

Program/Erase Suspend Command

The Program/Erase Suspend command is used to
pause a Program or Erase operation. One bus
write cycle is required to issue the Program/Erase
command and pau se the Prog ram/Erase control­ler.

During Program/Erase Suspend the Command In­terface will accept the Program/Erase Resume,
Read Array, Read Status Register, Read Electron­ic Signature and Read CFI Query commands. Ad-

12/45

M28W320EBT, M28W320EBB

ditionally, if the suspend operation was Erase then
the Program, Double Wo rd P rogram and Q uadru­ple Word Program commands will also be accept­ed. Only the blocks no t be i ng era se d may be read
or programmed correctly.

During a Program/Erase Suspend, the device can
be placed in a pseudo-standby mode by taking
Chip Ena ble to V
Reset turns to V

. Program/Erase is aborted if

IH

.

IL

See Appendix C, Figure 19 , Program Suspend &
Resume Flowchart and Pseudo Code, and Figure
21, Erase Suspend & Resume Flowchart and
Pseudo Code for flowcharts for using the Program/
Erase Suspend command.

Program/Erase Resume Command

The Program/Erase Resume command can be
used to restart the Program/Erase Controller after
a Program/Erase Suspend o peration has paused
it. One Bus Write cycle is required to issue the
command. Once the command is issued subse-

quent Bus Read operations read the Status Reg­ister.

See Appendix C, Figure 19, Program or Double
Word Program Suspend & Resume Flowchart and
Pseudo Code, an d Figure 21, Erase Sus pend &
Resume Flowchart and Pseudo Code for flow­charts for using the Program/Erase Resume com­mand.

Block Protection

Two parameter/lockable blocks (blocks #0 and #1)
can be protected against Program or Erase oper­ations. Unprotect ed blocks ca n be progra mmed or
erased.

To protect the two lockab le blocks set W rite Pro­tect to V

. When VPP is below V

IL

all blocks are

PPLK

protected. Any attempt to Program or Erase pro­tected blocks will abort, the data in the block will
not be changed and t he Status Register outputs
the error.

Table 6, Memory Blocks P rotection Truth Table,
defines the protection methods.

13/45

M28W320EBT, M28W320EBB

Table 4. Commands

Commands

No. of

Cycles

1st Cycle 2nd Cycle 3nd Cycle

Bus

Op.

Addr Data

Bus Write Operations

Bus

Addr Data

Op.

Bus

Op.

Addr Data

Read Memory Array Write X FFh
Read Status

Register
Read Electronic

Signature
Read CFI Query Write X 98h Read QA QD
Erase Write X 20h Write BA D0h

Program Write X

Double Word
Program

Quadruple Word
Program

Clear Status
Register

Program/Erase
Suspend

Program/Erase
Resume

Note: 1. X = Don’t C are, RA=Rea d Addre ss, RD =Read D ata, SRD =Stat us Regis ter Da ta, ID =Identif ier (Ma nufact ure and Devic e Code),

(3)

(4)

QA=Query Address, QD=Query Data, BA=Block Address, PA=Program Address, PD=Program Data, PRA=Protection Register Ad­dress, PRD=Protection Regis ter Data.

2. A0 =V

3. Program Addres ses 1 and 2 must be consecuti ve Addresses differing only for A0.

4. Program Addres ses 1,2,3 and 4 m ust be consecutive Addresses differing only for A0 and A1.

5. 55h is reserved.

6. To be c haracteriz ed.

outputs Manufacturer code, A0=VIHoutputs Device code. A ddress A7-A1 must be VIL.

IL

Write X 70h Read X SRD

Write X 90h Read

40h or

Write X 30h Write PA1 PD1 Write PA2 PD2

Write X

Write X 50h

Write X B0h

Write X D0h

56h

Read

Write PA PD

10h

(6)

Write PA1 PD1 Write PA2 PD2 Write PA3 PD3 Write

RA RD

(2)

SA

IDh

Table 5. Read Electronic Signature

Code Device E G W A0 A1-A7 A8-A20 DQ0-DQ7 DQ8-DQ15

Manufacture.
Code

M28W320EBT

Device Code

M28W320EBB

Note: RP = VIH.

14/45

V

V

V

IL

IL

V

V

IL

IL

V

V

IL

IL

V

IH

V

V

IH

V

V

IH

V

IL

V

IH

V

IH

Don’t Care 20h 00h

IL

Don’t Care BCh 88h

IL

Don’t Care BDh 88h

IL