ST M28W160BT, M28W160BB User Manual

1/39May 2000

M28W16 0BT

M28W160BB

16 Mbit (1Mb x16, Boot Block) Low Voltage Flash Memory

■ SUPPLY VOLTAGE

–V

= 2.7V to 3.6V: for Program, Erase and

Read

–V

DDQ

= 1.65V or 2.7V: Input/Output option

–V

= 12V: o ptional Supply Voltage for fast

Program

■ ACCESS TIME

– 2.7V to 3.6V: 90ns

– 2.7V to 3.6V: 100ns

■ PROGRAMMING TIME:

– 10µ s typical

– Double Word Programming Option

■ PROGRAM/ERASE CONTROLLER (P/E.C.)

■ COMMON FLASH INTERFACE

– 64 bit Security Code

■ MEMORY BLOCKS

– Parameter Blocks (Top or Bottom location)

– Main Blocks

■ BLOCK PROTECTION on TWO PARAMET ER

BLOCKS

–WP

for Block Protection

■ AUTOMATIC STAND-BY MODE

■ PROGRAM and ERASE SUSPEND

■ 100,000 PROGRAM/ERASE CYCL ES per

BLOCK

■ 20 YEARS of DATA RETENTION

– Defectivity below 1ppm/year

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Top Device Code, M28W160BT: 90h

– Bottom Device Code, M28W160BB: 91h

Figure 1. Logic Diagram

AI02628

A0-A19

DQ0-DQ15

M28W160BT

M28W160BB

DDQ

TSOP48 (N)

12 x 20mm

µBGA46 (GB)

8 x 6 solder balls

µBGA

查询M28W160B-GBT供应商

M28W160BT, M28W160BB

2/39

Figure 2. µBG A Co nn e ct i ons (Top view through package)

AI02629

87654321

A7V

A8A11A13

A0EDQ8DQ5DQ14A16

DQ0DQ9DQ3DQ6

DQ15

DDQ

DQ1DQ10V

DQ7V

DQ2

A5A17WA10A14

A1A3A6A9A12A15

RP A18

DQ4

DQ13

DQ12

DQ11

WP A19

Figure 3. TSOP Connection s

DQ3

DQ9

DQ2

DQ0

DQ6

DQ13

A17

A10 DQ14

DQ12

DQ10

DQ15

DQ4

DQ5

DQ7

AI02630

M28W160BT

M28W160BB

24 25

DQ8

A19

A18

DQ1

DQ11

A12

A13

A16

A11

DDQ

A15

A14

Table 1. Signal Names

A0-A19 Address Inputs

DQ0-DQ7 Data Input/Output, Command Inputs

DQ8-DQ15 Data Input/Output

Chip Enable

Output Enable

Write Enable

Reset

Write Protect

Supply Voltage

DDQ

Power Supply for

Input/Output Buffers

Optional Supply Voltage for

Fast Program & Erase

Ground

NC Not Connected Internally

3/39

M28W160BT, M28W160BB

DESCRIPTION

The M28W160B is a 16 Mbit non-volatile Flash

memory that can be erased electrically at the block

level and programmed i n-system on a Word-by-

Word basis. The device is of fered in the TS OP48

(10 x 20mm) and the µ BGA46, 0.75 mm ball pitch

packages. When shipped, all bits of the

M28W160B are in the ‘1’ state.

The array matrix organisation allows each block to

be erased and reprogrammed without affecting

other blocks. Each block can be programmed and

erased over 100,000 cycles. V

DDQ

allows to driv e

the I/O pin down t o 1.65V. An optional 12 V V

power supply is provided to speed up the program

phase at customer production line environment.

An internal Command Interface (C.I.) decodes the

instructions to access/modify the memory content.

The Program/Erase Controller (P /E.C.) automati-

cally executes the algorithms taking care of the

timings necessary for program and erase opera-

tions. Verification is performed too, unburdening

the microcontroller, while the Status Register

tracks the status of th e operation.

The following instructions are executed by the

M28W160B: Read Array , Read Electronic Signa-

ture, Read Status Register, Clear Status Register,

Program, Double Word Program, Block Erase,

Program/Erase Suspend, Program/Erase Re-

sume and CFI Query.

Organisation

The M28W160B is organised as 1 Mbit by 16 bits.

A0-A19 are the address l ines; DQ0 -DQ15 are the

Data Input/Output. Memory control is provided by

Chip Enable E

, Output Enable G and Write Enable

inputs. The Program and Erase operations are

managed automatically by the P/E.C. Block pro-

tection against Program or E rase provides addi-

tional data security.

The upper two (or lower two) parameter blocks

can be protected to secure the code content of the

memory . WP

controls protection and unprotection

operations.

Memory Blocks

The device features an asymmetrical blocked ar-

chitecture. The M28W160B has an array of 39

blocks: 8 Parameter Blocks of 4 KWord and 31

Main Blocks of 32 KWord. M28W 160BT has the

Parameter Blocks at the top of the memory ad-

dress space while the M28W160BB locates the

Parameter Blocks starting from the bottom. The

memory maps are shown in Tables 3 and 4.

The two upper parameter block c an be protected

from accidental programming or erasure using

. Each block can be erased separately. Erase

can be suspended in order to perform either read

or program in any other b lock and then resum ed.

Program can be s uspended to read data in any

other block and then resumed.

Table 2. Absolute Maximum Ratings

(1)

Note: 1. Except for the ratin g " Operating Temperature Range", stresses abo ve those listed in the T able "Abs ol ute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above those indi cated in the Operating sections of this s pecification is not impli ed. Exposure to Absolute M aximum Rating condi-

tions for extended per iods may aff ect device reliabilit y. Refer also to the STMicroel ectronics SURE Program an d other relevan t qual -

ity docum en ts .

2. Depends on range.

Symbol Parameter Value Unit

Ambient Operating Temperature

(2)

–40 to 85 °C

BIAS

Temperature Under Bias –40 to 125 °C

STG

Storage Temperature –55 to 155 °C

Input or Output Voltage

–0.6 to V

DDQ

+0.6

, V

DDQ

Supply Voltage –0.6 to 4.1 V

Program Voltage –0.6 to 13 V

M28W160BT, M28W160BB

4/39

Table 3. Top Boot Block Addresses,

M28W160BT

Size

(KWord)

Address Range

38 4 FF000-FFFFF

37 4 FE000-FEFFF

36 4 FD000-FDFFF

35 4 FC000-FCFFF

34 4 FB000-FBFFF

33 4 FA000-FAFFF

32 4 F9000-F9FFF

31 4 F8000-F8FFF

30 32 F0000-F7FFF

29 32 E8000-EFFFF

28 32 E0000-E7FFF

27 32 D8000-DFFFF

26 32 D0000-D7FFF

25 32 C8000-CFFFF

24 32 C0000-C7FFF

23 32 B8000-BFFFF

22 32 B0000-B7FFF

21 32 A8000-AFFFF

20 32 A0000-A7FFF

19 32 98000-9FFFF

18 32 90000-97FFF

17 32 88000-8FFFF

16 32 80000-87FFF

15 32 78000-7FFFF

14 32 70000-77FFF

13 32 68000-6FFFF

12 32 60000-67FFF

11 32 58000-5FFFF

10 32 50000-57FFF

9 32 48000-4FFFF

8 32 40000-47FFF

7 32 38000-3FFFF

6 32 30000-37FFF

5 32 28000-2FFFF

4 32 20000-27FFF

3 32 18000-1FFFF

2 32 10000-17FFF

1 32 08000-0FFFF

0 32 00000-07FFF

Table 4. Bottom Boot Block Addresses,

M28W160BB

Size

(KWord)

Address Range

38 32 F8000-FFFFF

37 32 F0000-F7FFF

36 32 E8000-EFFFF

35 32 E0000-E7FFF

34 32 D8000-DFFFF

33 32 D0000-D7FFF

32 32 C8000-CFFFF

31 32 C0000-C7FFF

30 32 B8000-BFFFF

29 32 B0000-B7FFF

28 32 A8000-AFFFF

27 32 A0000-A7FFF

26 32 98000-9FFFF

25 32 90000-97FFF

24 32 88000-8FFFF

23 32 80000-87FFF

22 32 78000-7FFFF

21 32 70000-77FFF

20 32 68000-6FFFF

19 32 60000-67FFF

18 32 58000-5FFFF

17 32 50000-57FFF

16 32 48000-4FFFF

15 32 40000-47FFF

14 32 38000-3FFFF

13 32 30000-37FFF

12 32 28000-2FFFF

11 32 20000-27FFF

10 32 18000-1FFFF

9 32 10000-17FFF

8 32 08000-0FFFF

7 4 07000-07FFF

6 4 06000-06FFF

5 4 05000-05FFF

4 4 04000-04FFF

3 4 03000-03FFF

2 4 02000-02FFF

1 4 01000-01FFF

0 4 00000-00FFF

5/39

M28W160BT, M28W160BB

SIGNAL DESCRIPTIONS

See Figure 1 and Table 1.

Address Inputs (A0-A19). The address signals

are inputs driven with CMOS vol tage level s. They

are latched during a write operation.

Data Input/Output (DQ0-DQ15). The data in-

puts, a word to be programmed or a comm and to

the C.I., are latched on the Chip Enable E

or Write

Enable W

rising edge, whichever occurs first. The

data output from the memory Array, the Electronic

Signature or Status Register is valid when Chip

Enable E

and Output Enable G are active. The

output is high impedance when the ch ip is dese-

lected, the outputs are disabled or RP

is tied to V

Commands are issued on DQ0-DQ7.

Chip Enable (E

). The Chip Enable input acti-

vates the memory control logic, input buffers, de-

coders and sense amplifiers. E

at V

deselects

the memory and red uces the power consumption

to the stand-by level. E

can also be used to control

writing to the command register and to the memo-

ry array, while W

remains at V

Output Enable (G

). The Output Enable controls

the data Input/Output buffers.

Write Enable (W

). This input controls writing to

the Command Register, Input Address and Dat a

latches.

Write Protect (WP

). Write Protect is an input to

protect or unprotect the two lockable parameter

blocks. When WP

is at V

, the locka ble bl ocks are

protected. Program or erase operations are not

achievable. When WP

is at V

, the lockable

blocks are unprotected and they can be pro-

grammed or erased (refer to Table 9).

Reset Input (RP

). The RP input provides hard-

ware reset of the memory. When RP

is at V

, the

memory is in reset mode : the outputs are put to

High-Z and the current consumption is minimised.

When RP

is at V

, the device is in norm al opera-

tion. Exiting reset mode the device enters read ar-

ray mode.

Supply Voltage (2.7V to 3.6V). V

pro-

vides the power supply to the internal core of the

memory device. It is the main power supply for all

operations (Read, Program and Erase). It ranges

from 2.7V to 3.6V.

DDQ

Supply Voltage (1.65V to V

). V

DDQ

provides the power supply to the I/O pins and en-

ables all Outputs to be powered independently

from V

. V

DDQ

can be tied to V

or it can use a

separate supply. It can be powered either from

1.65V to 2.2V or from 2.7V to 3.6V.

Program Supply Voltage (12V). V

both a control input and a power supply pin. T he

two functions are selected by the voltage range

applied to the pin.

If V

is kept in a low voltage range (0V to 3.6V)

is seen as a control input. In this case a volt-

age lower than V

PPLK

gives an absolute protection

against program or erase, whi le V

> V

PP1

en-

ables these functions. V

value is only sampled

at the beginning of a program or erase; a cha nge

in its value after the operation has been started

does not have any effect and program or erase are

carried on regu larl y.

If V

is used in the range 11.4V to 12.6V acts as

a power supply pin. In this condition V

value

must be stable until P/E algorithm is completed

(see Table 22 and 23).

Ground. V

is the reference for all the volt-

age measurements.

M28W160BT, M28W160BB

6/39

DEVICE OPERATIONS

Four control pins rule the hardware access t o the

Flash memory: E

, G, W, RP. The following opera-

tions can be performed using the appropriate bus

cycles: Read, Write the Command of an Instruc-

tion, Output Disable, Stand-by, Reset (see Table

5).

Read. Read operations are used to output the

contents of the Memory Array, the Electronic Sig-

nature, the Status Register and the CFI. Both Chip

Enable (E

) and Output Enabl e (G) must be at V

in order to perform the read operation. The Chip

Enable input should be used to enable the device.

Output Enable shoul d be used to gate data onto

the output indepe ndently of the device s election.

The data read depend on the previous command

written to the memory (see instructions RD, RSIG,

RSR, RCFI). Read Array is the default state of the

device when exiting Reset or after power-up.

Write. Write operations are used to give Com-

mands to the memory or to latch Input Data to be

programmed. A write operation is initiated when

Chip Enable E

and Write Enable W are at V

with

Output Enable G

at V

. Comm ands, Inp ut Data

and Addresses are latched on the rising edge of W

or E, whichever occur first.

Output Disa bl e . The data outputs are high im-

pedance when the Output Enable G

is at V

Stand-by. Stand-by disables most of the internal

circuitry allowing a substantial reduction of the cur-

rent consumption. The memory is in stand-by

when Chip Enable E

is at V

and the device is in

read mode. The power consumption is reduced to

the stand-by level and the o utputs are set to high

impedance, independently from the Output Enable

or Write Enable W inputs. If E switches to V

during program or erase operation, the device en-

ters in stand-by when finished.

Reset. During Reset mode all internal circuits are

switched off, the memory is deselected and the

outputs are put in high impedance. The memory is

in Reset mode when RP

is at V

. The power con-

sumption is reduced to the Stand-by level, inde-

pendently from the Chip Enabl e E

, Output En able

or Write Enable W inputs. If RP is pulled to V

during a Program or Erase, this operation is abort-

ed and the memory content is no longer valid as it

has been compromised by the aborted operation.

Table 5. User Bus Operations

(1)

Note: 1. X = V

or V

, V

PPH

= 12V ± 5%.

Table 6. Read Electronic Signature (RSIG Instruction)

Note: 1. RP = V

Operation E G W RP WP

DQ0-DQ15

Read

X Don’t Care Data Output

Write

or V

PPH

Data Input

Output Disable

X Don’t Care Hi-Z

Stand-by

X Don’t Care Hi-Z

Reset X X X

X Don’t Care Hi-Z

Code Device E

G W A0 A1-A7 A8-A19 DQ0-DQ7 DQ8-DQ15

Manufact. Code

Don’t Care 20h 00h

Device Code

M28W160BT

Don’t Care 90h 00h

M28W160BB

Don’t Care 91h 00h

7/39

M28W160BT, M28W160BB

INSTRUCTIONS AND COMMANDS

Eleven instructions are available (see Tables 7

and 8) to perform Read Memory Array, Read Sta-

tus Register, Read Electronic Signature, CFI Que-

ry, Erase, Program, Dou ble Word Program, Clear

Status Register, Program/Erase Suspend and

Program/Erase Resume. Status Register output

may be read at any time, during programming or

erase, to monitor the progress of the operation.

An internal Command Interface (C.I.) decodes the

instructions while an internal Program/Erase Con-

troller (P/E.C.) handles all timing and verifies the

correct execution of the Program and Erase in-

structions. P/E.C. provides a Status Register

whose bits indicate operation and exit status of the

internal algorithms.

The Command Interface is reset to Read Array

when power is first applied, when exiting from Re-

set or whenever V

is lower than V

LKO

. Com-

mand sequence must be followed exactly. Any

invalid combination of commands will reset the de-

vice to Read Array.

Read (RD)

The Read instruction consists of one write cycle

(refer to Device Operations section) giving the

command FFh. Next read operations will read the

addressed location and output the data. When a

device reset occurs, the memo ry is in Read Array

as default.

Read Status Register (RSR)

The Status Register indicates when a program or

erase operation is complete and the success or

failure of operation itself. Issue a Read Status

ister content.

The Read Status Register instruction may be is-

sued at any time, also when a Program/Erase op-

eration is ongoing. The following Read operations

output the content of the Status Register. The Sta-

tus Register is latched on the falling edge of E

signals, and can be read until E or G returns to

. Eithe r E or G must be t oggled to updat e the

latched data. Additionally, any read attempt during

program or erase operation will autom atically ou t-

put the content of the Status Register.

Read Electronic Signature (RSIG)

The Read Electronic Signature instruction con-

sists of one write cycle (refer to Device Operations

section) giving the command 90h. A subsequent

read will output the Manufacturer or the Device

Code (Electronic Signature) depending on the lev-

els of A0 (see Tables 6). The Electronic Signature

can be read from the memory allowing program-

ming equipment or applications to automatically

match their interface to the characteristics of

M28W160B. The Manufacturer Code is output

when the address lines A 0 is at V

, the Device

Code is output when A0 is at V

. Address A1-A7

must be kept to V

, other addresses are ignored.

The codes are output on DQ0-DQ7 with DQ8-

DQ15 at 00h.

CFI Query (RCFI)

The Common Flash Interface Query mode is en-

tered by writing 98h. Next read operations will read

the CFI data. The CFI data structure contains also

a security area; in this section, a 64 bit unique se-

curity number is written, starting at address 80h.

This area can be accessed only in read mode by

the final use and there are no ways of chang ing

the code after it has been written by ST. Write a

read instruction to return to Read mode (refer to

the Common Flash Interface section).

Table 7. Commands

Hex Code Command

00h, 01h, 60h,

2Fh, C0h

Invalid/Reserved

10h Alternative Program Set-up

20h Erase Set-up

30h Double Word Program Set-up

40h Program Set-up

50h Clear Status Register

70h Read Status Register

90h or 98h

Read Electronic Signature, or

CFI Query

B0h Program/Erase Suspend

D0h

Program/Erase Resume, or

Erase Confirm

FFh Read Array

M28W160BT, M28W160BB

8/39

Status Register bit b7 returns ’0’ while the erasure

is in progress and ’1’ when it has completed. After

completion the Status Register bit b5 returns ’1’ if

there has been a n Erase Failure. S tatus register

bit b1 returns ’1’ if the user is attempt ing to pro-

gram a protected blo ck. S tat us Regi s ter bit b3 re-

turns a ’1’ if V

is below V

PPLK

Erase aborts if RP

turns to V

. As da ta integ rity

cannot be guaranteed when the erase operation is

aborted, the erase must be repeated. A Clear Sta-

tus Register instruction must be issued to reset b1,

b3, b4 and b5 of th e Status Register. During the

execution of the erase by t he P /E.C., the memory

accepts only the RSR (Read Status Register) and

PES (Program/Erase Suspend) instructions.

Table 8. Instructions

Note: 1. X = Don’t Care.

2. The first cyc le of the RD, RSR, RSIG o r RCFI in st ruction is followed by read oper ations to read me m ory array, Status Register or

Electronic Signature codes. Any number of Read cycle can occur after one command cycle.

3. Signature address bit A0=V

will output Manufacturer code. Address bit A0=V

will output Device code. Address A7-A1 must be

kept to V

. Other address bits are i gnored.

4. Address 1 and Address 2 must be consecuti ve Addresses differing only for address bit A0.

Mne-

monic

Instruction Cycles

1st Cycle 2nd Cy cle 3nd Cy cle

Operat.

Addr.

(1)

Data Operat. Addr. Data Operat. Addr. Data

Read Memory

Array

1+ Write X FFh

Read

(2)

Read

Address

Data

RSR

Read Status

1+ Write X 70h

Read

(2)

Status

RSIG

Read

Electronic

Signature

1+ Write X

90h or

98h

Read

(2)

Signature

Address

(3)

Signatur e

RCFI CFI Qu ery 1+ Wri te 55h

98h or

90h

Read

(2)

CFI

Address

Query

EE Erase 2 Write X 20h Write

Bloc k

Address

D0h

PG Progra m 2 Write X

40h or

10h

Write Address

Data

Input

DPG

(4)

Double Word

Program

3 Write X 30h Write Address 1

Data

Input

Write Address 2

Data

Input

CLRS

Clear Status

1Write X 50h

PES

Program/

Erase

Suspend

1Write X B0h

PER

Program/

Erase

Resume

1Write X D0h

Erase (EE)

Block erasure sets all the bits within the selected

block to ’1’. One block at a time can be erased. It

is not necessary to program the block with 00h as

the P/E.C. will do it automatically before erasing.

This instruction uses two write cycles. The first

command written is the Erase Set up command

20h. The second command is the Erase Confirm

command D0h. An address within the block to be

erased is given and latched in to the mem ory dur-

ing the input of t he second com mand. If the s ec-

ond command given is not an erase conf irm, the

status register bits b4 and b5 are set and the in-

struction aborts.

Read operations output the status register after

erasure has started.

9/39

M28W160BT, M28W160BB

Table 9. Memory Blocks Protection Truth Table

Note: 1. Notes:1. X ’ = Don’t Care

2. RP

is the Reset/Power Down.

3. V

is the program or erase supply volta ge.

4. V

are logic high and low levels.

5. V

must be also gr eater than the Program V ol t age Lock-Out V

PPLK

Table 10. Status Register Bits

Note: Logic level ’1’ is High, ’0’ is Low.

(1,3)

(2,4)

(1,4)

Lockable Blocks Other Blocks

X Protected Protected

or V

PPH

(5)

Protected Unprotected

or V

PPH

(5)

Unprotected Unprotected

Mnemonic Bit Name

Logic

Level

Definition Note

P/ECS 7 P/E.C. Status

’1’ Ready Indicates the P/E.C. status, check during

Program or Erase, and on completion before

checking bits b4 or b5 for Program or Erase

Success

’0’ Busy

ESS 6

Erase

Suspend

Status

’1’ Suspended

On an Erase Suspend instruction P/ECS and

ESS bits are set to ’1’. ESS bit remains ’1’ until an

Erase Resume instruction is given.

’0’

In progress or

Completed

ES 5 Erase Status

’1’ Erase Error ES bit is set to ’1’ if P/E.C. has applied the

maximum number of erase pulses to the block

without achieving an erase verify.

’0’ Erase Success

PS 4

Program

Status

’1’ Program Error

PS bit set to ’1’ if the P/E.C. has failed to program

a word.

’0’ Program Success

VPPS 3

Status

’1’

Invalid, Abort VPPS bit is set if the V

voltage is below V

PPLK

when a Program or Erase instruction is executed.

is sampled only at the beginning of the

Erase/Program operation.

’0’

PSS 2

Program

Suspend

Status

’1’ Suspended

On a Program Suspend instruction P/ECS and

PSS bits are set to ’1’. PSS remains ’1’ until a

Program Resume Instruction is given

’0’

In Progress or

Completed

BPS 1

Block

Protection

Status

’1’

Program/Erase on

protected Block,

Abort

BPS bit is set to ’1’ if a Program or Erase

operation has been attempted on a protected

block

’0’

No operation to

protected blocks

0 Reserved

M28W160BT, M28W160BB

10/39

Program (PG)

The memory array can be programmed word-by-

word. This instruction uses two write cycles. The

first command written is the Program Set-up com-

mand 40h (or 10h). A second write operation latch-

es the Address and the Data to be written and

starts the P/E.C.

Read operations output the Status Register con-

tent after the programming has started. The Status

is in progress and ’1’ when it has completed. After

completion the Status register bit b4 returns ’1’ if

there has been a Program Failure. Status register

bit b1 returns ’1’ if the user is attempt ing to pro-

gram a protected blo ck. S tatu s Regi s ter bit b3 re-

turns a ’1’ if V

is below V

PPLK

. Programming

aborts if RP

goes to V

. As data integrity cannot

be guaranteed when the program operation is

aborted, the memory location must be erased and

reprogrammed. A Clear Status Register instruc-

tion must be issued to reset b4, b3 and b1 of the

Status Register.

During the execution of the program by the P/E.C.,

the memory accepts only the RSR (Read Status

structions.

Doubl e Word Prog ram (DPG)

This feature is offered to improve the programming

throughput, writing a page of two adjacent words

in parallel.The two words m ust differ only for the

address A0. Programm ing should not b e att emp t-

ed when V

is not at V

PPH

. The operation can

also be executed if V

is below V

PPH

but result

could be uncertain. This instruction uses three

write cycles. The first c ommand written is the Dou-

ble Word Program Set-Up command 30h. A sec-

ond write operation latc hes the Address and the

Data of the first w ord to be wri tten, the third write

operation latches the Address and the Data of the

second word to be written and starts the P/E.C.

Read operations output the Status Register con-

tent after the programming has started. The Status

is in progress and ’1’ when it has completed. After

completion the Status register bit b4 returns ’1’ if

there has been a Program Failure. Status register

bit b1 returns ’1’ if the user is attempt ing to pro-

gram a protected blo ck. S tatu s Regi s ter bit b3 re-

turns a ’1’ if V

is below V

PPLK

. Programming

aborts if RP

goes to V

. As data integrity cannot

be guaranteed when the program operation is

aborted, the memory location must be erased and

reprogrammed. A Clear Status Register instruc-

tion must be issued to reset b4, b3 and b1 of the

Status Register.

During the execution of the program by the P/E.C.,

the memory accepts only the RSR (Read Status

structions.

Clear Status Register (CLRS)

The Clear Status Register uses a single write op-

eration which clears bits b1, b3, b4 and b5 to ‘0’.

Its use is necessary before any new operation

when an error has been detected.

The Clear Status Register is executed w riting the

command 50h.

Program/Erase Suspend (PES)

Program/Erase suspend is accepted only during

the Program Erase instruction execu tion. When a

Program/Erase Suspend command is written to

the C.I., the P/E.C. freezes the Program/Erase op-

eration. Program/Erase Res ume (P ER) cont inues

the Program/Erase operation. Program/Erase

Suspend consists of writing the command B0h

without any specific address.

The Status Register bit b2 is set to ‘1’ (within 5µs)

when the program has been sus pended . b2 is set

to ‘0’ in case the program is completed or in

progress. The Status Register bit b6 is set to ‘1’

(within 30µs) when the erase has been sus pend-

ed. b6 is s et t o ‘0’ in cas e th e e rase is com plet ed

or in progress. The valid commands while erase is

suspended are Program/Erase Resume, Pro-

gram, Read Array, Read Status Register, Read

Identifier, CFI Query. While program is suspended

the same command set is valid except for program

instruction. During program/erase suspend mode,

the chip can be placed in a pseudo-stand-by mode

by taking E

to V

. This reduces active current con-

sumption. Program/Erase is aborted if RP

turns to

Program/Erase Resume (PER)

If a Program/Erase Suspend instruction was previ-

ously executed, the program/erase operation may

be resumed by issuing the command D0h. The

status register bit b2/b6 is cleared when program/

erase resumes. Read operations output the status

The suggested flow charts for programs that use

the programming, erasure and program/erase

suspend/resume features of the memories are

shown from Figures 10, 11, 12, 13 and 14.

11/39

M28W160BT, M28W160BB

Table 11. Program, Erase Times and Program /Eras e Endur ance Cycles

= 0 to 70°C or –40 to 85°C; V

= 2.7V to 3.6V)

Note: T

= 25 °C.

Parameter Test Conditions

M28W160B

Unit

Min

Typ

(1)

Max

Word Program

= V

10 200 µs

Double Word Program

= 12V ±5%

10 200 µs

Main Block Program

= 12V ±5%

0.16 5 sec

= V

0.32 5 sec

Parameter Block Program

= 12V ±5%

0.02 4 sec

= V

0.04 4 sec

Main Block Erase

= 12V ±5%

110 sec

= V

110 sec

Parameter Block Erase

= 12V ±5%

0.8 10 sec

= V

0.8 10 sec

Program/Erase Cycles (per Block) 100,000 cycles

M28W160BT, M28W160BB

12/39

BLOCK PROTECTION

Two parameter blocks (#0 and #1) can be protect-

ed against Program or Erase to ensure extra data

security. Unprotected blocks can be programmed

or erased.

tied to V

protects the two lockable b locks.

below V

PPLK

protects all the blo cks. A ny pro-

gram or erase operation on protected blocks is

aborted. The Status Register tracks when the

event occurs.

Table 9 defines the protection methods.

POWER CONSUMPTION

The M28W160B puts itself in one o f four different

modes depending on the statu s of the c ontrol sig-

nals: Active Power, Automatic Stand-by, Stand-by

and Reset define decreasing levels of current con-

sumption. These allow the memory power to be

minimised, in turn decreasing the overall system

power consumption. As different recovery time are

linked to the different modes, please refer to the

AC timing table to design your system.

Active Power

When E

is at V

and RP is at V

, the device is in

active mode. Refer to DC Characteristics to get

the values of the current supply consumption.

Automatic Stand-by

Automatic Stand-by provides a low power con-

sumption state during read mode. Following a

read operation, after a del ay c lose to the memory

access time, the device enters Automatic Stand-

by: the Supply Current is reduced to I

CC1

values.

The device keeps the last output data s table, till a

new location is accessed.

Stand-by or Reset

Refer to the Device Operations section.

Power Up

The Supply voltage V

and the Program S upply

voltage V

can be applied in any order. The

memory Command Interface is reset on power up

to Read Memory Array, but a negative transition of

Chip Enable E

or a change of the addresses is re-

quired to ensure valid data outputs. Care must be

taken to avoid w rites to t he memory when V

above V

LKO

. Writes can be inhibited by drivin g ei-

ther E

or W to V

. The memory is disabled if RP

is at V

Supply Rails

Normal precautions must be taken for supply volt-

age decoupling, each device in a system should

have the V

and V

rails decoupled with a

0.1µF capacitor close to the V

and V

pins.

The PCB trace widths should be sufficient to carry

the required V

program and erase currents.

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