ST M28LV64 User Manual

M28LV64

M28LV64

64K (8K x 8) LOW VOLTAGE PARALLEL EEPROM with SOFTWARE DATA PROTECTION

NOT FOR NEW DESIGN

FAST ACCESS TIME: 200ns

SINGLE LOW VOLTAGE OPERATION

LOW POWER CONSUMPTION

FAST WRITE CYCLE:

±	64 Bytes Page Write Operation	28
±	Byte or Page Write Cycle: 3ms Max

ENHANCED END OF WRITE DETECTION:

±Ready/Busy Open Drain Output (only on the M28LV64)

±Data Polling

±Toggle Bit

PAGE LOAD TIMER STATUS BIT

HIGH RELIABILITY SINGLE POLYSILICON, CMOS TECHNOLOGY:

±Endurance >100,000 Erase/Write Cycles

±Data Retention >40 Years

JEDEC APPROVED BYTEWIDE PIN OUT SOFTWARE DATA PROTECTION

The M28LV64 is replaced by the M28C64-xxW

DESCRIPTION

The M28LV64 is an 8K x 8 low power Parallel EEPROM fabricated with SGS-THOMSON proprietary single polysilicon CMOS technology. The device offers fast access time with low power dissipation and requires a 2.7V to 3.6V power supply.

Table 1. Signal Names

A0 - A12	Address Input
DQ0 - DQ7	Data Input / Output
W	Write Enable
E	Chip Enable
G	Output Enable
RB	Ready / Busy
VCC	Supply Voltage
VSS	Ground

1
PDIP28 (P)	PLCC32 (K)

28
1
SO28 (MS)	TSOP28 (N)
300 mils	8 x13.4mm

Figure 1. Logic Diagram

	VCC
13	8
A0-A12	DQ0-DQ7

W M28LV64

E

RB *

G

VSS

AI01538B

Note: * RB function is only available on the M28LV64.

May 1997

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This is information on a product still in production but not recommended for new designs.

M28LV64

Figure 2A. DIP Pin Connections

RB	1	28	VCC
A12	2	27	W
A7	3	26	NC
A6	4	25	A8
A5	5	24	A9
A4	6	23	A11
A3	7	M28LV64 22	G
A2	8	21	A10
A1	9	20	E
A0	10	19	DQ7
DQ0	11	18	DQ6
DQ1	12	17	DQ5
DQ2	13	16	DQ4
VSS	14	15	DQ3
		AI01539B

Warning: NC = Not Connected.

Figure 2C. SO Pin Connections

RB	1		28	VCC
A12	2		27	W
A7	3		26	NC
A6	4		25	A8
A5	5		24	A9
A4	6		23	A11
A3	7	M28LV64	22	G
A2	8		21	A10
A1	9		20	E
A0	10		19	DQ7
DQ0	11		18	DQ6
DQ1	12		17	DQ5
DQ2	13		16	DQ4
VSS	14		15	DQ3
		AI01541B

Warning: NC = Not Connected.

Figure 2B. LCC Pin Connections

	A7	A12	RB	DU	CC	W	NC
					V
A6				1	32		A8
A5							A9
A4							A11
A3							NC
A2	9		M28LV64				25 G
A1							A10
A0							E
NC							DQ7
DQ0				17			DQ6
	DQ1	DQ2			DQ3	DQ4	DQ5
			V	DU
			SS
							AI01540B

Warning: NC = Not Connected, DU = Don't Use.

Figure 2D. TSOP Pin Connections

G	22	21	A10
A11			E
A9			DQ7
A8			DQ6
NC			DQ5
W			DQ4
VCC	28	15	DQ3
		M28LV64	VSS
RB	1	14
A12			DQ2
A7			DQ1
A6			DQ0
A5			A0
A4			A1
A3	7	8	A2
		AI01542B

Warning: NC = Not Connected.

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			M28LV64
Table 2. Absolute Maximum Ratings (1)
Symbol	Parameter	Value	Unit
TA	Ambient Operating Temperature	± 40 to 85	°C
TSTG	Storage Temperature Range	± 65 to 150	°C
VCC	Supply Voltage	± 0.3 to 6.5	V
VIO	Input/Output Voltage	± 0.3 to VCC +0.6	V
VI	Input Voltage	± 0.3 to 6.5	V
VESD	Electrostatic Discharge Voltage (Human Body model) (2)	4000	V

Notes: 1. Except for the rating ºOperating Temperature Rangeº, stresses above those listed in the Table ºAbsolute Maximum Ratingsº may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents.

2. 100pF through 1500Ω; MIL-STD-883C, 3015.7

Figure 3. Block Diagram

		VPP GEN	RESET
	A6-A12	ADDRESS
		LATCH
	(Page Address)
			DECODE
			X
	A0-A5	ADDRESS
		LATCH
		Y	DECODE

RB	E	G	W
	CONTROL LOGIC

64K ARRAY

SENSE AND DATA LATCH

I/O BUFFERS

PAGE LOAD TIMER STATUS TOGGLE BIT DATA POLLING

DQ0-DQ7

AI01355

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M28LV64

Table 3. Operating Modes (1)

Mode	E	G	W	DQ0 - DQ7
Standby	1	X	X	Hi-Z
Output Disable	X	1	X	Hi-Z
Write Disable	X	X	1	Hi-Z
Read	0	0	1	Data Out
Write	0	1	0	Data In
Note: 1. 0 = VIL; 1 = VIH; X = VIL or VIH.

DESCRIPTION (cont'd)

The M28LV64 outputs the Ready/Busy write status, the M28LV64-aaaX(aaa= access time) has no Ready/Busy status and the relevant RB pin is Not Connected (NC). The circuit has been designed to offer a flexible microcontroller interface featuring both hardware and software handshaking with Ready/Busy, Data Polling and Toggle Bit. The M28LV64 supports 64 byte page write operation. A Software Data Protection (SDP) is also possible using the standard JEDEC algorithm.

PIN DESCRIPTION

Addresses (A0-A12). The address inputs select an 8-bit memory location during a read or write operation.

Chip Enable (E). The chip enable input must be low to enable all read/write operations. When Chip Enable is high, power consumption is reduced.

Output Enable (G). The Output Enable input controls the data output buffers and is used to initiate read operations.

Data In/ Out (DQ0 - DQ7). Data is written to or read from the M28LV64 through the I/O pins.

Write Enable (W). The Write Enable input controls the writing of data to the M28LV64.

Ready/Busy (RB). Ready/Busy is an open drain output that can be used to detect the end of the internal write cycle (this function appliesonly to the M28LV64).

OPERATION

In order to prevent data corruption and inadvertent writeoperationsan internal VCC comparator inhibits Write operation if VCC is below VWI (see Table 6). Access to thememory in writemode is allowed after a power-up as specified in Table 6.

Read

The M28LV64 is accessed like a static RAM. When E and G are low with W high, the data addressed is presented on the I/O pins. The I/O pins are high impedance when either G or E is high.

Write

Write operations are initiated when both W and E are low and G is high.The M28LV64 supports both E and W controlled write cycles. The Address is latched by the falling edge of E or W which ever occurs last and the Data on the rising edge of E or W which ever occurs first. Once initiated the write operation is internally timed until completion.

Page Write

Page write allows up to 64 bytes to be consecutively latched into the memory prior to initiating a programming cycle. All bytes must be located in a single page address, that is A6-A12 must be the same for all bytes. The page write can be initiated during any byte write operation.

Following the first byte write instruction the host may send another address and data with a minimum data transfer rate of tWHWH (see Figure 13). If a transition of E or W is not detected within tWHWH the internal programming cycle will start.

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Microcontroller Control Interface

The M28LV64 provides two write operation status bits and one status pin that can be used to minimize the system write cycle. These signals are available on the I/O port bits DQ7 or DQ6 of the memory during programming cycle only, or as the RB signal on a separate pin.

Figure 4. Status Bit Assignment

DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

DP TB PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z

DP = Data Polling

TB = Toggle Bit

PLTS = Page Load Timer Status

Data Polling bit (DQ7). During the internal write cycle, any attempt to read the last byte written will produce on DQ7 the complementary value of the previously latched bit. Once the write cycle is finished the true logic value appears on DQ7 in the read cycle.

Toggle bit (DQ6). The M28LV64 offers another way for determining when the internal write cycle is completed.During the internal Erase/Writecycle, DQ6 will toggle from º0º to º1º and º1º to º0º (the first read value is º0º) on subsequent attempts to read the memory. When the internal cycle is completed the toggling will stop and the device will be accessible for a new Read or Write operation.

Page Load Timer Status bit (DQ5). In the Page Write mode data may be latched by E or W up to 100μs after the previous byte. Up to 64 bytes may be input. The Data output (DQ5) indicates the status of the internal Page Load Timer. DQ5 may

M28LV64

be read by asserting Output Enable Low (tPLTS). DQ5 Low indicates the timer is running, High indicates time-out after which the write cycle will start and no new data may be input.

Re ady/ Busy p in (av ail ab le only on the M28LV64). The RB pin provides a signal at its open drain output which is low during the erase/write cycle, but which is released at the completionof the programming cycle.

Software Data Protection

The M28LV64 offers a software controlled write protection facility that allows the user to inhibit all write modes to the device including the Chip Erase instruction. This can be useful in protecting the memory from inadvertent write cycles that may occur due to uncontrolled bus conditions.

The M28LV64is shipped as standard in the ºunprotectedº state meaning that the memory contents can be changed as required by the user. After the Software Data Protection enable algorithm is issued, the device enters the ºProtect Modeº of operation where no further write commands have any effect on the memory contents. The device remains in this mode until a valid Software Data Protection (SDP) disable sequence is received whereby the device reverts to its ºunprotectedº state. The Software Data Protection is fully nonvolatile and is not changed by power on/off sequences.

To enable the Software Data Protection (SDP) the device requires the user to write (with a Page Write) three specific data bytes to three specific memory locations as per Figure 5. Similarly to disable the Software Data Protection the user has to write specific data bytes into six different locations as per Figure 6 (with a Page Write). This complex series ensures that the user will never enable or disable the Software Data Protection accidentally.

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M28LV64

Figure 5. Software Data Protection Enable Algorithm and Memory Write

		WRITE AAh in		WRITE AAh in
		Address 1555h		Address 1555h
	Page	WRITE 55h in	Page	WRITE 55h in
	Write		Write
		Address 0AAAh		Address 0AAAh
	Instruction		Instruction
	(Note 1)		(Note 1)
		WRITE A0h in		WRITE A0h in
		Address 1555h		Address 1555h
				WRITE
		SDP is set		is enabled
				Write Page
				(1 up to 64 bytes)

SDP ENABLE ALGORITHM	WRITE IN MEMORY
	WHEN SDP IS SET
	AI01356B

Note: 1. MSB Address bits (A6 to A12) differ during these specific Page Write operations.

Figure 6. Software Data Protection Disable Algorithm

WRITE AAh in

Address 1555h

WRITE 55h in

Address 0AAAh

WRITE 80h in

Page Address 1555h

Write

Instruction

WRITE AAh in

Address 1555h

WRITE 55h in

Address 0AAAh

WRITE 20h in

Address 1555h

Unprotected State

AI01357

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