ST M28C64 User Manual

1/24June 2000

M28C64

64 Kbit (8K x 8) Parallel EEPROM

With Software Data Protection

■ Fast Access Time:

–90nsatV

=5 V forM28C64 andM28C64-A

– 120 ns at V

=3 V for M28C64-xxW

■ Single Supply Voltage:

– 4.5 V to 5.5V for M28C64 and M28C64-A

– 2.7 V to 3.6V for M28C64-xxW

■ Low Power Consumption

■ Fast BYTE and PAGE WRITE (up to 64 Bytes)

– 1 ms at V

=4.5 V for M28C64-A

– 3 ms at V

=4.5 V for M28C64

– 5 ms at V

=2.7 V for M28C64-xxW

■ Enhanced Write Detection and Monitoring:

– Ready/Busy Open DrainOutput

– Data Polling

– Toggle Bit

– Page Load Timer Status

■ JEDEC Approved Bytewide Pin-Out

■ Software Data Protection

■ 100000 Erase/Write Cycles (minimum)

■ Data Retention (minimum):

– 40 Years for M28C64 and M28C64-xxW

– 10 Years for M28C64-A

Figure 1. Logic Diagram

AI01350C

A0-A12

DQ0-DQ7

M28C64

Table 1. Signal Names

A0-A12 Address Input

DQ0-DQ7 Data Input / Output

W Write Enable

E Chip Enable

G Output Enable

RB Ready / Busy

Supply Voltage

Ground

PDIP28 (BS)

SO28 (MS)

300 mil width

PLCC32 (KA)

TSOP28 (NS)

8 x 13.4 mm

M28C64

2/24

Figure 2A. DIP Connections

Note: 1. NC = Not Connected

Figure 2B. PLLC Connections

Note: 1. NC = Not Connected

2. DU = Do Not Use

DQ0

A10

DQ7

A11

DQ5DQ1

DQ2

DQ3V

DQ4

DQ6

A12

RB V

AI01351C

M28C64

AI01352D

A10

DQ4

DQ0

DQ1

DQ2

DQ3

A11

DQ6

DQ7

M28C64

A12

DQ5

Figure 2C. SO Connections

Note: 1. NC =Not Connected

Figure 2D. TSOP Connections

Note: 1. NC =Not Connected

DQ0

DQ1

A10

DQ7

DQ5

DQ4

AI01353C

M28C64

DQ2

DQ6

23 A11

DQ3

A12

DQ0

A11

DQ7

DQ5

DQ1

DQ2

DQ3

DQ4

DQ6

A12

AI01354C

M28C64

A10

DESCRIPTION

The M28C64 devices consist of 8192x8 bits of low

power, parallel EEPROM, fabricated with

STMicroelectronics’ proprietary single polysilicon

CMOS technology. The devices offer fast access

time, with low power dissipation, and require a

single voltage supply (5V or 3V, depending on the

option chosen).

The device has been designed to offer a flexible

microcontroller interface, featuring both hardware

and software handshaking, with Ready/Busy,

Data Polling and Toggle Bit. The device supports

a 64 byte Page Write operation. Software Data

Protection (SDP) is also supported, using the

standard JEDEC algorithm.

3/24

M28C64

Figure 3. Block Diagram

AI01355

ADDRESS

LATCH

A6-A12

(Page Address)

X DECODE

CONTROL LOGIC

64K ARRAY

ADDRESS

LATCH

A0-A5

Y DECODE

GEN RESET

SENSE AND DATA LATCH

I/O BUFFERS

RB E G W

PAGE

LOAD

TIMER STATUS

TOGGLE BIT

DATA POLLING

DQ0-DQ7

Table 2. Absolute Maximum Ratings

Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may

cause permanent damage to the device. These arestress ratings only, and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.

2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)

Symbol Parameter Value Unit

Ambient Operating Temperature -40 to 125 °C

STG

Storage Temperature -65 to 150 °C

Supply Voltage -0.3 to V

+1 V

Input or Output Voltage

-0.6 to V

+0.6

Input Voltage -0.3 to 6.5 V

ESD Electrostatic Discharge Voltage (Human Body model)

4000 V

M28C64

4/24

Table 3. Operating Modes

Note: 1. 0=V

;1=V

;X=V

or V

; V=12V ± 5%.

Mode E G W DQ0-DQ7

Stand-by 1 X X Hi-Z

Output Disable X 1 X Hi-Z

Write Disable X X 1 Hi-Z

Read 0 0 1 Data Out

Write 0 1 0 Data In

Chip Erase 0 V 0 Hi-Z

SIGNAL DESCRIPTION

The external connections to the device are

summarized in Table 1,and their use in Table 3.

Addresses (A0-A12). The address inputs are

used to select one byte from the memory array

during a read or write operation.

Data In/Out (DQ0-DQ7). The contents of the data

byte arewritten to,or read from,the memory array

through the Data I/O pins.

Chip Enable (E). The chip enable input must be

held low to enable read and write operations.

When Chip Enable is high, power consumption is

reduced.

Output Enable (G). The Output Enable input

controls the data output buffers, and is used to

initiate read operations.

Write Enable(W). TheWrite Enable input controls

whether the addressed locationis to be read, from

or written to.

Ready/Busy (RB). Ready/Busy is an open drain

output that can be used to detect the end of the

internal write cycle.

DEVICE OPERATION

In order to prevent datacorruption and inadvertent

write operations, an internal V

comparator

inhibits the Write operations if the V

voltage is

lowerthan V

(see Table 4A and Table4B). Once

the voltage applied on the V

pin goes over the

threshold (V

), write access to the

memory is allowed after a time-out t

PUW

,as

specified in Table 4A and Table 4B.

Further protection against data corruption is

offered by the E and W low pass filters: any glitch,

on the E and W inputs, witha pulsewidth less than

10 ns (typical) is internally filtered out to prevent

inadvertent write operations to the memory.

Table 4A. Power-Up Timing

for M28C64 (5V range)

= 0 to70 °C or –40 to 85 °C or –40 to 125 °C; V

= 4.5 to 5.5 V)

Note: 1. Sampled only, not 100% tested.

Table 4B. Power-Up Timing

for M28C64-xxW (3V range)

= 0 to70 °C or –40 to 85 °C; V

= 2.7 to 3.6 V)

Note: 1. Sampled only, not 100% tested.

Symbol Parameter Min. Max. Unit

PUR

Time Delay to Read Operation 1 µs

PUW

Time Delay to Write Operation (once V

≥ V

)10ms

Write Inhibit Threshold 3.0 4.2 V

Symbol Parameter Min. Max. Unit

PUR

Time Delay to Read Operation 1 µs

PUW

Time Delay to Write Operation (once V

≥ V

)15ms

Write Inhibit Threshold 1.5 2.5 V

5/24

M28C64

Read

The deviceis accessed like a static RAM. When E

and G are low, and W is high, the contents of the

addressed location are presented on the I/O pins.

Otherwise, when either G or Eis high,the I/Opins

revert to their high impedance state.

Write

Write operations are initiated when both W and E

are low and G is high. The device supports both

W-controlled and E-controlled write cycles (as

shown in Figure 11 and Figure12). The address is

latched during the falling edge of W or E (which

ever occurs later) and the data is latched on the

rising edge of W or E (which ever occurs first).

After a delay, t

WLQ5H

, that cannot be shorter than

the value specified in Table 10Ato Table 10C, the

internal write cycle starts. It continues, under

internal timing control, until the write operation is

complete. The commencement of this period can

be detected by reading the Page Load Timer

Status on DQ5. The end of the cycle can be

detected by reading the status of the Data Polling

and the Toggle Bit functions on DQ7 and DQ6.

Page Write

The Page Write mode allows up to 64 bytes to be

written on a single page in a single go. This is

achieved through a series of successive Write

operations, notwoof which are separatedbymore

than the t

WLQ5H

value (as specified in Table 10A

to Table 10C).

All bytes must be located on the same page

address (A12-A6 must be the same for all bytes).

The internal write cycle can start at any instant

after t

WLQ5H

. Once initiated, the write operation is

internally timed, and continues, uninterrupted,

until completion.

As with the single byte Write operation, described

above, the DQ5, DQ6 and DQ7 lines can be used

to detect the beginning and end of the internally

controlled phase of the Page Write cycle.

Software Data Protection (SDP)

The device offers a software-controlled write-

protection mechanism that allows the user to

inhibit all write operations to the device. This can

be useful for protecting the memory from

inadvertent write cycles that may occur during

periods of instability (uncontrolled bus conditions

when excessive noise is detected,or when power

supply levels are outside their specified values).

By default, the device is shipped in the

“unprotected” state: the memory contents can be

freely changed by the user. Once the Software

Data Protection Mode is enabled, all write

commands are ignored,and have no effecton the

memory contents.

The device remains in this mode until a valid

Software Data Protection disable sequence is

received. The device reverts to its “unprotected”

state.

The status of the Software Data Protection

(enabled or disabled) is represented by a non-

Figure 4. Software Data Protection Enable Algorithm and Memory Write

Note: 1. The most significant address bits (A12 to A6) differ during these specific Page Write operations.

AI01356C

Write AAh in

Address 1555h

Write 55h in

Address 0AAAh

Write A0h in

Address 1555h

SDP is set

Write AAh in

Address 1555h

Write 55h in

Address 0AAAh

Write A0h in

Address 1555h

Page Write

(1 up to 64 bytes)

Write to

Memory

When SDP is SET

SDP Enable Algorithm

Page Write

Timing

(see note 1)

Page Write

Timing

(see note 1)

Write

is enabled

Physical

Page Write

Instruction

M28C64

6/24

volatile latch, and is remembered across periods

of the power being off.

The Software Data Protection Enable command

consists of the writing of three specific data bytes

to three specific memory locations (each location

being on a different page), as shown in Figure 4.

Similarly to disable the Software Data Protection,

the user has to write specific data bytes into six

different locations, as shown in Figure 5. This

complex series of operations protects against the

chance of inadvertent enabling or disabling of the

Software Data Protection mechanism.

When SDP is enabled, the memoryarray can still

have data written to it, but the sequence is more

complex (and hence better protected from

inadvertent use). The sequence is as shown in

Figure 4. This consists of anunlock key, to enable

the write action, at the end of which the SDP

continues to be enabled. This allows the SDP to

be enabled, and data to be written, within a single

Write cycle (t

Software Chip Erase

Using this function, available on the M28C64 but

not on the M28C64-A or M28C64-xxW, the

contents of the entire memory are erased (set to

FFh) by holding Chip Enable (E) low, and holding

Output Enable (G) at V

+7.0V. The chip is

cleared when a 10 ms low pulse is applied to the

Write Enable (W) signal (seeFigure 7 and Table 5

for details).

Status Bits

The devices provide three status bits (DQ7, DQ6

and DQ5), and one output pin (RB), foruse during

write operations. These allow the application to

use the write time latency of the device for getting

on with other work. These signals areavailable on

the I/O port bits DQ7, DQ6 and DQ5 (but only

during programming cycle, once a byte or more

has been latched into the memory)or continuously

on the RB output pin.

Data Polling bit (DQ7). Theinternally timed write

cycle starts after t

WLQ5H

(defined in Table 10A to

Table 10C) has elapsed since the previous byte

was latched in to the memory. The value of the

DQ7 bit of this last byte, is used as a signal

Figure 5. Software Data Protection Disable Algorithm

AI01357B

Write AAhin

Address 1555h

Write 55h in

Address 0AAAh

Write 80h in

Address 1555h

Unprotected State

Write AAhin

Address 1555h

Write 55h in

Address 0AAAh

Write 20h in

Address 1555h

Page Write

Timing

Figure 6. Status Bit Assignment

AI02815

DP TB PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z

PLTS

Hi-Z

DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

= Data

Polling

= Toggle Bit

= Page Load Timer

Status

= High impedance

7/24

M28C64

Table 5. Chip Erase AC Characteristics

for M28C64 and M28C64-xxW

= 0 to70 °C or –40 to 85 °C or –40 to 125 °C; V

= 4.5 to 5.5 V)

= 0 to 70 °C or –40 to 85 °C; V

= 2.7 to 3.6 V)

Note: 1. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min. Max. Unit

ELWL

Chip Enable Low to Write Enable Low

G=V

+7V

1 µs

WHEH

Write Enable High to Chip Enable High G = V

+7V 0 ns

WLWH2

Write Enable Low to Write Enable High

G=V

+7V

10 ms

GLWH

Output Enable Low to Write Enable High

G=V

+7V

1 µs

WHRH

Write Enable High to WriteEnable Low G = V

+7V 3 ms

throughout this write operation: it is inverted while

the internal write operation is underway, and is

inverted back to its original value once the

operation is complete.

Toggle bit (DQ6). The device offers another way

for determining when the internal write cycle is

completed. During the internal Erase/Write cycle,

DQ6 toggles from ’0’ to ’1’ and ’1’ to ’0’ (the first

read value being ’0’) on subsequent attempts to

read any byte of the memory. When the internal

write cycle is complete, the toggling is stopped,

and the valuesread on DQ7-DQ0are those ofthe

addressed memory byte. This indicates that the

device is again available for new Read and Write

operations.

Page Load Timer Status bit (DQ5). An internal

timer is used to measure the period between

successive Write operations, up to t

WLQ5H

(defined in Table 10Ato Table 10C). The DQ5 line

is held low to show when this timer is running

(hence showing that the device has received one

write operation, and is waiting for the next). The

DQ5 line is held high when the counter has

overflowed (hence showingthat the device is now

starting the internal write to the memory array).

Ready/Busy pin. The RB pin is an open drain

output that isheld low duringthe erase/write cycle,

and that is released (allowed to float) at the

completion of the programming cycle.

Figure 7. Chip Erase AC Waveforms (M28C64 and M28C64-xxW)

AI01484B

tWLWH2tELWL

tGLWH

tWHRH

tWHEH

M28C64

8/24

Table 6A. Read Mode DC Characteristics for M28C64 and M28C64-A (5V range)

= 0 to70 °C or –40 to 85 °C or –40 to 125 °C; V

= 4.5 to 5.5 V)

Note: 1. All inputs and outputs open circuit.

Table 6B. Read Mode DC Characteristics for M28C64-xxW (3V range)

= 0 to70 °C or –40 to 85 °C; V

= 2.7 to 3.6 V)

Note: 1. All inputs and outputs open circuit.

Symbol Parameter Test Condition Min. Max. Unit

Input Leakage Current 0 V ≤ V

≤ V

10 µA

Output Leakage Current 0 V ≤ V

OUT

≤ V

10 µA

Supply Current (TTL inputs) E = V

,G=V

, f = 5 MHz 30 mA

Supply Current (CMOS inputs)

E=V

,G=V

, f = 5 MHz

25 mA

CC1

Supply Current (Stand-by) TTL

E=V

1mA

CC2

Supply Current (Stand-by) CMOS E > V

- 0.3V 100 µA

Input Low Voltage -0.3 0.8 V

Input High Voltage 2

+ 0.5

Output Low Voltage

= 2.1 mA

0.4 V

Output High Voltage I

= -400 µA 2.4 V

Symbol Parameter Test Condition Min. Max. Unit

Input Leakage Current

0V≤ V

≤ V

10 µA

Output Leakage Current 0 V ≤ V

OUT

≤ V

10 µA

Supply Current (CMOS inputs)

E=V

,G=V

, f = 5 MHz, V

= 3.3V 8 mA

E=V

,G=V

, f = 5 MHz, V

= 3.6V 10 mA

CC2

Supply Current (Stand-by) CMOS E > V

- 0.3V 20 µA

Input Low Voltage -0.3 0.6 V

Input High Voltage 2

+ 0.5

Output Low Voltage I

= 1.6 mA 0.2 V

Output High Voltage I

= -400 µA 0.8 V

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