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PRELIMINARY DATA
February 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M28C16B
M28C17B
16 Kbit (2K x 8) Parallel EEPROM
With Software Data Protection
■ Fast Access Time: 90 ns at V
CC
=5V
■ Single Supply Voltage:
– 4.5 V to 5.5 V for M28CxxB
– 2.7 V to 3.6 V for M28CxxB-W
■ Low Power Consumption
■ Fast BYTE and PAGE WRITE (up to 64 Bytes)
–3ms at V
CC
=4.5 V
–5ms at V
CC
=2.7 V
■ Enhanced Write Detection and Monitoring:
– Data Po lling
– Toggle Bit
– Page Load Timer Status
■ JEDEC Approved Bytewide Pin-Out
■ Software Data Protection
■ 100000 Erase/Write Cycles (minimum)
■ Data Retention (minimum): 40 Years
DESCRIPTION
The M28C16B an d M28C17B devices consist of
2048x8 bits of low power, parallel EEPROM, fabricated with STMicroelectronics’ proprietary single
polysilicon CMOS technology. The devices offer
fast access time, with low power dissipation , and
require a single voltage supply.
Figure 1. Logic Diagram
AI02816
11
A0-A10
W
DQ0-DQ7
V
CC
M28C16B
M28C17B
G
E
V
SS
8
RB
(M28C17B only)
Table 1. Signal Names
A0-A10 Address Input
DQ0-DQ7 Data Input / Output
W
Write Enable
E
Chip Enable
G
Output Enable
RB
Ready/Busy (M28C17B only)
V
CC
Supply Voltage
V
SS
Ground
PLCC32 (K)
Page 2
M28C16B, M28C17B
2/17
Figure 2A. PLLC Connections
Note: 1. NC = Not Connected
AI02817
NC
A8
A10
DQ4
17
A0
NC
DQ0
DQ1
DQ2NCDQ3
A6
A3
A2
A1
A5
A4
9
W
A9
1
NC
NC
DQ6
A7
DQ7
32
NC
V
CC
M28C16B
NC
NC
DQ5
G
E
25
V
SS
Figure 2B. PLLC Connections
Note: 1. NC = Not Connected
AI02830
NC
A8
A10
DQ4
17
A0
NC
DQ0
DQ1
DQ2NCDQ3
A6
A3
A2
A1
A5
A4
9
W
A9
1
NC
NC
DQ6
A7
DQ7
32
RB
V
CC
M28C17B
NC
NC
DQ5
G
E
25
V
SS
The M28C17B is like the M28C16B in every way,
except that it has an extra ready/busy
(RB) output.
The device has been designed to offer a flexible
microcontroller interface, featuring software handshaking, with Data Polling and Toggle Bit. The device supports a 64 byte Page Write operation.
Software Data Protection (SDP) is also supported,
using the standard JEDEC algorithm.
SIGNAL DESCRIPTION
The external connections to the device are summarized in Table 1, and their use in Table 3.
Addresses (A0-A10). The address inputs are
used to select one byte from the memory array
during a read or write operation.
Data In/Out (DQ0-DQ7). The contents of the data
byte are written to, or read from, the memory array
through the Data I/O pins.
Chip Enable (E
). The chip enable input must be
held low to enable read and write operations.
When Chip Enable is high, p ower consumpti on is
reduced.
Output Enable (G
). The Output Enable input con-
trols the data output buffers, and is used to initiate
read operations.
Write Enable (W
). The Write Enable input controls
whether the addressed location is to be read, from
or written to.
Ready/Busy
(RB). Ready/Busy (on the M28C17B
only) is an open drain output that can be us ed to
detect the end of the internal write cycle.
DEVICE OPERATION
In order to prevent data corruption and inadvertent
write operations, an internal V
CC
comparator in-
hibits the Write operations if the V
CC
voltage is
lower than V
WI
(see Table 4A). Once the voltage
applied on the V
CC
pin goes over the VWI thresh-
old (V
CC>VWI
), write access to the memory is al-
lowed after a time-out t
PUW
, as specified in Table
4A.
Further protection against data corruption is of-
fered by the E
and W low pass filters: any glitch,
on the E
and W inputs, with a pulse width less than
10 ns (typical) is inte rnally filtered out to prevent
inadvertent write operations to the memory.
Read
The device is accessed like a static RAM. When E
and G are low, and W is high, the contents of the
addressed location are presented on the I/ O pi ns.
Otherwise, when either G
or E is high, the I/O pins
revert to their high impedance state.
Write
Write operations are initiated when both W
and E
are low and G i s high. The device supports both
W
-controlled and E-controlled write cycles (as
shown in Figure 11 and Figure 12). The address is
latched during the falling edge of W
or E (which
ever occurs later) and the data is latche d on the
rising edge of W
or E (which ever occurs first). Af-
ter a delay, t
WLQ5H
, that cannot be shorter than the
value specified in Table 10A, the internal write cycle starts. It continues, under internal timing control, until the write operation is complete. The
commencement of this period can be det ecte d by
reading the Page Load Timer Status on DQ5. The
Page 3
3/17
M28C16B, M28C17B
Figure 3. Block Diagram
AI02818
ADDRESS
LATCH
A6-A10
(Page Address)
X DECODE
CONTROL LOGIC
16K ARRAY
ADDRESS
LATCH
A0-A5
Y DECODE
VPP GEN RESET
SENSE AND DATA LATCH
I/O BUFFERS
EGW
PAGE LOAD
TIMER STATUS
TOGGLE BIT
DATA POLLING
DQ0-DQ7
Table 2. Absolute Maximum Ratings
1
Note: 1. Except for the rating “Operat i ng Temperature Ra nge”, stresses above those listed in t he Table “A bsolute Maximum Ratings” m ay
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indi cated in t he Operating sect i ons of thi s specifi cation i s not impl i ed. Exposure to Absolute M aximum Rating c onditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-ST D-883C, 3015.7 (100 pF, 15 00 Ω)
Symbol Parameter Value Unit
T
A
Ambient Operating Temperature -40 to 125 °C
T
STG
Storage Temperature -65 to 150 °C
V
CC
Supply Voltage -0.3 to 6.5 V
V
IO
Input or Output Voltage
-0.6 to V
CC
+0.6
V
V
I
Input Voltage -0.3 to 6.5 V
V
ESD Electrostatic Discharge Voltage (Human Body model)
2
4000 V
Page 4
M28C16B, M28C17B
4/17
Table 3. Operating Modes
1
Note: 1. 0=VIL; 1=VIH; X = V
IH
or V
IL
; V=12V ± 5%.
Mode E G W DQ0-DQ7
Stand-by 1 X X Hi-Z
Output Disable X 1 X Hi-Z
Write Disable X X 1 Hi-Z
Read 0 0 1 Data Out
Write 0 1 0 Data In
Chip Erase 0 V 0 Hi-Z
end of the cycle can be detected by reading the
status of the Data Polling and the Toggle Bit functions on DQ7 and DQ6.
Page Write
The Page Write mode allows u p to 64 by tes to be
written on a single page in a single go. This is
achieved through a series of successive Write operations, no two of which are separated by more
than the t
WLQ5H
value (as specified in Table 10A).
The page write can be initiated during any byte
write operation. Following the first byte write instruction the host may send another address and
data with a minimum data transfer rate of:
1/t
WLQ5H
.
The internal write cycle can start at any instant after t
WLQ5H
. Once initiated, the write operation is internally timed, and continues, uninterrupt ed, until
completion.
All bytes must be located on the same page address (A10-A6 must be the same for all bytes).
Otherwise, the Page Write operation is not executed.
As with the single byte Write operation, described
above, the DQ5, DQ6 and DQ7 lines can be used
to detect the beginning and end of the internally
controlled phase of the Page Write cycle.
Software Data Protection (SDP)
The device offers a software-controlled write-protection mechanism that allows the user to inhibit all
write operations to the device. This c an be usef ul
for protecting the memory f rom inadvertent write
cycles that may occur during periods of instability
(uncontrolled bus conditions when excessive
noise is detected, or when power supply levels are
outside their specified values).
By default, the device is shipped in the “unprotected” state: the memory contents can be freely
changed by the user. Once the Software Data Protection Mode is enabled, all write com mands are
Table 4A. Power-Up Timing
1
for M28CxxB (5V range)
(T
A
= 0 to 70 °C or -40 to 85 °C; VCC = 4.5 to 5.5 V)
Note: 1. Sampled only, not 100% tested.
Table 4B. Power-Up Timing1 for M28CxxB-W (3V range)
(T
A
= 0 to 70 °C or -40 to 85 °C; VCC = 2.7 to 3.6 V)
Note: 1. Sampled only, not 100% tested.
Symbol Parameter Min. Max. Unit
t
PUR
Time Delay to Read Operation 1 µs
t
PUW
Time Delay to Write Operation (once VCC ≥ VWI)
10 ms
V
WI
Write Inhibit Threshold 3.0 4.2 V
Symbol Parameter Min. Max. Unit
t
PUR
Time Delay to Read Operation 1 µs
t
PUW
Time Delay to Write Operation (once VCC ≥ VWI)15ms
V
WI
Write Inhibit Threshold 1.5 2.5 V
Page 5
5/17
M28C16B, M28C17B
ignored, and have no effect on the memory contents .
The device remains in this mode until a valid Software Data Protection disable sequence is re-
ceived. The device reverts to its “unprotected”
state.
The status of the Software Data Protection (enabled or disabled) is represented by a non-volatile
latch, and is remembered across periods of the
power being off.
The Software Data Protection Enable command
consists of the writing of three specific data bytes
to three specific memory locations (each location
being on a different page), as shown in Figure 4.
Similarly to disable the Software Data Protection,
the user has to write specific data bytes into six dif-
ferent locations, as shown in Figure 6. This complex series of operations protects against the
chance of inadvertent enabling or disabling of the
Software Data Protection mechanism.
Figure 4. Software Data Protection Enable Algorithm and Memory Write
Note: 1. The most sign i ficant addre ss bits (A1 0 to A6) differ during the se specific Page Write operations.
AI02819
Write AAh in
Address 555h
Write 55h in
Address 2AAh
Write A0h in
Address 555h
SDP is set
Write AAh in
Address 555h
Write 55h in
Address 2AAh
Write A0h in
Address 555h
Page Write
(1 up to 64 bytes)
Write to Memory
When SDP is SET
SDP Enable Algorithm
Page Write
Timing
(see note 1)
Page Write
Timing
(see note 1)
Write
is Enabled
Physical
Page Write
Instruction
Figure 5. Sta tu s B it As si gnment
AI02815
DP TB PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
DP
TB
PLTS
Hi-Z
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
= Data Polling
= Toggle Bit
= Page Load Timer Status
= High impedance
Figure 6. Software Data Protection Disable
Algorithm
AI02820
Write AAh in
Address 555h
Write 55h in
Address 2AAh
Write 80h in
Address 555h
Unprotected State
Write AAh in
Address 555h
Write 55h in
Address 2AAh
Write 20h in
Address 555h
Page Write
Timing
Page 6
M28C16B, M28C17B
6/17
Table 5. Chip Erase AC Characteristics
1
(TA = 0 to 70 °C or -40 to 85 °C; VCC = 4.5 to 5.5 V or 2.7 to 3.6 V)
Note: 1. Sampled only, not 100% tested.
Symbol Parameter Test Condition Min. Max. Unit
t
ELWL
Chip Enable Low to Write Enable Low
G
= VCC + 7V
1 µs
t
WHEH
Write Enable High to Chip Enable High G = VCC + 7V 0 ns
t
WLWH2
Write Enable Low to Write Enable High G = VCC + 7V 10 ms
t
GLWH
Output Enable Low to Write Enable High
G
= VCC + 7V
1µs
t
WHRH
Write Enable High to Write Enable Low G = VCC + 7V 3 ms
Figure 7. Chip Erase AC Waveforms
AI01484B
E
G
W
tWLWH2tELWL
tGLWH
tWHRH
tWHEH
When SDP is enabled, the memory array can still
have data written to it, but the sequence is more
complex (and hence better protected from inadvertent use). The seque nce is as shown in Figure
4. This consists of an unlock key, to enable the
write action, at the end of which the SDP continues
to be enabled. This allows the SDP to be enabled,
and data to be written, within a single Write cycle
(t
WC
).
Software Chip Erase
The contents of the entire memory are erased ( set
to FFh) by holding Chip Enable (E
) low, and hold-
ing Output Enable (G
) at VCC+7.0V. The chip is
cleared when a 10 ms low pulse is applied to the
Write Enable (W
) signal (see Figure 7 and Table 5
for details).
Status Bits
The devices provide three status bits (DQ7, DQ6
and DQ5), for use d uring write operation s. These
allow the application to use t he write time la tency
of the device for getting on with other work. These
signals are available on the I/O port bits DQ7, DQ6
and DQ5 (but only during programming cycle,
once a byte or more has been latched into the
memory).
Data Polling bit (DQ7). The internally timed write
cycle starts after t
WLQ5H
(defined in Table 10A)
has elapsed since the previous byte was latched in
to the memory. The value of the DQ7 bit of this last
byte, is used as a signal throughout this write operation: it is inverted while the internal write operation is underway, and is inverted back to its
original value once the operation is complete.
Toggle bit (DQ6). The device offers another way
for determining when the internal write cycle is
completed. During the internal E rase/Write cycle,
DQ6 toggles from ’0’ to ’1’ and ’1’ to ’0’ (the first
read value being ’0’) on subsequent att empts to
read any byte of the memory. When the internal
write cycle is complete, the toggling is stopped,
and the values read on DQ7-DQ0 are those of the
addressed memory byte. This indicates that the
device is again avai lable for new Read and Write
operations.
Page Load Timer Status bit (DQ5). An internal
timer is used to measure the period bet ween suc -
Page 7
7/17
M28C16B, M28C17B
Table 6A. Read Mode DC Characteristics for M28CxxB (5V range)
(T
A
= 0 to 70 °C or -40 to 85 °C; VCC = 4.5 to 5.5 V)
Note: 1. All inputs and outputs op en circuit.
Table 6B. Read Mode DC Characteristics for M28CxxB-W (3V range)
(T
A
= 0 to 70 °C or -40 to 85 °C; VCC = 2.7 to 3.6 V)
Note: 1. All inputs and outputs op en circuit.
Symbol Parameter Test Condition Min. Max. Unit
I
LI
Input Leakage Curren t
0V ≤ V
IN
≤ V
CC
10 µA
I
LO
Output Leakage Current 0 V ≤ V
OUT
≤ V
CC
10 µA
I
CC
1
Supply Current (TTL inputs) E = VIL, G = VIL , f = 5 MHz 30 mA
Supply Current (CMOS inputs) E
= VIL, G = VIL , f = 5 MHz 25 mA
I
CC1
1
Supply Current (Stand-by) TTL
E
= V
IH
1mA
I
CC2
1
Supply Current (Stand-by) CMOS E > VCC - 0.3V 100 µA
V
IL
Input Low Voltage -0.3 0.8 V
V
IH
Input High Voltage 2
V
CC
+ 0.5
V
V
OL
Output Low Voltage
I
OL
= 2.1 mA
0.4 V
V
OH
Output High Voltage
I
OH
= -400 µA
2.4 V
Symbol Parameter Test Condition Min. Max. Unit
I
LI
Input Leakage Curren t
0V ≤ V
IN
≤ V
CC
10 µA
I
LO
Output Leakage Current
0V ≤ V
OUT
≤ V
CC
10 µA
I
CC
1
Supply Current (CMOS inputs)
E
= VIL, G = VIL , f = 5 MHz, VCC = 3.3V 8 mA
E
= VIL, G = VIL , f = 5 MHz, VCC = 3.6V 10 mA
I
CC2
1
Supply Current (Stand-by) CMOS E > VCC - 0.3V 20 µA
V
IL
Input Low Voltage -0.3 0.6 V
V
IH
Input High Voltage 2 VCC + 0.5 V
V
OL
Output Low Voltage
I
OL
= 1.6 mA 0.2 V
CC
V
V
OH
Output High Voltage
I
OH
= -400 µA 0.8 V
CC
V
cessive Write operations, up to t
WLQ5H
(defined in
Table 10A). The DQ5 line is held low to show
when this timer is running (hence showing that the
device has received one write operation, and is
waiting for the next). The DQ5 line is held high
when the counter has overflowed (hence showing
that the device is now starting the internal write to
the memory array).
Page 8
M28C16B, M28C17B
8/17
Table 7. Input and Ou t put Parameters1 (TA = 25 °C, f = 1 MHz)
Note: 1. Sampled only, not 100% tested.
Table 8. AC Measurement Conditions
Symbol Parameter Test Condition Min. Max. Unit
C
IN
Input Capacitance VIN = 0 V 6 pF
C
OUT
Output Capacitance
V
OUT
= 0 V
12 pF
Input Rise and Fall Times ≤ 20 ns
Input Pulse Voltages 0.4 V to 2.4 V
Input and Output Timing Reference Voltages 0.8 V to 2.0 V
Figure 8. AC Testing Input Output Waveforms
AI02821
2.4V
0.4V
2.0V
0.8V
Figure 9. AC Testing Equivalent Lo ad Circuit
AI02102B
OUT
CL = 100pF
CL includes JIG capacitance
I
OL
DEVICE
UNDER
TEST
I
OH
Page 9
9/17
M28C16B, M28C17B
Table 9A. Read Mode AC Characteristics for M28CxxB (5V range)
(T
A
= 0 to 70 °C or -40 to 85 °C; VCC = 4.5 to 5.5 V)
Note: 1. Output Hi-Z i s defined as th e poi nt at which data is no longer drive n.
Table 9B. Read Mode AC Characteristics for M28CxxB-W (3V range)
(T
A
= 0 to 70 °C or -40 to 85 °C; VCC = 2.7 to 3.6 V)
Note: 1. Output Hi-Z i s defined as th e poi nt at which data is no longer drive n.
Symbol Alt. Parameter
Test
Condition
M28CxxB
Unit-90 -12
Min Max Min Max
t
AVQV
t
ACC
Address Valid to Output Valid
E
= VIL,
G
= V
IL
90 120 ns
t
ELQV
t
CE
Chip Enable Low to Output Valid
G
= V
IL
90 120 ns
t
GLQV
t
OE
Output Enable Low to Output Valid
E
= V
IL
40 45 ns
t
EHQZ
1
t
DF
Chip Enable High to Output Hi-Z
G
= V
IL
040045ns
t
GHQZ
1
t
DF
Output Enable High to Output Hi-Z
E
= V
IL
040045ns
t
AXQX
t
OH
Address Transition to Output Transition
E
= VIL,
G
= V
IL
00ns
Symbol Alt. Parameter
Test
Condition
M28CxxB-W
Unit-12 -15
Min Max Min Max
t
AVQV
t
ACC
Address Valid to Output Valid
E
= VIL,
G
= V
IL
120 150 ns
t
ELQV
t
CE
Chip Enable Low to Output Valid
G
= V
IL
120 150 ns
t
GLQV
t
OE
Output Enable Low to Output Valid
E
= V
IL
80 80 ns
t
EHQZ
1
t
DF
Chip Enable High to Output Hi-Z
G
= V
IL
045050ns
t
GHQZ
1
t
DF
Output Enable High to Output Hi-Z
E
= V
IL
045050ns
t
AXQX
t
OH
Address Transition to Output Transition
E
= VIL,
G
= V
IL
00ns
Page 10
M28C16B, M28C17B
10/17
Table 10A. Write Mode AC Characteristics for M28CxxB (5V range)
(T
A
= 0 to 70 °C or -40 to 85 °C; VCC = 4.5 to 5.5 V)
Symbol Alt. Parameter Test Condition
M28C17B
Unit
Min Max
t
AVWL
t
AS
Address Valid to Write Enable Low
E
= VIL, G = V
IH
0ns
t
AVEL
t
AS
Address Valid to Chip Enable Low
G
= VIH, W = V
IL
0ns
t
ELWLtCES
Chip Enable Low to Write Enable Low
G
= V
IH
0ns
t
GHWLtOES
Output Enable High to Write Enable Low
E
= V
IL
0ns
t
GHELtOES
Output Enable High to Chip Enable Low
W
= V
IL
0ns
t
WLELtWES
Write Enable Low to Chip Enable Low
G
= V
IH
0ns
t
WLAX
t
AH
Write Enable Low to Address Transition 50 ns
t
ELAX
t
AH
Chip Enable Low to Address Transition 50 ns
t
WLDV
t
DV
Write Enable Low to Input Valid
E
= VIL, G = V
IH
1 µs
t
ELDV
t
DV
Chip Enable Low to Input Valid
G
= VIH, W = V
IL
1µs
t
ELEH
t
WP
Chip Enable Low to Chip Enable High 50 ns
t
WHEHtCEH
Write Enable High to Chip Enable High 0 ns
t
WHGLtOEH
Write Enable High to Output Enable Low 0 ns
t
EHGLtOEH
Chip Enable High to Output Enable Low 0 ns
t
EHWHtWEH
Chip Enable High to Write Enable High 0 ns
t
WHDX
t
DH
Write Enable High to Input Transition 0 ns
t
EHDX
t
DH
Chip Enable High to Input Transition 0 ns
t
WHWLtWPH
Write Enable High to Write Enable Low 50 ns
t
WLWHtWP
Write Enable Low to Write Enable High 50 ns
t
WLQ5HtBLC
Time-out After the Last Byte Write 100 µs
t
Q5HQ5XtWC
Write Cycle Time 3 ms
t
DVWH
t
DS
Data Valid before Write Enable High 50 ns
t
DVEH
t
DS
Data Valid before Chip Enable High 50 ns
Page 11
11/17
M28C16B, M28C17B
Table 10B. Write Mode AC Characteristics for M28CxxB-W (3V range)
(T
A
= 0 to 70 °C or -40 to 85 °C; VCC = 2.7 to 3.6 V)
Symbol Alt. Parameter Test Condition
M28C17B-xxW
Unit
Min Max
t
AVWL
t
AS
Address Valid to Write Enable Low
E
= VIL, G = V
IH
0ns
t
AVEL
t
AS
Address Valid to Chip Enable Low
G
= VIH, W = V
IL
0ns
t
ELWLtCES
Chip Enable Low to Write Enable Low
G
= V
IH
0ns
t
GHWLtOES
Output Enable High to Write Enable Low
E
= V
IL
0ns
t
GHELtOES
Output Enable High to Chip Enable Low
W
= V
IL
0ns
t
WLELtWES
Write Enable Low to Chip Enable Low
G
= V
IH
0ns
t
WLAX
t
AH
Write Enable Low to Address Transition 100 ns
t
ELAX
t
AH
Chip Enable Low to Address Transition 100 ns
t
WLDV
t
DV
Write Enable Low to Input Valid
E
= VIL, G = V
IH
1 µs
t
ELDV
t
DV
Chip Enable Low to Input Valid
G
= VIH, W = V
IL
1µs
t
ELEH
t
WP
Chip Enable Low to Chip Enable High 100 1000 ns
t
WHEHtCEH
Write Enable High to Chip Enable High 0 ns
t
WHGLtOEH
Write Enable High to Output Enable Low 0 ns
t
EHGLtOEH
Chip Enable High to Output Enable Low 0 ns
t
EHWHtWEH
Chip Enable High to Write Enable High 0 ns
t
WHDX
t
DH
Write Enable High to Input Transition 0 ns
t
EHDX
t
DH
Chip Enable High to Input Transition 0 ns
t
WHWLtWPH
Write Enable High to Write Enable Low 50 1000 ns
t
WLWHtWP
Write Enable Low to Write Enable High 100 ns
t
WLQ5HtBLC
Time-out after the last byte write 100 µs
t
Q5HQ5XtWC
Write Cycle Time 5 ms
t
DVWH
t
DS
Data Valid before Write Enable High 50 ns
t
DVEH
t
DS
Data Valid before Chip Enable High 50 ns
Page 12
M28C16B, M28C17B
12/17
Figure 10. Read Mode AC Waveforms (with Write Enable, W, high)
Note: 1. Write Enable (W) = V
IH
Figure 11. Write Mode AC Waveforms (Write Enable, W, controlled)
AI02822
VALID
tAVQV tAXQX
tGLQV tEHQZ
tGHQZ
DATA OUT
A0-A10
E
G
DQ0-DQ7
tELQV
Hi-Z
AI02823
VALID
tAVWL
A0-A10
E
G
DQ0-DQ7
DATA IN
W
tWLAX
tELWL
tGHWL
tWLDV
tWHEH
tWHGLtWLWH
tWHWL
tWHDXtDVWH
RB
tWHRL
Page 13
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M28C16B, M28C17B
Figure 12. Write Mode AC Waveforms (Chip Enable, E, controlled)
Figure 13. Page Write Mode AC Waveforms (Write Enable, W
, controlled)
AI02824
VALID
tAVEL
A0-A10
E
G
DQ0-DQ7
DATA IN
W
tELAX
tGHEL
tWLEL
tELDV
tEHGL
tEHDXtDVEH
RB
tEHRL
tELEH
tEHWH
tQ5HQ5X
AI02825
A0-A10
E
G
DQ0-DQ7 (in)
W
Addr 0
DQ5 (out)
RB
Addr 1 Addr 2 Addr n
tWLQ5H
tWLWH
tWHWL
tWHRL
Byte 0 Byte 1 Byte 2 Byte n
Page 14
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14/17
Figure 14. Software Protected Write Cycle Waveforms
Note: 1. A10 to A6 must specify the same pa ge address dur i ng each high-to-low trans i tion of W (or E). G must be high on l y wh en W and E
are both low.
Figure 15. Data Polling Sequence Waveforms
AI02826
A0-A5
E
G
DQ0-DQ7
W
tWLWH
tDVWH
Byte 0
tWHWL
A6-A10
tWLAX
tWHWH
tWHDX
tAVEL
555h 2AAh 555h
Byte 62 Byte 63AAh 55h A0h
Byte Address
Page Address
AI02827
A0-A10
E
G
DQ7
W
DQ7 DQ7DQ7 DQ7DQ7
Ready
Last WRITE Internal Write Sequence
Address of the last byte of the Page Write instruction
Page 15
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M28C16B, M28C17B
Table 11. Ordering Information Scheme
Example: M28C16 – 120 W K 6 TR
Ready/Busy
Option
16 Pin 1 = Not Connected TR Tape and Reel Packing
17 Pin 1 = Ready/Busy
Speed Temperature Range
90 90 ns (5V range only) 1 0 °C to 70 °C
120 120 ns 6 –40 °C to 85 °C
150 150 ns (3V range only)
Operating Voltage Package
blank 4.5 V to 5.5 V K PLCC32
W
2.7 V to 3.6 V
ORDERING INFORMATION
Devices are shipped from the factory with the
memory content set at all ‘1’s (FFh).
The notation used for the device number is as
shown in Table 11. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact the ST
Sales Office nearest to you.
Figure 16. Toggle Bit Sequence Waveforms
Note: 1. The Toggle Bit is first set to ‘0’.
AI02828
A0-A10
E
G
DQ6
W
ReadyLast WRITE
Internal Write Sequence
(1)
TOGGLE
Page 16
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16/17
Figure 17. PLCC (K)
Note: 1. Drawing is not to scal e.
PLCC
D
Ne E1 E
1 N
D1
Nd
CP
B
D2/E2
e
B1
A1
A
R
0.51 (.020)
1.14 (.045)
F
A2
Table 12. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
Symbol
mm inches
Typ. Min. Max. Typ. Min. Max.
A 2.54 3.56 0.100 0.140
A1 1.52 2.41 0.060 0.095
A2 – 0.38 – 0.015
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
D 12.32 12.57 0.485 0.495
D1 11.35 11.56 0.447 0.455
D2 9.91 10.92 0.390 0.430
E 14.86 15.11 0.585 0.595
E1 13.89 14.10 0.547 0.555
E2 12.45 13.46 0.490 0.530
e 1.27 – – 0.050 – –
F 0.00 0.25 0.000 0.010
R 0.89 – – 0.035 – –
N32 32
Nd 7 7
Ne 9 9
CP 0.10 0.004
Page 17
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M28C16B, M28C17B
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