ST M28C16B, M28C17B User Manual

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M28C16B
M28C17B

16 Kbit (2K x 8) Parallel EEPROM

With Software Data Protection

PRELIMINARY DATA

■ Fast Access Time: 90 ns at V

■ Single Supply Voltage:

CC

=5V

– 4.5 V to 5.5 V for M28CxxB
– 2.7 V to 3.6 V for M28CxxB-W

■ Low Power Consumption

■ Fast BYTE and PAGE WRITE (up to 64 Bytes)

–3ms at V
–5ms at V

■ Enhanced Write Detection and Monitoring:

CC
CC

=4.5 V
=2.7 V

– Data Po lling
– Toggle Bit
– Page Load Timer Status

■ JEDEC Approved Bytewide Pin-Out

■ Software Data Protection

■ 100000 Erase/Write Cycles (minimum)

■ Data Retention (minimum): 40 Years

DESCRIPTION

The M28C16B an d M28C17B devices consist of
2048x8 bits of low power, parallel EEPROM, fabri­cated with STMicroelectronics’ proprietary single
polysilicon CMOS technology. The devices offer
fast access time, with low power dissipation , and
require a single voltage supply.

PLCC32 (K)

Figure 1. Logic Diagram

V

CC

Table 1. Signal Names

W

11

M28C16B

E

G

M28C17B

V

SS

A0-A10 Address Input
DQ0-DQ7 Data Input / Output
W
E
G
RB
V

CC

V

SS

February 1999

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

Write Enable
Chip Enable
Output Enable
Ready/Busy (M28C17B only)
Supply Voltage

Ground

A0-A10

8

DQ0-DQ7

RB

(M28C17B only)

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M28C16B, M28C17B

Figure 2A. PLLC Connections

CC

NC

A7

NC

A6
A5
A4
A3
A2

9
A1
A0

NC

DQ0

Note: 1. NC = Not Connected

M28C16B

DQ1

DQ2NCDQ3

NC

SS

V

1

17

NC

32

W

V

A8
A9
NC
NC
G

25

A10
E
DQ7
DQ6

DQ4

DQ5

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The M28C17B is like the M28C16B in every way,
except that it has an extra ready/busy

(RB) output.

The device has been designed to offer a flexible
microcontroller interface, featuring software hand­shaking, with Data Polling and Toggle Bit. The de­vice supports a 64 byte Page Write operation.
Software Data Protection (SDP) is also supported,
using the standard JEDEC algorithm.

SIGNAL DESCRIPTION

The external connections to the device are sum­marized in Table 1, and their use in Table 3.

Addresses (A0-A10). The address inputs are
used to select one byte from the memory array
during a read or write operation.

Data In/Out (DQ0-DQ7). The contents of the data
byte are written to, or read from, the memory array
through the Data I/O pins.

Chip Enable (E

). The chip enable input must be

held low to enable read and write operations.
When Chip Enable is high, p ower consumpti on is
reduced.

Output Enable (G

). The Output Enable input con-

trols the data output buffers, and is used to initiate
read operations.

Write Enable (W

). The Write Enable input controls

whether the addressed location is to be read, from
or written to.

Ready/Busy

(RB). Ready/Busy (on the M28C17B

only) is an open drain output that can be us ed to
detect the end of the internal write cycle.

Figure 2B. PLLC Connections

CC

NC

A7

NC

A6
A5
A4
A3
A2

9
A1
A0

NC

DQ0

Note: 1. NC = Not Connected

M28C17B

DQ1

DQ2NCDQ3

NC

SS

V

1

17

RB

32

W

V

A8
A9
NC
NC
G

25

A10
E
DQ7
DQ6

DQ4

DQ5

AI02830

DEVICE OPERATION

In order to prevent data corruption and inadvertent
write operations, an internal V
hibits the Write operations if the V
lower than V
applied on the V
old (V

CC>VWI

lowed after a time-out t

(see Table 4A). Once the voltage

WI

pin goes over the VWI thresh-

CC

), write access to the memory is al-

PUW

comparator in-

CC

voltage is

CC

, as specified in Table

4A.
Further protection against data corruption is of-

fered by the E
on the E

and W low pass filters: any glitch,

and W inputs, with a pulse width less than
10 ns (typical) is inte rnally filtered out to prevent
inadvertent write operations to the memory.

Read

The device is accessed like a static RAM. When E
and G are low, and W is high, the contents of the
addressed location are presented on the I/ O pi ns.
Otherwise, when either G

or E is high, the I/O pins

revert to their high impedance state.

Write

Write operations are initiated when both W

and E
are low and G i s high. The device supports both
W

-controlled and E-controlled write cycles (as
shown in Figure 11 and Figure 12). The address is
latched during the falling edge of W

or E (which
ever occurs later) and the data is latche d on the
rising edge of W
ter a delay, t

or E (which ever occurs first). Af-

, that cannot be shorter than the

WLQ5H

value specified in Table 10A, the internal write cy­cle starts. It continues, under internal timing con­trol, until the write operation is complete. The
commencement of this period can be det ecte d by
reading the Page Load Timer Status on DQ5. The

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M28C16B, M28C17B

Table 2. Absolute Maximum Ratings

1

Symbol Parameter Value Unit

T

A

T

STG

V

CC

V

IO

V

I

V

ESD Electrostatic Discharge Voltage (Human Body model)

Note: 1. Except for the rating “Operat i ng Temperature Ra nge”, stresses above those listed in t he Table “A bsolute Maximum Ratings” m ay

cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indi cated in t he Operating sect i ons of thi s specifi cation i s not impl i ed. Exposure to Absolute M aximum Rating c ondi­tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.

2. MIL-ST D-883C, 3015.7 (100 pF, 15 00 Ω)

Ambient Operating Temperature -40 to 125 °C
Storage Temperature -65 to 150 °C
Supply Voltage -0.3 to 6.5 V
Input or Output Voltage

-0.6 to V

CC

+0.6

Input Voltage -0.3 to 6.5 V

2

4000 V

V

Figure 3. Block Diagram

EGW

A6-A10

(Page Address)

A0-A5

VPP GEN RESET

ADDRESS

LATCH

ADDRESS

LATCH

Y DECODE

X DECODE

CONTROL LOGIC

16K ARRAY

SENSE AND DATA LATCH

I/O BUFFERS

DQ0-DQ7

PAGE LOAD
TIMER STATUS
TOGGLE BIT
DATA POLLING

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M28C16B, M28C17B

IH

or V

1

; V=12V ± 5%.

IL

Otherwise, the Page Write operation is not execut­ed.

As with the single byte Write operation, described
above, the DQ5, DQ6 and DQ7 lines can be used
to detect the beginning and end of the internally
controlled phase of the Page Write cycle.

Software Data Protection (SDP)

The device offers a software-controlled write-pro­tection mechanism that allows the user to inhibit all
write operations to the device. This c an be usef ul
for protecting the memory f rom inadvertent write
cycles that may occur during periods of instability
(uncontrolled bus conditions when excessive
noise is detected, or when power supply levels are
outside their specified values).

By default, the device is shipped in the “unprotect­ed” state: the memory contents can be freely
changed by the user. Once the Software Data Pro­tection Mode is enabled, all write com mands are

Table 3. Operating Modes

Mode E G W DQ0-DQ7

Stand-by 1 X X Hi-Z
Output Disable X 1 X Hi-Z
Write Disable X X 1 Hi-Z
Read 0 0 1 Data Out
Write 0 1 0 Data In
Chip Erase 0 V 0 Hi-Z

Note: 1. 0=VIL; 1=VIH; X = V

end of the cycle can be detected by reading the
status of the Data Polling and the Toggle Bit func­tions on DQ7 and DQ6.

Page Write

The Page Write mode allows u p to 64 by tes to be
written on a single page in a single go. This is
achieved through a series of successive Write op­erations, no two of which are separated by more
than the t

value (as specified in Table 10A).

WLQ5H

The page write can be initiated during any byte
write operation. Following the first byte write in­struction the host may send another address and
data with a minimum data transfer rate of:

WLQ5H

.

1/t
The internal write cycle can start at any instant af-

ter t

. Once initiated, the write operation is in-

WLQ5H

ternally timed, and continues, uninterrupt ed, until
completion.

All bytes must be located on the same page ad­dress (A10-A6 must be the same for all bytes).

1

Table 4A. Power-Up Timing

(T

= 0 to 70 °C or -40 to 85 °C; VCC = 4.5 to 5.5 V)

A

Symbol Parameter Min. Max. Unit

t

PUR

t

PUW

V

WI

Note: 1. Sampled only, not 100% tested.

Time Delay to Read Operation 1 µs

Time Delay to Write Operation (once VCC ≥ VWI)
Write Inhibit Threshold 3.0 4.2 V

for M28CxxB (5V range)

10 ms

Table 4B. Power-Up Timing1 for M28CxxB-W (3V range)

= 0 to 70 °C or -40 to 85 °C; VCC = 2.7 to 3.6 V)

(T

A

Symbol Parameter Min. Max. Unit

t

PUR

t

PUW

V

WI

Note: 1. Sampled only, not 100% tested.

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Time Delay to Read Operation 1 µs
Time Delay to Write Operation (once VCC ≥ VWI)15ms
Write Inhibit Threshold 1.5 2.5 V

Figure 4. Software Data Protection Enable Algorithm and Memory Write

M28C16B, M28C17B

Write AAh in

Address 555h

Page Write

Timing

(see note 1)

Note: 1. The most sign i ficant addre ss bits (A1 0 to A6) differ during the se specific Page Write operations.

Write 55h in

Address 2AAh

Write A0h in

Address 555h

SDP is set

SDP Enable Algorithm

ignored, and have no effect on the memory con­tents .

The device remains in this mode until a valid Soft­ware Data Protection disable sequence is re-

Page Write

Timing

(see note 1)

Physical

Page Write

Instruction

ferent locations, as shown in Figure 6. This com­plex series of operations protects against the
chance of inadvertent enabling or disabling of the
Software Data Protection mechanism.

Write AAh in

Address 555h

Write 55h in

Address 2AAh

Write A0h in

Address 555h

Page Write

(1 up to 64 bytes)

Write to Memory

When SDP is SET

AI02819

ceived. The device reverts to its “unprotected”
state.

The status of the Software Data Protection (en­abled or disabled) is represented by a non-volatile
latch, and is remembered across periods of the
power being off.

The Software Data Protection Enable command
consists of the writing of three specific data bytes
to three specific memory locations (each location

Figure 6. Software Data Protection Disable
Algorithm

Write AAh in

Address 555h

being on a different page), as shown in Figure 4.
Similarly to disable the Software Data Protection,

the user has to write specific data bytes into six dif-

Write 55h in

Address 2AAh

Write
is Enabled

Figure 5. Sta tu s B it As si gnment

DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

DP TB PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z

DP

= Data Polling

TB

= Toggle Bit

PLTS

= Page Load Timer Status

Hi-Z

= High impedance

AI02815

Page Write

Timing

Write 80h in

Address 555h

Write AAh in

Address 555h

Write 55h in

Address 2AAh

Write 20h in

Address 555h

Unprotected State

AI02820

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M28C16B, M28C17B

Figure 7. Chip Erase AC Waveforms

E

G

W

tWHEH

tGLWH

Table 5. Chip Erase AC Characteristics

tWLWH2tELWL

1

tWHRH

(TA = 0 to 70 °C or -40 to 85 °C; VCC = 4.5 to 5.5 V or 2.7 to 3.6 V)

Symbol Parameter Test Condition Min. Max. Unit

t

ELWL

t

WHEH

t

WLWH2

t

GLWH

t

WHRH

Note: 1. Sampled only, not 100% tested.

Chip Enable Low to Write Enable Low

Write Enable High to Chip Enable High G = VCC + 7V 0 ns
Write Enable Low to Write Enable High G = VCC + 7V 10 ms
Output Enable Low to Write Enable High
Write Enable High to Write Enable Low G = VCC + 7V 3 ms

When SDP is enabled, the memory array can still
have data written to it, but the sequence is more
complex (and hence better protected from inad­vertent use). The seque nce is as shown in Figure

4. This consists of an unlock key, to enable the
write action, at the end of which the SDP continues
to be enabled. This allows the SDP to be enabled,
and data to be written, within a single Write cycle
(t

).

WC

Software Chip Erase

The contents of the entire memory are erased ( set
to FFh) by holding Chip Enable (E
ing Output Enable (G

) at VCC+7.0V. The chip is

) low, and hold-

cleared when a 10 ms low pulse is applied to the
Write Enable (W

) signal (see Figure 7 and Table 5

for details).

Status Bits

The devices provide three status bits (DQ7, DQ6
and DQ5), for use d uring write operation s. These
allow the application to use t he write time la tency
of the device for getting on with other work. These
signals are available on the I/O port bits DQ7, DQ6
and DQ5 (but only during programming cycle,

G

= VCC + 7V

G

= VCC + 7V

1 µs

1µs

once a byte or more has been latched into the
memory).

Data Polling bit (DQ7). The internally timed write
cycle starts after t

WLQ5H

(defined in Table 10A)
has elapsed since the previous byte was latched in
to the memory. The value of the DQ7 bit of this last
byte, is used as a signal throughout this write op­eration: it is inverted while the internal write oper­ation is underway, and is inverted back to its
original value once the operation is complete.

Toggle bit (DQ6). The device offers another way
for determining when the internal write cycle is
completed. During the internal E rase/Write cycle,
DQ6 toggles from ’0’ to ’1’ and ’1’ to ’0’ (the first
read value being ’0’) on subsequent att empts to
read any byte of the memory. When the internal
write cycle is complete, the toggling is stopped,
and the values read on DQ7-DQ0 are those of the
addressed memory byte. This indicates that the
device is again avai lable for new Read and Write
operations.

Page Load Timer Status bit (DQ5). An internal
timer is used to measure the period bet ween suc -

AI01484B

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