ST M28256 User Manual

M28256

M28256

256 Kbit (32Kb x8) Parallel EEPROM

with Software Data Protection

FAST ACCESS TIME:

±90ns at 5V

±120ns at 3V

SINGLE SUPPLY VOLTAGE:

±5V ± 10% for M28256

±2.7V to 3.6V for M28256-xxW

LOW POWER CONSUMPTION

FAST WRITE CYCLE:

±64 Bytes Page Write Operation

±Byte or Page Write Cycle

ENHANCED END of WRITE DETECTION:

±Data Polling

±Toggle Bit STATUS REGISTER

HIGH RELIABILITY DOUBLE POLYSILICON, CMOS TECHNOLOGY:

±Endurance >100,000 Erase/Write Cycles

±Data Retention >10 Years

JEDEC APPROVED BYTEWIDE PIN OUT ADDRESS and DATA LATCHED ON-CHIP SOFTWARE DATA PROTECTION

PRELIMINARY DATA

28

1
PDIP28 (BS)	PLCC32 (KA)

28
1
SO28 (MS)	TSOP28 (NS)
300 mils	8 x13.4mm

Figure 1. Logic Diagram

VCC

DESCRIPTION

The M28256 and M28256-Ware 32K x8 low power Parallel EEPROM fabricatedwith STMicroelectronics proprietary double polysilicon CMOS technology.

Table 1. Signal Names

A0-A14	Address Input
DQ0-DQ7	Data Input / Output
W	Write Enable
E	Chip Enable
G	Output Enable
VCC	Supply Voltage
VSS	Ground

15	8
A0-A14	DQ0-DQ7

W M28256

E

G

VSS

AI01885

January 1999

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This is preliminaryinformation on a new product now in developmentor undergoing evaluation . Detail s are subject to change without notice.

M28256

Figure 2A. DIP Pin Connections

A14	1	28	VCC
A12	2	27	W
A7	3	26	A13
A6	4	25	A8
A5	5	24	A9
A4	6	23	A11
A3	7	22	G
A2	8	M28256	A10
		21
A1	9	20	E
A0	10	19	DQ7
DQ0	11	18	DQ6
DQ1	12	17	DQ5
DQ2	13	16	DQ4
VSS	14	15	DQ3
		AI01886

Figure 2C. SO Pin Connections

A14	1	28	VCC
A12	2	27	W
A7	3	26	A13
A6	4	25	A8
A5	5	24	A9
A4	6	23	A11
A3	7	22	G
A2	8	M28256	A10
		21
A1	9	20	E
A0	10	19	DQ7
DQ0	11	18	DQ6
DQ1	12	17	DQ5
DQ2	13	16	DQ4
VSS	14	15	DQ3
		AI01888

Figure 2B. LCC Pin Connections

	A7	A12	A14	DU	CC	W	A13
					V
A6				1	32		A8
A5							A9
A4							A11
A3							NC
A2	9		M28256				25 G
A1							A10
A0							E
NC							DQ7
DQ0				17			DQ6
	DQ1	DQ2			DQ3	DQ4	DQ5
			V	DU
			SS
							AI01887

Warning: NC = Not Connected, DU = Don't Use.

Figure 2D. TSOP Pin Connections

G	22	21	A10
A11			E
A9			DQ7
A8			DQ6
A13			DQ5
W			DQ4
VCC	28	15	DQ3
		M28256	VSS
A14	1	14
A12			DQ2
A7			DQ1
A6			DQ0
A5			A0
A4			A1
A3	7	8	A2
		AI01889

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			M28256
Table 2. Absolute Maximum Ratings (1)
Symbol	Parameter	Value	Unit
TA	Ambient Operating Temperature (2)	± 40 to 85	°C
TSTG	Storage Temperature Range	± 65 to 150	°C
VCC	Supply Voltage	± 0.3 to 6.5	V
VIO	Input/Output Voltage	± 0.3 to VCC +0.6	V
VI	Input Voltage	± 0.3 to 6.5	V
VESD	Electrostatic Discharge Voltage (Human Body model) (3)	4000	V

Notes: 1. Except for the rating ºOperating Temperature Rangeº, stresses above those listed in the Table ºAbsolute Maximum Ratingsº may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

2.Depends on range.

3.100pF through 1500Ω; MIL-STD-883C, 3015.7

Figure 3. Block Diagram

		VPP GEN	RESET
	A6-A14	ADDRESS
		LATCH
	(Page Address)
			DECODE
			X
	A0-A5	ADDRESS
		LATCH
		Y	DECODE

E G W

CONTROL LOGIC

256K ARRAY

SENSE AND DATA LATCH

I/O BUFFERS

PAGE LOAD TIMER STATUS TOGGLE BIT DATA POLLING

DQ0-DQ7

AI01697

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M28256

Table 3. Operating Modes (1)

Mode	E	G	W	DQ0 - DQ7
Read	VIL	VIL	VIH	Data Out
Write	VIL	VIH	VIL	Data In
Standby / Write Inhibit	VIH	X	X	Hi-Z
Write Inhibit	X	X	VIH	Data Out or Hi-Z
Write Inhibit	X	VIL	X	Data Out or Hi-Z
Output Disable	X	VIH	X	Hi-Z
Notes: 1. X = VIH or VIL.

DESCRIPTION (Cont'd)

The devices offer fast access time with low power dissipation and requires a 5V or 3V power supply.

The circuit has been designed to offer a flexible microcontroller interface featuring both hardware and software handshaking with Data Polling and Toggle Bit and access to a status register. The devices support a 64 byte page write operation. A Software Data Protection (SDP) is also possible using the standard JEDEC algorithm.

PIN DESCRIPTION

Addresses (A0-A14). The address inputs select an 8-bit memory location during a read or write operation.

Chip Enable (E). The chip enable input must be low to enable all read/writeoperations.When Chip Enable is high, power consumption is reduced.

Output Enable (G). The Output Enable input controls the data output buffers and is used to initiate read operations.

Data In/ Out (DQ0DQ7). Data is written to or read from the memory through the I/O pins.

Write Enable (W). The Write Enable input controls the writing of data to the memory.

OPERATIONS Write Protection

In order to prevent data corruption and inadvertent write operations; an internal VCC comparatorinhibits Write operations if VCC is below VWI (see Table 7 andTable 9).Access to the memoryin write mode is allowed after a power-up as specified in Table 7 and Table 9.

Read

The device is accessed like a static RAM. When E and G are low with W high, the data addressed is presented on the I/O pins. The I/O pins are high impedance when either G or E is high.

Write

Write operations are initiated when both W and E are low and G is high.The device supports both E and W controlled write cycles. The Address is latched by the falling edge of E or W which ever occurs last and the Data on the rising edge of E or W which ever occurs first. Once initiated the write operation is internally timed until completion and the status of the Data Polling and the Toggle Bit functions on DQ7 and DQ6 is controlled accordingly.

Page Write

Page write allows up to 64 bytes within the same page to be consecutively latched into the memory prior to initiating a programming cycle. All bytes must be located in a single page address, that is A14-A6 must be the same for all bytes; if not, the Page Write instruction is not executed. The page write can be initiated by any byte write operation.

A page write is composed of successive Write instructions which have to be sequenced with a specific period of time between two consecutive Write instructions, period of time which has to be smaller than the tWHWH value (see Table 12 and Table 13).

If this period of time exceeds the tWHWH value, the internal programmingcycle will start. Once initiated the write operation is internally timed until completion and the status of the Data Polling and the Toggle Bit functions on DQ7 and DQ6 is controlled accordingly.

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Status Register

The devices provide several Write operation status flags that can be used to minimize the application write time. These signals are available on the I/O port bits during programming cycle only.

Data Polling bit (DQ7). During the internal write cycle, any attempt to read the last byte written will produce on DQ7 the complementary value of the previously latched bit. Once the write cycle is finished the true logic value appears on DQ7 in the read cycle.

Toggle bit (DQ6). The devices offer another way for determining when the internal write cycle is completed. During the internal Erase/Write cycle, DQ6 will toggle from º0º to º1º and º1º to º0º (the first read value is º0º) on subsequent attempts to read any byte of the memory. When the internal cycle is completed the toggling will stop and the data read on DQ7-DQ0 is the addressed memory byte. The device is now accessible for a new Read or Write operation.

Page Load TimerStatus bit (DQ5). Duringa Page Write instruction, the devices expect to receive the stream of data with a minimum period of time between each data byte. This period of time (tWHWH) is defined by the on-chip Page Load timer which running/overflow status is available on DQ5. DQ5 Low indicates that the timer is running, DQ5 High indicates the time-out after which the internal write cycle will start.

Figure 4. Status Bit Assignment

DQ7	DQ6		DQ5	DQ4	DQ3	DQ2	DQ1	DQ0
DP		TB	PLTS	X	X	X	X	X
DP	=	Data Polling
TB	=	Toggle Bit
PLTS	=	Page Load Timer Status

M28256

Software Data Protection

The devices offer a software controlled write protection facility that allows the user to inhibit all write modes to the device. This can be useful in protecting the memory from inadvertent write cycles that may occur due to uncontrolledbus conditions.

The devices are shipped as standardin the ºunprotectedº state meaning that the memory contents can be changed as required by the user. After the Software Data Protection enable algorithm is issued, the device enters the ºProtect Modeº of operation where no further write commands have any effect on the memory contents.

The devices remain in this mode until a valid Software Data Protection (SDP) disable sequence is received whereby the device reverts to its ºunprotectedº state. The Software Data Protection is fully non-volatile and is not changed by power on/off sequences. To enable the Software Data Protection (SDP) the device requires the user to write (with a Page Write addressing three specific data bytes to three specific memorylocations,each location in a different page) as per Figure 6. Similarly to disable the Software Data Protection the user has to write specific data bytes into six different locations as per Figure 5 (with a Page Write adressing different bytes in different pages).

Thiscomplexseries ensures that the userwill never enable or disable the Software Data Protection accidentally.

To write into the devices when SDP is set, the sequence shown in Figure 6 must be used. This sequence provides an unlock key to enable the write action, and at the same time SDP continues to be set.

An extension to this is where SDP is required to be set, and data is to be written.

Using the same sequence as above, the data can be written and SDP is set at the same time, giving both these actions in the same Write cycle (tWC).

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M28256

Figure 5. Software Data Protection Enable Algorithm and Memory Write

			SDP	SDP
			Set	not Set
	WRITE AAh in		WRITE AAh in
	Address 5555h		Address 5555h
Page	WRITE 55h in		WRITE 55h in
Write
	Address 2AAAh		Address 2AAAh
Instruction
		Page
	WRITE A0h in	Write	WRITE A0h in
	Address 5555h	Instruction	Address 5555h
				WRITE
	SDP is set			is enabled
			WRITE Data to
			be Written in
			any Address
			Write	Write Data
	SDP ENABLE ALGORITHM		in Memory	+
				SDP Set
				after tWC
				AI01698B

Figure 6. Software Data Protection Disable Algorithm

WRITE AAh in

Address 5555h

WRITE 55h in

Address 2AAAh

WRITE 80h in

Page Address 5555h

Write

Instruction

WRITE AAh in

Address 5555h

WRITE 55h in

Address 2AAAh

WRITE 20h in

Address 5555h

Unprotected State after

tWC (Write Cycle time)

AI01699B

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M28256

Table 4. AC Measurement Conditions

Input Rise and Fall Times	≤ 20ns
Input Pulse Voltages (M28256)	0.4V to 2.4V
Input Pulse Voltages (M28256-W)	0V to VCC ±0.3V
Input and Output Timing Ref. Voltages (M28256)	0.8V to 2.0V
Input and Output Timing Ref. Voltages (M28256-W)	0.5 VCC

Figure 7. AC Testing Input Output Waveforms		Figure 8. AC Testing Equivalent Load Circuit
4.5V to 5.5V Operating Voltage
2.4V	2.0V
0.4V	0.8V		IOL
		DEVICE
		UNDER			OUT
2.7V to 3.6V Operating Voltage		TEST
VCC ± 0.3V			IOH		CL = 100pF
	0.5 VCC
0V
	AI02101B	CL includes JIG capacitance
					AI02102B
Table 5. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol	Parameter	Test Condition	Min	Max	Unit
CIN	Input Capacitance	VIN = 0V		6	pF
COUT	Output Capacitance	VOUT = 0V		12	pF

Note: 1. Sampled only, not 100% tested.

Table 6. Read Mode DC Characteristics for M28256

(TA = 0 to 70°C or ±40 to 85°C; VCC = 4.5V to 5.5V)

Symbol	Parameter	Test Condition	Min	Max	Unit
ILI	Input Leakage Current	0V ≤ VIN ≤ VCC		10	μA
ILO	Output Leakage Current	0V ≤ VIN ≤ VCC		10	μA
(1)	Supply Current (TTL inputs)	E = VIL, G = VIL , f = 5 MHz		30	mA
ICC
	Supply Current (CMOS inputs)	E = VIL, G = VIL , f = 5 MHz		25	mA
(1)	Supply Current (Standby) TTL	E = VIH		1	mA
ICC1
(1)	Supply Current (Standby) CMOS	E > VCC ±0.3V		100	μA
ICC2
VIL	Input Low Voltage		± 0.3	0.8	V
VIH	Input High Voltage		2	VCC + 0.5	V
VOL	Output Low Voltage	IOL = 2.1 mA		0.4	V
VOH	Output High Voltage	IOH = ±400 μA	2.4

Note: 1. All I/O's open circuit.

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