ST M27W801 User Manual

M27W801-100B6TR

M27W801

8 Mbit (1Mb x8) Low Voltage UV EPROM and OTP EPROM

■2.7V to 3.6V SUPPLY VOLTAGE in READ OPERATION

■ACCESS TIME:

±80ns at VCC = 3.0V to 3.6V

±100ns at VCC = 2.7V to 3.6V

■PIN COMPATIBLE with M27C801

■LOW POWER CONSUMPTION:

±15μA max Standby Current

±15mA max Active Current at 5MHz

■PROGRAMMING TIME 50μs/byte

■HIGH RELIABILITY CMOS TECHNOLOGY

±2,000V ESD Protection

±200mA Latchup Protection Immunity

■ELECTRONIC SIGNATURE

±Manufacturer Code: 20h

±Device Code: 42h

DESCRIPTION

The M27W801 is a low voltage 8 Mbit EPROM offered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems requiring large data or program storage and is organized as 1,048,576 by 8 bits.

The M27W801 operates in the read mode with a supply voltage as low as 2.7V at ±40 to 85°C temperature range. The decrease in operating power allows either a reduction of the size of the battery or an increase in the time between battery recharges.

The FDIP32W (window ceramic frit-seal package) has a transparent lids which allow the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure.

For applications where the content is programmed only one time and erasure is not required, the M27W801 is offered in PDIP32, PLCC32 and TSOP32 (8 x 20 mm) packages.

32	32
1	1
FDIP32W (F)	PDIP32 (B)

PLCC32 (K)	TSOP32 (N)
	8 x 20 mm

Figure 1. Logic Diagram

	VCC
20	8
A0-A19	Q0-Q7

E M27W801

GVPP

VSS

AI02363

April 2000

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M27W801

Figure 2A. DIP Connections

Figure 2B. PLCC Connections

A19	1	32	VCC
A16	2	31	A18
A15	3	30	A17
A12	4	29	A14
A7	5	28	A13
A6	6	27	A8
A5	7	26	A9
A4	8	M27W801 25	A11
A3	9	24	GVPP
A2	10	23	A10
A1	11	22	E
A0	12	21	Q7
Q0	13	20	Q6
Q1	14	19	Q5
Q2	15	18	Q4
VSS	16	17	Q3
		AI02671

Figure 2C. TSOP Connections

A11	1		32	GVPP
A9				A10
A8				E
A13				Q7
A14				Q6
A17				Q5
A18				Q4
VCC	8	M27W801	25	Q3
A19	9	(Normal)	24	VSS
A16				Q2
A15				Q1
A12				Q0
A7				A0
A6				A1
A5				A2
A4	16		17	A3
			AI02366

	A12	A15	A16	A19	CC	A18	A17
					V
A7				1	32			A14
A6								A13
A5								A8
A4								A9
A3	9		M27W801				25	A11
A2								GVPP
A1								A10
A0								E
Q0				17				Q7
	Q1	Q2	SS Q3		Q4	Q5	Q6
			V
								AI02365

Table 1. Signal Names

A0-A19	Address Inputs
Q0-Q7	Data Outputs
E	Chip Enable
GVPP	Output Enable / Program Supply
VCC	Supply Voltage
VSS	Ground

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M27W801

Table 2. Absolute Maximum Ratings (1)

Symbol

TA

TBIAS

TSTG

VIO (2)

VCC

VA9 (2)

VPP

Parameter	Value	Unit
Ambient Operating Temperature (3)	±40 to 125	°C
Temperature Under Bias	±50 to 125	°C
Storage Temperature	±65 to 150	°C
Input or Output Voltage (except A9)	±2 to 7	V
Supply Voltage	±2 to 7	V
A9 Voltage	±2 to 13.5	V
Program Supply Voltage	±2 to 14	V

Note: 1. Except for the rating ºOperating Temperature Rangeº, stresses above those listed in the Table ºAbsolute Maximum Ratingsº may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

2.Minimum DC voltage on Input or Output is ±0.5V with possible undershoot to ±2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.

3.Depends on range.

Table 3. Operating Modes

Mode	E	GVPP	A9	Q7-Q0
Read	VIL	VIL	X	Data Out
Output Disable	VIL	VIH	X	Hi-Z
Program	VIL Pulse	VPP	X	Data In
Program Inhibit	VIH	VPP	X	Hi-Z
Standby	VIH	X	X	Hi-Z
Electronic Signature	VIL	VIL	VID	Codes
Note: X = VIH or VIL, VID = 12V ± 0.5V.

Table 4. Electronic Signature

Identifier	A0	Q7	Q6	Q5	Q4	Q3	Q2	Q1	Q0	Hex Data
Manufacturer's Code	VIL	0	0	1	0	0	0	0	0	20h
Device Code	VIH	0	1	0	0	0	0	1	0	42h

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M27W801

Table 5. AC Measurement Conditions

	High Speed	Standard
Input Rise and Fall Times	≤ 10ns	≤ 20ns (10% to 90%)
Input Pulse Voltages	0 to 3V	0.4V to 2.4V
Input and Output Timing Ref. Voltages	1.5V	0.8V and 2V

Figure 3. AC Testing Input Output Waveform	Figure 4. AC Testing Load Circuit
	1.3V
High Speed
3V	1N914
1.5V
0V	3.3kΩ
	DEVICE
Standard	UNDER	OUT
	TEST
2.4V	CL
2.0V
0.8V

0.4V

CL = 30pF for High Speed

AI01822

CL = 100pF for Standard
CL includes JIG capacitance	AI01823B

Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz)

Symbol	Parameter	Test Condition	Min	Max	Unit
CIN	Input Capacitance	VIN = 0V		6	pF
COUT	Output Capacitance	VOUT = 0V		12	pF

Note: 1. Sampled only, not 100% tested.

DEVICE OPERATION

The operating modes of the M27W801 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for GVPP and 12V on A9 for Electronic Signature and Margin Mode Set or Reset.

Read Mode

The M27W801 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time

(tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of tGLQV from the falling edge of G, assuming that E has been low and the addresses have been sta-

ble for at least tAVQV-tGLQV.

Standby Mode

The M27W801 has a standby mode which reduces the supply current from 15mA to 20μA with low voltage operation VCC ≤ 3.6V, see Read Mode DC Characteristics table for details. The M27W801 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the GVPP input.

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M27W801

Table 7. Read Mode DC Characteristics (1)

(TA = ±40 to 85 °C; VCC = 2.7V to 3.6V; VPP = VCC)

Symbol

Parameter

Test Condition

Min

Max

Unit

ILI	Input Leakage Current
ILO	Output Leakage Current
ICC	Supply Current
ICC1	Supply Current (Standby) TTL
ICC2	Supply Current (Standby) CMOS
IPP	Program Current
VIL	Input Low Voltage
VIH (2)	Input High Voltage
VOL	Output Low Voltage
VOH	Output High Voltage TTL

0V ≤ VIN ≤ VCC		±10	μA
0V ≤ VOUT ≤ VCC		±10	μA
E = VIL, GVPP = VIL, IOUT = 0mA,		15	mA
f = 5MHz, VCC ≤ 3.6V
E = VIH		1	mA
E > VCC ± 0.2V, VCC ≤ 3.6V		15	μA
VPP = VCC		10	μA
	±0.6	0.2 VCC	V
	0.7 VCC	VCC + 0.5	V
IOL = 2.1mA		0.4	V
IOH = ±1mA	3.6		V

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Maximum DC voltage on Output is VCC +0.5V.

Two Line Output Control

Because EPROMs are usually used in larger memory arrays, the product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows:

a.the lowest possible memory power dissipation,

b.complete assurance that output bus contention will not occur.

For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device.

System Considerations

The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output. The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. It is recommended that a 0.1μF ceramic capacitor be used on every device between VCC and VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7μF bulk electrolytic capacitor should be used between VCC and VSS for every eight devices. The bulk capacitor should be located near the power supply connection point. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces.

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