ST M27W512 User Manual

M27W512-100B6TR

M27W512

512 Kbit (64Kb x8) Low Voltage UV EPROM and OTP EPROM

■2.7V to 3.6V SUPPLY VOLTAGE in READ OPERATION

■ACCESS TIME:

±70ns at VCC = 3.0V to 3.6V

±80ns at VCC = 2.7V to 3.6V

■PIN COMPATIBLE with M27C512

■LOW POWER CONSUMPTION:

±15μA max Standby Current

±15mA max Active Current at 5MHz

■PROGRAMMING TIME 100μs/byte

■HIGH RELIABILITY CMOS TECHNOLOGY

±2,000V ESD Protection

±200mA Latchup Protection Immunity

■ELECTRONIC SIGNATURE

±Manufacturer Code: 20h

±Device Code: 3Dh

DESCRIPTION

The M27W512 is a low voltage 512 Kbit EPROM offered in the two range UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems and is organized as 65,536 by 8 bits.

The M27W512 operates in the read mode with a supply voltage as low as 2.7V at ±40 to 85°C temperature range. The decrease in operating power allows either a reduction of the size of the battery or an increase in the time between battery recharges.

The FDIP28W (window ceramic frit-seal package) has transparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure.

For applications where the content is programmed only one time and erasure is not required, the M27W512 is offered in PDIP28, PLCC32 and TSOP28 (8 x 13.4 mm) packages.

28	28
1	1
FDIP28W (F)	PDIP28 (B)

PLCC32 (K)	TSOP28 (N)
	8 x 13.4 mm

Figure 1. Logic Diagram

	VCC
16	8
A0-A15	Q0-Q7

E M27W512

GVPP

VSS

AI01584

March 2000

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M27W512

Figure 2A. DIP Connections

A15	1	28	VCC
A12	2	27	A14
A7	3	26	A13
A6	4	25	A8
A5	5	24	A9
A4	6	23	A11
A3	7	22	GVPP
A2	8	M27W512 21	A10
A1	9	20	E
A0	10	19	Q7
Q0	11	18	Q6
Q1	12	17	Q5
Q2	13	16	Q4
VSS	14	15	Q3
		AI02679

Figure 2C. TSOP Connections

GVPP	22	21	A10
A11			E
A9			Q7
A8			Q6
A13			Q5
A14			Q4
VCC	28	15	Q3
		M27W512	VSS
A15	1	14
A12			Q2
A7			Q1
A6			Q0
A5			A0
A4			A1
A3	7	8	A2
		AI01586

Figure 2B. LCC Connections

	A7	A12	A15	DU	CC	A14	A13
					V
A6				1	32		A8
A5							A9
A4							A11
A3							NC
A2	9		M27W512				25 GVPP
A1							A10
A0							E
NC							Q7
Q0				17			Q6
			SS
	Q1	Q2		DU	Q3	Q4	Q5
			V
							AI01585

Table 1. Signal Names

A0-A15	Address Inputs
Q0-Q7	Data Outputs
E	Chip Enable
GVPP	Output Enable / Program Supply
VCC	Supply Voltage
VSS	Ground
NC	Not Connected Internally
DU	Don't Use

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M27W512

Table 2. Absolute Maximum Ratings (1)

Symbol

TA

TBIAS

TSTG

VIO (2)

VCC

VA9 (2)

VPP

Parameter	Value	Unit
Ambient Operating Temperature (3)	±40 to 125	°C
Temperature Under Bias	±50 to 125	°C
Storage Temperature	±65 to 150	°C
Input or Output Voltage (except A9)	±2 to 7	V
Supply Voltage	±2 to 7	V
A9 Voltage	±2 to 13.5	V
Program Supply Voltage	±2 to 14	V

Note: 1. Except for the rating ºOperating Temperature Rangeº, stresses above those listed in the Table ºAbsolute Maximum Ratingsº may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

2.Minimum DC voltage on Input or Output is ±0.5V with possible undershoot to ±2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.

3.Depends on range.

Table 3. Operating Modes

Mode	E	GVPP	A9	Q7-Q0
Read	VIL	VIL	X	Data Out
Output Disable	VIL	VIH	X	Hi-Z
Program	VIL Pulse	VPP	X	Data In
Program Inhibit	VIH	VPP	X	Hi-Z
Standby	VIH	X	X	Hi-Z
Electronic Signature	VIL	VIL	VID	Codes
Note: X = VIH or VIL, VID = 12V ± 0.5V.

Table 4. Electronic Signature

Identifier	A0	Q7	Q6	Q5	Q4	Q3	Q2	Q1	Q0	Hex Data
Manufacturer's Code	VIL	0	0	1	0	0	0	0	0	20h
Device Code	VIH	0	0	1	1	1	1	0	1	3Dh

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M27W512

Table 5. AC Measurement Conditions

	High Speed	Standard
Input Rise and Fall Times	≤ 10ns	≤ 20ns
Input Pulse Voltages	0 to 3V	0.4V to 2.4V
Input and Output Timing Ref. Voltages	1.5V	0.8V and 2V

Figure 3. AC Testing Input Output Waveform	Figure 4. AC Testing Load Circuit
	1.3V
High Speed
3V	1N914
1.5V
0V	3.3kΩ
	DEVICE
Standard	UNDER	OUT
	TEST
2.4V	CL
2.0V
0.8V

0.4V

CL = 30pF for High Speed

AI01822

CL = 100pF for Standard
CL includes JIG capacitance	AI01823B

Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz)

Symbol	Parameter	Test Condit ion	Min	Max	Unit
CIN	Input Capacitance	VIN = 0V		6	pF
COUT	Output Capacitance	VOUT = 0V		12	pF

Note: 1. Sampled only, not 100% tested.

DEVICE OPERATION

The modes of operations of the M27W512 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for GVPP and 12V on A9 for Electronic Signature.

Read Mode

The M27W512 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time

(tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of tGLQV from the falling edge of G, assuming that E has been low and the addresses have been sta-

ble for at least tAVQV-tGLQV.

Standby Mode

The M27W512 has a standby mode which reduces the supply current from 15mA to 15μA with low voltage operation VCC ≤ 3.6V, see Read Mode DC

Characteristics table for details. The M27W512 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the GVPP input.

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M27W512

Table 7. Read Mode DC Characteristics (1)

(TA = ±40 to 85°C; VCC = 2.7V to 3.6V; VPP = VCC)

Symbol	Parameter	Test Condition	Min	Max	Unit
ILI	Input Leakage Current	0V ≤ VIN ≤ VCC		±10	μA
ILO	Output Leakage Current	0V ≤ VOUT ≤ VCC		±10	μA
ICC		E = VIL, G = VIL,
	Supply Current	IOUT = 0mA, f = 5MHz		15	mA
		VCC ≤ 3.6V
ICC1	Supply Current (Standby) TTL	E = VIH		1	mA
ICC2	Supply Current (Standby) CMOS	E > VCC ± 0.2V,		15	μA
		VCC ≤ 3.6V
IPP	Program Current	VPP = VCC		10	μA
VIL	Input Low Voltage		±0.6	0.2 VCC	V
VIH (2)	Input High Voltage		0.7 VCC	VCC + 0.5	V
VOL	Output Low Voltage	IOL = 2.1mA		0.4	V
VOH	Output High Voltage TTL	IOH = ±1mA	2.4		V

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Maximum DC voltage on Output is VCC +0.5V.

Two Line Output Control

Because EPROMs are usually used in larger memory arrays, the product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows:

a.the lowest possible memory power dissipation,

b.complete assurance that output bus contention will not occur.

For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device.

System Considerations

The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output.

The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. It is recommended that a 0.1μF ceramic capacitor be used on every device between VCC and VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7μF bulk electrolytic capacitor should be used between VCC and VSS for every eight devices. The bulk capacitor should be located near the power supply connection point.The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces.

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