ST M27W402 User Manual
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M27W402
4 Mbit (256Kb x16) Low Voltage UV EPROM and OTP EPROM
■ 2.7V to 3.6V SUPPLY VOLTAGEin READ
OPERATION
■ ACCESS TIME:
–80nsatVCC= 3.0V to 3.6V
– 100ns at VCC= 2.7V to 3.6V
■ PIN COMPATIBLE with M27C4002
■ LOW POWERCONSUMPTION:
–15µA max Standby Current
– 15mA max Active Current at 5MHz
■ PROGRAMMING TIME 100µs/word
■ HIGHRELIABILITY CMOS TECHNOLOGY
– 2,000V ESD Protection
– 200mA Latchup Protection Immunity
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Device Code: 0044h
40
1
FDIP40W (F) PDIP40 (B)
PLCC44 (K) TSOP40 (N)
Figure 1. Logic Diagram
40
1
10 x 20 mm
DESCRIPTION
The M27W402 is a low voltage 4 Mbit EPROM offered in the two range UV (Ultra Violet Erase) and
OTP (one time programmable). It is ideally suited
for microprocessorsystems requiringlarge data or
program storage and is organised as 262,144 by
16 bits.
The M27W402 operates in the read mode with a
supply voltageas low as2.7V at –40 to 85°C temperature range. The decrease in operating power
allows either a reduction of the size of the battery
or an increase in the time between battery recharges.
The FDIP40W (window ceramic frit-seal package)
has a transparent lids which allow the user to expose thechip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the
device by following the programming procedure.
For applications wherethe content is programmed
only one time and erasure is not required, the
M27W402 is offered in PDIP40, PLCC44 and
TSOP40 (10 x 20 mm) packages.
V
18
A0-A17 Q0-Q15
E
G
V
CC
M27W402
V
SS
PP
16
AI01863
1/15March 2000
M27W402
Figure 2A. DIP Connections
V
1
PP
2
Q15
3
4
Q14
5
Q13
Q12
6
Q11
7
Q10
8
Q9
9
Q8
10
V
SS
Q7
Q6
Q5
Q4
Q3
Q2
Q0
M27W402
11
12
13
14
15
16
17
18
19
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
2120
AI02672
V
CC
A17E
A16
A15
A14
A13
A12
A11
A10
A9
V
SS
A8
A7
A6
A5
A4
A3
A2Q1
A1
A0G
Figure 2B. LCC Connections
Q13
Q14
Q15
CC
NC
VPPE
1
44
A17
V
Q12
Q11
Q10
Q9 A10
Q8
V
SS
12
M27W402
NC
Q6
Q5
Q4
23
G
A0
Q3
Q2
Q1
Q0
NC
A1
A16
A2
A15
A3
A14
34
A4
A13
A12
A11
A9
V
SS
NC
A8Q7
A7
A6
A5
AI01865
Figure 2C. TSOP Connections
A9
A10
A11
A12 A6
A13
A14
A15
A16
A17
V
CC
V
PP
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
1
M27W402
10
(Normal)
11
E
20 21
40
31
30
AI01866
V
SS
A8
A7
A5
A4
A3
A2
A1
A0
G
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
V
SS
Table 1. Signal Names
A0-A17 Address Inputs
Q0-Q15 Data Outputs
E Chip Enable
G Output Enable
V
PP
V
CC
V
SS
NC Not Connected Internally
Program Supply
Supply Voltage
Ground
2/15
M27W402
Table 2. Absolute Maximum Ratings
(1)
Symbol Parameter Value Unit
T
A
T
BIAS
T
STG
(2)
V
IO
V
CC
(2)
V
A9
V
PP
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute MaximumRatings” may
cause permanent damage to the device. These are stress ratings onlyand operation ofthe device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure toAbsolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SUREProgram and otherrelevant quality documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
3. Depends on range.
Ambient Operating Temperature
Temperature Under Bias –50 to 125 °C
Storage Temperature –65 to 150 °C
Input or Output Voltage (except A9) –2 to 7 V
Supply Voltage –2 to 7 V
A9 Voltage –2 to 13.5 V
Program Supply Voltage –2 to 14 V
+0.5V with possible overshoot to VCC+2V for a period less than 20ns.
CC
(3)
–40 to 85 °C
Table 3. Operating Modes
Mode E G A9
Read
Output Disable V
Program
V
Verify V
Program Inhibit
Standby
Electronic Signature
Note: X = VIHor VIL,VID= 12V ± 0.5V.
V
IL
IL
Pulse V
IL
IH
V
IH
V
IH
V
IL
V
IL
V
IH
IH
V
IL
V
IH
X
XV
X
XVPPData Out
X
XX
V
IL
V
ID
V
PP
V
or V
CC
SS
or V
CC
SS
V
PP
V
PP
V
or V
CC
SS
V
CC
Q15-Q0
Data Out
Hi-Z
Data In
Hi-Z
Hi-Z
Codes
Table 4. Electronic Signature
Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data
Manufacturer’s Code
Device Code
Note: Outputs Q15-Q8 are set to ’0’.
V
IL
V
IH
00100000 20h
01000100 44h
3/15
M27W402
Table 5. AC Measurement Conditions
High Speed Standard
Input Rise and Fall Times ≤ 10ns ≤ 20ns
Input Pulse Voltages 0 to 3V 0.4V to 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V
Figure 3. AC Testing Input Output Waveform
High Speed
3V
1.5V
0V
Standard
2.4V
0.4V
Table 6. Capacitance
Symbol Parameter Test Condition Min Max Unit
C
IN
C
OUT
Note: Sampled only, not 100% tested.
Input Capacitance
Output Capacitance V
(1)
(TA=25°C, f = 1 MHz)
2.0V
0.8V
AI01822
Figure 4. AC Testing Load Circuit
1.3V
1N914
3.3kΩ
DEVICE
UNDER
TEST
C
L
CL= 30pF for HighSpeed
CL= 100pF for Standard
CLincludes JIG capacitance
V
=0V
IN
=0V 12 pF
OUT
6pF
OUT
AI01823B
DEVICE OPERATION
The operation modes of theM27W402 are listed in
the Operating Modes table. A single power supply
is required in the read mode. All inputs are TTL
levels exceptfor VPPand 12Von A9 for Electronic
Signature.
Read Mode
The M27W402 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable(G) is the outputcontrol and should
be used to gate data to the output pins, independent of device selection. Assuming that the ad-
4/15
dresses are stable, the address access time
(t
) is equal to the delay from E to output
AVQV
(t
). Data is availableatthe outputaftera delay
ELQV
of t
from the falling edge of G, assuming that
GLQV
E has been lowand the addresses havebeen stable for at least t
AVQV-tGLQV
.
Standby Mode
The M27W402 has a standby mode which reduces the supply current from 15mA to 15µAwith low
voltage operation VCC≤ 3.6V, see Read ModeDC
Characteristics table for details. The M27W402 is
placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the G input.
M27W402
Table 7. Read Mode DC Characteristics
(1)
(TA= –40to 85°C; VCC= 2.7V to 3.6V; VPP=VCC)
Symbol Parameter Test Condition Min Max Unit
I
I
I
CC
I
CC1
I
CC2
I
V
V
IH
V
V
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
Input Leakage Current
LI
Output Leakage Current
LO
Supply Current
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
PP
Input Low Voltage –0.6
IL
(2)
Input High Voltage
Output Low Voltage
OL
Output High Voltage TTL
OH
2. Maximum DC voltage on Output is V
CC
+0.5V.
I
OUT
0V ≤ V
0V ≤ V
E=V
E>V
I
≤ V
IN
CC
≤ V
OUT
CC
,G=VIL,
IL
= 0mA, f = 5MHz,
≤ 3.6V
V
CC
E=V
IH
– 0.2V,
CC
V
≤ 3.6V
CC
V
PP=VCC
I
= 2.1mA
OL
= –400µA
OH
±10 µA
±10 µA
15 mA
1mA
15 µA
10 µA
0.2 V
CC
0.7 V
CCVCC
2.4 V
+ 0.5
0.4 V
V
V
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, the product features a 2 line control function whichaccommodates the use of multiple memory connection.
The two line control function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, Eshould be decodedand usedas the primary device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system controlbus. This ensures that all deselected memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs requirecareful decoupling of the
devices. The supply current, ICC, has three segments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the fallingand rising edges of E. Themagnitude of
the transient current peaks is dependent on the
output capacitive and inductive loading of the device. The associated transient voltage peaks can
be suppressed by complying withthe two line output control and by properly selected decoupling
capacitors.It isrecommended that a 0.1µF ceramic capacitor be used on everydevice between V
CC
and VSS. This should be a high frequency capacitor of low inherent inductance and should be
placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be
used between VCCand VSSfor every eight devices. The bulk capacitor should be located near the
power supply connection point.Thepurpose of the
bulk capacitor is to overcome the voltage drop
caused bythe inductive effects of PCB traces.
5/15
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