ST M27W201 User Manual
M27W201
2 Mbit (256Kb x 8) Low Voltage UV EPROM and OTP EPROM
■ 2.7V to 3.6V LOW VOLTAGE in READ
OPERATION
■ ACCESS TIME:
–70nsatV
–80nsatV
■ PIN COMPATIBLE with M27C2001
■ LOW POWER CONSUMPTION:
=3.0Vto3.6V
CC
=2.7Vto3.6V
CC
– 15µA m ax Standby Current
– 15mA max Active Current at 5MHz
■ PROGRAMMING TIME 100µs/byte
■ HIGH RELIABILITY CMOS TECHNOLOGY
– 2,000V ESD Protection
– 200mA Latch up Protection Immunity
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 61h
32
1
FDIP32W (F) PDIP32 (B)
PLCC32 (K) TSOP32 (N)
32
1
8 x 20 mm
DESCRIPTION
The M27W201 is a low voltage 2 Mbit EPRO M offered in the two range UV (ultra violet erase) and
OTP (one time programmable). It is ideally suited
for microprocessor systemsrequiring large data or
program storage and is organised as262,144 by 8
bits.
The M27W201 operates in the read mode with a
supply voltage as low as 2.7V at –40 t o 85°C temperature range. The decrease in operating power
allows either a reduction of the size of the battery
or an increase in the time between battery recharges.
The FDIP32W (window ceramic frit-seal package)
has a transparent lid which allows the user to expose the chip to ultraviolet light t o erase the bit pattern. A new pattern can then be written to the
device by following the programming procedu re .
For application where the content is programmed
only one time and erasure is not required, the
M27W201 is offered in PDIP32, PLCC32 and
TSOP32 (8 x 20mm and 8 x 14mm) packages.
TSOP32 (NZ)
8 x 14 mm
Figure 1. Logic Diagram
V
CC
18
A0-A17
P
E
G
M27W201
V
SS
V
PP
8
Q0-Q7
AI01359
1/16October 2001
M27W201
Figure 2A. DIP Connections
V
1
PP
2
A15
3
A12
4
5
A7
6
A6
7
A5
8
A4
A3
A2
A1
A0
Q0
Q2
SS
M27W201
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
AI02675
V
CC
PA16
A17
A14
A13
A8
A9
A11
G
A10
E
Q7
Q6
Q5Q1
Q4
Q3V
Figure 2B. LCC Connections
A16
A7
A6
A5
A4
A3
A2
A1
A0
Q0
A12
9
Q1
VPPV
A15
1
32
M27W201
17
Q2
Q3
SS
V
Q4
CC
P
Q5
A17
25
Q6
A14
A13
A8
A9
A11
G
A10
E
Q7
AI01360
Figure 2C. TSOP Connections
A11 G
A9
A8
A13
A14
A17
V
CC
V
PP
A16
A15
A12
A7
A6
A5
A4 A3
1
P
8
M27W201
9
16 17
32
25
24
AI01361
A10
E
Q7
Q6
Q5
Q4
Q3
V
SS
Q2
Q1
Q0
A0
A1
A2
Table 1. Signal Names
A0-A17 Address Inputs
Q0-Q7 Data Outputs
E
G
P
V
PP
V
CC
V
SS
Chip Enable
Output Enable
Program
Program Supply
Supply Voltage
Ground
2/16
M27W201
Table 2. Absolute Maximum Ratings
(1)
Symbol Parameter Value Unit
T
A Ambient Operating Temperature
T
BIAS
T
STG
(2)
V
IO
V
CC
(2)
V
A9
V
PP
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditionsfor extended periodsmayaffect device reliability.Refer also to theSTMicroelectronics SURE Programand other relevant quality documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
3. Depends on range.
Temperature Under Bias –50 to 125 °C
Storage Temperature –65 to 150 °C
Input or Output Voltage (except A9) –2 to 7 V
Supply Voltage –2 to 7 V
A9 Voltage –2 to 13.5 V
Program Supply Voltage –2 to 14 V
+0.5VwithpossibleovershoottoVCC+2V for a period less than 20ns.
CC
(3)
–40 to 125 °C
Table 3. Operating Modes
Mode E
Read
Output Disable
Program
Verify
Program Inhibit
Standby
Electronic Signature
Note: X = VIHor VIL,VID= 12V ± 0.5V.
G P A9
V
IL
V
IL
V
IL
V
IL
V
IH
V
IH
V
IL
V
IL
V
IH
V
IH
V
IL
XX
XX
VILPulse
V
IH
X
X
XXX
XXX
V
IL
V
IH
V
ID
V
PP
V
or V
CC
SS
V
or V
CC
SS
V
PP
V
PP
V
PP
V
or V
CC
SS
V
CC
Q7-Q0
Data Out
Hi-Z
Data In
Data Out
Hi-Z
Hi-Z
Codes
Table 4. Electronic Signature
Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data
Manufacturer’s Code
Device Code
V
IL
V
IH
00100000 20h
01100001 61h
3/16
M27W201
Table 5. AC M easurement Conditions
High Speed Standard
Input Rise and Fall Times ≤ 10ns ≤ 20ns
Input Pulse Voltages 0 to 3V 0.4V to 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V
Figure 3. AC Testing Input Output Waveform
High Speed
3V
1.5V
0V
Standard
2.4V
0.4V
Table 6. Capacitance
Symbol Parameter Test Condition Min Max Unit
C
IN
C
OUT
Note: 1. Sampled only, not 100% tested.
(1)
(TA=25°C,f=1MHz)
Input Capacitance
Output Capacitance
2.0V
0.8V
AI01822
Figure 4. AC Testing Load Circuit
1.3V
DEVICE
UNDER
TEST
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
V
=0V
IN
V
=0V
OUT
1N914
3.3kΩ
CL
6pF
12 pF
OUT
AI01823B
DEVICE OPERATION
Theoperating modes of the M27W201 are l isted in
the Operating Modes table. A s ingle power supply
is required in the read mode. All inputs are TTL
levels except for V
and 12V on A9 for Electronic
PP
Signature.
Read Mode
The M27W201 has two control functions, both of
which must be logicall y active in order to obtain
data at the outputs. Chip Enable (E
) is the power
control and should be used for device selection.
Output Enable (G
) is the output control and should
be used to gate dat a to the out put pi ns , ind ependent of device selection. Assum ing that the addresses are s ta ble, the address access time
4/16
(t
) is equal to the delay from E to output
AVQV
(t
).Data is available at the output after a delay
ELQV
of t
E
ble for at least t
from the falling edge of G, assuming that
GLQV
has been l ow an d the address es have been sta-
AVQV-tGLQV
.
Standby Mode
The M27W201 has a st andby mode which reduces the supply current from 15mA to 15µA with low
voltage operation V
≤ 3.6V, see Read Mode DC
CC
Characteristics table for details.The M27W201 is
placed in the standby mode by applying a CMOS
high signal to the E
input. When in the standby
mode, the outp uts are in a high impedance state,
independent of the G
input.
M27W201
Table 7. Read Mode DC Char acteri stics
(1)
(TA= –40 to 85 °C; VCC=2.7Vto3.6V;VPP=VCC)
Symbol Parameter Test Condition Min Max Unit
I
I
LO
I
CC
I
CC
I
CC
I
PP
V
V
IH
V
V
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
Input Leakage Current
LI
Output Leakage Current
Supply Current
1
Supply Current (Standby) TTL
2
Supply Current (Standby) CMOS
Program Current
Input Low Voltage –0.6
IL
(2)
Input High Voltage
Output Low Voltage
OL
Output High Voltage TTL
OH
2. Maximum DC voltage on Output is V
CC
+0.5V.
I
OUT
0V ≤ V
0V ≤ V
E
E
I
OH
≤ V
IN
CC
≤ V
OUT
=VIL,G=VIL,
=0mA,f=5MHz
V
CC
E =V
>VCC– 0.2V
V
CC
V
PP=VCC
I
= 2.1mA
OL
= –400µA
CC
≤ 3.6V
IH
≤ 3.6V
±10 µA
±10 µA
15 mA
1mA
15 µA
10 µA
0.2 V
CC
0.7 V
CCVCC
2.4 V
+ 0.5
0.4 V
V
V
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E
ry device selecting function, while G
should be decoded and used as the prima-
should be
made a common connection to all devices in the
array and connected to the READ
line from the
system control bus. This ensures that all deselected memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, I
, has three seg-
CC
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E
. The magnitude of
the transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output.
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic
capacitor be used on every device between V
CC
and VSS. This should be a high frequency capacitor of low inherent inductance and should be
placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be
used between V
and VSSfor every eight devic-
CC
es. The bulk capacitor should be located near the
power supply connection point.The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
5/16
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