ST M27V401 User Manual
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4 Mbit (512Kb x8) Low Voltage UV EPROM and OTP EPROM
■ LOW VOLTAGEREAD OPERATION:
3V to 3.6V
■ FAST ACCESS TIME: 120ns
■ LOW POWER CONSUMPTION:
– Active Current15mA at 5MHz
– Standby Current 20µA
■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V
■ PROGRAMMING TIME: 100µs/byte (typical)
■ ELECTRONIC SIGNATURE
– Manufacturer Code:20h
– Device Code: 41h
M27V401
32
1
FDIP32W (F) PDIP32 (B)
32
1
DESCRIPTION
The M27V401 is a low voltage 4 Mbit EPROM offered in the two range UV (ultra violet erase) and
OTP (one time programmable). It is ideally suited
for microprocessorsystems requiringlarge data or
program storageand is organised as 524,288 by8
bits.
The M27V401 operates in the read mode with a
supply voltage as low as 3V. The decrease in operating power allows either a reduction of the size
of the battery or an increase in the time between
battery recharges.
The FDIP32W (window ceramic frit-seal package)
has a transparent lid which allow the user to expose thechipto ultraviolet light to erase the bit pattern. A new pattern can then be written to the
device by following the programmingprocedure.
Table 1. Signal Names
A0-A18 Address Inputs
Q0-Q7 Data Outputs
E Chip Enable
G Output Enable
V
PP
V
CC
Program Supply
Supply Voltage
PLCC32 (K) TSOP32 (N)
8 x20 mm
Figure 1. Logic Diagram
CC
M27V401
V
SS
V
PP
V
19
A0-A18 Q0-Q7
E
G
8
AI00695B
V
SS
Ground
1/15May 1998
M27V401
Figure 2A. DIP Pin Connections
V
PP
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q2
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
M27V401
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
AI01861
V
CC
A18A16
A17
A14
A13
A8
A9
A11
G
A10
E
Q7
Q6
Q5Q1
Q4
Q3V
Figure 2B. LCC Pin Connections
CC
VPPV
32
Q3
Q4
A18
Q5
A7
A6
A5
A4
A3
A2
A1
A0
Q0
A16
A12
A15
1
9
Q1
Q2
M27V401
17
SS
V
A17
25
Q6
A14
A13
A8
A9
A11
G
A10
E
Q7
AI00696
Figure 2C. TSOP Pin Connections
A11 G
A9
A8
A13
A14
A17
A18
V
CC
V
PP
A16
A15
A12
A7
A6
A5
A4 A3
1
M27V401
8
(Normal)
9
16 17
32
25
24
AI01156B
A10
E
Q7
Q6
Q5
Q4
Q3
V
SS
Q2
Q1
Q0
A0
A1
A2
For applications wherethe content is programmed
only one time and erasure is not required, the
M27V201 is offered in PDIP32, PLCC32 and
TSOP32 (8 x 20 mm) packages.
DEVICE OPERATION
The operating modes of the M27V401 are listed in
the Operating Modes table. A single power supply
is required in the read mode. All inputs are TTL
levels except for VPPand 12V on A9 for Electronic
Signature.
Read Mode
The M27V401 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output controlandshould
be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time
(t
) is equal to the delay from E to output
AVQV
(t
). Data is available at the output after a delay
ELQV
of t
from the falling edge of G, assuming that
GLQV
E has been low andthe addresses havebeen stable for at least t
AVQV-tGLQV
.
2/15
M27V401
Table 2. Absolute Maximum Ratings
(1)
Symbol Parameter Value Unit
T
A
T
BIAS
T
STG
(2)
V
IO
V
CC
(2)
V
A9
V
PP
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings onlyand operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periodsmay affect device reliability. Referalsoto the STMicroelectronics SURE Program andotherrelevant quality documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
3. Depends on range.
Ambient Operating Temperature
Temperature Under Bias –50 to 125 °C
Storage Temperature –65 to 150 °C
Input or Output Voltage (except A9) –2 to 7 V
Supply Voltage –2 to 7 V
A9 Voltage –2 to 13.5 V
Program Supply Voltage –2 to 14 V
+0.5V with possible overshoot to VCC+2V for a period less than 20ns.
CC
(3)
–40 to 125 °C
Table 3. Operating Modes
Mode E G A9
Read
Output Disable V
Program
V
Verify V
Program Inhibit
Standby
Electronic Signature
Note: X = VIHor VIL,VID= 12V ± 0.5V.
V
IL
IL
Pulse V
IL
IH
V
IH
V
IH
V
IL
V
IL
V
IH
IH
V
IL
V
IH
X
XV
X
XVPPData Out
X
XX
V
IL
V
ID
V
PP
V
or V
CC
SS
or V
CC
SS
V
PP
V
PP
V
or V
CC
SS
V
CC
Q0-Q7
Data Out
Hi-Z
Data In
Hi-Z
Hi-Z
Codes
Table 4. Electronic Signature
Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data
Manufacturer’s Code
Device Code
V
IL
V
IH
Standby Mode
The M27V401 hasa standby modewhich reduces
the supply current from 15mA to 20µA with low
voltage operationVCC≤ 3.6V, see Read Mode DC
00100000 20h
01000001 41h
placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the G input.
Characteristics Table for details. The M27V401 is
3/15
M27V401
Table 5. AC Measurement Conditions
High Speed Standard
Input Rise and Fall Times ≤ 10ns ≤ 20ns
Input Pulse Voltages 0 to3V 0.4V to 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V
Figure 3. Testing Input Output Waveform
High Speed
3V
1.5V
0V
Standard
2.4V
0.4V
Table 6. Capacitance
(1)
(TA=25°C, f = 1 MHz)
2.0V
0.8V
AI01822
Figure 4. AC Testing Load Circuit
1.3V
1N914
3.3kΩ
DEVICE
UNDER
TEST
C
L
CL= 30pF for High Speed
CL= 100pF for Standard
CLincludes JIG capacitance
OUT
AI01823B
Symbol Parameter Test Condition Min Max Unit
V
C
IN
C
OUT
Note: Sampled only, not 100% tested.
Input Capacitance
Output Capacitance V
=0V
IN
=0V 12 pF
OUT
6pF
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2line control function which accommodates the use of multiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
a. complete assurance that output bus contention
will not occur.
4/15
For the most efficient use of these two control
lines, E should be decoded and used as the primary device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselected memory devicesare in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
M27V401
Table 7. Read Mode DC Characteristics
(1)
(TA= 0 to 70 °C or –40 to 85°C; VCC= 3.3V ± 10%; VPP=VCC)
Symbol Parameter TestCondition Min Max Unit
I
I
I
CC
I
CC1
I
CC2
I
V
V
IH
V
V
Note: 1. VCCmust be applied simultaneously with orbefore VPPand removed simultaneously or after VPP.
Table 8A. Read Mode AC Characteristics
Input Leakage Current
LI
Output Leakage Current
LO
Supply Current
E=V
IL
f = 5MHz, V
0V ≤ V
0V ≤ V
,G=VIL,I
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
PP
Input Low Voltage –0.3 0.8 V
IL
(2)
Input High Voltage 2
Output Low Voltage
OL
Output High Voltage TTL
OH
Output High Voltage CMOS
2. Maximum DC voltage on Output is V
CC
+0.5V.
(1)
E>V
CC
I
OH
I
OH
≤ V
IN
CC
≤ V
OUT
CC
= 0mA,
OUT
≤ 3.6V
CC
E=V
IH
–0.2V,VCC≤ 3.6V
V
PP=VCC
I
= 2.1mA
OL
= –400µA
= –100µAV
2.4 V
–0.7V
CC
±10 µA
±10 µA
15 mA
1mA
20 µA
10 µA
V
+1
CC
0.4 V
(TA= 0 to 70 °C or –40 to 85°C; VCC= 3.3V ± 10%; VPP=VCC)
M27V401
Symbol Alt Parameter Test Condition
Min Max Min Max
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
AXQX
Note: 1. VCCmust be applied simultaneously with orbefore VPPand removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
(2)
(2)
t
Address Valid to Output Valid
ACC
t
Chip Enable Low to Output Valid
CE
t
Output Enable Low to Output Valid
OE
t
Chip Enable High to Output Hi-Z
DF
t
Output Enable High to Output Hi-Z
DF
Address Transition to Output
t
OH
Transition
E=V
G=V
G=V
E=V
,G=V
IL
E=V
E=V
,G=V
IL
IL
IL
IL
IL
IL
IL
120 150 ns
120 150 ns
60 80 ns
0 50 0 50 ns
0 50 0 50 ns
00ns
V
V
Unit-120 -150
5/15
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