ST M27V401 User Manual

M27V401

M27V401

4 Mbit (512Kb x8) Low Voltage UV EPROM and OTP EPROM

■LOW VOLTAGE READ OPERATION: 3V to 3.6V

■FAST ACCESS TIME: 120ns

■LOW POWER CONSUMPTION:

±Active Current 15mA at 5MHz

±Standby Current 20μA

■PROGRAMMING VOLTAGE: 12.75V ± 0.25V

■PROGRAMMING TIME: 100μs/byte (typical)

■ELECTRONIC SIGNATURE

±Manufacturer Code: 20h

±Device Code: 41h

DESCRIPTION

The M27V401 is a low voltage 4 Mbit EPROM offered in the two range UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems requiring large data or program storage and is organised as 524,288 by 8 bits.

The M27V401 operates in the read mode with a supply voltage as low as 3V. The decrease in operating power allows either a reduction of the size of the battery or an increase in the time between battery recharges.

The FDIP32W (window ceramic frit-seal package) has a transparent lid which allow the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure.

Table 1. Signal Names

A0-A18	Address Inputs
Q0-Q7	Data Outputs
E	Chip Enable
G	Output Enable
VPP	Program Supply
VCC	Supply Voltage
VSS	Ground

32	32
1	1
FDIP32W (F)	PDIP32 (B)

PLCC32 (K)	TSOP32 (N)
	8 x 20 mm

Figure 1. Logic Diagram

VCC	VPP
19	8
A0-A18	Q0-Q7

E M27V401

G

VSS

AI00695B

May 1998

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M27V401

Figure 2A. DIP Pin Connections

VPP	1	32	VCC
A16	2	31	A18
A15	3	30	A17
A12	4	29	A14
A7	5	28	A13
A6	6	27	A8
A5	7	26	A9
A4	8	25	A11
A3	9	M27V401	G
		24
A2	10	23	A10
A1	11	22	E
A0	12	21	Q7
Q0	13	20	Q6
Q1	14	19	Q5
Q2	15	18	Q4
VSS	16	17	Q3
		AI01861

Figure 2C. TSOP Pin Connections

A11	1		32	G
A9				A10
A8				E
A13				Q7
A14				Q6
A17				Q5
A18				Q4
VCC	8	M27V401	25	Q3
VPP	9	(Normal)	24	VSS
A16				Q2
A15				Q1
A12				Q0
A7				A0
A6				A1
A5				A2
A4	16		17	A3
			AI01156B

Figure 2B. LCC Pin Connections

	A12	A15	A16	PP	CC	A18	A17
				V	V
A7				1	32			A14
A6								A13
A5								A8
A4								A9
A3	9		M27V401				25	A11
A2								G
A1								A10
A0								E
Q0				17				Q7
	Q1	Q2	SS Q3		Q4	Q5	Q6
			V

AI00696

For applications where the content is programmed only one time and erasure is not required, the M27V201 is offered in PDIP32, PLCC32 and TSOP32 (8 x 20 mm) packages.

DEVICE OPERATION

The operating modes of the M27V401 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for VPP and 12V on A9 for Electronic Signature.

Read Mode

The M27V401 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time

(tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of tGLQV from the falling edge of G, assuming that E has been low and the addresses have been sta-

ble for at least tAVQV-tGLQV.

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M27V401

Table 2. Absolute Maximum Ratings (1)

Symbol

TA

TBIAS

TSTG

VIO (2)

VCC

VA9 (2)

VPP

Parameter	Value	Unit
Ambient Operating Temperature (3)	±40 to 125	°C
Temperature Under Bias	±50 to 125	°C
Storage Temperature	±65 to 150	°C
Input or Output Voltage (except A9)	±2 to 7	V
Supply Voltage	±2 to 7	V
A9 Voltage	±2 to 13.5	V
Program Supply Voltage	±2 to 14	V

Note: 1. Except for the rating ºOperating Temperature Rangeº, stresses above those listed in the Table ºAbsolute Maximum Ratingsº may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

2.Minimum DC voltage on Input or Output is ±0.5V with possible undershoot to ±2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.

3.Depends on range.

Table 3. Operating Modes

Mode	E	G	A9	VPP	Q0-Q7
Read	VIL	VIL	X	VCC or VSS	Data Out
Output Disable	VIL	VIH	X	VCC or VSS	Hi-Z
Program	VIL Pulse	VIH	X	VPP	Data In
Verify	VIH	VIL	X	VPP	Data Out
Program Inhibit	VIH	VIH	X	VPP	Hi-Z
Standby	VIH	X	X	VCC or VSS	Hi-Z
Electronic Signature	VIL	VIL	VID	VCC	Codes

Note: X = VIH or VIL, VID = 12V ± 0.5V.

Table 4. Electronic Signature

Identifier	A0	Q7	Q6	Q5	Q4	Q3	Q2	Q1	Q0	Hex Data
Manufacturer's Code	VIL	0	0	1	0	0	0	0	0	20h
Device Code	VIH	0	1	0	0	0	0	0	1	41h

Standby Mode

The M27V401 has a standby mode which reduces the supply current from 15mA to 20μA with low voltage operation VCC ≤ 3.6V, see Read Mode DC Characteristics Table for details. The M27V401 is

placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input.

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M27V401

Table 5. AC Measurement Conditions

	High Speed	Standard
Input Rise and Fall Times	≤ 10ns	≤ 20ns
Input Pulse Voltages	0 to 3V	0.4V to 2.4V
Input and Output Timing Ref. Voltages	1.5V	0.8V and 2V

Figure 3. Testing Input Output Waveform		Figure 4. AC Testing Load Circuit
			1.3V
High Speed
3V				1N914
	1.5V
0V				3.3kΩ
		DEVICE
Standard		UNDER			OUT
		TEST
2.4V	2.0V			CL
0.4V	0.8V
	AI01822	CL = 30pF for High Speed
		CL = 100pF for Standard
		CL includes JIG capacitance			AI01823B
Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz)
Symbol	Parameter	Test Condit ion	Min	Max	Unit
CIN	Input Capacitance	VIN = 0V		6	pF
COUT	Output Capacitance	VOUT = 0V		12	pF

Note: Sampled only, not 100% tested.

Two Line Output Control

Because EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows:

a. the lowest possible memory power dissipation,

a.complete assurance that output bus contention will not occur.

For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device.

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					M27V401
Table 7. Read Mode DC Characteristics (1)
(TA = 0 to 70 °C or ±40 to 85°C; VCC = 3.3V ± 10%; VPP = VCC)
Symbol	Parameter	Test Condition	Min	Max	Unit

	ILI	Input Leakage Current
	ILO	Output Leakage Current
	ICC	Supply Current
	ICC1	Supply Current (Standby) TTL
	ICC2	Supply Current (Standby) CMOS
	IPP	Program Current
	VIL	Input Low Voltage
	VIH (2)	Input High Voltage
	VOL	Output Low Voltage
	VOH	Output High Voltage TTL
		Output High Voltage CMOS

0V ≤ VIN ≤ VCC		±10	μA
0V ≤ VOUT ≤ VCC		±10	μA
E = VIL, G = VIL, IOUT = 0mA,		15	mA
f = 5MHz, VCC ≤ 3.6V
E = VIH		1	mA
E > VCC ± 0.2V, VCC ≤ 3.6V		20	μA
VPP = VCC		10	μA
	±0.3	0.8	V
	2	VCC + 1	V
IOL = 2.1mA		0.4	V
IOH = ±400μA	2.4		V
IOH = ±100μA	VCC ±0.7V		V

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Maximum DC voltage on Output is VCC +0.5V.

Table 8A. Read Mode AC Characteristics (1)

(TA = 0 to 70 °C or ±40 to 85°C; VCC = 3.3V ± 10%; VPP = VCC)

				M27V401
Symbol	Alt	Parameter	Test Conditio n	-120	-150	Unit
				Min Max	Min Max

tAVQV	tACC
tELQV	tCE
tGLQV	tOE
(2)	tDF
tEHQZ
tGHQZ (2)	tDF
tAXQX	tOH

Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z

Output Enable High to Output Hi-Z

Address Transition to Output Transition

E = VIL, G = VIL		120		150	ns
G = VIL		120		150	ns
E = VIL		60		80	ns
G = VIL	0	50	0	50	ns
E = VIL	0	50	0	50	ns
E = VIL, G = VIL	0		0		ns

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested.

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