ST M27C256B User Manual
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256 Kbit (32Kb x 8) UV EPROM and OTP EPROM
■ 5V ± 10% SUPPLY VOLTAGE in READ
OPERATION
■ ACCESS TIME: 45ns
■ LOW POWER CONSUMPTION:
– Active Current 30mA at 5MHz
– Standby Current 100µA
■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V
■ PROGRAMMING TIME: 100µs/word
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 8Dh
M27C256B
28
1
FDIP28W (F) PDIP28 (B)
28
1
DESCRIPTION
The M27C256B is a 256 Kbit EPROM offered in
the two ranges UV (ultra violet erase) and OTP
(one time programmable). It is ideally suited for microprocessor systems and is organized as 32,768
by 8 bits.
The FDIP28W (window ceramic frit-seal package)
has a transparent lid which all ows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the
device by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M27C256B is offered in PDIP28, PLCC32 and
TSOP28 (8 x 13.4 mm) packages.
PLCC32 (C) TSOP28 (N)
8 x 13.4 mm
Figure 1. Logic Diagram
V
15
A0-A14 Q0-Q7
E
G
V
CC
M27C256B
PP
8
V
SS
AI00755B
1/16August 2002
M27C256B
Figure 2A. DIP Connections
V
1
PP
A12
2
3
A7
4
A6
5
A5
6
A4
7
A3
A2
A1
A0
Q0
Q2
SS
M27C256B
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AI00756
V
CC
A14
A13
A8
A9
A11
G
A10
E
Q7
Q6
Q5Q1
Q4
Q3V
Figure 2B. LCC Connections
PP
V
A6
A5
A4
A3
A2
A1
A0
NC
Q0
A7
9
Q1
DU
A12
32
1
M27C256B
17
Q2
SS
DU
V
V
Q3
CC
A14
Q4
A13
25
Q5
A8
A9
A11
NC
G
A10
E
Q7
Q6
AI00757
Figure 2C. TSOP Connections
22
G
A11
A9
A8
A13
A14
V
V
A12
CC
PP
A7
A6
A5
A4
A3
28
M27C256B
1
78
AI00614B
21
15
14
A10
E
Q7
Q6
Q5
Q4
Q3
V
SS
Q2
Q1
Q0
A0
A1
A2
Table 1. Signal Names
A0-A14 Address Inputs
Q0-Q7 Data Outputs
E
G
V
PP
V
CC
V
SS
NC Not Connected Internally
DU Don’t Use
Chip Enable
Output Enable
Program Supply
Supply Voltage
Ground
2/16
M27C256B
Table 2. Absolute Maximum Ratings
(1)
Symbol Parameter Value Unit
T
A Ambient Operating Temperature
T
BIAS
T
STG
(2)
V
IO
V
CC
(2)
V
A9
V
PP
Note: 1. Except for the ratin g " Operating Temperat ure Range", stresses above th ose listed in the Tabl e " A bsolute M aximum Rat i ngs" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indi cated in t he Operating sect i ons of thi s specif i cation is not imp l i ed. Exposure to Absolute Maximum Rating c onditions for extended per iods may aff ect device reliabilit y. Refer also to the STMicroe lectronics SURE Program an d other relevan t quality docum en ts .
2. Minimum DC vo ltage on Inpu t or Out put is – 0.5V w ith poss ible un dershoot to –2. 0V fo r a peri od les s than 20ns. Ma ximum DC
voltage on Output is V
3. Depends on range.
Temperature Under Bias –50 to 125 °C
Storage Temperature –65 to 150 °C
Input or Output Voltage (except A9) –2 to 7 V
Supply Voltage –2 to 7 V
A9 Voltage –2 to 13.5 V
Program Supply Voltage –2 to 14 V
+0.5V with possible overshoot to VCC +2V for a period l ess than 20ns.
CC
(3)
–40 to 125 °C
Table 3. Operating Modes
Mode E
Read
Output Disable
Program
Verify
Program Inhibit
Standby
Electronic Signature
Note: X = VIH or VIL, VID = 12V ± 0.5V.
V
IL
V
IL
VIL Pulse V
V
IH
V
IH
V
IH
V
IL
G A9
V
IL
V
IH
IH
V
IL
V
IH
X
X
X
X
X
XX
V
IL
V
ID
V
PP
V
CC
V
CC
V
PP
V
PP
V
PP
V
CC
V
CC
Data Out
Data Out
Q7-Q0
Hi-Z
Data In
Hi-Z
Hi-Z
Codes
Table 4. Electronic Signature
Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data
Manufacturer’s Code
Device Code
V
IL
V
IH
00100000 20h
10001101 8Dh
3/16
M27C256B
Table 5. AC Measurement Conditions
High Speed Standard
Input Rise and Fall Times ≤ 10ns ≤ 20ns
Input Pulse Voltages 0 to 3V 0.4V to 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V
Figure 3. AC Testing Input Output Waveform
High Speed
3V
1.5V
0V
Standard
2.4V
0.4V
Table 6. Capacitance
Symbol Parameter Test Condition Min Max Unit
C
IN
C
OUT
Note: 1. Sampled only, not 100% tested.
Input Capacitance
Output Capacitance
(1)
(TA = 25 °C, f = 1 MHz)
2.0V
0.8V
AI01822
Figure 4. AC Testing Load Circuit
1.3V
1N914
3.3kΩ
DEVICE
UNDER
TEST
CL
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
V
V
IN
OUT
= 0V
= 0V
6pF
12 pF
OUT
AI01823B
DEVICE OPERATION
The operating modes of the M27C256B are listed
in the Operating Modes. A single power sup ply is
required in the read mode. All inputs are TTL levels except for V
and 12V on A 9 for Electronic
PP
Signature.
Read Mode
The M27C256B has tw o cont rol func tions, bo th of
which must be logically ac tive in order to obtain
data at the output s. Chip Enable (E
) is the power
control and should be used for device selection.
Output Enable (G
) is the output control and should
be used to gate data to the output pins, independent of device selection. Assuming that the ad-
4/16
dresses are stable, the address access time
) is equal to the delay from E to output
(t
AVQV
(t
). Data is av ailable at the output after delay
ELQV
of t
E
ble for at least t
from the falling edge of G, assuming that
GLQV
has been low and the addresses have been sta-
AVQV-tGLQV
.
Standby Mode
The M27C256B has a standby mode which reduces the supply current from 30mA to 100µA. The
M27C256B is placed in the standby mode by applying a CMOS high signal to the E
input. When in
the standby mode, the outputs are in a high impedance state, independent of the G
input.
M27C256B
Table 7. Read Mode DC Characteristics
(1)
(TA = 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Symbol Parameter Test Condition Min Max Unit
I
I
LO
I
CC
I
CC1
I
CC2
I
PP
V
V
IH
V
V
Note: 1. VCC must be ap pl i e d simultaneously with or before VPP and removed simultaneously or af ter VPP.
Table 8A. Read Mode AC Characteristics
Input Leakage Current 0V ≤ VIN ≤ V
LI
(1)
0V ≤ V
E
= VIL, G = VIL,
I
= 0mA, f = 5MHz
OUT
E
E
> VCC – 0.2V
V
PP
I
= 2.1mA
OL
I
OH
= –100µA VCC – 0.7V
I
OH
Output Leakage Curren t
Supply Current
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
Input Low Voltage –0.3 0.8 V
IL
(2)
Input High Voltage 2
Output Low Voltage
OL
Output High Voltage TTL
OH
Output High Voltage CMOS
2. Maximu m DC voltage on Output is V
CC
+0.5 V .
≤ V
OUT
= V
IH
= V
CC
= –1mA
CC
CC
3.6 V
±10 µA
±10 µA
30 mA
1mA
100 µA
100 µA
V
CC
+ 1
V
0.4 V
V
(TA = 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
M27C256B
Symbol Alt Parameter Test Condition
-45
(3)
Min Max Min Max Min Max Min Max
t
AVQVtACC
t
ELQV
t
GLQVtOE
(2)
t
EHQZ
(2)
t
GHQZ
t
AXQXtOH
Note: 1. VCC must be ap pl i e d simultaneously with or before VPP and removed simultaneously or af ter VPP.
2. Sampled only, not 100% tested.
3. Speed obt ai ned with Hi gh S peed AC measurement conditions.
Address Valid to
Output Valid
Chip Enable Low to
t
CE
Output Valid
Output Enable Low to
Output Valid
Chip Enable High to
t
DF
Output Hi-Z
Output Enable High
t
DF
to Output Hi-Z
Address Transition to
Output Transition
= VIL, G = V
E
= V
G
= V
E
= V
G
= V
E
= VIL, G = V
E
IL
IL
IL
IL
IL
IL
45 60 70 80 ns
45 60 70 80 ns
25 30 35 40 ns
025030030030ns
025030030030ns
0000ns
-60 -70 -80
Unit
Two Line Outp ut C ontrol
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. comple te assuranc e that output bus contention
will not occur.
For the most efficient use of these two control
lines, E
ry device selecting function, while G
should be decoded and used as the prima-
should be
made a common connectio n to all devices in the
array and connected to the READ
line from the
system control bus. This ensures that all deselected memory devices are in their low power standby
mode and that the output pins are only active
when data is desired from a particular memory device.
5/16
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