M27C2001-10B1TR
M27C2001
2 Mbit (256Kb x 8) UV EPROM and OTP EPROM
■ 5V ± 10% SUPPLY VOLTAGE in READ
OPERATION |
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■ ACCESS TIME: 55ns |
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■ LOW POWER CONSUMPTION: |
32 |
32 |
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± Active Current 30mA at 5MHz |
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± Standby Current 100μA |
1 |
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1 |
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FDIP32W (F) |
PDIP32 (B) |
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■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V |
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■ PROGRAMMING TIME: 100μs/word |
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■ ELECTRONIC SIGNATURE |
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± Manufacturer Code: 20h |
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± Device Code: 61h |
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DESCRIPTION |
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LCCC32W (L) |
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The M27C2001 is a high speed 2 Mbit EPROM offered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems requiring large programs and is organised as 262,144 by 8 bits.
The FDIP32W (window ceramic frit-seal package) and LCCC32W (leadless chip carrier package) have a transparent lids which allow the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure.
For applications where the content is programmed only one time and erasure is not required, the M27C2001 is offered in PDIP32, PLCC32 and TSOP32 (8 x 20 mm) packages.
PLCC32 (C) |
TSOP32 (N) |
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8 x 20 mm |
Figure 1. Logic Diagram
VCC |
VPP |
18 |
8 |
A0-A17 |
Q0-Q7 |
P M27C2001
E
G
VSS
AI00716B
November 2000 |
1/17 |
M27C2001
Figure 2A. DIP Connections
VPP |
1 |
32 |
VCC |
A16 |
2 |
31 |
P |
A15 |
3 |
30 |
A17 |
A12 |
4 |
29 |
A14 |
A7 |
5 |
28 |
A13 |
A6 |
6 |
27 |
A8 |
A5 |
7 |
26 |
A9 |
A4 |
8 |
25 |
A11 |
A3 |
9 |
M27C2001 |
G |
24 |
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A2 |
10 |
23 |
A10 |
A1 |
11 |
22 |
E |
A0 |
12 |
21 |
Q7 |
Q0 |
13 |
20 |
Q6 |
Q1 |
14 |
19 |
Q5 |
Q2 |
15 |
18 |
Q4 |
VSS |
16 |
17 |
Q3 |
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AI00717 |
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Figure 2C. TSOP Connections
A11 |
1 |
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32 |
G |
A9 |
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A10 |
A8 |
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E |
A13 |
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Q7 |
A14 |
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Q6 |
A17 |
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Q5 |
P |
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Q4 |
VCC |
8 |
M27C2001 |
25 |
Q3 |
VPP |
9 |
(Normal) |
24 |
VSS |
A16 |
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Q2 |
A15 |
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Q1 |
A12 |
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Q0 |
A7 |
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A0 |
A6 |
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A1 |
A5 |
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A2 |
A4 |
16 |
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17 |
A3 |
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AI01153B |
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Figure 2B. LCC Connections
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A12 |
A15 |
A16 |
PP |
CC |
P |
A17 |
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V |
V |
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A7 |
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1 |
32 |
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A14 |
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A6 |
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A13 |
A5 |
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A8 |
A4 |
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A9 |
A3 |
9 |
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M27C2001 |
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25 |
A11 |
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A2 |
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G |
A1 |
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A10 |
A0 |
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E |
Q0 |
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17 |
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Q7 |
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Q1 |
Q2 |
SS Q3 |
Q4 |
Q5 |
Q6 |
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V |
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AI00718
Table 1. Signal Names
A0-A17 |
Address Inputs |
Q0-Q7 |
Data Outputs |
E |
Chip Enable |
G |
Output Enable |
P |
Program |
VPP |
Program Supply |
VCC |
Supply Voltage |
VSS |
Ground |
2/17
M27C2001
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
TBIAS
TSTG
VIO (2)
VCC
VA9 (2)
VPP
Parameter |
Value |
Unit |
Ambient Operating Temperature (3) |
±40 to 125 |
°C |
Temperature Under Bias |
±50 to 125 |
°C |
Storage Temperature |
±65 to 150 |
°C |
Input or Output Voltage (except A9) |
±2 to 7 |
V |
Supply Voltage |
±2 to 7 |
V |
A9 Voltage |
±2 to 13.5 |
V |
Program Supply Voltage |
±2 to 14 |
V |
Note: 1. Except for the rating ºOperating Temperature Rangeº, stresses above those listed in the Table ºAbsolute Maximum Ratingsº may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
2.Minimum DC voltage on Input or Output is ±0.5V with possible undershoot to ±2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.
3.Depends on range.
Table 3. Operating Modes
Mode |
E |
G |
P |
A9 |
VPP |
Q7-Q0 |
Read |
VIL |
VIL |
X |
X |
VCC or VSS |
Data Out |
Output Disable |
VIL |
VIH |
X |
X |
VCC or VSS |
Hi-Z |
Program |
VIL |
VIH |
VIL Pulse |
X |
VPP |
Data In |
Verify |
VIL |
VIL |
VIH |
X |
VPP |
Data Out |
Program Inhibit |
VIH |
X |
X |
X |
VPP |
Hi-Z |
Standby |
VIH |
X |
X |
X |
VCC or VSS |
Hi-Z |
Electronic Signature |
VIL |
VIL |
VIH |
VID |
VCC |
Codes |
Note: X = VIH or VIL, VID = 12V ± 0.5V. |
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Table 4. Electronic Signature
Identifier |
A0 |
Q7 |
Q6 |
Q5 |
Q4 |
Q3 |
Q2 |
Q1 |
Q0 |
Hex Data |
Manufacturer's Code |
VIL |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
20h |
Device Code |
VIH |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
1 |
61h |
3/17
M27C2001
Table 5. AC Measurement Conditions
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High Speed |
Standard |
Input Rise and Fall Times |
≤ 10ns |
≤ 20ns |
Input Pulse Voltages |
0 to 3V |
0.4V to 2.4V |
Input and Output Timing Ref. Voltages |
1.5V |
0.8V and 2V |
Figure 3. AC Testing Input Output Waveform |
Figure 4. AC Testing Load Circuit |
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1.3V |
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High Speed |
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3V |
1N914 |
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1.5V |
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0V |
3.3kΩ |
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DEVICE |
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Standard |
UNDER |
OUT |
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TEST |
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2.4V |
CL |
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2.0V |
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0.8V |
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0.4V
CL = 30pF for High Speed
AI01822
CL = 100pF for Standard |
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CL includes JIG capacitance |
AI01823B |
Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz)
Symbol |
Parameter |
Test Condit ion |
Min |
Max |
Unit |
CIN |
Input Capacitance |
VIN = 0V |
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6 |
pF |
COUT |
Output Capacitance |
VOUT = 0V |
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12 |
pF |
Note: 1. Sampled only, not 100% tested.
DEVICE OPERATION
The operating modes of the M27C2001 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for VPP and 12V on A9 for Electronic Signature.
Read Mode
The M27C2001 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the addresses are stable, the address access time
(tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of tGLQV from the falling edge of G, assuming that E has been low and the addresses have been sta-
ble for at least tAVQV-tGLQV.
Standby Mode
The M27C2001 has a standby mode which reduces the supply current from 30mA to 100μA. The M27C2001 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input.
4/17
M27C2001
Table 7. Read Mode DC Characteristics (1)
(TA = 0 to 70 °C or ±40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Symbol Parameter Test Condition Min Max Unit
ILI |
Input Leakage Current |
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ILO |
Output Leakage Current |
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ICC |
Supply Current |
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ICC1 |
Supply Current (Standby) TTL |
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ICC2 |
Supply Current (Standby) CMOS |
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IPP |
Program Current |
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VIL |
Input Low Voltage |
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(2) |
Input High Voltage |
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VIH |
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VOL |
Output Low Voltage |
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VOH |
Output High Voltage TTL |
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Output High Voltage CMOS |
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0V ≤ VIN ≤ VCC |
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±10 |
μA |
0V ≤ VOUT ≤ VCC |
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±10 |
μA |
E = VIL, G = VIL, |
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30 |
mA |
IOUT = 0mA, f = 5MHz |
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E = VIH |
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1 |
mA |
E > VCC ± 0.2V |
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100 |
μA |
VPP = VCC |
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10 |
μA |
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±0.3 |
0.8 |
V |
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2 |
VCC + 1 |
V |
IOL = 2.1mA |
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0.4 |
V |
IOH = ±400μA |
2.4 |
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V |
IOH = ±100μA |
VCC ± 0.7V |
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V |
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Maximum DC voltage on Output is VCC +0.5V.
Table 8A. Read Mode AC Characteristics (1)
(TA = 0 to 70 °C or ±40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
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M27C2001 |
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Symbol |
Alt |
Parameter |
Test Condition |
-55 (3) |
-70 |
-80 |
-90 |
Unit |
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Min |
Max |
Min |
Max |
Min |
Max |
Min |
Max |
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tAVQV |
tACC |
Address Valid to |
E = VIL, G = VIL |
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55 |
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70 |
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80 |
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90 |
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Output Valid |
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tELQV |
tCE |
Chip Enable Low to |
G = VIL |
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55 |
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70 |
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80 |
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90 |
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Output Valid |
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tGLQV |
tOE |
Output Enable Low |
E = VIL |
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30 |
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35 |
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40 |
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40 |
ns |
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to Output Valid |
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tEHQZ (2) |
tDF |
Chip Enable High to |
G = VIL |
0 |
30 |
0 |
30 |
0 |
30 |
0 |
30 |
ns |
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Output Hi-Z |
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tGHQZ (2) |
tDF |
Output Enable High |
E = VIL |
0 |
30 |
0 |
30 |
0 |
30 |
0 |
30 |
ns |
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to Output Hi-Z |
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tAXQX |
tOH |
Address Transition to |
E = VIL, G = VIL |
0 |
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0 |
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0 |
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0 |
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Output Transition |
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Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2.Sampled only, not 100% tested.
3.In case of 45ns speed see High Speed AC measurement conditions.
Two Line Output Control
Because EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows:
a.the lowest possible memory power dissipation,
b.complete assurance that output bus contention will not occur.
For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device.
5/17
M27C2001
Table 8B. Read Mode AC Characteristics (1)
(TA = 0 to 70 °C or ±40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
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M27C2001 |
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Symbol |
Alt |
Parameter |
Test Condition |
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-10 |
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-12 |
-15/-20/-25 Unit |
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Min |
Max |
Min |
Max |
Min |
Max |
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tAVQV |
tACC |
Address Valid to Output |
E = VIL, G = VIL |
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100 |
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120 |
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150 |
ns |
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Valid |
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tELQV |
tCE |
Chip Enable Low to |
G = VIL |
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100 |
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120 |
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150 |
ns |
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Output Valid |
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tGLQV |
tOE |
Output Enable Low to |
E = VIL |
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50 |
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50 |
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60 |
ns |
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Output Valid |
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(2) |
tDF |
Chip Enable High to |
G = VIL |
0 |
30 |
0 |
40 |
0 |
50 |
ns |
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tEHQZ |
Output Hi-Z |
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t |
(2) |
tDF |
Output Enable High to |
E = VIL |
0 |
30 |
0 |
40 |
0 |
50 |
ns |
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Output Hi-Z |
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GHQZ |
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tAXQX |
tOH |
Address Transition to |
E = VIL, G = VIL |
0 |
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0 |
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0 |
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Output Transition |
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Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested.
Figure 5. Read Mode AC Waveforms
A0-A17 |
VALID |
VALID |
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tAVQV |
tAXQX |
E |
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tGLQV |
tEHQZ |
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G |
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tELQV |
tGHQZ |
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Q0-Q7 |
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Hi-Z |
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AI00719B |
System Considerations
The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output. The associated transient voltage peaks can be suppressed by complying with the two line
output control and by properly selected decoupling capacitors. It is recommended that a 0.1μF ceramic capacitor be used on every device between VCC and VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7μF bulk electrolytic capacitor should be used between VCC and VSS for every eight devices. The bulk capacitor should be located near the power supply connection point. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces.
6/17