ST M24M01-R User Manual

M24M01-R M24M01-DF

1-Mbit serial I²C bus EEPROM

Features

■Compatible with all I2C bus modes:

–1 MHz Fast-mode Plus

–400 kHz Fast mode

–100 kHz Standard mode

■Memory array:

–1 Mbit (128 Kbytes) of EEPROM

–Page size: 256 bytes

–Additional Write lockable page (M24M01-D order codes)

■Write

–Byte Write within 5 ms

–Page Write within 5 ms

■Single supply voltage: 1.7 V to 5.5 V

■Operating temperature range: from -40 °C up to +85 °C

■Random and sequential Read modes

■Write protect of the whole memory array

■Enhanced ESD/Latch-Up protection

■More than 4 million Write cycles

■More than 200-year data retention

■Packages

–RoHS compliant and halogen-free (ECOPACK®)

Datasheet − production data

SO8 (MN) 150 mil width

TSSOP8 (DW)

WLCSP (CS)

April 2012

Doc ID 12943 Rev 9

1/41

This is information on a product in full production.

www.st.com

Contents	M24M01-R M24M01-DF

Contents

1	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
2	Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9

2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Chip Enable (E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.6.1 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3	Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
4	Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		12
	4.1	Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	4.2	Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	4.3	Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	4.4	Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	4.5	Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
5	Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
	5.1	Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15

5.1.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.3 Write Identification Page (M24M01-D only) . . . . . . . . . . . . . . . . . . . . . . 18 5.1.4 Lock Identification Page (M24M01-D only) . . . . . . . . . . . . . . . . . . . . . . 18 5.1.5 ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . 19 5.1.6 Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 20

5.2 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.2.1 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2/41	Doc ID 12943 Rev 9

M24M01-R M24M01-DF	Contents

5.2.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.2.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.3 Read Identification Page (M24M01-D only) . . . . . . . . . . . . . . . . . . . . . . . 22 5.4 Read the lock status (M24M01-D only) . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.4.1 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6	Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
7	Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
8	DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
9	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33
10	Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	37
11	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	38

Doc ID 12943 Rev 9

3/41

List of tables	M24M01-R M24M01-DF

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3. Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4. Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 6. Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 7. Operating conditions (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 8. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 9. Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 10. Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 11. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 12. DC characteristics (voltage range R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 13. DC characteristics (voltage range F, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 14. 400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 15. 1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 16. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 33 Table 17. SO8N – 8 lead plastic small outline, 150 mils body width, package data . . . . . . . . . . . . . . 34 Table 18. WLCSP8 – Wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . 35 Table 19. WLCSP – Wafer level chip size package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 20. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 21. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4/41	Doc ID 12943 Rev 9

M24M01-R M24M01-DF	List of figures

List of figures

Figure 1.	Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 6
Figure 2.	8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 7
Figure 3.	WLCSP connections for die identified by process letter A (bump side view) . . . . . . . . . . .	. 7
Figure 4.	WLCSP connections for die identified by process letter K (bump side view) . . . . . . . . . . .	. 8
Figure 5.	Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 9
Figure 6.	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
Figure 7.	I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
Figure 8.	Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . .	16
Figure 9.	Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . .	17
Figure 10.	Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
Figure 11.	Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
Figure 12.	AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
Figure 13.	Maximum Rbus value versus bus parasitic capacitance (Cbus) for
	an I2C bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
Figure 14.	Maximum Rbus value versus bus parasitic capacitance Cbus) for
	an I2C bus at maximum frequency fC = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
Figure 15.	AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
Figure 16.	TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . .	33
Figure 17.	SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . .	34
Figure 18.	Standard WLCSP8 – Wafer level chip scale package outline (for die
	identified by process letter A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	35
Figure 19.	Thin WLCSP – Wafer level chip size package outline (for die identified
	by process letter K). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	36

Doc ID 12943 Rev 9

5/41

Description	M24M01-R M24M01-DF

1 Description

The M24M01 is a 1 Mb I2C-compatible EEPROM (Electrically Erasable PROgrammable Memory) organized as 128 K × 8 bits.

The M24M01-R can operate with a supply voltage from 1.8 V to 5.5 V, and the M24M01-DF can operate with a supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of -40 °C / +85 °C.

The M24M01-D offers an additional page, named the Identification Page (256 bytes). The Identification Page can be used to store sensitive application parameters which can be (later) permanently locked in Read-only mode.

Figure 1. Logic diagram

	6##
% %	3$!
3#,	- XXX
7#
	633

.4 7

Table 1.			Signal names
			Signal name	Function	Direction
	E1, E2			Chip Enable	Input
	SDA			Serial Data	I/O
	SCL			Serial Clock	Input
				Write Control	Input
	WC
	VCC			Supply voltage
	VSS			Ground

6/41	Doc ID 12943 Rev 9

M24M01-R M24M01-DF											Description
	Figure 2. 8-pin package connections
			- -
	$5								6##
	%									7#
	%							3#,
	633							3$!
								-3 6

1.DU: Don't Use (if connected, must be connected to VSS)

2.See Section 9: Package mechanical data for package dimensions, and how to identify pin 1.

Figure 3. WLCSP connections for die identified by process letter A (bump side view)

)NDEX

6##	3#,	3$!
7#		633
$5	%	%

-3 6

1.DU: Don't Use (if connected, must be connected to VSS)

2.See Section 9: Package mechanical data for package dimensions, and how to identify pin 1.

Doc ID 12943 Rev 9

7/41

Description	M24M01-R M24M01-DF

Figure 4. WLCSP connections for die identified by process letter K (bump side view)

	VCC	W	SCL
			SDA
	DU		VSS
		E1	E2

MS30220V1

1.DU: Don't Use (if connected, must be connected to VSS)

2.See Section 9: Package mechanical data for package dimensions, and how to identify pin 1.

Caution: As EEPROM cells lose their charge (and so their binary value) when exposed to ultra violet (UV) light, EEPROM dice delivered in wafer form by STMicroelectronics must never be exposed to UV light.

8/41	Doc ID 12943 Rev 9

M24M01-R M24M01-DF	Signal description

2 Signal description

2.1Serial Clock (SCL)

The signal applied on the SCL input is used to strobe the data available on SDA(in) and to output the data on SDA(out).

2.2Serial Data (SDA)

SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected (Figure 13 indicates how to calculate the value of the pull-up resistor).

2.3Chip Enable (E1, E2)

These input signals are used to set the value that is to be looked for on the two bits (b3, b2) of the 7-bit device select code. These inputs must be tied to VCC or VSS, to establish the device select code as shown in Figure 5. When not connected (left floating), these inputs are read as low (0,0).

Figure 5. Device select code

VCC

VCC

M24xxx M24xxx

Ei							Ei
VSS							VSS

Ai12806

2.4Write Control (WC)

This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either driven low or left floating.

When Write Control (WC) is driven high, device select and address bytes are acknowledged, Data bytes are not acknowledged.

Doc ID 12943 Rev 9

9/41

Signal description	M24M01-R M24M01-DF

2.5VSS (ground)

VSS is the reference for the VCC supply voltage.

2.6Supply voltage (VCC)

2.6.1Operating supply voltage VCC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 8: DC and AC parameters). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins.

This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (tW).

2.6.2Power-up conditions

The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage (see Operating conditions in Section 8: DC and AC parameters) and the rise time must not vary faster than 1 V/µs.

2.6.3Device reset

In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included.

At power-up, the device does not respond to any instruction until VCC has reached the internal reset threshold voltage. This threshold is lower than the minimum VCC operating voltage (see Operating conditions in Section 8: DC and AC parameters). When VCC passes over the POR threshold, the device is reset and enters the Standby Power mode; however, the device must not be accessed until VCC reaches a valid and stable DC voltage within the specified [VCC(min), VCC(max)] range (see Operating conditions in Section 8: DC and AC parameters).

In a similar way, during power-down (continuous decrease in VCC), the device must not be accessed when VCC drops below VCC(min). When VCC drops below the internal reset threshold voltage, the device stops responding to any instruction sent to it.

2.6.4Power-down conditions

During power-down (continuous decrease in VCC), the device must be in the Standby Power mode (mode reached after decoding a Stop condition, assuming that there is no internal write cycle in progress).

10/41

Doc ID 12943 Rev 9

M24M01-R M24M01-DF	Memory organization

3 Memory organization

The memory is organized as shown in Figure 6.

Figure 6. Block diagram

7#					(IGH VOLTAGE
%			#ONTROLTLOGIC
					GENERATOR
%

3#,
3$!	) / SHIFTSREGISTER

!DDRESSRREGISTER	$ATA
ANDNCOUNTER	REGISTER
99DECODER
	PAGE
	)DENTIFICATION PAGE
	88DECODER

-3 6

Doc ID 12943 Rev 9

11/41

Device operation	M24M01-R M24M01-DF

4 Device operation

The device supports the I2C protocol. This is summarized in Figure 7. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The device is always a slave in all communications.

Figure 7. I2C bus protocol
SCL
SDA
	START		SDA	SDA		STOP
			Input	Change
	Condition					Condition
SCL	1	2	3	7	8	9
SDA	MSB					ACK
	START
	Condition
SCL	1	2	3	7	8	9
SDA	MSB					ACK
						STOP
						Condition
						AI00792B

12/41

Doc ID 12943 Rev 9

M24M01-R M24M01-DF	Device operation

4.1Start condition

Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer instruction. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition.

4.2Stop condition

Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high. A Stop condition terminates communication between the device and the bus master. A Read instruction that is followed by NoAck can be followed by a Stop condition to force the device into the Standby mode.

A Stop condition at the end of a Write instruction triggers the internal Write cycle.

4.3Data input

During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven low.

4.4Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to acknowledge the receipt of the eight data bits.

4.5Device addressing

To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 7 (on Serial Data (SDA), most significant bit first).

Table 2.

Device select code

Device type identifier(1)

Chip Enable

Address bits

RW

address(2)

When accessing

b7

b6

b5

b4

b3

b2

b1

b0

the memory

1

0

1

0

E2

E1

A16

RW

When accessing

the Identification

1

0

1

1

E2

E1

A16

RW

page

1.The most significant bit, b7, is sent first.

2.E2,E1 are compared against the external pin on the memory device.

Doc ID 12943 Rev 9

13/41