ST M24LR64-R User Manual

64 Kbit EEPROM with password protection & dual interface:

SO8 (MN)

150 mils width

UFDFPN8 (MB)

2 × 3 mm

TSSOP8 (DW)

Sawn wafer on UV tape

400 kHz I²C serial bus & ISO 15693 RF protocol at 13.56 MHz

Features

I2C interface

■ Two-wire I

protocol

■ Single supply voltage:

– 1.8 V to 5.5 V

■ Byte and Page Write (up to 4 bytes)

■ Random and Sequential Read modes

■ Self-timed programming cycle

■ Automatic address incrementing

■ Enhanced ESD/latch-up protection

Contactless interface

C serial interface supports 400 kHz

M24LR64-R

■ ISO 15693 and ISO 18000-3 mode 1

compatible

■ 13.56 MHz ±7k Hz carrier frequency

■ To tag: 10% or 100% ASK modulation using

1/4 (26 Kbit/s) or 1/256 (1.6 Kbit/s) pulse position coding

■ From tag: load modulation using Manchester

coding with 423 kHz and 484 kHz subcarriers in low (6.6 kbit/s) or high (26 kbit/s) data rate mode. Supports the 53 kbit/s data rate with Fast commands

■ Internal tuning capacitance: 27.5 pF

■ 64-bit unique identifier (UID)

■ Read Block & Write (32-bit Blocks)

Memory

■ 64 Kbit EEPROM organized into:

– 8192 bytes in I – 2048 blocks of 32 bits in RF mode

■ Write time

–I

C: 5 ms (Max.)

– RF: 5.75 ms including the internal Verify

time

C mode

■ More than 1 Million write cycles

■ Multiple password protection in RF mode

■ Single password protection in I

■ More than 40-year data retention

■ Package

– ECOPACK2

(RoHS compliant and

C mode

Halogen-free)

January 2012 Doc ID 15170 Rev 14 1/128

www.st.com

Contents M24LR64-R

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3 Chip Enable (E0, E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.4 Antenna coil (AC0, AC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5 V

2.6 Supply voltage (V

ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.6.1 Operating supply voltage V

2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 User memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4 System memory area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.1 M24LR64-R RF block security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.2 Example of the M24LR64-R security protection . . . . . . . . . . . . . . . . . . . . 25

4.3 I2C_Write_Lock bit area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.4 System parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.5 M24LR64-R I

4.5.1 I2C Present Password command description . . . . . . . . . . . . . . . . . . . . 27

4.5.2 I

C password security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

C Write Password command description . . . . . . . . . . . . . . . . . . . . . . 28

C device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.4 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.5 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.6 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.7 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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5.8 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.9 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 34

5.10 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.11 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.12 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.13 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.14 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6 User memory initial state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7 RF device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.1 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.2 Initial dialog for vicinity cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.2.1 Power transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.2.2 Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.2.3 Operating field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8 Communication signal from VCD to M24LR64-R . . . . . . . . . . . . . . . . . 40

9 Data rate and data coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.1 Data coding mode: 1 out of 256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.2 Data coding mode: 1 out of 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.3 VCD to M24LR64-R frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.4 Start of frame (SOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

10 Communications signal from M24LR64-R to VCD . . . . . . . . . . . . . . . . 47

10.1 Load modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.2 Subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.3 Data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

11 Bit representation and coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

11.1 Bit coding using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

11.1.1 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

11.1.2 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

11.2 Bit coding using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

11.3 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

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11.4 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

12 M24LR64-R to VCD frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

12.1 SOF when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

12.2 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

12.3 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

12.4 SOF when using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

12.5 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

12.6 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

12.7 EOF when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

12.8 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

12.9 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

12.10 EOF when using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

12.11 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

12.12 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

13 Unique identifier (UID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

14 Application family identifier (AFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

15 Data storage format identifier (DSFID) . . . . . . . . . . . . . . . . . . . . . . . . . 57

15.1 CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

16 M24LR64-R protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

17 M24LR64-R states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

17.1 Power-off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

17.2 Ready state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

17.3 Quiet state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

17.4 Selected state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

18 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

18.1 Addressed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

18.2 Non-addressed mode (general request) . . . . . . . . . . . . . . . . . . . . . . . . . 62

18.3 Select mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

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19 Request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

19.1 Request flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

20 Response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

20.1 Response flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

20.2 Response error code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

21 Anticollision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

21.1 Request parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

22 Request processing by the M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . 69

23 Explanation of the possible cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

24 Inventory Initiated command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

25 Timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

25.1 t1: M24LR64-R response delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

25.2 t2: VCD new request delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

25.3 t

: VCD new request delay in the absence of a response from

the M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

26 Commands codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

26.1 Inventory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

26.2 Stay Quiet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

26.3 Read Single Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

26.4 Write Single Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

26.5 Read Multiple Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

26.6 Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

26.7 Reset to Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

26.8 Write AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

26.9 Lock AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

26.10 Write DSFID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

26.11 Lock DSFID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

26.12 Get System Info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

26.13 Get Multiple Block Security Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

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26.14 Write-sector Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

26.15 Lock-sector Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

26.16 Present-sector Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

26.17 Fast Read Single Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

26.18 Fast Inventory Initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

26.19 Fast Initiate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

26.20 Fast Read Multiple Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

26.21 Inventory Initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

26.22 Initiate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

27 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

28 I2C DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

29 RF electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

30 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

31 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Appendix A Anticollision algorithm (informative) . . . . . . . . . . . . . . . . . . . . . . . 123

A.1 Algorithm for pulsed slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Appendix B CRC (informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

B.1 CRC error detection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

B.2 CRC calculation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Appendix C Application family identifier (AFI) (informative) . . . . . . . . . . . . . . 126

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

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M24LR64-R List of tables

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 2. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 3. Address most significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4. Address least significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5. Sector details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 6. Sector Security Status Byte area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 7. Sector security status byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 8. Read / Write protection bit setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 9. Password Control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 10. Password system area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 11. M24LR64-R sector security protection after power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 12. M24LR64-R sector security protection after a valid presentation of password 1 . . . . . . . . 25 Table 13. I2C_Write_Lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 14. System parameter sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 15. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 16. 10% modulation parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 17. Response data rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 18. UID format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 19. CRC transmission rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 20. VCD request frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 21. M24LR64-R Response frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 22. M24LR64-R response depending on Request_flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 23. General request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 24. Definition of request flags 1 to 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 25. Request flags 5 to 8 when Bit 3 = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 26. Request flags 5 to 8 when Bit 3 = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 27. General response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 28. Definitions of response flags 1 to 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 29. Response error code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 30. Inventory request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 31. Example of the addition of 0-bits to an 11-bit mask value . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 32. Timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 33. Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 34. Inventory request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 35. Inventory response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 36. Stay Quiet request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 37. Read Single Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 38. Read Single Block response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . 77 Table 39. Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 40. Read Single Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 41. Write Single Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 42. Write Single Block response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . 79 Table 43. Write Single Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 44. Read Multiple Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 45. Read Multiple Block response format when Error_flag is NOT set. . . . . . . . . . . . . . . . . . . 81 Table 46. Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 47. Read Multiple Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . 82 Table 48. Select request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

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List of tables M24LR64-R

Table 49. Select Block response format when Error_flag is NOT set. . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 50. Select response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 51. Reset to Ready request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 52. Reset to Ready response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . 84 Table 53. Reset to ready response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 54. Write AFI request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 55. Write AFI response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 56. Write AFI response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 57. Lock AFI request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 58. Lock AFI response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 59. Lock AFI response format when Error_flag is set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 60. Write DSFID request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 61. Write DSFID response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 62. Write DSFID response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 63. Lock DSFID request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 64. Lock DSFID response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 65. Lock DSFID response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 66. Get System Info request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 67. Get System Info response format when Error_flag is NOT set. . . . . . . . . . . . . . . . . . . . . . 93 Table 68. Get System Info response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 69. Get Multiple Block Security Status request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 70. Get Multiple Block Security Status response format when Error_flag is NOT set . . . . . . . 95 Table 71. Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 72. Get Multiple Block Security Status response format when Error_flag is set . . . . . . . . . . . . 96 Table 73. Write-sector Password request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 74. Write-sector Password response format when Error_flag is NOT set . . . . . . . . . . . . . . . . 97 Table 75. Write-sector Password response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . 97 Table 76. Lock-sector Password request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 77. Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 78. Lock-sector Password response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . 99 Table 79. Lock-sector Password response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . 99 Table 80. Present-sector Password request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 81. Present-sector Password response format when Error_flag is NOT set . . . . . . . . . . . . . 101 Table 82. Present-sector Password response format when Error_flag is set . . . . . . . . . . . . . . . . . . 101 Table 83. Fast Read Single Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 84. Fast Read Single Block response format when Error_flag is NOT set . . . . . . . . . . . . . . . 103 Table 85. Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 86. Fast Read Single Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . 103 Table 87. Fast Inventory Initiated request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 88. Fast Inventory Initiated response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 89. Fast Initiate request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 90. Fast Initiate response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 91. Fast Read Multiple Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 92. Fast Read Multiple Block response format when Error_flag is NOT set. . . . . . . . . . . . . . 107 Table 93. Sector security status if Option_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 94. Fast Read Multiple Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . 108 Table 95. Inventory Initiated request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 96. Inventory Initiated response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 97. Initiate request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 98. Initiate Initiated response format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 99. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 100. I

C operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

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Table 101. AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 102. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 103. I Table 104. I

C DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

C AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 105. RF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 106. Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 107. SO8N – 8-lead plastic small outline, 150 mils body width, package data. . . . . . . . . . . . . 118 Table 108. UFDFPN8 (MLP8) – Ultra thin fine pitch dual flat package no lead

2 x 3 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 109. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . 120 Table 110. Ordering information scheme for packaged devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 111. Ordering information scheme for bare die devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 112. CRC definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 113. AFI coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 114. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

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List of figures M24LR64-R

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 3. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 4. I

Figure 5. I Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 7. Memory sector organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 8. I Figure 9. I Figure 10. Write mode sequences with I2C_Write_Lock bit = 1 (data write inhibited) . . . . . . . . . . . . . 31 Figure 11. Write mode sequences with I2C_Write_Lock bit = 0 (data write enabled) . . . . . . . . . . . . . 33 Figure 12. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 13. Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 14. 100% modulation waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 15. 10% modulation waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 16. 1 out of 256 coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 17. Detail of a time period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 18. 1 out of 4 coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 19. 1 out of 4 coding example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 20. SOF to select 1 out of 256 data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 21. SOF to select 1 out of 4 data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 22. EOF for either data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 23. Logic 0, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 24. Logic 0, high data rate x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 25. Logic 1, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 26. Logic 1, high data rate x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 27. Logic 0, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 28. Logic 0, low data rate x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 29. Logic 1, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 30. Logic 1, low data rate x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 31. Logic 0, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 32. Logic 1, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 33. Logic 0, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 34. Logic 1, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 35. Start of frame, high data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 36. Start of frame, high data rate, one subcarrier x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 37. Start of frame, low data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 38. Start of frame, low data rate, one subcarrier x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 39. Start of frame, high data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 40. Start of frame, low data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 41. End of frame, high data rate, one subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 42. End of frame, high data rate, one subcarriers x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 43. End of frame, low data rate, one subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 44. End of frame, low data rate, one subcarriers x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 45. End of frame, high data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 46. End of frame, low data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 47. M24LR64-R decision tree for AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

C Fast mode (fC = 400 kHz): maximum R

capacitance (C

C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

C Present Password command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

C Write Password command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

bus

value versus bus parasitic

bus

10/128 Doc ID 15170 Rev 14

M24LR64-R List of figures

Figure 48. M24LR64-R protocol timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 49. M24LR64-R state transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 50. Principle of comparison between the mask, the slot number and the UID . . . . . . . . . . . . . 68 Figure 51. Description of a possible anticollision sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 52. Stay Quiet frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 53. Read Single Block frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . 78 Figure 54. Write Single Block frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . 80 Figure 55. Read Multiple Block frame exchange between VCD and M24LR64-R. . . . . . . . . . . . . . . . 82 Figure 56. Select frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 57. Reset to Ready frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . 84 Figure 58. Write AFI frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 59. Lock AFI frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure 60. Write DSFID frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . 90 Figure 61. Lock DSFID frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . 92 Figure 62. Get System Info frame exchange between VCD and M24LR64-R. . . . . . . . . . . . . . . . . . . 94 Figure 63. Get Multiple Block Security Status frame exchange between VCD and M24LR64-R . . . . 96 Figure 64. Write-sector Password frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . 98 Figure 65. Lock-sector Password frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . 100 Figure 66. Present-sector Password frame exchange between VCD and M24LR64-R . . . . . . . . . . 102 Figure 67. Fast Read Single Block frame exchange between VCD and M24LR64-R . . . . . . . . . . . . 104 Figure 68. Fast Initiate frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . 106 Figure 69. Fast Read Multiple Block frame exchange between VCD and M24LR64-R. . . . . . . . . . . 108 Figure 70. Initiate frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 71. AC test measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 72. I

C AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Figure 73. M24LR64-R synchronous timing, transmit and receive . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Figure 74. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . 118 Figure 75. UFDFPN8 (MLP8) – Ultra thin fine pitch dual flat package no lead

2 x 3 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 76. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . 120

Doc ID 15170 Rev 14 11/128

Description M24LR64-R

AI15106b

E0-E1 SDA

M24LR64-R

SCL

AC0

AC1

1 Description

The M24LR64-R device is a dual-interface, electrically erasable programmable memory (EEPROM). It features an I also a contactless memory powered by the received carrier electromagnetic wave. The M24LR64-R is organized as 8192 × 8 bits in the I

C interface and can be operated from a VCC power supply. It is

C mode and as 2048 × 32 bits in the ISO

15693 and ISO 18000-3 mode 1 RF mode.

Figure 1. Logic diagram

C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The

devices carry a built-in 4-bit device type identifier code (1010) in accordance with the I

bus definition.

The device behaves as a slave in the I

C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a device select code and Read/Write bit (RW

) (as described in Ta bl e 2 ), terminated by an acknowledge bit.

When writing data to the memory, the device inserts an acknowledge bit during the 9

bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.

In the ISO15693/ISO18000-3 mode 1 RF mode, the M24LR64-R is accessed via the

13.56 MHz carrier electromagnetic wave on which incoming data are demodulated from the received signal amplitude modulation (ASK: amplitude shift keying). The received ASK wave is 10% or 100% modulated with a data rate of 1.6 Kbit/s using the 1/256 pulse coding mode or a data rate of 26 Kbit/s using the 1/4 pulse coding mode.

Outgoing data are generated by the M24LR64-R load variation using Manchester coding with one or two subcarrier frequencies at 423 kHz and 484 kHz. Data are transferred from the M24LR64-R at 6.6 Kbit/s in low data rate mode and 26 Kbit/s high data rate mode. The M24LR64-R supports the 53 Kbit/s in high data rate mode in one subcarrier frequency at 423 kHz.

The M24LR64-R follows the ISO 15693 and ISO 18000-3 mode 1 recommendation for radio-frequency power and signal interface.

12/128 Doc ID 15170 Rev 14

M24LR64-R Description

SDAV

SCL

E1AC0

E0 V

AC1

AI15107

1 2 3 4

8 7 6 5

Table 1. Signal names

Signal name Function Direction

E0, E1 Chip Enable Input

SDA Serial Data I/O

SCL Serial Clock Input

AC0, AC1 Antenna coils I/O

Supply voltage

Ground

Figure 2. 8-pin package connections

1. See Package mechanical data section for package dimensions, and how to identify pin-1.

Doc ID 15170 Rev 14 13/128

Signal description M24LR64-R

Ai12806

M24xxx

2 Signal description

2.1 Serial Clock (SCL)

This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to V most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output.

2.2 Serial Data (SDA)

This bidirectional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to V the value of the pull-up resistor can be calculated).

. (Figure 4 indicates how the value of the pull-up resistor can be calculated). In

. (Figure 4 indicates how

2.3 Chip Enable (E0, E1)

These input signals are used to set the value that is to be looked for on the two least significant bits (b2, b1) of the 7-bit device select code. These inputs must be tied to V V

, to establish the device select code as shown in Figure 3. When not connected (left

floating), these inputs are read as low (0,0).

Figure 3. Device select code

2.4 Antenna coil (AC0, AC1)

These inputs are used to connect the device to an external coil exclusively. It is advised to not connect any other DC or AC path to AC0 and AC1 pads. When correctly tuned, the coil is used to power and access the device using the ISO 15693 and ISO 18000-3 mode 1 protocols.

14/128 Doc ID 15170 Rev 14

M24LR64-R Signal description

2.5 VSS ground

VSS is the reference for the VCC supply voltage.

2.6 Supply voltage (VCC)

This pin can be connected to an external DC supply voltage.

Note: An internal voltage regulator allows the external voltage applied on V

M24LR64-R, while preventing the internal power supply (rectified RF waveforms) to output a DC voltage on the V

2.6.1 Operating supply voltage V

pin.

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [V

(min), VCC(max)] range must be applied (see Tab l e 1 00 ). To

maintain a stable DC supply voltage, it is recommended to decouple the V suitable capacitor (usually of the order of 10 nF) close to the V

CC/VSS

This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal I²C write cycle (t

2.6.2 Power-up conditions

When the power supply is turned on, VCC rises from VSS to VCC. The VCC rise time must not vary faster than 1V/µs.

2.6.3 Device reset

In order to prevent inadvertent write operations during power-up, a power-on reset (POR) circuit is included. At power-up (continuous rise of V instruction until V lower than the minimum V

has reached the power-on reset threshold voltage (this threshold is

operating voltage defined in Ta bl e 1 00 ). When VCC passes

over the POR threshold, the device is reset and enters the Standby Power mode, however, the device must not be accessed until V within the specified [V

(min), VCC(max)] range.

has reached a valid and stable VCC voltage

In a similar way, during power-down (continuous decrease in V below the power-on reset threshold voltage, the device stops responding to any instruction sent to it.

), the device does not respond to any

), as soon as VCC drops

to supply the

line with a

package pins.

2.6.4 Power-down conditions

During power-down (continuous decay of VCC), the device must be in Standby Power mode (mode reached after decoding a Stop condition, assuming that there is no internal write cycle in progress).

Doc ID 15170 Rev 14 15/128

Signal description M24LR64-R

100

10 100 1000

Bus line capacitor (pF)

Bus line pull-up resistor

)

When t

LOW

= 1.3 µs (min value for

= 400 kHz), the R

bus

× C

bus

time constant m ust be below the 400 ns time constant line represented on the left.

I²C bus master

M24xxx

bus

SCL

SDA

ai14796b

bus

× C

bus

= 400 ns

Here R

bus

× C

bus

= 120 ns

4 kΩ

30 pF

SCL

SDA

SCL

SDA

Start

Condition

SDA

Input

SDA

Change

AI00792B

Stop

Condition

1 23 7 89

MSB

ACK

Start

Condition

SCL

1 23 7 89

MSB ACK

Stop

Condition

Figure 4. I2C Fast mode (fC = 400 kHz): maximum R

Figure 5. I

capacitance (C

C bus protocol

bus

)

value versus bus parasitic

bus

16/128 Doc ID 15170 Rev 14

M24LR64-R Signal description

Table 2. Device select code

Device type identifier

(1)

Chip Enable address

b7 b6 b5 b4 b3 b2 b1 b0

Device select code1010E2

1. The most significant bit, b7, is sent first.

2. E0 and E1 are compared against the respective external pins on the memory device.

3. E2 is not connected to any external pin. It is however used to address the M24LR64-R as described in

Section 3 and Section 4.

Table 3. Address most significant byte

(3)

E1 E0 RW

b15 b14 b13 b12 b11 b10 b9 b8

Table 4. Address least significant byte

b7 b6 b5 b4 b3 b2 b1 b0

(2)

Doc ID 15170 Rev 14 17/128

User memory organization M24LR64-R

3 User memory organization

The M24LR64-R is divided into 64 sectors of 32 blocks of 32 bits as shown in Tab l e 5 .

Figure 7 shows the memory sector organization. Each sector can be individually read-

and/or write-protected using a specific password command. Read and write operations are possible if the addressed data are not in a protected sector.

The M24LR64-R also has a 64-bit block that is used to store the 64-bit unique identifier (UID). The UID is compliant with the ISO 15963 description, and its value is used during the anticollision sequence (Inventory). This block is not accessible by the user and its value is written by ST on the production line.

The M24LR64-R includes an AFI register that stores the application family identifier, and a DSFID register that stores the data storage family identifier used in the anticollision algorithm.

The M24LR64-R has four additional 32-bit blocks that store an I password codes.

Figure 6. Block diagram

C password plus three RF

AC0

AC1

RF V

EEPROM

Row decoder

Latch

Logic

Power management

I2C

Contact V

SCL SDA

ai15123

18/128 Doc ID 15170 Rev 14

M24LR64-R User memory organization

0 1 Kbit EEPROM sector 5 bits

1 1 Kbit EEPROM sector 5 bits

2 1 Kbit EEPROM sector 5 bits

3 1 Kbit EEPROM sector 5 bits

60 1 Kbit EEPROM sector 5 bits

61 1 Kbit EEPROM sector 5 bits

62 1 Kbit EEPROM sector 5 bits

63 1 Kbit EEPROM sector 5 bits

I2C Password System

RF Password 1 System

RF Password 2 System

RF Password 3 System

8 bit DSFID System

8 bit AFI System

64 bit UID System

Sector Area Sector security status

ai15124

Figure 7. Memory sector organization

Sector details

The M24LR64-R user memory is divided into 64 sectors. Each sector contains 1024 bits. The protection scheme is described in Section 4: System memory area.

In RF mode, a sector provides 32 blocks of 32 bits. Each read and write access are done by block. Read and write block accesses are controlled by a Sector Security Status byte that defines the access rights to all the 32 blocks contained in the sector. If the sector is not protected, a Write command updates the complete 32 bits of the selected block.

In I

C mode, a sector provides 128 bytes that can be individually accessed in read and write modes. When protected by the corresponding I2C_Write_Lock bit, the entire sector is writeprotected. To access the user memory, the device select code used for any I must have the E2 Chip Enable address at 0.

C command

Doc ID 15170 Rev 14 19/128

User memory organization M24LR64-R

Table 5. Sector details

Sector

number

RF block

address

I2C byte

address

Bits [31:24] Bits [23:16] Bits [15:8] Bits [7:0]

0 0 user user user user

1 4 user user user user

2 8 user user user user

3 12 user user user user

4 16 user user user user

5 20 user user user user

6 24 user user user user

7 28 user user user user

8 32 user user user user

9 36 user user user user

10 40 user user user user

11 44 user user user user

12 48 user user user user

13 52 user user user user

14 56 user user user user

15 60 user user user user

16 64 user user user user

17 68 user user user user

18 72 user user user user

19 76 user user user user

20 80 user user user user

21 84 user user user user

22 88 user user user user

23 92 user user user user

24 96 user user user user

25 100 user user user user

26 104 user user user user

27 108 user user user user

28 112 user user user user

29 116 user user user user

30 120 user user user user

31 124 user user user user

20/128 Doc ID 15170 Rev 14

M24LR64-R User memory organization

Table 5. Sector details (continued)

Sector

number

... ... ... ... ... ... ...

RF block

address

32 128 user user user user

33 132 user user user user

34 136 user user user user

35 140 user user user user

36 144 user user user user

37 148 user user user user

38 152 user user user user

39 156 user user user user

... ... ... ... ... ...

I2C byte address

Bits [31:24] Bits [23:16] Bits [15:8] Bits [7:0]

Doc ID 15170 Rev 14 21/128

User memory organization M24LR64-R

Table 5. Sector details (continued)

Sector

number

RF block

address

2016 8064 user user user user

2017 8068 user user user user

2018 8072 user user user user

2019 8076 user user user user

2020 8080 user user user user

2021 8084 user user user user

2022 8088 user user user user

2023 8092 user user user user

2024 8096 user user user user

2025 8100 user user user user

2026 8104 user user user user

2027 8108 user user user user

2028 8112 user user user user

2029 8116 user user user user

2030 8120 user user user user

2031 8124 user user user user

2032 8128 user user user user

I2C byte address

Bits [31:24] Bits [23:16] Bits [15:8] Bits [7:0]

2033 8132 user user user user

2034 8136 user user user user

2035 8140 user user user user

2036 8144 user user user user

2037 8148 user user user user

2038 8152 user user user user

2039 8156 user user user user

2040 8160 user user user user

2041 8164 user user user user

2042 8168 user user user user

2043 8172 user user user user

2044 8176 user user user user

2045 8180 user user user user

2046 8184 user user user user

2047 8188 user user user user

22/128 Doc ID 15170 Rev 14

M24LR64-R System memory area

4 System memory area

4.1 M24LR64-R RF block security

The M24LR64-R provides a special protection mechanism based on passwords. Each memory sector of the M24LR64-R can be individually protected by one out of three available passwords, and each sector can also have Read/Write access conditions set.

Each memory sector of the M24LR64-R is assigned with a Sector security status byte including a Sector Lock bit, two Password Control bits and two Read/Write protection bits as shown in Ta bl e 7 . Tab le 6 describes the organization of the Sector security status byte which can be read using the Read Single Block and Read Multiple Block commands with the Option_flag set to ‘1’.

On delivery, the default value of the SSS bytes is reset to 00h.

Table 6. Sector Security Status Byte area

I2C byte address Bits [31:24] Bits [23:16] Bits [15:8] Bits [7:0]

E2 = 1 0 SSS 3 SSS 2 SSS 1 SSS 0

E2 = 1 4 SSS 7 SSS 6 SSS 5 SSS 4

E2 = 1 8 SSS 11 SSS 10 SSS 9 SSS 8

E2 = 1 12 SSS 15 SSS 14 SSS 13 SSS 12

E2 = 1 16 SSS 19 SSS 18 SSS 17 SSS 16

E2 = 1 20 SSS 23 SSS 22 SSS 21 SSS 20

E2 = 1 24 SSS 27 SSS 26 SSS 25 SSS 24

E2 = 1 28 SSS 31 SSS 30 SSS 29 SSS 28

E2 = 1 32 SSS 35 SSS 34 SSS 33 SSS 32

E2 = 1 36 SSS 39 SSS 38 SSS 37 SSS 36

E2 = 1 40 SSS 43 SSS 42 SSS 41 SSS 40

E2 = 1 44 SSS 47 SSS 46 SSS 45 SSS 44

E2 = 1 48 SSS 51 SSS 50 SSS 49 SSS 48

E2 = 1 52 SSS 55 SSS 54 SSS 53 SSS 52

E2 = 1 56 SSS 59 SSS 58 SSS 57 SSS 56

E2 = 1 60 SSS 63 SSS 62 SSS 61 SSS 60

Table 7. Sector security status byte organization

0 0 0 Password Control bits

Read / Write protection

bits

Sector

Lock

When the Sector Lock bit is set to ‘1’, for instance by issuing a Lock-sector Password command, the 2 Read/Write protection bits (b

, b2) are used to set the Read/Write access of

the sector as described in Ta b l e 8 .

Doc ID 15170 Rev 14 23/128

System memory area M24LR64-R

Table 8. Read / Write protection bit setting

Sector

Lock

Sector access when password

, b

presented

Sector access when password not

presented

0 xx Read Write Read Write

1 00 Read Write Read No Write

1 01 Read Write Read Write

1 10 Read Write No Read No Write

1 11 Read No Write No Read No Write

The next 2 bits of the Sector security status byte (b3, b4) are the Password Control bits. The value these two bits is used to link a password to the sector as defined in Ta b le 9 .

Table 9. Password Control bits

b4, b

Password

00 The sector is not protected by a Password

01 The sector is protected by the Password 1

10 The sector is protected by the Password 2

11 The sector is protected by the Password 3

The M24LR64-R password protection is organized around a dedicated set of commands plus a system area of three password blocks where the password values are stored. This system area is described in Ta bl e 1 0.

Table 10. Password system area

Block number 32-bit password number

1 Password 1

2 Password 2

3 Password 3

The dedicated password commands are:

● Write-sector Password:

The Write-sector Password command is used to write a 32-bit block into the password system area. This command must be used to update password values. After the write cycle, the new password value is automatically activated. It is possible to modify a password value after issuing a valid Present-sector Password command. On delivery, the three default password values are set to 0000 0000h and are activated.

● Lock-sector Password:

The Lock-sector Password command is used to set the Sector security status byte of the selected sector. Bits b

to b1 of the Sector security status byte are affected by the

Lock-sector Password command. The Sector Lock bit, b After issuing a Lock-sector Password command, the protection settings of the selected sector are activated. The protection of a locked block cannot be changed in RF mode. A Lock-sector Password command sent to a locked sector returns an error code.

24/128 Doc ID 15170 Rev 14

, is set to ‘1’ automatically.

M24LR64-R System memory area

● Present-sector Password:

The Present-sector Password command is used to present one of the three passwords to the M24LR64-R in order to modify the access rights of all the memory sectors linked to that password (Ta bl e 8 ) including the password itself. If the presented password is correct, the access rights remain activated until the tag is powered off or until a new Present-sector Password command is issued. If the presented password value is not correct, all the access rights of all the memory sectors are deactivated.

● Sector security status byte area access conditions in I

In I

C mode, read access to the Sector security status byte area is always allowed.

Write access depends on the correct presentation of the I

C mode:

C password (see I2C

Present Password command description on page 27).

To access the Sector security status byte area, the device select code used for any I

command must have the E2 Chip Enable address at 1.

An I

C write access to a Sector security status byte re-initializes the RF access

condition to the given memory sector.

4.2 Example of the M24LR64-R security protection

Ta bl e 1 1 and Ta bl e 1 2 show the sector security protections before and after a valid Present-

sector Password command. Tab le 1 1 shows the sector access rights of an M24LR64-R after power-up. After a valid Present-sector Password command with password 1, the memory sector access is changed as shown in Ta b le 12 .

Table 11. M24LR64-R sector security protection after power-up

Sector address

0 Protection: Standard Read No Write xxx 00001

1 Protection: Pswd 1 Read No Write xxx 01001

2 Protection: Pswd 1 Read Write xxx 01011

3 Protection: Pswd 1 No Read No Write xxx 01101

4 Protection: Pswd 1 No Read No Write xxx 01111

Table 12. M24LR64-R sector security protection after a valid presentation of

Sector security status byte

7b6b5b4b3b2b1b0

password 1

Sector address

0 Protection: Standard Read No Write xxx 0 0 0 0 1

1 Protection: Pswd 1 Read Write xxx 0 1 0 0 1

2 Protection: Pswd 1 Read Write xxx 0 1 0 1 1

3 Protection: Pswd 1 Read Write xxx 0 1 1 0 1

4 Protection: Pswd 1 Read No Write xxx 0 1 1 1 1

Sector security status byte

b7b6b5b4b3b2b1b

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System memory area M24LR64-R

4.3 I2C_Write_Lock bit area

In the I2C mode only, it is possible to protect individual sectors against Write operations. This feature is controlled by the I2C_Write_Lock bits stored in the 8 bytes of the I2C_Write_Lock bit area starting from the location 2048 (see Ta bl e 1 3 ). Using these 64 bits, it is possible to write-protect all the 64 sectors of the M24LR64-R memory.

Each bit controls the I possible to unprotect a sector in the I the corresponding sector is unprotected. When the bit is set to 1, the corresponding sector is write-protected.

In I

C mode, read access to the I2C_Write_Lock bit area is always allowed. Write access depends on the correct presentation of the I

To access the I2C_Write_Lock bit area, the device select code used for any I must have the E2 Chip Enable address at 1.

On delivery, the default value of the 8 bytes of the I2C_Write_Lock bit area is reset to 00h.

Table 13. I2C_Write_Lock bit

I2C byte address Bits [31:24] Bits [23:16] Bits [15:8] Bits [7:0]

E2 = 1 2048 sectors 31-24 sectors 23-16 sectors 15-8 sectors 7-0

E2 = 1 2052 sectors 63-56 sectors 55-48 sectors 47-40 sectors 39-32

C write access to a specific sector as shown in Ta b le 13 . It is always

C mode. When an I2C_Write_Lock bit is reset to 0,

C password.

C command

4.4 System parameters

The M24LR64-R provides the system area required by the ISO 15693 RF protocol, as shown in Ta bl e 1 4 .

The first 32-bit block starting from I is used to activate/deactivate the write protection of the protected sector in I power-on, all user memory sectors protected by the I2C_Write_Lock bits can be read but cannot be modified. To remove the write protection, it is necessary to use the I Password described in Figure 8. When the password is correctly presented — that is, when all the presented bits correspond to the stored ones — it is also possible to modify the I password using the I

The next three 32-bit blocks store the three RF passwords. These passwords are neither read- nor write- accessible in the I

The next 2 bytes are used to store the AFI, at I location 2323. These 2 values are used during the RF Inventory sequence. They are readonly in the I

C mode.

The next 8 bytes, starting from location 2324, store the 64-bit UID programmed by ST on the production line. Bytes at I used by the RF Get_System_Info command. The UID, Mem_Size and IC Ref values are read-only data.

C Write Password command described in Figure 9.

C locations 2332 to 2335 store the IC Ref and the Mem_Size data

C address 2304 stores the I2C password. This password

C mode.

C location 2322, and the DSFID, at I2C

C mode. At

C Present

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M24LR64-R System memory area

Table 14. System parameter sector

I2C byte address Bits [31:24] Bits [23:16] Bits [15:8] Bits [7:0]

E2 = 1 2304 I

E2 = 1 2308 RF password 1

E2 = 1 2312 RF password 2

E2 = 1 2316 RF password 3

E2 = 1 2320 DSFID (FFh) AFI (00h) ST reserved ST reserved

E2 = 1 2324 UID UID UID UID

E2 = 1 2328 UID (E0h) UID (02h) UID UID

E2 = 1 2332 Mem_Size (03 07FFh) IC Ref (2Ch)

1. Delivery state: I2C password= 0000 0000h, RF password = 0000 0000h,

C password

(1)

4.5 M24LR64-R I2C password security

The M24LR64-R controls I2C sector write access using the 32-bit-long I2C password and the 64-bit I2C_Write_Lock bit area. The I commands: I

C Present Password and I2C Write Password.

C password value is managed using two I2C

4.5.1 I2C Present Password command description

The I2C Present Password command is used in I2C mode to present the password to the M24LR64-R in order to modify the write access rights of all the memory sectors protected by the I2C_Write_Lock bits, including the password itself. If the presented password is correct, the access rights remain activated until the M24LR64-R is powered off or until a new I Present Password command is issued.

Following a Start condition, the bus master sends a device select code with the Read/Write bit (RW in Figure 8, and waits for two I responds to each address byte with an acknowledge bit, and then waits for the 4 password data bytes, the validation code, 09h, and a resend of the 4 password data bytes. The most significant byte of the password is sent first, followed by the least significant bytes.

It is necessary to send the 32-bit password twice to prevent any data corruption during the sequence. If the two 32-bit passwords sent are not exactly the same, the M24LR64-R does not start the internal comparison.

When the bus master generates a Stop condition immediately after the Ack bit (during the “10 condition at any other time does not trigger the internal delay. During that delay, the M24LR64-R compares the 32 received data bits with the 32 bits of the stored I If the values match, the write access rights to all protected sectors are modified after the internal delay. If the values do not match, the protected sectors remains protected.

) reset to 0 and the Chip Enable bit E2 at 1. The device acknowledges this, as shown

bit” time slot), an internal delay equivalent to the write cycle time is triggered. A Stop

C password address bytes 09h and 00h. The device

C password.

During the internal delay, Serial Data (SDA) is disabled internally, and the device does not respond to any requests.

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System memory area M24LR64-R

ai15125b

Start

Device select

code

Password

address 09h

Password

address 00h

Password

[31:24]

Ack

R/W

Ack Ack Ack

Device select code = 1010 1 E1 E0

Password

[23:16]

Password

[15:8]

Password

[7:0]

Ack Ack Ack

Ack generated during

bit time slot.

Stop

Validation

code 09h

Ack

Password

[31:24]

Ack

Password

[23:16]

Password

[15:8]

Password

[7:0]

Ack Ack Ack

Figure 8. I2C Present Password command

4.5.2 I2C Write Password command description

The I2C Write Password command is used to write a 32-bit block into the M24LR64-R I2C password system area. This command is used in I value. It cannot be used to update any of the RF passwords. After the write cycle, the new

C password value is automatically activated. The I2C password value can only be modified

after issuing a valid I

On delivery, the I

C Present Password command.

C default password value is set to 0000 0000h and is activated.

C mode to update the I2C password

Following a Start condition, the bus master sends a device select code with the Read/Write bit (RW in Figure 9, and waits for the two I

) reset to 0 and the Chip Enable bit E2 at 1. The device acknowledges this, as shown

C password address bytes, 09h and 00h. The device responds to each address byte with an acknowledge bit, and then waits for the 4 password data bytes, the validation code, 07h, and a resend of the 4 password data bytes. The most significant byte of the password is sent first, followed by the least significant bytes.

It is necessary to send twice the 32-bit password to prevent any data corruption during the write sequence. If the two 32-bit passwords sent are not exactly the same, the M24LR64-R does not modify the I

When the bus master generates a Stop condition immediately after the Ack bit (during the

bit time slot), the internal write cycle is triggered. A Stop condition at any other time

C password value.

does not trigger the internal write cycle.

During the internal write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests.

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M24LR64-R System memory area

Figure 9. I2C Write Password command

Ack

Ack Ack Ack

Device select

code

Start

Validation

code 07h

Device select code = 1010 1 E1 E0 Ack generated during

Password

address 09h

R/W

Ack

New password

[31:24]

Ack

bit time slot.

Password

address 00h

New password

[23:16]

New password

[31:24]

Ack Ack Ack

New password

[15:8]

New password

[23:16]

New password

[7:0]

New password

[15:8]

Stop

New password

[7:0]

ai15126

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I2C device operation M24LR64-R

5 I2C device operation

The device supports the I2C protocol. This is summarized in Figure 5. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24LR64-R device is always a slave in all communications.

5.1 Start condition

Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer command. The device continuously monitors (except during a write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given.

5.2 Stop condition

Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Standby mode. A Stop condition at the end of a Write command triggers the internal write cycle.

5.3 Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9 acknowledge the receipt of the eight data bits.

clock pulse period, the receiver pulls Serial Data (SDA) low to

5.4 Data Input

During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven low.

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