ST M24LR16E-R User Manual

M24LR16E-R

16-bit EEPROM with password protection, dual interface & energy harvesting: 400 kHz I²C bus & ISO 15693 RF protocol at 13.56 MHz

Features

I2C interface

■Two-wire I2C serial interface supports 400 kHz protocol

■Single supply voltage:

– 1.8 V to 5.5 V

■Byte and Page Write (up to 4 bytes)

■Random and Sequential read modes

■Self-timed programming cycle

■Automatic address incrementing

■Enhanced ESD/latch-up protection

■I²C timeout

Contactless interface

■ISO 15693 and ISO 18000-3 mode 1 compatible

■13.56 MHz ±7k Hz carrier frequency

■To tag: 10% or 100% ASK modulation using 1/4 (26 Kbit/s) or 1/256 (1.6 Kbit/s) pulse position coding

■From tag: load modulation using Manchester coding with 423 kHz and 484 kHz subcarriers in low (6.6 kbit/s) or high (26 kbit/s) data rate mode. Supports the 53 kbit/s data rate with Fast commands

■Internal tuning capacitance: 27.5pF

■64-bit unique identifier (UID)

■Read Block & Write (32-bit blocks)

Datasheet −production data

SO8 (MN) 150 mils width

UFDFPN8 (MC) 2 x 3 mm

TSSOP8 (DW)

Sawn wafer on UV tape

Memory

■16-Kbit EEPROM organized into:

–2048 bytes in I2C mode

–512 blocks of 32 bits in RF mode

■Write time

–I2C: 5 ms (max.)

–RF: 5.75 ms including the internal Verify time

Digital output pin

■User configurable pin: RF write in progress or RF busy mode

Energy harvesting

■Analog pin for energy harvesting

■4 sink current configurable ranges

■More than 1 million write cycles

■More than 40-year data retention

■Multiple password protection in RF mode

■Single password protection in I2C mode

■Package

–ECOPACK2® (RoHS compliant and Halogen-free)

June 2012

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This is information on a product in full production.

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Contents	M24LR16E-R

Contents

1	Description .		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
2	Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			15
	2.1	Serial clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
	2.2	Serial data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
	2.3	RF Write in progress / RF Busy (RF WIP/BUSY) . . . . . . . . . . . . . . . . . . .		15
	2.4	Energy harvesting analog output (Vout) . . . . . . . . . . . . . . . . . . . . . . . . . .		15
	2.5	Antenna coil (AC0, AC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
		2.5.1	Device reset in RF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
	2.6	VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
	2.7	Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16

2.7.1 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.7.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.7.3 Device reset in I²C mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.7.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3	User memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			19
4	System memory area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			24
	4.1	M24LR16E-R block security in RF mode . . . . . . . . . . . . . . . . . . . . . . . . .		24
		4.1.1	Example of the M24LR16E-R security protection in RF mode . . . . . . .	26
	4.2	M24LR16E-R block security in I²C mode (I2C_Write_Lock bit area) . . . . 27
	4.3	Configuration byte and Control register . . . . . . . . . . . . . . . . . . . . . . . . . .		27
		4.3.1	RF WIP/BUSY pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
		4.3.2	Energy harvesting configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
		4.3.3	FIELD_ON indicator bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29
		4.3.4	Configuration byte access in I²C and RF modes . . . . . . . . . . . . . . . . . .	30
		4.3.5	Control register access in I²C or RF mode . . . . . . . . . . . . . . . . . . . . . .	30
	4.4	ISO 15693 system parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		30
5	I2C device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			32
	5.1	Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		32
	5.2	Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		32

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5.3 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.5 I²C timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.5.1 I²C timeout on Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.5.2 I²C timeout on clock period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.6 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.7 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.8 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.9 Page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.10 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 37 5.11 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.12 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.13 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.14 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.15 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.16 M24LR16E-R I2C password security . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.16.1 I2C present password command description . . . . . . . . . . . . . . . . . . . . . 40 5.16.2 I2C write password command description . . . . . . . . . . . . . . . . . . . . . . . 41

6	M24LR16E-R memory initial state . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		42
7	RF device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		43
	7.1	RF communication and energy harvesting . . . . . . . . . . . . . . . . . . . . . . . .	43
	7.2	Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	44
	7.3	Initial dialog for vicinity cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	45

7.3.1 Power transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.3.2 Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.3.3 Operating field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8	Communication signal from VCD to M24LR16E-R . . . . . . . . . . . . . . . .			46
9	Data rate and data coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			48
	9.1	Data coding mode:	1 out of 256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	48
	9.2	Data coding mode:	1 out of 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
	9.3	VCD to M24LR16E-R frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		51

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9.4 Start of frame (SOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10	Communication signal from M24LR16E-R to VCD . . . . . . . . . . . . . . . .		53
	10.1	Load modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	53
	10.2	Subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	53
	10.3	Data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	53

11	Bit representation and coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			54
	11.1	Bit coding using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		54
		11.1.1	High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	54
		11.1.2	Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	55
	11.2	Bit coding using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		56
		11.2.1	High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	56
		11.2.2	Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	56

12	M24LR16E-R to VCD frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	57
	12.1 SOF when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	57

12.1.1 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.1.2 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

12.2 SOF when using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

12.2.1 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.2.2 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

12.3 EOF when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

12.3.1 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.3.2 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

12.4 EOF when using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

12.4.1 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12.4.2 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

13	Unique identifier (UID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	61
14	Application family identifier (AFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	62
15	Data storage format identifier (DSFID) . . . . . . . . . . . . . . . . . . . . . . . . .	63
	15.1 CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	63
16	M24LR16E-R protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	64

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17	M24LR16E-R states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		66
	17.1	Power-off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	66
	17.2	Ready state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	66
	17.3	Quiet state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	66
	17.4	Selected state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	66

18	Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		68
	18.1	Addressed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	68
	18.2	Non-addressed mode (general request) . . . . . . . . . . . . . . . . . . . . . . . . .	68
	18.3	Select mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	68

19	Request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		69
	19.1	Request flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	69
20	Response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		71
	20.1	Response flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	71
	20.2	Response error code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	72
21	Anticollision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		73
	21.1	Request parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	73
22	Request processing by the M24LR16E-R . . . . . . . . . . . . . . . . . . . . . . .		75
23	Explanation of the possible cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		76
24	Inventory Initiated command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		78
25	Timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		79
	25.1	t1: M24LR16E-R response delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	79
	25.2	t2: VCD new request delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	79
	25.3	t3: VCD new request delay when no response is received
		from the M24LR16E-R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	79
26	Command codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		80
	26.1	Inventory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	81
	26.2	Stay Quiet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	83

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	26.3	Read Single Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . 84
	26.4	Write Single Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 85
	26.5	Read Multiple Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 89
	26.6	Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 90
	26.7	Reset to Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 92
	26.8	Write AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 93
	26.9	Lock AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 94
	26.10	Write DSFID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 96
	26.11	Lock DSFID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 97
	26.12	Get System Info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 99
	26.13	Get Multiple Block Security Status . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 101
	26.14	Write-sector Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 102
	26.15	Lock-sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 104
	26.16	Present-sector Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 105
	26.17	Fast Read Single Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 108
	26.18	Fast Inventory Initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 109
	26.19	Fast Initiate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 111
	26.20	Fast Read Multiple Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 112
	26.21	Inventory Initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 113
	26.22	Initiate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 115
	26.23	ReadCfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 116
	26.24	WriteEHCfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 117
	26.25	WriteDOCfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 118
	26.26	SetRstEHEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 120
	26.27	CheckEHEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 121
27	Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . 123
28	I2C DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . 124
29	RF electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . 128
30	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . 134
31	Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . 137

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Appendix A Anticollision algorithm (informative) . . . . . . . . . . . . . . . . . . . .		. . . 138
A.1	Algorithm for pulsed slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 138
Appendix B	CRC (informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 139
B.1	CRC error detection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 139
B.2	CRC calculation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 139

Appendix C Application family identifier (AFI) (informative) . . . . . . . . . . . . . . 141

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

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List of tables	M24LR16E-R

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 2. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 3. Address most significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 4. Address least significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 5. Sector details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 6. Sector security status byte area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 7. Sector security status byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 8. Read / Write protection bit setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 9. Password control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 10. Password system area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 11. M24LR16E-R sector security protection after power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 12. M24LR16E-R sector security protection after a valid presentation of password 1 . . . . . . . 26 Table 13. I2C_Write_Lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 14. Configuration byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 15. Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 16. EH_enable bit value after power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 17. System parameter sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 18. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 19. 10% modulation parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 20. Response data rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 21. UID format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 22. CRC transmission rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 23. VCD request frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 24. M24LR16E-R Response frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 25. M24LR16E-R response depending on Request_flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 26. General request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 27. Definition of request flags 1 to 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 28. Request flags 5 to 8 when Bit 3 = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 29. Request flags 5 to 8 when Bit 3 = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 30. General response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 31. Definitions of response flags 1 to 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 32. Response error code definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 33. Inventory request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 34. Example of the addition of 0-bits to an 11-bit mask value . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 35. Timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 36. Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 37. Inventory request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 38. Inventory response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 39. Stay Quiet request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 40. Read Single Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 41. Read Single Block response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . 84 Table 42. Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 43. Read Single Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 44. Write Single Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 45. Write Single Block response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . 85 Table 46. Write Single Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 47. Read Multiple Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 48. Read Multiple Block response format when Error_flag is NOT set. . . . . . . . . . . . . . . . . . . 89

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Table 49. Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 50. Read Multiple Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . 90 Table 51. Select request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 52. Select Block response format when Error_flag is NOT set. . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 53. Select response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 54. Reset to Ready request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 55. Reset to Ready response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . 92 Table 56. Reset to ready response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 57. Write AFI request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 58. Write AFI response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 59. Write AFI response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 60. Lock AFI request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 61. Lock AFI response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 62. Lock AFI response format when Error_flag is set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 63. Write DSFID request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 64. Write DSFID response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 65. Write DSFID response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 66. Lock DSFID request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 67. Lock DSFID response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 68. Lock DSFID response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 69. Get System Info request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 70. Get System Info response format when Protocol_extension_flag = 0 and

Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 71. Get System Info response format when Protocol_extension_flag = 1 and

Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 72. Get System Info response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 73. Get Multiple Block Security Status request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 74. Get Multiple Block Security Status response format when Error_flag is NOT set . . . . . . 101 Table 75. Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 76. Get Multiple Block Security Status response format when Error_flag is set . . . . . . . . . . . 102 Table 77. Write-sector Password request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 78. Write-sector Password response format when Error_flag is NOT set . . . . . . . . . . . . . . . 103 Table 79. Write-sector Password response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . 103 Table 80. Lock-sector request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 81. Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 82. Lock-sector response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 83. Lock-sector response format when Error_flag is set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 84. Present-sector Password request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 85. Present-sector Password response format when Error_flag is NOT set . . . . . . . . . . . . . 106 Table 86. Present-sector Password response format when Error_flag is set . . . . . . . . . . . . . . . . . . 106 Table 87. Fast Read Single Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 88. Fast Read Single Block response format when Error_flag is NOT set . . . . . . . . . . . . . . . 108 Table 89. Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 90. Fast Read Single Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . 108 Table 91. Fast Inventory Initiated request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 92. Fast Inventory Initiated response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 93. Fast Initiate request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 94. Fast Initiate response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 95. Fast Read Multiple Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 96. Fast Read Multiple Block response format when Error_flag is NOT set. . . . . . . . . . . . . . 112 Table 97. Sector security status if Option_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 98. Fast Read Multiple Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . 113

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Table 99. Inventory Initiated request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 100. Inventory Initiated response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 101. Initiate request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 102. Initiate Initiated response format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 103. ReadCfg request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 104. ReadCfg response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 105. ReadCfg response format when Error_flag is set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 106. WriteEHCfg request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 107. WriteEHCfg response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 108. WriteEHCfg response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 109. WriteDOCfg request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 110. WriteDOCfg response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 111. WriteDOCfg response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 112. SetRstEHEn request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 113. SetRstEHEn response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . 120 Table 114. SetRstEHEn response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 115. CheckEHEn request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 116. CheckEHEn response format when Error_flag is NOT set. . . . . . . . . . . . . . . . . . . . . . . . 121 Table 117. CheckEHEn response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 118. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Table 119. I2C operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 120. AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 121. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 122. I2C DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 123. I2C AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 124. RF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 125. Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 126. Energy harvesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Table 127. SO8N – 8-lead plastic small outline, 150 mils body width, package data. . . . . . . . . . . . . 134 Table 128. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead

2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 129. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . 136 Table 130. Ordering information scheme for packaged devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Table 131. CRC definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Table 132. AFI coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Table 133. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

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List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 3. I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic

capacitance (Cbus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 4. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 5. Circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 6. Memory sector organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 7. I²C timeout on Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 8. Write mode sequences with I2C_Write_Lock bit = 1 (data write inhibited). . . . . . . . . . . . . 34 Figure 9. Write mode sequences with I2C_Write_Lock bit = 0 (data write enabled) . . . . . . . . . . . . . 36 Figure 10. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 11. Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 12. I2C present password command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 13. I2C write password command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 14. 100% modulation waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 15. 10% modulation waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 16. 1 out of 256 coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 17. Detail of a time period. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 18. 1 out of 4 coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 19. 1 out of 4 coding example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 20. SOF to select 1 out of 256 data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 21. SOF to select 1 out of 4 data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 22. EOF for either data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 23. Logic 0, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 24. Logic 0, high data rate, fast commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 25. Logic 1, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 26. Logic 1, high data rate, fast commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 27. Logic 0, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 28. Logic 0, low data rate, fast commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 29. Logic 1, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 30. Logic 1, low data rate, fast commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 31. Logic 0, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 32. Logic 1, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 33. Logic 0, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 34. Logic 1, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 35. Start of frame, high data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 36. Start of frame, high data rate, one subcarrier, fast commands. . . . . . . . . . . . . . . . . . . . . . 57 Figure 37. Start of frame, low data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 38. Start of frame, low data rate, one subcarrier, fast commands . . . . . . . . . . . . . . . . . . . . . . 58 Figure 39. Start of frame, high data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 40. Start of frame, low data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 41. End of frame, high data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 42. End of frame, high data rate, one subcarrier, fast commands . . . . . . . . . . . . . . . . . . . . . . 59 Figure 43. End of frame, low data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 44. End of frame, low data rate, one subcarrier, Fast commands . . . . . . . . . . . . . . . . . . . . . . 59 Figure 45. End of frame, high data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 46. End of frame, low data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 47. M24LR16E-R decision tree for AFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

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List of figures	M24LR16E-R

Figure 48. M24LR16E-R protocol timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 49. M24LR16E-R state transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 50. Principle of comparison between the mask, the slot number and the UID . . . . . . . . . . . . . 74 Figure 51. Description of a possible anticollision sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 52. M24LR16 RF-Busy management following Inventory command . . . . . . . . . . . . . . . . . . . . 82 Figure 53. Stay Quiet frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . . . . . . . 83 Figure 54. Read Single Block frame exchange between VCD and M24LR16E-R. . . . . . . . . . . . . . . . 85 Figure 55. Write Single Block frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . 86 Figure 56. M24LR16 RF-Busy management following Write command . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 57. M24LR16 RF-Wip management following Write command . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure 58. Read Multiple Block frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . 90 Figure 59. Select frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 60. Reset to Ready frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . . . 92 Figure 61. Write AFI frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 62. Lock AFI frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 63. Write DSFID frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . . . . . 97 Figure 64. Lock DSFID frame exchange between VCD and M24LR16E-R. . . . . . . . . . . . . . . . . . . . . 98 Figure 65. Get System Info frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . 100 Figure 66. Get Multiple Block Security Status frame exchange between VCD and M24LR16E-R . . 102 Figure 67. Write-sector Password frame exchange between VCD and M24LR16E-R . . . . . . . . . . . 103 Figure 68. Lock-sector frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . . . . . 105 Figure 69. Present-sector Password frame exchange between VCD and M24LR16E-R . . . . . . . . . 107 Figure 70. Fast Read Single Block frame exchange between VCD and M24LR16E-R. . . . . . . . . . . 109 Figure 71. Fast Initiate frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . . . . . 111 Figure 72. Fast Read Multiple Block frame exchange between VCD and M24LR16E-R . . . . . . . . . 113 Figure 73. Initiate frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . . . . . . . . . 115 Figure 74. ReadCfg frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . . . . . . . 116 Figure 75. WriteEHCfg frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . . . . . 118 Figure 76. WriteDOCfg frame exchange between VCD and M24LR16E-R. . . . . . . . . . . . . . . . . . . . 119 Figure 77. SetRstEHEn frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . . . . 121 Figure 78. CheckEHEn frame exchange between VCD and M24LR16E-R. . . . . . . . . . . . . . . . . . . . 122

Figure 79. AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Figure 80. I2C AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 81. ASK modulated signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Figure 82. Vout min vs. Isink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure 83. Range 11 domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure 84. Range 10 domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Figure 85. Range 01 domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Figure 86. Range 00 domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Figure 87. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . 134 Figure 88. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead

2 × 3mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Figure 89. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . 136

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M24LR16E-R	Description

1 Description

The M24LR16E-R device is a dual-interface, electrically erasable programmable memory (EEPROM). It features an I2C interface and can be operated from a VCC power supply. It is also a contactless memory powered by the received carrier electromagnetic wave. The M24LR16E-R is organized as 2048 × 8 bits in the I2C mode and as 512 × 32 bits in the ISO 15693 and ISO 18000-3 mode 1 RF mode.

The M24LR16E-R also features an energy harvesting analog output, as well as a userconfigurable digital output pin toggling during either RF write in progress or RF busy mode.

Figure 1. Logic diagram

		VCC
SCL							Vout
SDA		M24LR16E-R
AC0
AC1							RF WIP/
							#64:
		VSS
							MS19740V1

I2C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The devices carry a built-in 4-bit device type identifier code (1010) in accordance with the I2C bus definition.

The device behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a device select code and Read/Write bit (RW) (as described in Table 2), terminated by an acknowledge bit.

When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.

In the ISO15693/ISO18000-3 mode 1 RF mode, the M24LR16E-R is accessed via the 13.56 MHz carrier electromagnetic wave on which incoming data are demodulated from the received signal amplitude modulation (ASK: amplitude shift keying). When connected to an antenna, the operating power is derived from the RF energy and no external power supply is required. The received ASK wave is 10% or 100% modulated with a data rate of 1.6 Kbit/s

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Description	M24LR16E-R

using the 1/256 pulse coding mode or a data rate of 26 Kbit/s using the 1/4 pulse coding mode.

Outgoing data are generated by the M24LR16E-R load variation using Manchester coding with one or two subcarrier frequencies at 423 kHz and 484 kHz. Data are transferred from the M24LR16E-R at 6.6 Kbit/s in low data rate mode and 26 Kbit/s high data rate mode. The M24LR16E-R supports the 53 Kbit/s fast mode in high data rate mode using one subcarrier frequency at 423 kHz.

The M24LR16E-R follows the ISO 15693 and ISO 18000-3 mode 1 recommendation for radio-frequency power and signal interface.

The M24LR16E-R provides an Energy harvesting mode on the analog output pin Vout. When the Energy harvesting mode is activated, the M24LR16E-R can output the excess energy coming from the RF field on the Vout analog pin. In case the RF field strength is insufficient or when Energy harvesting mode is disabled, the analog output pin Vout goes into high-Z state and Energy harvesting mode is automatically stopped.

The M24LR16E-R features a user configurable digital out pin RF WIP/BUSY that can be used to drive a micro controller interrupt input pin (available only when the M24LR16E-R is correctly powered on the Vcc pin).

When configured in the RF write in progress mode (RF WIP mode), the RF WIP/BUSY pin is driven low for the entire duration of the RF internal write operation. When configured in the RF busy mode (RF BUSY mode), the RF WIP/BUSY pin is driven low for the entire duration of the RF command progress.

The RF WIP/BUSY pin is an open drain output and must be connected to a pull-up resistor.

Table 1.	Signal names
	Signal name	Function	Direction
Vout		Energy harvesting Output	Analog output
SDA		Serial Data	I/O
SCL		Serial Clock	Input
AC0, AC1		Antenna coils	I/O
VCC		Supply voltage
RF WIP/BUSY		Digital signal	Digital output
VSS		Ground

Figure 2. 8-pin package connections

Vout				1	8		VCC
AC0			2		7		RF WIP/BUSY
AC1			3		6		SCL
VSS		4			5		SDA	MS19742V1

1. See Section 30 for package dimensions, and how to identify pin-1.

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M24LR16E-R	Signal descriptions

2 Signal descriptions

2.1Serial clock (SCL)

This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output.

2.2Serial data (SDA)

This bidirectional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated).

2.3RF Write in progress / RF Busy (RF WIP/BUSY)

This configurable output signal is used either to indicate that the M24LR16E-R is executing an internal write cycle from the RF channel or that an RF command is in progress. RF WIP and signals are available only when the M24LR16E-R is powered by the Vcc pin. It is an open drain output and a pull up resistor must be connected from RF WIP/BUSY to VCC.

2.4Energy harvesting analog output (Vout)

This analog output pin is used to deliver the analog voltage Vout available when the Energy harvesting mode is enabled and the RF field strength is sufficient. When the Energy harvesting mode is disabled or the RF field strength is not sufficient, the energy harvesting analog voltage output Vout is in High-Z state.

2.5Antenna coil (AC0, AC1)

These inputs are used to connect the device to an external coil exclusively. It is advised not to connect any other DC or AC path to AC0 or AC1.

When correctly tuned, the coil is used to power and access the device using the ISO 15693 and ISO 18000-3 mode 1 protocols.

2.5.1Device reset in RF mode

To ensure a proper reset of the RF circuitry, the RF field must be turned off (100% modulation) for a minimum tRF_OFF period of time.

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Signal descriptions	M24LR16E-R

2.6VSS ground

VSS is the reference for the VCC supply voltage and Vout analog output voltage.

2.7Supply voltage (VCC)

	This pin can be connected to an external DC supply voltage.
Note:	An internal voltage regulator allows the external voltage applied on VCC to supply the
	M24LR16E-R, while preventing the internal power supply (rectified RF waveforms) to output
	a DC voltage on the VCC pin.

2.7.1 Operating supply voltage VCC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 119). To maintain a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF) close to the VCC/VSS package pins.

This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal I²C write cycle (tW).

2.7.2Power-up conditions

When the power supply is turned on, VCC rises from VSS to VCC. The VCC rise time must not vary faster than 1V/µs.

2.7.3Device reset in I²C mode

In order to prevent inadvertent write operations during power-up, a power-on reset (POR) circuit is included. At power-up (continuous rise of VCC), the device does not respond to any I²C instruction until VCC has reached the power-on reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Table 119). When VCC passes over the POR threshold, the device is reset and enters the Standby power mode. However, the device must not be accessed until VCC has reached a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range.

In a similar way, during power-down (continuous decrease in VCC), as soon as VCC drops below the power-on reset threshold voltage, the device stops responding to any instruction sent to it.

2.7.4Power-down conditions

During power-down (continuous decay of VCC), the device must be in Standby power mode (mode reached after decoding a Stop condition, assuming that there is no internal write cycle in progress).

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M24LR16E-R	Signal descriptions

Figure 3. I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic capacitance (Cbus)

resistor	100
						When tLOW = 1.3 µs (min value for
p						fC = 400 kHz), the Rbus × Cbus		VCC
upll-u (k )						time constant must be below the
						represented on the left.
		R				400 ns time constant line
	10
		bus
line		×	C					Rbus
	Here Rbus × Cbus	= 120 ns	bus =	400
Bus	4 kΩ				n
					s	I²C bus	SCL
								M24xxx
						master
	1						SDA
	30 pF							Cbus
	10		100			1000
		Bus line capacitor (pF)

						ai14796b
Figure 4. I2C bus protocol
SCL
SDA
	Start		SDA	SDA		Stop
			Input	Change
	Condition					Condition
SCL	1	2	3	7	8	9
SDA	MSB					ACK
	Start
	Condition
SCL	1	2	3	7	8	9
SDA	MSB					ACK
						Stop
						Condition
						AI00792B

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Signal descriptions

M24LR16E-R

Table 2.

Device select code

Device type identifier(1)

Chip Enable address

RW

b7

b6

b5

b4

b3

b2

b1

b0

Device select code

1

0

1

0

E2(2)

1

1

RW

1.The most significant bit, b7, is sent first.

2.E2 is not connected to any external pin. It is however used to address the M24LR16E-R as described in

Section 3 and Section 4.

Table 3.	Address most significant byte
b15	b14	b13	b12	b11	b10	b9	b8
Table 4.	Address least significant byte
b7	b6	b5	b4	b3	b2	b1	b0

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M24LR16E-R	User memory organization

3 User memory organization

The M24LR16E-R is divided into 16 sectors of 32 blocks of 32 bits, as shown in Table 5. Figure 6 shows the memory sector organization. Each sector can be individually readand/or write-protected using a specific password command. Read and write operations are possible if the addressed data are not in a protected sector.

The M24LR16E-R also has a 64-bit block that is used to store the 64-bit unique identifier (UID). The UID is compliant with the ISO 15963 description, and its value is used during the anticollision sequence (Inventory). This block is not accessible by the user and its value is written by ST on the production line.

The M24LR16E-R includes an AFI register that stores the application family identifier, and a DSFID register that stores the data storage family identifier used in the anticollision algorithm.

The M24LR16E-R has four 32-bit blocks that store an I2C password plus three RF password codes.

Figure 5. Circuit diagram

AC0

RF

AC1

RF VCC

Row decoder

Vout

EEPROM

RF WIP/BUSY

Latch
						SCL
Logic			2	C
			I			SDA

Power management Contact VCC

VCC

VSS

MS19780V1

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	User memory organization				M24LR16E-R
		Figure 6. Memory sector organization
		Sector		Area	Sector security
					status
		0			5 bits
				1 Kbit EEPROM sector
		1		1 Kbit EEPROM sector	5 bits
		2			5 bits
				1 Kbit EEPROM sector
		3			5 bits
				1 Kbit EEPROM sector
		12			5 bits
				1 Kbit EEPROM sector
		13		1 Kbit EEPROM sector	5 bits
		14		1 Kbit EEPROM sector	5 bits
		15		1 Kbit EEPROM sector	5 bits
				I²C password	System
				RF password 1	System
				RF password 2	System
				RF password 3
					System
				8-bit DSFID
					System
				8-bit AFI
					System
				64-bit UID
				8-bit configuration	System
				16-bit I²C Write Lock_bit	System
				80-bit SSS	System
					MS19741V1

Sector details

The M24LR16E-R user memory is divided into 16 sectors. Each sector contains 1024 bits. The protection scheme is described in Section 4: System memory area.

In RF mode, a sector provides 32 blocks of 32 bits. Each read and write access is done by block. Read and write block accesses are controlled by a Sector Security Status byte that defines the access rights to the 32 blocks contained in the sector. If the sector is not protected, a Write command updates the complete 32 bits of the selected block.

In I2C mode, a sector provides 128 bytes that can be individually accessed in Read and Write modes. When protected by the corresponding I2C_Write_Lock bit, the entire sector is write-protected. To access the user memory, the device select code used for any I2C command must have the E2 Chip Enable address at 0.

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	Table 5.	Sector details
	Sector	RF block	I2C byte	Bits [31:24]	Bits [23:16]		Bits [15:8]	Bits [7:0]
	number	address	address
		0	0	user	user		user	user
		1	4	user	user		user	user
		2	8	user	user		user	user
		3	12	user	user		user	user
		4	16	user	user		user	user
		5	20	user	user		user	user
		6	24	user	user		user	user
		7	28	user	user		user	user
		8	32	user	user		user	user
		9	36	user	user		user	user
		10	40	user	user		user	user
		11	44	user	user		user	user
		12	48	user	user		user	user
		13	52	user	user		user	user
		14	56	user	user		user	user
	0	15	60	user	user		user	user
		16	64	user	user		user	user
		17	68	user	user		user	user
		18	72	user	user		user	user
		19	76	user	user		user	user
		20	80	user	user		user	user
		21	84	user	user		user	user
		22	88	user	user		user	user
		23	92	user	user		user	user
		24	96	user	user		user	user
		25	100	user	user		user	user
		26	104	user	user		user	user
		27	108	user	user		user	user
		28	112	user	user		user	user
		29	116	user	user		user	user
		30	120	user	user		user	user
		31	124	user	user		user	user

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	Table 5.	Sector details (continued)
	Sector	RF block	I2C byte	Bits [31:24]	Bits [23:16]	Bits [15:8]	Bits [7:0]
	number	address	address
		32	128	user	user	user	user
		33	132	user	user	user	user
		34	136	user	user	user	user
		35	140	user	user	user	user
	1
		36	144	user	user	user	user
		37	148	user	user	user	user
		38	152	user	user	user	user
		39	156	user	user	user	user
		...	...	...	...	...	...
	...	...	...	...	...	...	...

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	Table 5.	Sector details (continued)
	Sector	RF block	I2C byte	Bits [31:24]	Bits [23:16]		Bits [15:8]	Bits [7:0]
	number	address	address
		480	1920	user	user		user	user
		481	1924	user	user		user	user
		482	1928	user	user		user	user
		483	1932	user	user		user	user
		484	1936	user	user		user	user
		485	1940	user	user		user	user
		486	1944	user	user		user	user
		487	1948	user	user		user	user
		488	1952	user	user		user	user
		489	1956	user	user		user	user
		490	1960	user	user		user	user
		491	1964	user	user		user	user
		492	1968	user	user		user	user
		493	1972	user	user		user	user
		494	1976	user	user		user	user
	15	495	1980	user	user		user	user
		496	1984	user	user		user	user
		497	1988	user	user		user	user
		498	1992	user	user		user	user
		499	1996	user	user		user	user
		500	2000	user	user		user	user
		501	2004	user	user		user	user
		502	2008	user	user		user	user
		503	2012	user	user		user	user
		504	2016	user	user		user	user
		505	2020	user	user		user	user
		506	2024	user	user		user	user
		507	2028	user	user		user	user
		508	2032	user	user		user	user
		509	2036	user	user		user	user
		510	2040	user	user		user	user
		511	2044	user	user		user	user

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4 System memory area

4.1M24LR16E-R block security in RF mode

The M24LR16E-R provides a special protection mechanism based on passwords. In RF mode, each memory sector of the M24LR16E-R can be individually protected by one out of three available passwords, and each sector can also have Read/Write access conditions set.

Each memory sector of the M24LR16E-R is assigned with a Sector security status byte including a Sector Lock bit, two Password Control bits and two Read/Write protection bits, as shown in Table 7.

Table 6 describes the organization of the Sector security status byte, which can be read using the Read Single Block and Read Multiple Block commands with the Option_flag set to 1.

On delivery, the default value of the SSS bytes is set to 00h.

Table 6.	Sector security status byte area
I2C byte address			Bits [31:24]	Bits [23:16]	Bits [15:8]	Bits [7:0]
E2 = 1		0	SSS 3	SSS 2	SSS 1	SSS 0
E2 = 1		4	SSS 7	SSS 6	SSS 5	SSS 4
E2 = 1		8	SSS 11	SSS 10	SSS 9	SSS 8
E2 = 1		12	SSS 15	SSS 14	SSS 13	SSS 12

	Table 7.	Sector security status byte organization
	b7	b6	b5	b4	b3	b2	b1	b0
	0	0	0	Password control bits		Read / Write		Sector
						protection bits		Lock

When the Sector Lock bit is set to 1, for instance by issuing a Lock-sector command, the two Read/Write protection bits (b1, b2) are used to set the Read/Write access of the sector as described in Table 8.

	Table 8.	Read / Write protection bit setting
	Sector	b2, b1	Sector access		Sector access
	Lock		when password presented		when password not presented
	0	xx	Read	Write	Read	Write
	1	00	Read	Write	Read	No Write
	1	01	Read	Write	Read	Write
	1	10	Read	Write	No Read	No Write
	1	11	Read	No Write	No Read	No Write

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The next two bits of the Sector security status byte (b3, b4) are the password control bits. The value of these two bits is used to link a password to the sector, as defined in Table 9.

Table 9.	Password control bits
b4, b3		Password
00		The sector is not protected by a password.
01		The sector is protected by password 1.
10		The sector is protected by password 2.
11		The sector is protected by password 3.

The M24LR16E-R password protection is organized around a dedicated set of commands, plus a system area of three password blocks where the password values are stored. This system area is described in Table 10.

Table 10.	Password system area
Add
1	Password 1
2	Password 2
3	Password 3

The dedicated commands for protection in RF mode are:

●Write-sector password:

The Write-sector password command is used to write a 32-bit block into the password system area. This command must be used to update password values. After the write cycle, the new password value is automatically activated. It is possible to modify a password value after issuing a valid Present-sector password command. On delivery, the three default password values are set to 0000 0000h and are activated.

●Lock-sector:

The Lock-sector command is used to set the sector security status byte of the selected

sector. Bits b4 to b1 of the sector security status byte are affected by the Lock-sector command. The sector lock bit, b0, is set to 1 automatically. After issuing a Lock-sector command, the protection settings of the selected sector are activated. The protection of a locked block cannot be changed in RF mode. A Lock-sector command sent to a locked sector returns an error code.

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●Present-sector password:

The Present-sector password command is used to present one of the three passwords to the M24LR16E-R in order to modify the access rights of all the memory sectors linked to that password (Table 8) including the password itself. If the presented password is correct, the access rights remain activated until the tag is powered off or until a new Present-sector password command is issued. If the presented password value is not correct, all the access rights of all the memory sectors are deactivated.

●Sector security status byte area access conditions in I2C mode:

In I2C mode, read access to the sector security status byte area is always allowed. Write access depends on the correct presentation of the I2C password (see

Section 5.16.1: I2C present password command description).

To access the Sector security status byte area, the device select code used for any I2C command must have the E2 Chip Enable address at 1.

An I2C write access to a sector security status byte re-initializes the RF access condition to the given memory sector.

4.1.1Example of the M24LR16E-R security protection in RF mode

Table 11 and Table 12 show the sector security protections before and after a valid Presentsector password command. Table 11 shows the sector access rights of an M24LR16E-R after power-up. After a valid Present-sector password command with password 1, the memory sector access is changed as shown in Table 12.

Table 11. M24LR16E-R sector security protection after power-up

Sector				Sector security status byte
address				b7b6b5	b4	b3	b2	b1	b0
0	Protection: standard	Read	No Write	xxx	0	0	0	0	1
1	Protection: pswd 1	Read	No Write	xxx	0	1	0	0	1
2	Protection: pswd 1	Read	Write	xxx	0	1	0	1	1
3	Protection: pswd 1	No Read	No Write	xxx	0	1	1	0	1
4	Protection: pswd 1	No Read	No Write	xxx	0	1	1	1	1

Table 12.	M24LR16E-R sector security protection after a valid presentation of
	password 1
Sector				Sector security status byte
address				b7b6b5	b4 b3 b2 b1 b0
0	Protection: standard	Read	No Write	xxx	0	0	0	0	1
1	Protection: pswd 1	Read	Write	xxx	0	1	0	0	1
2	Protection: pswd 1	Read	Write	xxx	0	1	0	1	1
3	Protection: pswd 1	Read	Write	xxx	0	1	1	0	1
4	Protection: pswd 1	Read	No Write	xxx	0	1	1	1	1

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4.2M24LR16E-R block security in I²C mode (I2C_Write_Lock bit area)

In the I2C mode only, it is possible to protect individual sectors against Write operations. This feature is controlled by the I2C_Write_Lock bits stored in the 2 bytes of the I2C_Write_Lock bit area. I2C_Write_Lock bit area starts from location 2048 (see Table 13). To access the I2C_Write_Lock bit area, the device select code used for any I2C command must have the E2 Chip Enable address at 1.

Using these 16 bits, it is possible to write-protect all the 16 sectors of the M24LR16E-R memory. Each bit controls the I2C write access to a specific sector as shown in Table 13. It is always possible to unprotect a sector in the I2C mode. When an I2C_Write_Lock bit is reset to 0, the corresponding sector is unprotected. When the bit is set to 1, the corresponding sector is write-protected.

In I2C mode, read access to the I2C_Write_Lock bit area is always allowed. Write access depends on the correct presentation of the I2C password.

On delivery, the default value of the eight bytes of the I2C_Write_Lock bit area is reset to 00h.

m

Table 13. I2C_Write_Lock bit

I2C byte address			Bits [15:8]	Bits [7:0]
E2 = 1		2048	sectors 15-8	sectors 7-0

4.3Configuration byte and Control register

The M24LR16E-R offers an 8-bit non-volatile Configuration byte located at I²C location 2320 of the system area used to store the RF WIP/BUSY pin and the energy harvesting configuration (see Table 14).

The M24LR16E-R also offers an 8-bit volatile Control register located at I²C location 2336 of the system area used to store the energy harvesting enable bit as well as a FIELD_ON bit indicator (see Table 15).

4.3.1RF WIP/BUSY pin configuration

The M24LR16E-R features a configurable open drain output RF WIP/BUSY pin used to provide RF activity information to an external device.

The RF WIP/BUSY pin functionality depends on the value of bit 3 of the Configuration byte.

●RF busy mode

When bit 3 of the Configuration byte is set to 0, the RF WIP/BUSY pin is configured in RF busy mode.

The purpose of this mode is to indicate to the I²C bus master whether the M24LR16E-R is busy in RF mode or not.

In this mode, the RF WIP/BUSY pin is tied to 0 from the RF command Start Of Frame (SOF) until the end of the command execution.

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If a bad RF command is received, the RF WIP/BUSY pin is tied to 0 from the RF command SOF until the reception of the RF command CRC. Otherwise, the RF WIP/BUSY pin is in high-Z state.

When tied to 0, the RF WIP/BUSY signal returns to High-Z state if the RF field is cut-off.

During execution of I²C commands, the RF WIP/BUSY pin remains in high-Z state.

●RF Write in progress

When bit 3 of the Configuration byte is set to 1, the RF WIP/BUSY pin is configured in RF Write in progress mode.

The purpose of this mode is to indicate to the I²C bus master that some data have been changed in RF mode.

In this mode, the RF WIP/BUSY pin is tied to 0 for the duration of an internal write operation (i.e. between the end of a valid RF write command and the beginning of the RF answer).

During execution of I²C write operations, the RF WIP/BUSY pin remains in high-Z state.

4.3.2Energy harvesting configuration

The M24LR16E-R features an Energy harvesting mode on the Vout analog output.

The general purpose of the Energy harvesting mode is to deliver a part of the nonnecessary RF power received by the M24LR16E-R on the AC0-AC1 RF input in order to supply an external device. The current consumption on the analog voltage output Vout is limited to ensure that the M24LR16E-R is correctly supplied during the powering of the external device.

When the Energy harvesting mode is enabled and the power delivered on the AC0-AC1 RF input exceeds the minimum required PAC0-AC1_min, the M24LR16E-R is able to deliver a limited and unregulated voltage on the Vout pin, assuming the current consumption on the Vout does not exceed the Isink_max maximum value.

If one of the condition above is not met, the analog voltage output pin Vout is set in High-Z state.

For robust applications using the Energy harvesting mode, four current fan-out levels can be chosen.

●Vout sink current configuration

The sink current level is chosen by programming EH_cfg1 and EH_cfg0 into the Configuration byte (see Table 14).

The minimum power level required on AC0-AC1 RF input PAC0-AC1_min, the delivered voltage Vout, as well as the maximum current consumption Isink_max on the Vout pin corresponding to the <EH_cfg1,EH_cfg0> bit values are described in Table 126.

Table 14.		Configuration byte
I2C byte address			Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	BIT 1	BIT 0
E2=1		2320	X(1)	X(1)	X(1)	X(1)	RF WIP/BUSY	EH_mode	EH_cfg1	EH_cfg0

1. Bit 7 to Bit 4 are don’t care bits.

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●Energy harvesting enable control

Delivery of Energy harvesting analog output voltage on the Vout pin depends on the value of the EH_enable bit of the volatile Control register (see Table 15).

Table 15.	Control register
I2C byte address		Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	BIT 1	BIT 0
E2=1	2336	0(1)	0(1)	0(1)	0(1)	0(1)	0(1)	FIELD_ON(1)	EH_enable

1.Bit 7 to Bit 1 are read-only bits.

–When set to 1, the EH_enable bit enables the Energy harvesting mode, meaning

that the Vout analog output signal is delivered when the PAC0-AC1_min and Isink_max conditions corresponding to the chosen sink current configuration bit are met (see

Table 126).

–When set to 0, the EH_enable bit disable the Energy harvesting mode and the analog output Vout remains in set in High-Z state.

●Energy harvesting default mode control

At power-up, in I²C or RF mode, the EH_enable bit is updated according to the value of the EH_mode bit stored in the non-volatile Configuration byte (see Table 16). In other words, the EH_mode bit is used to configure whether the Energy harvesting mode is enabled or not by default.

Table 16. EH_enable bit value after power-up

	EH_mode value	EH_enable after power-up	Energy harvesting
			after power-up
	0	1	enabled
	1	0	disabled

4.3.3FIELD_ON indicator bit

The FIELD_ON bit indicator located as Bit 1 of the Control register is a read-only bit used to indicate when the RF power level delivered to the M24LR16E-R is sufficient to execute RF commands.

●When FIELD_ON = 0, the M24LR16E-R is not able to execute any RF commands.

●When FIELD_ON =1, the M24LR16E-R is able to execute any RF commands.

Note:	During read access to the Control register in RF mode, the FIELD_ON bit is always read
	at 1.

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4.3.4Configuration byte access in I²C and RF modes

In I²C mode, read and write accesses to the non-volatile Configuration byte are always allowed. To access the Configuration byte, the device select code used for any I²C command must have the E2 Chip enable address at 1.

The dedicated commands to access the Configuration byte in RF mode are:

●Read configuration byte command (ReadCfg):

The ReadCfg command is used to read the eight bits of the Configuration byte.

●Write energy harvesting configuration command (WriteEHCfg):

The WriteEHCfg command is used to write the EH_mode, EH_cfg1 and EH_cfg0 bits into the Configuration byte.

●Write RF WIP/BUSY pin configuration command (WriteDOCfg):

The WriteDOCfg command is used to write the RF WIP/BUSY bit into the Configuration byte.

After any write access to the Configuration byte, the new configuration is automatically applied.

4.3.5Control register access in I²C or RF mode

In I²C mode, read and write accesses to the volatile Control register are always allowed. To access the Control register, the device select code used for any I²C command must have the E2 Chip enable address at 1.

The dedicated commands to access the Control register in RF mode are:

●Check energy harvesting enable bit command (CheckEHEn):

The CheckEHEn command is used to read the eight bits of the Control register. When it is run, the FIELD_ON bit is always read at 1.

●Set/reset energy harvesting enable bit command (SetRstEHEn):

The SetRstEHEn command is used to set or reset the value of the EH_enable bit into the Control register.

4.4ISO 15693 system parameters

The M24LR16E-R provides the system area required by the ISO 15693 RF protocol, as shown in Table 17.

The first 32-bit block starting from I2C address 2304 stores the I2C password. This password is used to activate/deactivate the write protection of the protected sector in I2C mode. At power-on, all user memory sectors protected by the I2C_Write_Lock bits can be read but cannot be modified. To remove the write protection, it is necessary to use the I2C present password described in Figure 12. When the password is correctly presented — that is, when all the presented bits correspond to the stored ones — it is also possible to modify the I2C password using the I2C write password command described in Figure 13.

The next three 32-bit blocks store the three RF passwords. These passwords are neither readnor writeaccessible in the I2C mode.

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