ST M24C32-W, M24C32-R, M24C32-F, M24C32-X, M24C32-DF User Manual

M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF

32-Kbit serial I²C bus EEPROM

Features

■Compatible with all I2C bus modes:

–1 MHz

–400 kHz

–100 kHz

■Memory array:

–32 Kbit (4 Kbytes) of EEPROM

–Page size: 32 bytes

–Additional Write lockable page (M24C32-D order codes)

■Single supply voltage:

–1.7 V to 5.5 V over –40 °C / +85 °C

–1.6 V to 5.5 V over –20 °C / +85 °C

■Write:

–Byte Write within 5 ms (10 ms when VCC = 1.6 V)

–Page Write within 5 ms (10 ms when VCC = 1.6 V)

■Random and sequential Read modes

■Write protect of the whole memory array

■Enhanced ESD/Latch-Up protection

■More than 4 million Write cycles

■More than 200-year data retention

■Packages:

–RoHS compliant and halogen-free (ECOPACK®)

Datasheet − production data

TSSOP8 (DW) 169 mil width

SO8 (MN) 150 mil width

PDIP8 (BN)

UFDFPN8 (MB, MC)

July 2012

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This is information on a product in full production.

www.st.com

Contents	M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF

Contents

1	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
2	Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8

2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Chip Enable (E2, E1, E0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.6.1 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3	Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		10
4	Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
	4.1	Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
	4.2	Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
	4.3	Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
	4.4	Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
	4.5	Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
5	Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		14
	5.1	Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14

5.1.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.3 Write Identification Page (M24C32-D only) . . . . . . . . . . . . . . . . . . . . . . 17 5.1.4 Lock Identification Page (M24C32-D only) . . . . . . . . . . . . . . . . . . . . . . 17 5.1.5 ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . 18 5.1.6 Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 19

5.2 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.2.1 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF			Contents
	5.2.2	Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 21
	5.2.3	Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 21
	5.3 Read Identification Page (M24C32-D only) . . . . . . . . . . . . . . . . . . .		. . . . 21
	5.4 Read the lock status (M24C32-D only) . . . . . . . . . . . . . . . . . . . . . .		. . . . 21
6	Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 22
7	Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 23
8	DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 24
9	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 34
10	Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 38
11	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 39

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List of tables	M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3. Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4. Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 6. Operating conditions (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 7. Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 8. Operating conditions (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 9. Operating conditions (voltage range X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 10. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 11. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 12. Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 13. Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 14. DC characteristics (M24C32-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 15. DC characteristics (M24C32-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 16. DC characteristics (M24C32-F, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 17. DC characteristics (M24C32-X, device grade 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 18. 400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 19. 1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 20. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 34 Table 21. SO8N – 8 lead plastic small outline, 150 mils body width, package data . . . . . . . . . . . . . . 35 Table 22. PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package mechanical data. . . . . . . . . . . . 36 Table 23. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead

2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 24. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 25. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF	List of figures

List of figures

Figure 1.	Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 6
Figure 2.	8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 7
Figure 3.	Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 8
Figure 4.	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
Figure 5.	I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
Figure 6.	Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . .	15
Figure 7.	Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . .	16
Figure 8.	Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
Figure 9.	Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
Figure 10.	AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
Figure 11.	Maximum Rbus value versus bus parasitic capacitance (Cbus) for
	an I2C bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
Figure 12.	Maximum Rbus value versus bus parasitic capacitance Cbus) for
	an I2C bus at maximum frequency fC = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
Figure 13.	AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33
Figure 14.	TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . .	34
Figure 15.	SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . .	35
Figure 16.	PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package outline . . . . . . . . . . . . . . . . . . .	36
Figure 17.	UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package outline . . . . . . .	37

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Description	M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF

1 Description

The M24C32 is a 32-Kbit I2C-compatible EEPROM (Electrically Erasable PROgrammable Memory) organized as 4 K × 8 bits.

The M24C32-W can operate with a supply voltage from 2.5 V to 5.5 V, the M24C32-R can operate with a supply voltage from 1.8 V to 5.5 V, and the M24C32-F and M24C32-DF can operate with a supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of -40 °C / +85 °C; while the M24C32-X can operate with a supply voltage from 1.6 V to 5.5 V over an ambient temperature range of -20 °C / +85 °C.

The M24C32-D offers an additional page, named the Identification Page (32 bytes). The Identification Page can be used to store sensitive application parameters which can be (later) permanently locked in Read-only mode.

Figure 1. Logic diagram

	6##
% %	3$!
	- XXX
3#,
7#

				633	!) F
Table 1.			Signal names
			Signal name	Function	Direction
	E2, E1, E0			Chip Enable	Input
	SDA			Serial Data	I/O
	SCL			Serial Clock	Input
				Write Control	Input
	WC
	VCC			Supply voltage
	VSS			Ground

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M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF

Description

Figure 2. 8-pin package connections

%

6##

%

7#

%

3#,

633

3$!

!) F

1. See Section 9: Package mechanical data for package dimensions, and how to identify pin 1.

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Signal description	M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF

2 Signal description

2.1Serial Clock (SCL)

The signal applied on the SCL input is used to strobe the data available on SDA(in) and to output the data on SDA(out).

2.2Serial Data (SDA)

SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull-up resistor must be connected from Serial Data (SDA) to VCC (Figure 11 indicates how to calculate the value of the pull-up resistor).

2.3Chip Enable (E2, E1, E0)

(E2,E1,E0) input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code (see Table 2). These inputs must be tied to VCC or VSS, as shown in Figure 3. When not connected (left floating), these inputs are read as low (0).

Figure 3. Device select code

VCC

VCC

M24xxx M24xxx

Ei							Ei
VSS							VSS

Ai12806

2.4Write Control (WC)

This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either driven low or left floating.

When Write Control (WC) is driven high, device select and address bytes are acknowledged, Data bytes are not acknowledged.

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M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF	Signal description

2.5VSS (ground)

VSS is the reference for the VCC supply voltage.

2.6Supply voltage (VCC)

2.6.1Operating supply voltage VCC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 8: DC and AC parameters). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins.

This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (tW).

2.6.2Power-up conditions

The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage (see Operating conditions in Section 8: DC and AC parameters) and the rise time must not vary faster than 1 V/µs.

2.6.3Device reset

In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included.

At power-up, the device does not respond to any instruction until VCC has reached the internal reset threshold voltage. This threshold is lower than the minimum VCC operating voltage (see Operating conditions in Section 8: DC and AC parameters). When VCC passes over the POR threshold, the device is reset and enters the Standby Power mode; however, the device must not be accessed until VCC reaches a valid and stable DC voltage within the specified [VCC(min), VCC(max)] range (see Operating conditions in Section 8: DC and AC parameters).

In a similar way, during power-down (continuous decrease in VCC), the device must not be accessed when VCC drops below VCC(min). When VCC drops below the internal reset threshold voltage, the device stops responding to any instruction sent to it.

2.6.4Power-down conditions

During power-down (continuous decrease in VCC), the device must be in the Standby Power mode (mode reached after decoding a Stop condition, assuming that there is no internal write cycle in progress).

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Memory organization	M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF

3 Memory organization

The memory is organized as shown below.

Figure 4. Block diagram

7#					(IGH VOLTAGE
%			#ONTROLTLOGIC
					GENERATOR
%

3#,
3$!	) / SHIFTSREGISTER

!DDRESSRREGISTER	$ATA
ANDNCOUNTER	REGISTER
99DECODER
	PAGE
	)DENTIFICATION PAGE
	88DECODER

-3 6

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M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF	Device operation

4 Device operation

The device supports the I2C protocol. This is summarized in Figure 5. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The device is always a slave in all communications.

Figure 5. I2C bus protocol
SCL
SDA
	START		SDA	SDA		STOP
			Input	Change
	Condition					Condition
SCL	1	2	3	7	8	9
SDA	MSB					ACK
	START
	Condition
SCL	1	2	3	7	8	9
SDA	MSB					ACK
						STOP
						Condition
						AI00792B

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Device operation	M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF

4.1Start condition

Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer instruction. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition.

4.2Stop condition

Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high. A Stop condition terminates communication between the device and the bus master. A Read instruction that is followed by NoAck can be followed by a Stop condition to force the device into the Standby mode.

A Stop condition at the end of a Write instruction triggers the internal Write cycle.

4.3Data input

During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven low.

4.4Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to acknowledge the receipt of the eight data bits.

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