M24256-BW M24256-BR M24256-BF
M24256-DR M24256-DF
256-Kbit serial I²C bus EEPROM
Features
■Compatible with all I2C bus modes:
–1 MHz
–400 kHz
–100 kHz
■Single supply voltage and high speed:
–1 MHz clock from 1.7 V to 5.5 V
■Memory array:
–256 Kbit (32 Kbytes) of EEPROM
–Page size: 64 bytes
–Additional Write lockable page (M24256-D order codes)
■Write:
–Byte Write within 5 ms
–Page Write within 5 ms
■Operating temperature range: from -40-20 °C up to +85125 °C
■Random and sequential Read modes
■Write protect of the whole memory array
■Enhanced ESD/Latch-Up protection
■More than 4 million Write cycles
■More than 200-year data retention
■Packages:
–RoHS compliant and halogen-free (ECOPACK®)
Datasheet − production data
TSSOP8 (DW) 169 mil width
SO8 (MN) 150 mil width
UFDFPN8
(MC)
WLCSP (CS)
August 2012 |
Doc ID 6757 Rev 27 |
1/41 |
This is information on a product in full production. |
www.st.com |
Contents |
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF |
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Contents
1 |
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
6 |
2 |
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
8 |
2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Chip Enable (E2, E1, E0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.1 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 |
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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4.1 |
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
12 |
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4.2 |
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
12 |
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4.4 |
Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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4.5 |
Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
13 |
5 |
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
14 |
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5.1 |
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
14 |
5.1.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.3 Write Identification Page (M24256-D only) . . . . . . . . . . . . . . . . . . . . . . 17 5.1.4 Lock Identification Page (M24256-D only) . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.5 ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . 18 5.1.6 Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 19
5.2 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2.1 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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Contents |
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5.2.2 |
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.2.3 |
Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 21 |
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5.3 Read Identification Page (M24256-D only) . . . . . . . . . . . . . . . . . . . |
. . . . 21 |
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5.4 Read the lock status (M24256-D only) . . . . . . . . . . . . . . . . . . . . . . . |
. . . . 21 |
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6 |
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . 22 |
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7 |
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . 23 |
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8 |
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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9 |
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . 33 |
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10 |
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . 38 |
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11 |
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . 39 |
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List of tables |
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF |
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List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3. Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4. Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 6. Operating conditions (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 7. Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 8. Operating conditions (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 9. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 10. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 11. Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 12. Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 13. DC characteristics (M24256-BW, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 14. DC characteristics (M24256-BR, M24256-DR, device grade 6) . . . . . . . . . . . . . . . . . . . . . 27 Table 15. DC characteristics (M24256-BF, M24256-DF, device grade 6) . . . . . . . . . . . . . . . . . . . . . 28 Table 16. 400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 17. 1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 18. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 33 Table 19. SO8N – 8 lead plastic small outline, 150 mils body width, package data . . . . . . . . . . . . . . 34 Table 20. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 21. M24256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package mechanical data. 37 Table 22. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 23. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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List of figures |
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List of figures
Figure 1. |
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 6 |
Figure 2. |
8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 7 |
Figure 3. |
WLCSP connections (top view, marking side, with balls on the underside) . . . . . . . . . . . . |
. 7 |
Figure 4. |
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 8 |
Figure 5. |
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
10 |
Figure 6. |
I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
11 |
Figure 7. |
Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . |
15 |
Figure 8. |
Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . |
16 |
Figure 9. |
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
19 |
Figure 10. |
Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
20 |
Figure 11. |
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
24 |
Figure 12. |
Maximum Rbus value versus bus parasitic capacitance (Cbus) for |
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an I2C bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
31 |
Figure 13. |
Maximum Rbus value versus bus parasitic capacitance Cbus) for |
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an I2C bus at maximum frequency fC = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
31 |
Figure 14. |
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
32 |
Figure 15. |
TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . |
33 |
Figure 16. |
SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . |
34 |
Figure 17. |
UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package outline . . . . . . . |
35 |
Figure 18. |
M24256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline . . . . . . . . |
36 |
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Description |
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF |
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The M24256 is a 256-Kbit I2C-compatible EEPROM (Electrically Erasable PROgrammable Memory) organized as 32 K × 8 bits.
The M24256-BW can operate with a supply voltage from 2.5 V to 5.5 V, the M24256-BR and M24256-DR can operate with a supply voltage from 1.8 V to 5.5 V, and the M24256-BF and M24256-DF can operate with a supply voltage from 1.7 V to 5.5 V. All these devices operate with a clock frequency of 1 MHz (or less), over an ambient temperature range of –40 °C / +85 °C.
The M24256-Dx offers an additional page, named the Identification Page (64 bytes). The Identification Page can be used to store sensitive application parameters which can be (later) permanently locked in Read-only mode.
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% % |
3$! |
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3#, |
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7# |
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633 |
!) F |
Table 1. |
Signal names |
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Signal name |
Function |
Direction |
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E2, E1, E0 |
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Chip Enable |
Input |
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SDA |
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Serial Data |
I/O |
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SCL |
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Serial Clock |
Input |
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Write Control |
Input |
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WC |
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VCC |
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Supply voltage |
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VSS |
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Ground |
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Description |
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Figure 2. 8-pin package connections |
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6## |
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7# |
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1.DU: Don't Use (if connected, must be connected to VSS)
2.See Section 9: Package mechanical data for package dimensions, and how to identify pin 1.
7# |
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6## |
633 |
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3$! |
3#, |
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-3 6
Caution: As EEPROM cells lose their charge (and so their binary value) when exposed to ultra violet (UV) light, EEPROM dice delivered in wafer form or in WLCSP package by STMicroelectronics must never be exposed to UV light.
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Signal description |
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF |
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The signal applied on the SCL input is used to strobe the data available on SDA(in) and to output the data on SDA(out).
SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull-up resistor must be connected from Serial Data (SDA) to VCC (Figure 12 indicates how to calculate the value of the pull-up resistor).
(E2,E1,E0) input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code (see Table 2). These inputs must be tied to VCC or VSS, as shown in Figure 4. When not connected (left floating), these inputs are read as low (0).
VCC |
VCC |
M24xxx M24xxx
Ei |
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VSS |
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VSS |
Ai12806
This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either driven low or left floating.
When Write Control (WC) is driven high, device select and address bytes are acknowledged, Data bytes are not acknowledged.
2.5VSS (ground)
VSS is the reference for the VCC supply voltage.
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Signal description |
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2.6Supply voltage (VCC)
2.6.1Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 8: DC and AC parameters). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (tW).
2.6.2Power-up conditions
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage (see Operating conditions in Section 8: DC and AC parameters) and the rise time must not vary faster than 1 V/µs.
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included.
At power-up, the device does not respond to any instruction until VCC has reached the internal reset threshold voltage. This threshold is lower than the minimum VCC operating voltage (see Operating conditions in Section 8: DC and AC parameters). When VCC passes over the POR threshold, the device is reset and enters the Standby Power mode; however, the device must not be accessed until VCC reaches a valid and stable DC voltage within the specified [VCC(min), VCC(max)] range (see Operating conditions in Section 8: DC and AC parameters).
In a similar way, during power-down (continuous decrease in VCC), the device must not be accessed when VCC drops below VCC(min). When VCC drops below the power-on-reset threshold voltage, the device stops responding to any instruction sent to it.
2.6.4Power-down conditions
During power-down (continuous decrease in VCC), the device must be in the Standby Power mode (mode reached after decoding a Stop condition, assuming that there is no internal write cycle in progress).
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Memory organization |
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF |
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The memory is organized as shown below.
7# |
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#ONTROLTLOGIC |
(IGH VOLTAGE |
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GENERATOR |
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3#, |
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3$! |
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) / SHIFTSREGISTER |
!DDRESSRREGISTER |
$ATA |
ANDNCOUNTER |
REGISTER |
99DECODER |
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PAGE |
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)DENTIFICATION PAGE |
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88DECODER |
-3 6
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Device operation |
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The device supports the I2C protocol. This is summarized in Figure 6. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The device is always a slave in all communications.
Figure 6. I2C bus protocol |
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SCL |
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SDA |
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START |
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SDA |
SDA |
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STOP |
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Input |
Change |
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Condition |
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Condition |
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SCL |
1 |
2 |
3 |
7 |
8 |
9 |
SDA |
MSB |
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ACK |
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START |
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Condition |
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SCL |
1 |
2 |
3 |
7 |
8 |
9 |
SDA |
MSB |
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ACK |
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STOP |
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Condition |
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AI00792B |
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Device operation |
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF |
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Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer instruction. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition.
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high. A Stop condition terminates communication between the device and the bus master. A Read instruction that is followed by NoAck can be followed by a Stop condition to force the device into the Standby mode.
A Stop condition at the end of a Write instruction triggers the internal Write cycle.
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven low.
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to acknowledge the receipt of the eight data bits.
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Doc ID 6757 Rev 27 |
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF |
Device operation |
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To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 2 (on Serial Data (SDA), most significant bit first).
Table 2. |
Device select code |
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Device type identifier(1) |
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Chip Enable address(2) |
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RW |
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b7 |
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b6 |
b5 |
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b4 |
b3 |
b2 |
b1 |
b0 |
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Device select code |
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when addressing the |
1 |
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0 |
1 |
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0 |
E2 |
E1 |
E0 |
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RW |
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memory array |
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Device select code |
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when accessing the |
1 |
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0 |
1 |
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1 |
E2 |
E1 |
E0 |
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RW |
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Identification page |
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1.The most significant bit, b7, is sent first.
2.E0, E1 and E2 are compared against the respective external pins on the memory device.
When the device select code is received, the device only responds if the Chip Enable Address is the same as the value on the Chip Enable (E2, E1, E0) inputs.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the device select code, it deselects itself from the bus, and goes into Standby mode.
Doc ID 6757 Rev 27 |
13/41 |