ST LSM330DL User Manual

3D accelerometer sensor and 3D gyroscope sensor

Features

■ Analog supply voltage 2.4 V to 3.6 V

■ Digital supply voltage I/Os, 1.8V

■ Low-power mode

■ Power-down mode

■ 3 independent acceleration channels and 3

angular rate channels

■ ±2g/±4g/±8g/±16g dynamic, selectable full-

scale acceleration range

■ ±250/±500/±2000 dps dynamic, selectable full-

scale angular rate

■ SPI/I

■ Programmable interrupt generator for free-fall

■ ECOPACK

Applications

■ GPS navigation systems

■ Impact recognition and logging

■ Gaming and virtual reality input devices

■ Motion-activated functions

■ Intelligent power saving for handheld devices

■ Vibration monitoring and compensation

■ Free-fall detection

■ 6D-orientation detection

C serial interface (16-bit data output)

and motion detection

, RoHS, and “Green” compliant

LSM330DL

Linear sensor module

Preliminary data

LLGA 28L 7.5 x 4.4 x 1.1 mm

ST’s family of modules leverages a robust and mature manufacturing process already used for the production of micromachined accelerometers.

The various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces are based on CMOS technology that allows designing a dedicated circuit which is trimmed to better match the sensing element characteristics.

The LSM330DL has a dynamic, user-selectable full-scale acceleration range of ±2g/±4g/±8g/±16g and an angular rate of ±250/±500/±2000 deg/sec.

The accelerometer and gyroscope sensors can be either activated or put in low-power / powerdown mode separately for power-saving optimized applications. The LSM330DL is available in a plastic land grid array (LGA) package.

Several years ago ST successfully pioneered the use of this package for accelerometers. Today, ST has the broadest manufacturing capability in the world and unrivalled expertise for the production of sensors in a plastic LGA package.

Description

The LSM330DL is a system-in-package featuring a 3D digital accelerometer and a 3D digital gyroscope.

Table 1. Device summary

Part number Temperature range [°C] Package Packing

LSM330DL -40 to +85 LGA-28 Tray

LSM330DLTR -40 to +85 LGA-28 Tape & reel

July 2011 Doc ID 022018 Rev 1 1/54

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

www.st.com

Contents LSM330DL

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2 Module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.3 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.4.1 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.4.2 I2C - inter-IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.6.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.6.2 Zero level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1 External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.2 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.1 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.2.1 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2.2 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2.3 SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

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LSM330DL Contents

7 Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.1 CTRL_REG1_A (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.2 CTRL_REG2_A (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.3 CTRL_REG3_A (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.4 CTRL_REG4_A (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.5 CTRL_REG5_A (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.6 CTRL_REG6_A (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.7 REFERENCE/DATACAPTURE_A (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.8 STATUS_REG_A (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.9 OUT_X_L_A (28h), OUT_X_H_A (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.10 OUT_Y_L_A (2Ah), OUT_Y_H_A (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.11 OUT_Z_L _A(2Ch), OUT_Z_H_A (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.12 FIFO_CTRL_REG_A (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.13 FIFO_SRC_REG_A (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.14 INT1_CFG_A (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.15 INT1_SRC_A (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.16 INT1_THS_A (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.17 INT1_DURATION_A (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.18 CLICK_CFG _A (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.19 CLICK_SRC_A (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.20 CLICK_THS_A (3Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.21 TIME_LIMIT_A (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.22 TIME_LATENCY_A (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.23 TIME WINDOW_A (3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.24 CTRL_REG1_G (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.25 CTRL_REG2_G (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.26 CTRL_REG3_G (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.27 CTRL_REG4_G (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.28 CTRL_REG5_G (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.29 REFERENCE/DATACAPTURE_G (25h) . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.30 OUT_TEMP_G (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.31 STATUS_REG_G (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.32 OUT_X_L_G (28h), OUT_X_H_G (29h) . . . . . . . . . . . . . . . . . . . . . . . . . 44

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Contents LSM330DL

7.33 OUT_Y_L_G (2Ah), OUT_Y_H_G (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.34 OUT_Z_L_G (2Ch), OUT_Z_H_G (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.35 FIFO_CTRL_REG_G (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.36 FIFO_SRC_REG_G (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.37 INT1_CFG_G (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.38 INT1_SRC_G (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.39 INT1_THS_XH_G (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.40 INT1_THS_XL_G (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.41 INT1_THS_YH_G (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.42 INT1_THS_YL_G (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.43 INT1_THS_ZH_G (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.44 INT1_THS_ZL_G (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.45 INT1_DURATION_G (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4/54 Doc ID 022018 Rev 1

LSM330DL List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 3. Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 5. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 6. SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 7. I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 9. Part list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 10. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 11. Serial interface terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 12. Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 13. Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 14. Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 22

Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 22

Table 16. Linear acceleration SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 17. Angular rate SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 18. Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 19. CTRL_REG1_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 20. CTRL_REG1_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 21. Data rate configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 22. Operating mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 23. CTRL_REG2_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 24. CTRL_REG2_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 25. High-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 26. CTRL_REG3_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 27. CTRL_REG3_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 28. CTRL_REG4_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 29. CTRL_REG4_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 30. CTRL_REG5_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 31. CTRL_REG5_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 32. CTRL_REG6_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 33. CTRL_REG6 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 34. REFERENCE/DATACAPTURE_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 35. REFERENCE/DATACAPTURE_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 36. STATUS_REG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 37. STATUS_REG_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 38. FIFO_CTRL_REG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 39. FIFO_CTRL_REG_A register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 40. FIFO mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 41. FIFO_SRC_REG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 42. INT1_CFG_REG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 43. INT1_CFG_REG_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 44. Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 45. INT1_SRC_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 46. INT1_SRC_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 47. INT1_THS_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 48. INT1_THS_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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List of tables LSM330DL

Table 49. INT1_DURATION_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 50. INT1_DURATION_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 51. CLICK_CFG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 52. CLICK_CFG_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 53. CLICK_SRC_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 54. CLICK_SRC_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 55. CLICK_THS_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 56. CLICK_SRC_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 57. TIME_LIMIT_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 58. TIME_LIMIT_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 59. TIME_LATENCY_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 60. TIME_LATENCY_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 61. TIME_WINDOW_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 62. TIME_WINDOW_A description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 63. CTRL_REG1_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 64. CTRL_REG1_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 65. DR and BW configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 66. Power mode selection configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 67. CTRL_REG2_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 68. CTRL_REG2_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 69. High-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 70. High-pass filter cutoff frequency configuration [Hz] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 71. CTRL_REG3_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 72. CTRL_REG3_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 73. CTRL_REG4_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 74. CTRL_REG4_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 75. CTRL_REG5_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 76. CTRL_REG5_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 77. Out_Sel configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 78. INT_SEL configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 79. REFERENCE/DATACAPTURE_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 80. REFERENCE/DATACAPTURE_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 81. OUT_TEMP_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 82. OUT_TEMP_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 83. STATUS_REG_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 84. STATUS_REG_G description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 85. FIFO_CTRL_REG_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 86. FIFO_CTRL_REG_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 87. FIFO mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 88. FIFO_SRC_REG_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 89. FIFO_SRC_REG_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 90. INT1_CFG_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 91. INT1_CFG_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 92. INT1_SRC_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 93. INT1_SRC_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 94. INT1_THS_XH_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 95. INT1_THS_XH_G description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 96. INT1_THS_XL_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 97. INT1_THS_XL_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 98. INT1_THS_YH_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 99. INT1_THS_YH_G description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 100. INT1_THS_YL_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

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LSM330DL List of tables

Table 101. INT1_THS_YL_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 102. INT1_THS_ZH_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 103. INT1_THS_ZH_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 104. INT1_THS_ZL_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 105. INT1_THS_ZL_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 106. INT1_DURATION_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 107. INT1_DURATION_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 108. LLGA 7.5 x 4.4 x 1.1 28L mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 109. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Doc ID 022018 Rev 1 7/54

List of figures LSM330DL

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 2. Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 3. SPI slave timing diagram (2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 4. I2C slave timing diagram (3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 5. LSM330DL electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 6. Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 7. SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 8. Multiple bytes SPI read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 9. SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 10. Multiple bytes SPI write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 11. SPI read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 12. INT1_Sel and Out_Sel configuration block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 13. Wait disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 14. Wait enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 15. LLGA 7.5 x 4.4 x 1.1 28L package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

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LSM330DL Block diagram and pin description

1 Block diagram and pin description

1.1 Block diagram

Figure 1. Block diagram

I (a)

I (

Ω)

Sensing Block

Feedback+

Feedback-

Drive-

Drive+

X+

Sensing Interface

Y+

Z+

Z-

Y-

X-

X+

Y+

Z+

Z-

Y-

X-

MUX

VOLTAGE

GAIN

AMPLIFIER

CHARGE AMPLIFIER

DEMODULATOR

ANALOG CONDITIONING

A/D Control

LOW-PASS

FILTER

AUTOMATIC

GAIN

CONTROL

Logicconverter

I2C/SPI

CS_A/G

SDA/SDI_A/G

SDO_A/G

INT1_A

INT2_A

INT1_G

DRDY_G/INT2_G

SCL_A/G

REFERENCE

CONTROL LOGIC

INTERRUPT GEN.

TRIMMING

CIRCUITS

SET/RESET

CIRCUITS

CLOCK

PHASE

GENERATOR

AM09285V1

Doc ID 022018 Rev 1 9/54

Block diagram and pin description LSM330DL

1.2 Pin description

Figure 2. Pin connections

+Ω

DIRECTION OF DETECTABLE

+Ω

ACCELERATIONS

Vdd_IO_A

Res

VCONT

GND

DIRECTION OF DETECTABLE

ANGULAR RATE

SDA/SDI_A

Res

Table 2. Pin description

Pin# Name Function

Accelerometer:

1SDA/SDI_A

2 Res Reserved, connect to GND

3SDO_A

C serial data (SDA) SPI serial data input (SDI) 3-wire interface serial data output (SDO)

Accelerometer: SPI serial data output (SDO)

C least significant bit of the device address (SA0)

SDO_A

SCL_A

DRDY_G/INT2_G

Res

LSM330DL

(BOTTOM VIEW)

Res

Vdd

Res

INT1_G

INT1_A

SDO_G

FILTVDD

FILTIN Y

Res

INT2_A

CS_A

CS_G

SDA/SDI_G

Res

Vdd_IO_G

SCL_G

Res

Vdd

Res

AM09256V1

Accelerometer:

4SCL_A

C serial clock (SCL) SPI serial port clock (SPC)

5 DRDY_G/INT2_G Gyroscope data ready/interrupt signal 2

6 INT1_A Accelerometer interrupt signal

Gyroscope:

7SDO_G

SPI serial data output (SDO) I2C least significant bit of the device address (SA0)

8 INT2_A Accelerometer interrupt signal

Gyroscope:

9SDA/SDI_G

C serial data (SDA) SPI serial data input (SDI) 3-wire interface serial data output (SDO)

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LSM330DL Block diagram and pin description

Table 2. Pin description (continued)

Pin# Name Function

Gyroscope:

10 CS_G

11 Res Reserved, connect to GND

12 Vdd_IO_G Gyroscope power supply for I/O pins

13 SCL_G

14 Res Reserved connect to GND

15 Vdd Power supply

16 Res Reserved, connect to GND

17 CS_A

18 Res Reserved, connect to GND

SPI enable

C/SPI mode selection (1: SPI idle mode / I2C communication enabled; 0: SPI communication mode / I

C disabled)

Gyroscope:

C serial clock (SCL)

I SPI serial port clock (SPC)

Accelerometer:

SPI enable

C/SPI mode selection (1: SPI idle mode / I2C communication

I enabled; 0: SPI communication mode / I

C disabled)

19 Res Reserved, connect to GND

20 Res Reserved, connect to GND

21 INT1_G Gyroscope interrupt signal 1

22 Vdd Power supply

23 Res Reserved, connect to GND

24 Res Reserved, connect to GND

25 GND 0 V power supply

26 VCONT PLL filter connection

27 Res Reserved, connect to GND

28 Vdd_IO_A Accelerometer power supply for I/O pins

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Module specifications LSM330DL

zHz

2 Module specifications

2.1 Mechanical characteristics

The values given in the following table are for the conditions Vdd = 3 V, T = 25 °C unless otherwise noted.

Table 3. Mechanical characteristics

Symbol Parameter Test conditions Min. Typ.

LA_FS

G_FS Angular rate measurement range

LA_So Linear acceleration sensitivity

G_So Angular rate sensitivity

LA_So

G_So Angular rate sensitivity change vs. temp. from -40 to +85°C ±2 %

LA_TyOff Typical zero-

G_TyOff Typical zero-rate level

LA_TCOff Zero-

G_TCOff Zero-rate level change vs. temperature

An Acceleration noise density

Rn Rate noise density FS bit set to 00, BW = 50 Hz 0.03 dps/

Top Operating temperature range -40 +85 °C

1. Typical specifications are not guaranteed.

2. Verified by wafer level test and measurement of initial offset and sensitivity.

3. Typical zero-g level offset value after MSL3 preconditioning.

4. Offset can be eliminated by enabling the built-in high-pass filter.

Linear acceleration measurement range

Linear acceleration Sensitivity change vs. temperature

g level change vs. temperature Max delta from 25 °C ±0.5 mg/°C

(a)

(2)

g level offset accuracy

(4)

(2)

(1)

FS bit set to 00 ±2

FS bit set to 01 ±4

FS bit set to 10 ±8

FS bit set to 11 ±16

FS bit set to 00 ±250

FS bit set to 10 ±2000

FS bit set to 00 1

FS bit set to 01 2

FS bit set to 10 4

FS bit set to 11 12

FS bit set to 00 8.75

FS bit set to 01 17.5

FS bit set to 10 70

FS bit set to 00 ±0.05 %/°C

(3)

FS bit set to 00 ±60 mg

FS bit set to 00 10 LSb

FS bit set to 00 from -40 to +85°C

FS bit set to 00, normal mode, ODR bit set to 1001

±0.03 dps/°C

220 µ

Max. Unit

mg/digit

mdps/

dpsFS bit set to 01 ±500

digit

a. The product is factory calibrated at 3 V. The operational power supply range is from 2.4 V to 3.6 V.

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LSM330DL Module specifications

2.2 Electrical characteristics

The values given in the following table are for the conditions Vdd = 3 V, T = 25 °C unless otherwise noted.

Table 4. Electrical characteristics

Symbol Parameter Test conditions Min. Typ.

Vdd Supply voltage 2.4 3.6 V

Vdd_IO Power supply for I/O 1.71 Vdd+0.1 V

LA_Idd

LA_IddLowP

LA current consumption in normal mode

LA current consumption in low-power mode

ODR = 50 Hz 11

ODR = 1 Hz 2

ODR = 50 Hz 6 µA

(1)

Max. Unit

µA

LA_IddPdn

G_Idd

G_IddLowP

G_IddPdn

VIH Digital high-level input voltage 0.8*Vdd_IO V

VIL Digital low-level input voltage 0.2*Vdd_IO V

VOH High-level output voltage 0.9*Vdd_IO V

VOL Low-level output voltage 0.1*Vdd_IO V

Top Operating temperature range -40 +85 °C

1. Typical specifications are not guaranteed.

2. Sleep mode introduces a faster turn-on time compared to power-down mode.

LA current consumption in power-down mode

AR current consumption in normal mode

AR supply current in sleep mode

AR current consumption in power-down mode

T = 25 °C 0.5 µA

6.1 mA

(2)

T = 25 °C 5 µA

1.5 mA

2.3 Temperature sensor characteristics

The values given in the following table are for the conditions Vdd = 3.0 V, T=25 °C, unless otherwise noted.

Table 5. Temperature sensor characteristics

Symbol Parameter Test condition Min. Typ.

TSDr

TODR Temperature refresh rate 1 Hz

Top Operating temperature range -40 +85 °C

1. The product is factory calibrated at 3.0 V.

2. Typical specifications are not guaranteed.

Temperature sensor output change vs. temperature

Doc ID 022018 Rev 1 13/54

(1)

(2)

-1 °C/digit

Max. Unit

Module specifications LSM330DL

2.4 Communication interface characteristics

2.4.1 SPI - serial peripheral interface

The values given in the following table are subject to the general operating conditions for Vdd and T

Table 6. SPI slave timing values

Symbol Parameter

(1)

Val ue

Unit

Min Max

c(SPC)

su(CS)

h(CS)

su(SI)

h(SI)

v(SO)

h(SO)

dis(SO)

1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production.

Figure 3. SPI slave timing diagram

(3)

SPC

(3)

SPI clock cycle 100 ns

SPI clock frequency 10 MHz

CS setup time 6

CS hold time 8

SDI input setup time 5

SDI input hold time 15

SDO valid output time 50

SDO output hold time 9

SDO output disable time 50

(b)

su(CS)

c(SPC)

h(CS)

(3)

MSB IN

MSB OUT

h(SI)

v(SO)

LSB IN

h(SO)

LSB OUT

su(SI)

(3)

SDI

(3)

SDO

3. Data on CS, SPC, SDI and SDO concern the following pins: CS_A/G, SCL_A/G, SDA/SDI_A/G, SDO_A/G

b. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.

14/54 Doc ID 022018 Rev 1

(3)

dis(SO)

(3)

LSM330DL Module specifications

2.4.2 I2C - inter-IC control interface

The values given in the following table are subject to the general operating conditions for Vdd and T

Table 7. I2C slave timing values

Symbol Parameter

(1)

I2C standard mode

I2C fast mode

Min Max Min Max

(1)

Unit

(SCL)

w(SCLL)

w(SCLH)

su(SDA)

h(SDA)

r(SDA) tr(SCL)

f(SDA) tf(SCL)

h(ST)

su(SR)

su(SP)

w(SP:SR)

SCL clock frequency 0 100 0 400 kHz

SCL clock low time 4.7 1.3

SCL clock high time 4.0 0.6

SDA setup time 250 100 ns

SDA data hold time 0.01 3.45 0 0.9 µs

SDA and SCL rise time 1000

SDA and SCL fall time 300

START condition hold time 4 0.6

Repeated START condition setup time 4.7 0.6

STOP condition setup time 4 0.6

Bus free time between STOP and START condition

1. SCL (SCL_A/G pin), SDA (SDA_A/G pin)

Figure 4. I2C slave timing diagram

START

(3)

20 + 0.1C

4.7 1.3

µs

(2)

300

µs

REPEATED

START

SDA

f(SDA)

r(SDA)

su(SDA)

h(SDA)

SCL

w(SCLL)

h(ST)

1. Data based on standard I

w(SCLH)

C protocol requirement, not tested in production.

r(SCL)

f(SCL)

2 Cb = total capacitance of one bus line, in pF

3. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.

Doc ID 022018 Rev 1 15/54

su(SR)

su(SP)

w(SP:SR)

START

STOP

AM09238V1

Module specifications LSM330DL

2.5 Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 8. Absolute maximum ratings

Symbol Ratings Maximum value Unit

Vdd Supply voltage -0.3 to 4.8 V

Vdd_IO I/O pins supply voltage -0.3 to 4.8 V

Input voltage on any control pin (SCL_A/G, SDA/SDI_A/G, SDO_A/G, CS_A/G)

Acceleration (any axis, powered, Vdd = 3 V)

-0.3 to Vdd_IO +0.3 V

3000 g for 0.5 ms

10000 g for 0.1 ms

Vin

POW

UNP

STG

Acceleration (any axis, unpowered)

Operating temperature range -40 to +85 °C

Storage temperature range -40 to +125 °C

ESD Electrostatic discharge protection 2 (HBM) kV

Note: Supply voltage on any pin should never exceed 4.8 V

This is a device sensitive to mechanical shock, improper handling can cause permanent damage to the part

This is an ESD-sensitive device, improper handling can cause permanent damage to the part

3000 g for 0.5 ms

10000 g for 0.1 ms

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LSM330DL Module specifications

2.6 Terminology

2.6.1 Sensitivity

Linear acceleration sensitivity can be determined by applying 1 g acceleration to the device. As the sensor can measure DC accelerations, this can be done easily by pointing the axis of interest towards the center of the Earth, noting the output value, rotating the sensor by 180 degrees (point to the sky) and then noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and also very little over time. The sensitivity tolerance describes the range of sensitivities of a large population of sensors.

Angular rate sensitivity describes the angular rate gain of the sensor and can be determined by applying a defined angular velocity to it. This value changes very little over temperature and also very little over time.

2.6.2 Zero level

Linear acceleration zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g on the X-axis and 0 g on the Y-axis whereas the Z-axis will measure 1 g. The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as 2’s complement number). A deviation from the ideal value in this case is called zero-g offset. Offset is to some extent a result of stress to the MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Zero-g level change vs. temperature” (refer toTable 3). The zero-g level tolerance (TyOff) describes the standard deviation of the range of zero-g levels of a population of sensors.

The angular rate zero-rate level describes the actual output value if there is no angular rate present. Zero-rate level of precise MEMS sensors is, to some extent, a result of stress to the sensor and therefore the zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. This value changes very little over temperature and also very little over time.

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