fall, motion detection and magnetic field
detection
®
, RoHS and “Green” compliant
LSM303D
Datasheet — preliminary data
Description
The LSM303D is a system-in-package featuring a
3D digital linear acceleration sensor and a 3D
digital magnetic sensor.
The LSM303D has linear acceleration full-scales
of ±2g / ±4g / ±6g / ±8g / ±16g and a magnetic
field full-scale of±2 / ±4 / ±8 / ±12 gauss. All fullscales available are fully selectable by the user.
The LSM303D includes an I
that supports standard and fast mode 100 kHz
and 400 kHz and SPI serial standard interface.
The system can be configured to generate an
interrupt signal for free-fall, motion detection and
magnetic field detection. Thresholds and timing of
interrupt generators are programmable by the end
user on the fly.
Magnetic and accelerometer parts can be
enabled or put into power-down mode separately.
The LSM303D is available in plastic land grid
array package (LGA) and is guaranteed to
operate over an extended temperature range from
-40 °C to +85 °C.
Table 1.Device summary
Part number
Temperature
range [°C]
2
C serial bus interface
Package Packaging
LSM303D-40 to +85LGA-16Tray
LSM303DTR-40 to +85LGA-16
June 2012Doc ID 023312 Rev 11/54
This is preliminar y information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
7
SDO
SA0
SPI serial data output (SDO)
2
I
C less significant bit of the device address (SA0)
SPI enable
8CS
2
C/SPI mode selection (1: SPI idle mode / I2C communication
I
enabled; 0: SPI communication mode / I
9INT 2Interrupt 2
10ReservedConnect to GND
11INT 1Interrupt 1
12GND0 V supply
13GND0 V supply
14VddPower supply
15C1Capacitor connection (C1)
16GND0 V supply
2
C disabled)
Doc ID 023312 Rev 19/54
Module specificationsLSM303D
2 Module specifications
2.1 Sensor characteristics
@ Vdd = 2.5 V, T = 25 °C unless otherwise noted
Table 3.Sensor characteristics
SymbolParameterTest conditionsMin.Typ.
LA_FS
M_FSMagnetic measurement range
LA_SoLinear acceleration sensitivity
M_GNMagnetic sensitivity
LA_TCSo
M_TCSo
LA_TyOff
LA_TCOff
LA_An
Linear acceleration
measurement range
Linear acceleration sensitivity
change vs. temperature
Magnetic sensitivity change
vs. temperature
Linear acceleration typical
zero-g level offset
accuracy
Linear acceleration zero-g
level change vs. temperature
Linear acceleration noise
density
(3),(4)
(2)
Linear acceleration FS=±2g0.061
Linear acceleration FS=±4g0.122
Linear acceleration FS=±6g0.183
Linear acceleration FS=±8g0.244
Linear acceleration FS=±16g0.732
Magnetic FS=±2gauss0.080
Magnetic FS=±4gauss0.160
Magnetic FS=±8gauss0.320
Magnetic FS=±12gauss0.479
Max. delta from 25 °C±0.5m
Linear acceleration FS=2g;
ODR = 100 Hz
(a)
.
(1)
Max.Unit
±2
±4
±6
±8
±16
±2
±4
±8
±12
±0.01%/°C
±0.05%/°C
±60mg
g
gauss
mg/LSB
mgauss/
LSB
g/°C
150
ug/
sqrt(Hz)
a. The product is factory calibrated at 2.5 V. The operational power supply range is from 2.16 V to 3.6 V.
10/54Doc ID 023312 Rev 1
LSM303DModule specifications
Table 3.Sensor characteristics (continued)
SymbolParameterTest conditionsMin.Typ.
(1)
Max.Unit
M_RMagnetic noise density
M_CAS
Magnetic cross-axis
sensitivity
M_EFMaximum exposed field
Magnetic FS = 2gauss;
LR setting
CTRL5 (M_RES [1,0]) = 00b
Cross field = 0.5 gauss
Applied = ±3 gauss
No permitting effect on zero
reading
5
±1
10000gauss
mgauss/
RMS
%FS/
gauss
Sensitivity starts to degrade.
M_DFMagnetic disturbing field
LA_ST
Linear acceleration self-test
positive difference
(6)
Automatic S/R pulse restores
the sensitivity
(5)
±2g range, X, Y-axis
AST = 1 see Table 37
±2g range, Z-axis
AST = 1 see Table 37
70
70
20gauss
1700
1700
TopOperating temperature range-40+85°C
1. Typical specifications are not guaranteed.
2. Verified by wafer level test and measurement of initial offset and sensitivity.
3. Typical zero-g level offset value after MSL3 preconditioning.
4. Offset can be eliminated by enabling the built-in high-pass filter.
5. Set/reset pulse is automatically applied at each conversion cycle.
“Self-test output change” is defined as: OUTPUT[mg]
6.
(CTRL5 AST bit =1)
- OUTPUT[mg]
(
CTRL5 AST bit =0
.
)
mg
2.2 Temperature sensor characteristics
@ Vdd = 2.5 V, T = 25 °C unless otherwise noted
Table 4.Temperature sensor characteristics
SymbolParameterTest conditionsMin.Typ.
TSDr
TODRTemperature refresh rate
Top Operating temperature range-40+85°C
1. Typical specifications are not guaranteed.
2. Refer to Table 47: Magnetic data rate configuration.
Temperature sensor output
change vs. temperature
-
b. The product is factory calibrated at 2.5 V.
(b)
.
(1)
8LSB/°C
M_ODR
(2)
[2:0]
Max.Unit
Hz
Doc ID 023312 Rev 111/54
Module specificationsLSM303D
2.3 Electrical characteristics
@ Vdd = 2.5 V, T = 25 °C unless otherwise noted.
Table 5.Electrical characteristics
SymbolParameter
Tes t
conditions
Min.Typ.
(1)
Max.Unit
VddSupply voltage2.163.6V
Vdd_IOModule power supply for I/O1.711.8Vdd+0.1
LR setting
Idd
eCompass
in normal mode
(2)
current consumption
(3)
CTRL5 (M_RES
[1,0]) = 00b, see
300µA
Ta bl e 4 5
IddSL
Current consumption in
power-down
(4)
1µA
TopOperating temperature range-40+85
1. Typical specifications are not guaranteed.
2. eCompass
3. Magnetic sensor setting ODR =6.25 Hz, accelerometer sensor ODR = 50 Hz and magnetic high resolution setting.
4. Linear accelerometer and magnetic sensor in power-down mode.
: accelerometer - magnetic sensor.
°C
12/54Doc ID 023312 Rev 1
LSM303DModule specifications
SPC
CS
SDI
SDO
t
su(CS)
t
v(SO)
t
h(SO)
t
h(SI)
t
su(SI)
t
h(CS)
t
dis(SO)
t
c(SPC)
MSB IN
MSB OUT
LSB OUT
LSB IN
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
2.4 Communication interface characteristics
2.4.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Table 6.SPI slave timing values
(1)
Val ue
SymbolParameter
Min.Max.
tc(SPC)SPI clock cycle100ns
fc(SPC)SPI clock frequency10MHz
tsu(CS)CS setup time5
th(CS)CS hold time20
tsu(SI)SDI input setup time5
th(SI)SDI input hold time15
tv(SO)SDO valid output time50
th(SO)SDO output hold time5
tdis(SO)SDO output disable time50
Unit
ns
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
tested in production.
(2)
Figure 3.SPI slave timing diagram
2. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.
Doc ID 023312 Rev 113/54
Module specificationsLSM303D
SD A
SCL
t
f(SD A )
t
su(SP)
t
w(SCLL)
t
su(SD A)
t
r(SDA )
t
su(SR)
t
h(ST)
t
w(SCLH )
t
h(SDA )
t
r(SCL)
t
f(SCL)
t
w(SP:SR)
STAR T
REPEATED
STA RT
STO P
STA RT
2.4.2 Sensor I2C - inter IC control interface
Subject to general operating conditions for Vdd and Top.
Table 7.I2C slave timing values
SymbolParameter
I2C standard mode
(1)
I2C fast mode
Min.Max.Min.Max.
(1)
Unit
f
(SCL)
t
w(SCLL)
t
w(SCLH)
t
su(SDA)
t
h(SDA)
t
r(SDA) tr(SCL)
t
f(SDA) tf(SCL)
t
h(ST)
t
su(SR)
t
su(SP)
t
w(SP:SR)
SCL clock frequency01000400kHz
SCL clock low time4.71.3
SCL clock high time4.00.6
SDA setup time250100ns
SDA data hold time03.4500.9µs
SDA and SCL rise time100020 + 0.1C
SDA and SCL fall time30020 + 0.1C
START condition hold time40.6
Repeated START condition
setup time
4.70.6
STOP condition setup time40.6
Bus free time between STOP
and START condition
4.71.3
1. Data based on standard I2C protocol requirement, not tested in production.
2. Cb = total capacitance of one bus line, in pF.
Figure 4.I
2
C slave timing diagram
(3)
µs
(2)
b
(2)
b
300
ns
300
µs
3. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
14/54Doc ID 023312 Rev 1
LSM303DModule specifications
This is a mechanical shock sensitive device, improper handling can cause permanent
damage to the part
This is an ESD sensitive device, improper handling can cause permanent damage to
the part
2.5 Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 8.Absolute maximum ratings
SymbolRatingsMaximum valueUnit
VddSupply voltage-0.3 to 4.8V
Vdd_IOI/O pins supply voltage-0.3 to 4.8V
Vin
Input voltage on any control pin (SCL/SPC,
SDA/SDI/SDO, SDO/SA0, CS)
-0.3 to Vdd_IO +0.3V
A
A
T
POW
UNP
T
OP
STG
Acceleration (any axis, powered, Vdd = 2.5 V)
Acceleration (any axis, unpowered)
Operating temperature range-40 to +85°C
Storage temperature range-40 to +125°C
Note:Supply voltage on any pin should never exceed 4.8 V.
3,000 for 0.5 msg
10,000 for 0.1 msg
3,000 for 0.5 msg
10,000 for 0.1 msg
Doc ID 023312 Rev 115/54
TerminologyLSM303D
3 Terminology
3.1 Set/reset pulse
The set/reset pulse is an automatic operation performed before each magnetic acquisition
cycle to de-gauss the sensor and to ensure alignment of the magnetic dipoles and therefore
the linearity of the sensor itself.
3.2 Sensitivity
3.2.1 Linear acceleration sensor sensitivity
Sensitivity describes the gain of the sensor and can be determined, for example, by applying
1 g acceleration to it. As the sensor can measure DC accelerations this can be done easily
by pointing the axis of interest towards the center of the earth, noting the output value,
rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again.
By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value
from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the
sensor. This value changes very little over temperature and also time. The sensitivity
tolerance describes the range of sensitivities of a large population of sensors.
3.2.2 Magnetic sensor sensitivity
Sensitivity describes the gain of the sensor and can be determined, for example, by applying
a magnetic field of 1 gauss to it.
3.3 Zero-g level
Zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal
output signal if no acceleration is present. A sensor in a steady-state on a horizontal surface
measures 0 g in X-axis and 0 g in Y-axis, whereas the Z-axis measures 1 g. The output is
ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, data
expressed as 2’s complement). A deviation from the ideal value in this case is called Zero-g
offset. Offset is, to some extent, a result of stress to MEMS sensor and therefore the offset
can slightly change after mounting the sensor onto a printed circuit board or exposing it to
extensive mechanical stress. Offset changes little over temperature, see “Zero-g level
change vs. temperature”. The Zero-g level tolerance (TyOff) describes the standard
deviation of the range of Zero-g levels of a population of sensors.
3.4 Zero-gauss level
Zero-gauss level offset describes the deviation of an actual output signal from the ideal
output if no magnetic field is present. Thanks to the set/reset pulse and to the magnetic
sensor read-out chain, the offset is dynamically cancelled. The Zero-gauss level does not
show any dependencies from temperature and power supply.
16/54Doc ID 023312 Rev 1
LSM303DFunctionality
4 Functionality
4.1 Self-test
Self-test allows to check the linear acceleration sensor functionality without moving it. The
self-test function is off when the self-test bit (ST) is programmed to ‘0‘. When the self-test bit
is programmed to ‘1’, an actuation force is applied to the sensor, simulating a definite input
acceleration. In this case the sensor outputs exhibit a change in their DC levels which are
related to the selected full-scale through the device sensitivity. When self-test is activated,
the device output level is given by the algebraic sum of the signals produced by the
acceleration acting on the sensor and by the electrostatic test-force. If the output signals
change within the amplitude specified inside Section 2.1, then the sensor is working
properly and the parameters of the interface chip are within the defined specifications.
4.2 Temperature sensor
The LSM303D features an internal temperature sensor. Temperature data can be enabled
by setting the TEMP_EN bit on the CTRL5 (24h) register to 1.
Both TEMP_OUT_H and TEMP_OUT_L registers must be read.
Temperature data is stored inside TEMP_OUT_L (05h), TEMP_OUT_H (06h) as 2’s
complement data in 12-bit format, right justified.
The output data rate of the temperature sensor is set by M_ODR [2:0] in CTRL5 (24h) and is
equal to the magnetic sensor output data rate.
4.3 FIFO
The LSM303D embeds an acceleration data FIFO for each of the three output channels, X,
Y and Z. This allows a consistent power saving for the system, as the host processor does
not need to continuously poll data from the sensor, but it can wake up only when needed
and burst the significant data out from the FIFO. This buffer can work according to four
different modes: Bypass mode, FIFO mode, Stream mode and Stream-to-FIFO mode. Each
mode is selected by the FIFO_MODE bits. Programmable threshold level, FIFO_empty or
FIFO_Full events can be enabled to generate dedicated interrupts on the INT1/2 pin.
Bypass mode
In Bypass mode, the FIFO is not operational and for this reason it remains empty. As
described in Figure 5, for each channel only the first address is used. The remaining FIFO
slots are empty.
FIFO mode
In FIFO mode, data from X, Y and Z channels are stored in the FIFO. A FIFO threshold
interrupt can be enabled in order to be raised when the FIFO is filled to the level specified by
the internal register. The FIFO continues filling until it is full. When full, the FIFO stops
collecting data from the input channels.
Doc ID 023312 Rev 117/54
FunctionalityLSM303D
Stream mode
In Stream mode, data from X, Y and Z measurements are stored in the FIFO. A FIFO
threshold interrupt can be enabled and set as in FIFO mode.The FIFO continues filling until
it’s full. When full, the FIFO discards the older data as the new arrive.
Stream-to-FIFO mode
In Stream-to-FIFO mode, data from X, Y and Z measurements are stored in the FIFO. A
FIFO threshold interrupt can be enabled in order to be raised when the FIFO is filled to the
level specified by the internal register. The FIFO continues filling until it’s full. When full, the
FIFO discards the older data as the new arrive. Once a trigger event occurs, the FIFO starts
operating in FIFO mode.
Bypass-to-Stream mode
In Bypass-to-Stream mode, the FIFO starts operating in Bypass mode and once a trigger
event occurs (related to IG_CFG1 (30h) register events), the FIFO starts operating in
Stream mode.
Retrieve data from FIFO
FIFO data is read through OUT_X_A, OUT_Y_A and OUT_Z_A registers. When the FIFO is
in Stream, Trigger or FIFO mode, a read operation to the OUT_X_A, OUT_Y_A or
OUT_Z_A registers provides the data stored in the FIFO. Each time data is read from the
FIFO, the oldest X, Y and Z data are placed in the OUT_X_A, OUT_Y_A and OUT_Z_A
registers and both single read and read_burst operations can be used.
4.4 Factory calibration
The IC interface is factory calibrated. The trimming values are stored inside the device by a
non-volatile memory. Anytime the device is turned on, the trimming parameters are
downloaded into the registers to be used during normal operation. This allows the user to
use the device without further calibration.
18/54Doc ID 023312 Rev 1
LSM303DApplication hints
CS
C3= 10µF
Vdd
C4 = 100nF
GND
Vdd_IO
SDO/SA0
SDA/SDI/SDO
INT 1
SCL/SPC
Digital signal from/to signal controller. Signal’s levels are defined by proper selection of Vdd_IO
1
5
8
13
TOP VIEW
6
9
1416
9
5
INT 2
C1= 4.7µF
C2=0.22µF
AM12678V1
5 Application hints
Figure 5.LSM303D electrical connection
5.1 External capacitors
The C1 and C2 external capacitors should be low SR value ceramic type construction (typ.
suggested value 200 mΩ). Reservoir capacitor C1 is nominally 4.7 µF in capacitance, with
the set/reset capacitor C2 nominally 0.22 µF in capacitance.
The device core is supplied through the Vdd line. Power supply decoupling capacitors
(C4=100 nF ceramic, C3=10 µF Al) should be placed as near as possible to the supply pin
of the device (common design practice). All the voltage and ground supplies must be
present at the same time to have proper behavior of the IC (refer to Figure 5).
The functionality of the device and the measured acceleration/magnetic field data is
selectable and accessible through the I
5.2 Pull-up resistors
The functions, the threshold and the timing of the two interrupt pins (INT1 and INT2) can be
completely programmed by the user through the I
If an I2C interface is used, pull-up resistors (suggested value 10 kΩ) must be placed on the
2
two I
C bus lines.
2
C/SPI interfaces.
Doc ID 023312 Rev 119/54
2
C/SPI interfaces.
Application hintsLSM303D
5.3 Digital Interface power supply
This digital interface, dedicated to the linear acceleration and to the magnetic field signal, is
capable of operating with a standard power supply (Vdd) or using a dedicated power supply
(Vdd_IO).
5.4 Soldering information
The LGA package is compliant with ECOPACK®, RoHS and “Green” standards.
It is qualified for soldering heat resistance according to JEDEC J-STD-020.
Leave “Pin 1 Indicator” unconnected during soldering.
Land pattern and soldering recommendations are available at www.st.com/mems
5.5 High-current wiring effects
High current in wiring and printed circuit trace can be the cause of errors in magnetic field
measurements for compassing.
Conductor generated magnetic fields add to the earth’s magnetic field creating errors in
compass heading computations.
Keep currents higher than 10 mA a few millimeters further away from the sensor IC.
.
20/54Doc ID 023312 Rev 1
LSM303DDigital interfaces
6 Digital interfaces
The registers embedded in the LSM303D may be accessed through both the I2C and SPI
serial interfaces. The latter may be SW-configured to operate either in 3-wire or 4-wire
interface mode.
The serial interfaces are mapped onto the same pins. To select/exploit the I
CS line must be tied high (i.e connected to Vdd_IO).
Table 9.Serial interface pin description
Pin namePin description
2
C interface, the
CS
SCL/SPC
SDA/SDI/SDO
SDO/SA0
I2C/SPI mode selection (1: SPI idle mode / I2C communication enabled; 0: SPI
communication mode / I
2
I
C serial clock (SCL)
SPI serial port clock (SPC)
2
I
C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
SPI serial data output (SDO)
2
I
C less significant bit of the device address (SA0)
6.1 I2C serial interface
The LSM303D I2C is a bus slave. The I2C is employed to write data into registers whose
content can also be read back.
The relevant I
Table 1 0 .I2C terminology
TransmitterThe device which sends data to the bus
ReceiverThe device which receives data from the bus
2
C terminology is given in the table below.
TermDescription
2
C disabled)
Master
SlaveThe device addressed by the master
The device which initiates a transfer, generates clock signals and terminates a
transfer
There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial
data line (SDA). The latter is a bi-directional line used for sending and receiving the data
to/from the interface. Both lines must be connected to Vdd_IO through external pull-up
resistors. When the bus is free, both lines are high.
2
The I
C interface is compliant with fast mode (400 kHz) I2C standards as well as with normal
mode.
Doc ID 023312 Rev 121/54
Digital interfacesLSM303D
6.1.1 I2C operation
The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the master, the bus is considered busy. The next byte of data
transmitted after the START condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a START condition with its address. If they match, the device considers itself
addressed by the master.
The slave address (SAD) associated to the LSM303D is 00111xxb, whereas the xx bits are
modified by the SDO/SA0 pin in order to modify the device address. If the SDO/SA0 pin is
connected to the voltage supply, the address is 0011101b, otherwise, if the SDO/SA0 pin is
connected to ground, the address is 0011110b. This solution permits the connection and
addressing of two different accelerometers to the same I
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line low so that it
remains stable low during the high period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data
received.
2
The I
C embedded in the LSM303D behaves as a slave device and the following protocol
must be adhered to. After the START condition (ST) a slave address is sent, once a slave
acknowledge (SAK) has been returned, an 8-bit sub-address is transmitted: the 7 LSb
represent the actual register address while the MSb enables address auto-increment. If the
MSb of the SUB field is 1, the SUB (register address) is automatically incremented to allow
multiple data read/write.
2
C lines.
The slave address is completed with a read/write bit. If the bit is ‘1’ (read), a repeated
START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (write)
the master transmits to the slave with direction unchanged. Ta b le 1 1 explains how the
SAD+read/write bit pattern is composed, listing all the possible configurations.
Table 11.SAD+read/write patterns
CommandSDO/SA0 pin SAD[6:2]SAD[1:0]R/WSAD+R/W
Read0001111013D
Write0001111003C
Read1001110113B
Write1001110103A
Table 12.Transfer when master is writing one byte to slave
MasterSTSAD + WSUBDATASP
SlaveSAKSAKSAK
22/54Doc ID 023312 Rev 1
LSM303DDigital interfaces
Table 13.Transfer when master is writing multiple bytes to slave
MasterSTSAD + WSUBDATADATASP
SlaveSAKSAKSAKSAK
Table 14.Transfer when master is receiving (reading) one byte of data from slave
MasterSTSAD + WSUBSRSAD + RNMAKSP
SlaveSAKSAKSAKDATA
Table 15.Transfer when master is receiving (reading) multiple bytes of data from slave
Master ST SAD+WSUBSR SAD+RMAKMAKNMAKSP
SlaveSAKSAKSAK DATADATADATA
Data is transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of
bytes sent per transfer is unlimited. Data is transferred with the most significant bit (MSb)
first. If a receiver cannot receive another complete byte of data until it has performed some
other function, it can hold the clock line, SCL, LOW to force the transmitter into a wait state.
Data transfer only continues when the receiver is ready for another byte and releases the
data line. If a slave receiver does not acknowledge the slave address (i.e. it is not able to
receive because it is performing some real-time function) the data line must be left HIGH by
the slave. The master can then abort the transfer. A low to high transition on the SDA line
while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to ‘1’ while SUB(6-0) represents the
address of the first register to be read.
In the communication format presented, MAK is master acknowledge and NMAK is no
master acknowledge.
6.2 SPI bus interface
The SPI is a bus slave. The SPI allows writing and reading the registers of the device.
The serial interface interacts with the outside world through 4 wires: CS, SPC, SDI and
SDO.
Doc ID 023312 Rev 123/54
Digital interfacesLSM303D
CS
SPC
SDI
SDO
RW
AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
MS
AM10129V1
Figure 6.Read and write protocol
CS is the serial port enable and is controlled by the SPI master. It goes low at the start of the
transmission and goes back high at the end. SPC is the serial port clock and it is controlled
by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are
respectively the serial port data input and output. These lines are driven at the falling edge
of SPC and should be captured at the rising edge of SPC.
Both the read register and write register commands are completed in 16 clock pulses or in
multiples of 8 in the case of multiple byte read/write. Bit duration is the time between two
falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling
edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just
before the rising edge of CS.
bit 0: RW
bit. When 0, the data DI(7:0) is written to the device. When 1, the data DO(7:0)
from the device is read. In the latter case the chip drives SDO at the start of bit 8.
bit 1: MS
bit. When 0, the address remains unchanged in multiple read/write commands.
When 1, the address is auto-incremented in multiple read/write commands.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written to the device (MSb first).
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
In multiple read/write commands, further blocks of 8 clock periods are added. When the MS
bit is 0, the address used to read/write data remains the same for every block. When the MS
bit is 1, the address used to read/write data is incremented at every block.
The function and the behavior of SDI and SDO remain unchanged.
24/54Doc ID 023312 Rev 1
LSM303DDigital interfaces
CS
SPC
SDI
SDO
RW
DO7 DO6 DO5DO4 DO3 DO2 DO1 DO0
AD5 AD4 AD3 AD2 AD1 AD0
MS
AM10130V1
C S
SPC
SDI
SDO
RW
DO7DO6DO5DO4DO3 DO 2 DO1 DO 0
AD5 AD4AD3 AD2 AD1 AD0
DO15 DO 14 DO 13 DO 12 DO11 DO 10 D O9 D O8
M S
AM10131V1
6.2.1 SPI read
Figure 7.SPI read protocol
The SPI read command is performed with 16 clock pulses. The multiple byte read command
is performed by adding blocks of 8 clock pulses to the previous one.
bit 0: READ bit. The value is 1.
bit 1: MS
bit. When 0, do not increment address; when 1, increment address in multiple
reading.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
bit 16-... : data DO(...-8). Further data in multiple byte reading.
DI7 DI6 DI5 DI4 DI3 DI 2 DI1 DI0 DI15 D I1 4 DI13 DI12 DI 11 DI10 DI 9 DI8
MS
AM10133V1
6.2.2 SPI write
Figure 9.SPI write protocol
The SPI write command is performed with 16 clock pulses. The multiple byte write
command is performed by adding blocks of 8 clock pulses to the previous one.
bit 0: WRITE bit. The value is 0.
bit 1: MS
bit. When 0, do not increment address; when 1, increment address in multiple
writing.
bit 2 -7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written to the device (MSb first).
bit 16-... : data DI(...-8). Further data in multiple byte writing.
3-wire mode is entered by setting the bit SIM (SPI serial interface mode selection) to ‘1’ in
CTRL2 (21h).
26/54Doc ID 023312 Rev 1
LSM303DDigital interfaces
CS
SPC
SDI/O
RW
DO7 DO6 DO5 DO4 DO3 DO 2 DO 1 DO 0
AD5 AD 4 AD3 AD2 AD1 AD 0MS
AM10134V1
Figure 11.SPI read protocol in 3-wire mode
The SPI read command is performed with 16 clock pulses:
bit 0: READ bit. The value is 1.
bit 1: MS
bit. When 0, do not increment address; when 1, increment address in multiple
reading.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
Multiple read command is also available in 3-wire mode.
Doc ID 023312 Rev 127/54
Output register mappingLSM303D
7 Output register mapping
The table below provides a listing of the 8-bit registers embedded in the device, and the
related addresses:
Table 16.Register address map
Register address
NameType
HexBinary
Reserved--00-04----Reserved
TEMP_OUT_Lr05000 0101Output
TEMP_OUT_Hr06000 0110Output
STATUS_Mr07000 0111Output
OUT_X_L_Mr08000 1000Output
OUT_X_H_Mr09000 1001Output
OUT_Y_L_Mr0A000 1010Output
OUT_Y_H_Mr0B000 1011Output
DefaultComment
OUT_Z_L_Mr0C000 1100Output
OUT_Z_H_Mr0D000 1101Output
Reserved--0E000 1110--Reserved
WHO_AM_Ir0F000 111101001001
Reserved--10-11----Reserved
INT_CTRL_Mrw12001 001011101000
INT_SRC_Mr13001 0011Output
INT_THS_L_Mrw14001 010000000000
INT_THS_H_Mrw15001 010100000000
OFFSET_X_L_Mrw16001 011000000000
OFFSET_X_H_Mrw17001 011100000000
OFFSET_Y_L_Mrw18001 0100000000000
OFFSET_Y_H_Mrw19001 0100100000000
OFFSET_Z_L_Mrw1A001 0101000000000
OFFSET_Z_H_Mrw1B001 0101100000000
REFERENCE_Xrw1C001 0110000000000
REFERENCE_Yrw1D001 0110100000000
REFERENCE_Zrw1E001 0111000000000
CTRL0rw1F001 111100000000
CTRL1rw20010 000000000111
CTRL2rw21010 000100000000
28/54Doc ID 023312 Rev 1
LSM303DOutput register mapping
Table 16.Register address map (continued)
Register address
NameType
HexBinary
CTRL3rw22010 001000000000
CTRL4rw23010 001100000000
CTRL5rw24010 010000011000
CTRL6rw25010 010100100000
CTRL7rw26010 011000000001
STATUS_Ar27010 0111Output
OUT_X_L_Ar28010 1000Output
OUT_X_H_Ar29010 1001Output
OUT_Y_L_Ar2A010 1010Output
OUT_Y_H_Ar2B010 1011Output
OUT_Z_L_Ar2C010 1100Output
OUT_Z_H_Ar2D010 1101Output
DefaultComment
FIFO_CTRLrw2E010 111000000000
FIFO_SRCr2F010 1111Output
IG_CFG1rw30011 000000000000
IG_SRC1r31011 0001Output
IG_THS1rw32011 001000000000
IG_DUR1rw33011 001100000000
IG_CFG2rw34011 010000000000
IG_SRC2r35011 0101Output
IG_THS2rw36011 011000000000
IG_DUR2rw37011 011100000000
CLICK_CFGrw38011 100000000000
CLICK_SRCr39011 1001Output
CLICK_THSrw3A011 101000000000
TIME_LIMITrw3B011 101100000000
TIME _LATENCYrw3C011 110000000000
TIME_WINDOWrw3D011 110100000000
Act_THSrw3E011 111000000000
Act_DURrw3F011 111100000000
Registers marked as Reserved must not be changed. Writing to these registers may cause
permanent damage to the device.
Doc ID 023312 Rev 129/54
Output register mappingLSM303D
The content of the registers that are loaded at boot should not be changed. They contain the
factory calibration values. Their content is automatically restored when the device is
powered up.
30/54Doc ID 023312 Rev 1
LSM303DRegister description
8 Register description
The device contains a set of registers which are used to control its behavior and to retrieve
acceleration and magnetic data. The register address, consisting of 7 bits, is used to identify
them and to write the data through the serial interface.
8.1 TEMP_OUT_L (05h), TEMP_OUT_H (06h)
Temperature sensor data. Temperature data is stored as 2’s complement data in 12-bit
format, right justified.
Refer to Section 4.2 for details on how to enable and read the temperature sensor output
data.
Magnetic X, Y and Z-axis and temperature data overrun. Default value: 0
(0: no overrun has occurred; 1: a new set of data has overwritten the previous ones)
Temperature data overrun if T_ONLY bit inCTRL7 (26h) is set to ‘1’. Default value: 0.
(0: no overrun has occurred; 1: a new data for the Z-axis has overwritten the previous
one)
(0: no overrun has occurred; 1: a new data for the Y-axis has overwritten the previous
one)
(0: no overrun has occurred; 1: a new data for the X-axis has overwritten the previous
one)
X, Y and Z-axis and temperature new data available. Default value: 0
(0: a new set of data is not yet available; 1: a new set of data is available)
Temperature new data available if the T_ONLY bit inCTRL7 (26h) is set to ‘1’.
(0: a new data for the Z-axis is not yet available; 1: a new data for the Z-axis is available)
(0: a new data for the Y-axis is not yet available; 1: a new data for the Y-axis is available)
XMDAX-axis new data available. Default value: 0
(0: a new data for the X-axis is not yet available; 1: a new data for the X-axis is available)
Doc ID 023312 Rev 131/54
Register descriptionLSM303D
8.3 OUT_X_L_M (08h), OUT_X_H_M (09h)
X-axis magnetic data. The value is expressed in 16-bit as 2’s complement.
8.4 OUT_Y_L_M (0Ah), OUT_X_H_M (0Bh)
Y-axis magnetic data. The value is expressed in 16-bit as 2’s complement.
8.5 OUT_X_L_M (0Ch), OUT_X_H_M (0Dh)
Z-axis magnetic data. The value is expressed in 16-bit as 2’s complement.
8.6 WHO_AM_I (0Fh)
Table 19.WHO_AM_I register
0 1 0 01001
Device identification register.
8.7 INT_CTRL_M (12h)
Table 20.INT_CTRL_M register
XMIENYMIENZMIENPP_ODMIEAMIEL4DMIEN
Table 21.INT_CTRL_M description
XMIENEnable interrupt recognition on X-axis for magnetic data. Default value: 0.
(0: interrupt active low; 1: interrupt active high)
MIELLatch interrupt request on INT_SRC_M (13h) register. Default value: 0.
(0: interrupt request not latched; 1: interrupt request latched)
Once the MIEL is set to ‘1’, the interrupt is cleared by reading the INT_SRC_M (13h)
register.
32/54Doc ID 023312 Rev 1
LSM303DRegister description
Table 21.INT_CTRL_M description (continued)
4D4D enable: 4D detection on acceleration data is enabled when 6D bit in IG_CFG1
(30h) is set to 1. Default value: 0.
MIENEnable interrupt generation for magnetic data. Default value: 0.
AFDSFiltered acceleration data selection. Default value: 0
(0: internal filter bypassed; 1: data from internal filter sent to output register and FIFO)
T_ONLYTemperature sensor only mode. Default value: 0
If this bit is set to ‘1’, the temperature sensor is on while the magnetic sensor is off.
MLPMagnetic data low-power mode. Default value: 0
If this bit is ‘1’, the M_ODR [2:0] is set to 3.125 Hz independently from the MODR settings. Once the bit is set to ‘0’, the magnetic data rate is configured by MODR bits in
AOIAnd/Or combination of interrupt events. Default value: 0.
Refer to Ta bl e 6 4
6D6-direction detection function enabled. Default value: 0.
Refer to Ta bl e 6 4
ZHIE/
ZUPE
ZLIE/
ZDOWNE
YHIE/
YUPE
YLIE/
YDOWNE
XHIE/
XUPE
XLIE/
XDOWNE
Enable interrupt generation on Z high event or on direction recognition. Default
value: 0 (0: disable interrupt request; 1: enable interrupt request)
Enable interrupt generation on Z low event or on direction recognition. Default
value: 0 (0: disable interrupt request; 1: enable interrupt request)
Enable interrupt generation on Y high event or on direction recognition. Default
value: 0 (0: disable interrupt request; 1: enable interrupt request.)
Enable interrupt generation on Y low event or on direction recognition. Default
value: 0 (0: disable interrupt request; 1: enable interrupt request.)
Enable interrupt generation on X high event or on direction recognition. Default
value: 0 (0: disable interrupt request; 1: enable interrupt request.)
Enable interrupt generation on X low event or on direction recognition. Default
value: 0 (0: disable interrupt request; 1: enable interrupt request.)
Content of this register is loaded at boot.
Write operation at this address is possible only after system boot.
Doc ID 023312 Rev 143/54
Register descriptionLSM303D
Table 64.Interrupt mode
AOI6DInterrupt mode
00OR combination of interrupt events
016-direction movement recognition
10AND combination of interrupt events
116-direction position recognition
Difference between AOI-6D = ‘01’ and AOI-6D = ‘11’.
AOI-6D = ‘01’ is movement recognition. An interrupt is generated when orientation moves
from an unknown zone to a known zone. The interrupt signal stays for a duration ODR.
AOI-6D = ‘11’ is direction recognition. An interrupt is generated when orientation is inside a
known zone. The interrupt signal stays until orientation is inside the zone.
8.31 IG_SRC1 (31h)
Inertial interrupt generator 1 status register.
Table 65.IG_SRC1 register
0 IA ZHZLYHYLXHXL
Table 66.IG_SRC1 register description
IA
ZH
ZL
YH
YL
XH
XL
Interrupt status. Default value: 0
(0: no interrupt has been generated; 1: one or more interrupts have been generated)
Z high. Default value: 0
(0: no interrupt; 1: Z high event has occurred)
Z low. Default value: 0
(0: no interrupt; 1: Z low event has occurred)
Y high. Default value: 0
(0: no interrupt; 1: Y high event has occurred)
Y low. Default value: 0
(0: no interrupt; 1: Y low event has occurred)
X high. Default value: 0
(0: no interrupt; 1: X high event has occurred)
X low. Default value: 0
(0: no interrupt; 1: X low event has occurred)
Reading at this address clears the IG_SRC1 (31h) IA bit (and the interrupt signal on the
corresponding interrupt pin) and allows the refreshment of data in the IG_SRC1 (31h)
register if the latched option was chosen.
D6 - D0 bits set the minimum duration of the interrupt 1 event to be recognized. Duration
steps and maximum values depend on the ODR chosen.
8.34 IG_CFG2 (34h)
This register contains the settings for the inertial interrupt generator 2.
Table 71.IG_CFG2 register
AOI6DZHIE/
Table 72.IG_CFG2 register description
AOIAnd/Or combination of interrupt events. Default value: 0. Refer to Ta bl e 7 3
6D6-direction detection function enabled. Default value: 0. Refer to Ta bl e 7 3
ZHIE/
ZUPE
ZLIE/
ZDOWNE
YHIE/
YUPE
YLIE/
YDOWNE
Enable interrupt generation on Z high event or on direction recognition. Default
value: 0 (0: disable interrupt request; 1: enable interrupt request)
Enable interrupt generation on Z low event or on direction recognition. Default
value: 0 (0: disable interrupt request; 1: enable interrupt request)
Enable interrupt generation on Y high event or on direction recognition. Default
value: 0 (0: disable interrupt request; 1: enable interrupt request.)
Enable interrupt generation on Y low event or on direction recognition. Default
value: 0 (0: disable interrupt request; 1: enable interrupt request.)
ZUPE
ZLIE/
ZDOWNE
YHIE/
YUPE
YLIE/
YDOWNE
XHIE/
XUPE
XLIE/
XDOWNE
Doc ID 023312 Rev 145/54
Register descriptionLSM303D
Table 72.IG_CFG2 register description (continued)
XHIE/
XUPE
XLIE/
XDOWNE
Enable interrupt generation on X high event or on direction recognition. Default
value: 0 (0: disable interrupt request; 1: enable interrupt request.)
Enable interrupt generation on X low event or on direction recognition. Default
value: 0 (0: disable interrupt request; 1: enable interrupt request.)
Content of this register is loaded at boot.
Write operation at this address is possible only after system boot.
Table 73.Interrupt mode
AOI6DInterrupt mode
00OR combination of interrupt events
016-direction movement recognition
10AND combination of interrupt events
116-direction position recognition
Difference between AOI-6D = ‘01’ and AOI-6D = ‘11’.
AOI-6D = ‘01’ is movement recognition. An interrupt is generated when orientation moves
from an unknown zone to a known zone. The interrupt signal stays for a duration ODR.
AOI-6D = ‘11’ is direction recognition. An interrupt is generated when orientation is inside a
known zone. The interrupt signal stays until orientation is inside the zone.
8.35 IG_SRC2 (35h)
This register contains the status for the inertial interrupt generator 2.
Table 74.IG_SRC2 register
0 IA ZHZLYHYLXHXL
Table 75.IG_SRC2 register description
IA
ZH
ZL
Interrupt generator 2 status. Default value: 0
(0: no interrupt has been generated; 1: one or more interrupts have been generated)
Z high. Default value: 0
(0: no interrupt; 1: Z high event has occurred)
Z low. Default value: 0
(0: no interrupt; 1: Z low event has occurred)
YH
YL
46/54Doc ID 023312 Rev 1
Y high. Default value: 0
(0: no interrupt; 1: Y high event has occurred)
Y low. Default value: 0
(0: no interrupt; 1: Y low event has occurred)
LSM303DRegister description
Table 75.IG_SRC2 register description (continued)
XH
X high. Default value: 0
(0: no interrupt; 1: X high event has occurred)
XL
Reading at this address clears the IG_SRC2 (35h) IA bit (and the interrupt signal on the
corresponding interrupt pin) and allows the refreshment of data in the IG_SRC2 (35h)
register if the latched option was chosen.
X low. Default value: 0
(0: no interrupt; 1: X low event has occurred)
TLI [6:0]Click-click time limit. Default value: 000 0000
8.42 TIME_LATENCY (3Ch)
Table 88.TIME_LATENCY register
TLA7TLA6TLA5TLA4TLA3TLA2TLA1TLA0
Table 89.TIME_LATENCY description
TLA [7:0]Click-click time latency. Default value: 000 0000
8.43 TIME WINDOW (3Dh)
Table 90.TIME_WINDOW register
TW7TW6TW5TW4TW3TW2TW1TW0
Table 91.TIME_WINDOW description
TW [7:0]Click-click time window
Doc ID 023312 Rev 149/54
Register descriptionLSM303D
8.44 Act_THS (3Eh)
Table 92.Act_THS register
--ACTH6ACTH5ACTH4ACTH3ACTH2ACTH1ACTH0
Table 93.Act_THS register description
ACTH [6:0]Sleep to Wake, Return to Sleep activation threshold
1LSb = 16mg
8.45 Act_DUR (3Fh)
Table 94.Act_DUR register
ActD7ActD6ActD5ActD4ActD3ActD2ActD1ActD0
Table 95.Act_DUR description
ActD [7:0]Sleep to Wake, Return to Sleep duration
DUR = (Act_DUR + 1)*8/ODR
50/54Doc ID 023312 Rev 1
LSM303DPackage Information
9 Package Information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
®
packages, depending on their level of environmental compliance. ECOPACK
Doc ID 023312 Rev 151/54
Package InformationLSM303D
7983231_M
Table 96.TFLGA 3x3x1.0 16L mechanical data
mm
Dim.
Min.Typ.Max.
A11
A20.785
A30.200
D12.8503.0003.150
E12.8503.0003.150
L11.0001.060
L22.0002.060
N10.500
N21.000
M0.0400.100
P10.875
P21.275
T10.2900.3500.410
T20.1900.2500.310
d0.150
k0.050
Figure 12.TFLGA 3x3x1.0 16L mechanical drawing
52/54Doc ID 023312 Rev 1
LSM303DRevision history
10 Revision history
Table 97.Document revision history
DateRevisionChanges
22-Jun-20121Initial release.
Doc ID 023312 Rev 153/54
LSM303D
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