LD39100XX
LD39100XX12, LD39100XX25
1 A, low quiescent current, low noise voltage regulator
Features
■Input voltage from 1.5 to 5.5 V
■Ultra low dropout voltage (200 mV typ. at 1 A load)
■Very low quiescent current (20 µA typ. at no load, 200 µA typ. at 1 A load, 1 µA max in off mode)
■Very low noise with no bypass capacitor (30 µVRMS at VOUT = 0.8 V)
■Output voltage tolerance: ± 2.0 % @ 25 °C
■1 A guaranteed output current
■Wide range of output voltages available on request: 0.8 V to 4.5 V with 100 mV step and adjustable from 0.8 V
■Logic-controlled electronic shutdown
■Stabilized with ceramic capacitors COUT = 1 µF
■Internal current and thermal limit
■DFN6 (3 x 3 mm) package
■Temperature range: - 40 °C to 125 °C
Applications
■Printers
■Personal digital assistants (PDAs)
■Cordless phones
■Consumer applications
DFN6 (3 x 3 mm)
with a typical dropout voltage of 200 mV. The device is stable due to the use of ceramic capacitors on the input and output. The ultra low drop-voltage, low quiescent current and low noise features make it suitable for low power battery powered applications. Power supply rejection is 65 dB at low frequencies and starts to roll off at 10 kHz. An enable logic control function puts the LD39100xx in shutdown mode, allowing a total current consumption lower than 1 µA. The device also includes short-circuit constant current limiting and thermal protection.
Description
The LD39100xx provides 1 A maximum current from an input voltage ranging from 1.5 V to 5.5 V
Table 1. |
Device summary |
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Part numbers |
Order codes |
Output voltages |
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LD39100XX |
LD39100PUR |
Adj. from 0.8 V |
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LD39100XX12 |
LD39100PU12R |
1.2 V |
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LD39100XX25 |
LD39100PU25R |
2.5 V |
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October 2011 |
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Doc ID 15676 Rev 3 |
1/23 |
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www.st.com
Contents |
LD39100XX, LD39100XX12, LD39100XX25 |
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Contents
1 |
Circuit schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 3 |
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Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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4 |
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
15 |
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6.1 |
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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6.2 |
Enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
17 |
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6.3 |
Power Good function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
17 |
7 |
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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8 |
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2/23 |
Doc ID 15676 Rev 3 |
LD39100XX, LD39100XX12, LD39100XX25 |
Circuit schematics |
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IN |
Power-good |
PG |
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signal |
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IN |
BandGap reference
OpAmp |
Current |
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limit |
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Thermal |
OUT |
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protection |
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ADJ |
EN |
Internal |
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enable |
GND
IN |
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Power-good |
PG |
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signal |
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IN |
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BandGap |
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reference |
Current |
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OpAmp |
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limit |
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Thermal |
OUT |
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protection |
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R1 |
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NC |
EN |
Internal |
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R2 |
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enable |
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GND |
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Doc ID 15676 Rev 3 |
3/23 |
Pin configuration |
LD39100XX, LD39100XX12, LD39100XX25 |
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EN |
VIN |
EN |
VIN |
GND |
NC |
GND |
ADJ |
PG |
VOUT |
PG |
VOUT |
LD39100PUxx LD39100PU
Table 2. |
Pin description |
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Symbol |
Pin n° |
Function |
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LD39100PU |
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LD39100PUxx |
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EN |
1 |
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1 |
Enable pin logic input: Low = shutdown, High = active |
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GND |
2 |
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2 |
Common ground |
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PG |
3 |
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3 |
Power Good |
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VOUT |
4 |
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4 |
Output voltage |
ADJ |
5 |
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- |
Adjust pin |
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VIN |
6 |
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6 |
Input voltage of the LDO |
NC |
- |
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5 |
Not connected |
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GND |
EXP pad |
Exposed pad must be connected to GND |
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4/23 |
Doc ID 15676 Rev 3 |
LD39100XX, LD39100XX12, LD39100XX25 |
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Maximum ratings |
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3 |
Maximum ratings |
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Table 3. |
Absolute maximum ratings |
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Symbol |
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Parameter |
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Value |
Unit |
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VIN |
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DC input voltage |
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-0.3 to 7 |
V |
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VOUT |
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DC output voltage |
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-0.3 to VIN + 0.3 (7 V max) |
V |
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EN |
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Enable pin |
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-0.3 to VIN + 0.3 (7 V max) |
V |
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PG |
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Power Good pin |
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-0.3 to 7 |
V |
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ADJ |
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Adjust pin |
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4 |
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V |
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IOUT |
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Output current |
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Internally limited |
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PD |
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Power dissipation |
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Internally limited |
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TSTG |
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Storage temperature range |
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- 65 to 150 |
°C |
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TOP |
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Operating junction temperature range |
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- 40 to 125 |
°C |
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Note: |
Absolute maximum ratings are those values beyond which damage to the device may occur. |
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Functional operation under these conditions is not implied. All values are referred to GND. |
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Table 4. |
Thermal data |
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Symbol |
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Parameter |
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Value |
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Unit |
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RthJA |
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Thermal resistance junction-ambient |
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55 |
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°C/W |
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RthJC |
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Thermal resistance junction-case |
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10 |
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°C/W |
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Table 5. |
ESD performance |
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Symbol |
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Parameter |
Test conditions |
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Value |
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Unit |
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ESD |
ESD protection voltage |
HBM |
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4 |
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kV |
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MM |
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0.4 |
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kV |
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Doc ID 15676 Rev 3 |
5/23 |
Electrical characteristics |
LD39100XX, LD39100XX12, LD39100XX25 |
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TJ = 25 °C, VIN = 1.8 V, CIN = COUT = 1 µF, IOUT = 100 mA, VEN = VIN, unless otherwise specified.
Table 6. |
Electrical characteristics for the LD39100PU |
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Symbol |
Parameter |
Test conditions |
Min. |
Typ. |
Max. |
Unit |
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VIN |
Operating input voltage |
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1.5 |
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5.5 |
V |
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VADJ |
VADJ accuracy |
IOUT=10mA, TJ = 25°C |
784 |
800 |
816 |
mV |
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IOUT=10mA, -40°C<TJ<125°C |
776 |
800 |
824 |
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IADJ |
Adjust pin current |
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1 |
µA |
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VOUT |
Static line regulation |
VOUT+1 V ≤ VIN ≤ 5.5 V, |
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0.01 |
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%/V |
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IOUT=100mA |
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V |
Transient line regulation (1) |
VIN=500mV, IOUT=100mA, tR=5µs |
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10 |
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mVpp |
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OUT |
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VIN=500mV, IOUT=100mA, tF=5µs |
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10 |
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VOUT |
Static load regulation |
IOUT=10mA to 1A |
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0.002 |
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%/mA |
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V |
Transient load regulation (1) |
IOUT=10mA to 1A, tR=5µs |
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40 |
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mVpp |
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OUT |
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IOUT=1A to 10mA, tF=5µs |
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40 |
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VDROP |
Dropout voltage (2) |
IOUT=1A, VO fixed to 1.5V |
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200 |
400 |
mV |
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-40°C<TJ<125°C |
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eN |
Output noise voltage |
10Hz to 100kHz, IOUT=100mA, |
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30 |
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µVRMS |
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VOUT=0.8V |
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VIN=1.8V+/-VRIPPLE |
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VRIPPLE=0.25V, freq. = 1kHz |
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65 |
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SVR |
Supply voltage rejection |
IOUT=10mA |
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dB |
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VO = 0.8 V |
VIN=1.8V+/-VRIPPLE |
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VRIPPLE=0.25V, freq.=10kHz |
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62 |
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IOUT=100mA |
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IOUT=0mA |
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20 |
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IOUT=0mA, -40°C<TJ<125°C |
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50 |
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IQ |
Quiescent current |
IOUT=0 to 1A |
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200 |
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µA |
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IOUT=0 to 1A, -40°C<TJ<125°C |
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300 |
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VIN input current in off mode: |
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0.001 |
1 |
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VEN=GND(3) |
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Rising edge |
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0.92* |
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VOUT |
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Power good output threshold |
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V |
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PG |
Falling edge |
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0.8* |
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VOUT |
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Power good output voltage low |
Isink=6mA open drain output |
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0.4 |
V |
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ISC |
Short-circuit current |
RL=0 |
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1.5 |
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A |
6/23 |
Doc ID 15676 Rev 3 |
LD39100XX, LD39100XX12, LD39100XX25 |
Electrical characteristics |
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Table 6. Electrical characteristics for the LD39100PU (continued)
Symbol |
Parameter |
Test conditions |
Min. |
Typ. |
Max. |
Unit |
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VEN |
Enable input logic low |
VIN=1.5V to 5.5V, -40°C<TJ<125°C |
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0.4 |
V |
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Enable input logic high |
0.9 |
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V |
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IEN |
Enable pin input current |
VEN= VIN |
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0.1 |
100 |
nA |
tON |
Turn-on time (4) |
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30 |
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µs |
TSHDN |
Thermal shutdown |
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160 |
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°C |
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Hysteresis |
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20 |
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Capacitance (see typical |
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COUT |
Output capacitor |
performance characteristics for |
1 |
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22 |
µF |
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stability) |
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1.All transient values are guaranteed by design, not production tested
2.Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply for output voltages below 1.5 V
3.PG pin floating
4.Turn-on time is time measured between the enable input just exceeding VEN high value and the output voltage just reaching 95% of its nominal value
Doc ID 15676 Rev 3 |
7/23 |