ST LD39100PUR, LD39100PU12R, LD39100PU25R User Manual

LD39100XX

LD39100XX12, LD39100XX25

1 A, low quiescent current, low noise voltage regulator

Features

■Input voltage from 1.5 to 5.5 V

■Ultra low dropout voltage (200 mV typ. at 1 A load)

■Very low quiescent current (20 µA typ. at no load, 200 µA typ. at 1 A load, 1 µA max in off mode)

■Very low noise with no bypass capacitor (30 µVRMS at VOUT = 0.8 V)

■Output voltage tolerance: ± 2.0 % @ 25 °C

■1 A guaranteed output current

■Wide range of output voltages available on request: 0.8 V to 4.5 V with 100 mV step and adjustable from 0.8 V

■Logic-controlled electronic shutdown

■Stabilized with ceramic capacitors COUT = 1 µF

■Internal current and thermal limit

■DFN6 (3 x 3 mm) package

■Temperature range: - 40 °C to 125 °C

Applications

■Printers

■Personal digital assistants (PDAs)

■Cordless phones

■Consumer applications

DFN6 (3 x 3 mm)

with a typical dropout voltage of 200 mV. The device is stable due to the use of ceramic capacitors on the input and output. The ultra low drop-voltage, low quiescent current and low noise features make it suitable for low power battery powered applications. Power supply rejection is 65 dB at low frequencies and starts to roll off at 10 kHz. An enable logic control function puts the LD39100xx in shutdown mode, allowing a total current consumption lower than 1 µA. The device also includes short-circuit constant current limiting and thermal protection.

Description

The LD39100xx provides 1 A maximum current from an input voltage ranging from 1.5 V to 5.5 V

Table 1.	Device summary
	Part numbers	Order codes	Output voltages
	LD39100XX	LD39100PUR	Adj. from 0.8 V
	LD39100XX12	LD39100PU12R	1.2 V
	LD39100XX25	LD39100PU25R	2.5 V
October 2011		Doc ID 15676 Rev 3	1/23

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Contents	LD39100XX, LD39100XX12, LD39100XX25

Contents

1	Circuit schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 3
2	Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		4
3	Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		5
4	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		6
5	Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .		10
6	Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
	6.1	Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
	6.2	Enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
	6.3	Power Good function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
7	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		18
8	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		22

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LD39100XX, LD39100XX12, LD39100XX25	Circuit schematics

1 Circuit schematics

Figure 1. Schematic diagram for the LD39100PU

IN	Power-good	PG
	signal
		IN

BandGap reference

OpAmp	Current
	limit
	Thermal	OUT
	protection
		ADJ

EN	Internal
	enable

GND

Figure 2. Schematic diagram for the LD39100PUxx

IN		Power-good	PG
		signal
			IN
	BandGap
	reference	Current
	OpAmp
		limit
		Thermal	OUT
		protection
			R1
			NC
EN	Internal		R2
	enable
		GND

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Pin configuration	LD39100XX, LD39100XX12, LD39100XX25

2 Pin configuration

Figure 3. Pin connection (top view)

EN	VIN	EN	VIN
GND	NC	GND	ADJ
PG	VOUT	PG	VOUT

LD39100PUxx LD39100PU

Table 2.	Pin description
Symbol	Pin n°			Function
	LD39100PU		LD39100PUxx
EN	1		1	Enable pin logic input: Low = shutdown, High = active
GND	2		2	Common ground
PG	3		3	Power Good
VOUT	4		4	Output voltage
ADJ	5		-	Adjust pin
VIN	6		6	Input voltage of the LDO
NC	-		5	Not connected
GND	EXP pad			Exposed pad must be connected to GND

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LD39100XX, LD39100XX12, LD39100XX25							Maximum ratings
3	Maximum ratings
Table 3.	Absolute maximum ratings
Symbol		Parameter				Value				Unit
VIN		DC input voltage				-0.3 to 7				V
VOUT		DC output voltage		-0.3 to VIN + 0.3 (7 V max)						V
EN		Enable pin		-0.3 to VIN + 0.3 (7 V max)						V
PG		Power Good pin				-0.3 to 7				V
ADJ		Adjust pin				4				V
IOUT		Output current			Internally limited
PD		Power dissipation			Internally limited
TSTG		Storage temperature range				- 65 to 150				°C
TOP		Operating junction temperature range				- 40 to 125				°C
Note:	Absolute maximum ratings are those values beyond which damage to the device may occur.
	Functional operation under these conditions is not implied. All values are referred to GND.
Table 4.	Thermal data
Symbol		Parameter					Value			Unit
RthJA		Thermal resistance junction-ambient				55				°C/W
RthJC		Thermal resistance junction-case				10				°C/W
Table 5.	ESD performance
Symbol		Parameter	Test conditions				Value			Unit
ESD	ESD protection voltage		HBM				4			kV
			MM				0.4			kV

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Electrical characteristics	LD39100XX, LD39100XX12, LD39100XX25

4 Electrical characteristics

TJ = 25 °C, VIN = 1.8 V, CIN = COUT = 1 µF, IOUT = 100 mA, VEN = VIN, unless otherwise specified.

	Table 6.	Electrical characteristics for the LD39100PU
	Symbol	Parameter	Test conditions	Min.	Typ.	Max.	Unit
	VIN	Operating input voltage		1.5		5.5	V
	VADJ	VADJ accuracy	IOUT=10mA, TJ = 25°C	784	800	816	mV
			IOUT=10mA, -40°C<TJ<125°C	776	800	824
	IADJ	Adjust pin current				1	µA
	VOUT	Static line regulation	VOUT+1 V ≤ VIN ≤ 5.5 V,		0.01		%/V
			IOUT=100mA
	V	Transient line regulation (1)	VIN=500mV, IOUT=100mA, tR=5µs		10		mVpp
	OUT		VIN=500mV, IOUT=100mA, tF=5µs		10
	VOUT	Static load regulation	IOUT=10mA to 1A		0.002		%/mA
	V	Transient load regulation (1)	IOUT=10mA to 1A, tR=5µs		40		mVpp
	OUT		IOUT=1A to 10mA, tF=5µs		40
	VDROP	Dropout voltage (2)	IOUT=1A, VO fixed to 1.5V		200	400	mV
			-40°C<TJ<125°C
	eN	Output noise voltage	10Hz to 100kHz, IOUT=100mA,		30		µVRMS
			VOUT=0.8V
			VIN=1.8V+/-VRIPPLE
			VRIPPLE=0.25V, freq. = 1kHz		65
	SVR	Supply voltage rejection	IOUT=10mA				dB
		VO = 0.8 V	VIN=1.8V+/-VRIPPLE
			VRIPPLE=0.25V, freq.=10kHz		62
			IOUT=100mA
			IOUT=0mA		20
			IOUT=0mA, -40°C<TJ<125°C			50
	IQ	Quiescent current	IOUT=0 to 1A		200		µA
			IOUT=0 to 1A, -40°C<TJ<125°C			300
			VIN input current in off mode:		0.001	1
			VEN=GND(3)
			Rising edge		0.92*
					VOUT
		Power good output threshold					V
	PG		Falling edge		0.8*
					VOUT
		Power good output voltage low	Isink=6mA open drain output			0.4	V
	ISC	Short-circuit current	RL=0		1.5		A

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LD39100XX, LD39100XX12, LD39100XX25	Electrical characteristics

Table 6. Electrical characteristics for the LD39100PU (continued)

Symbol	Parameter	Test conditions	Min.	Typ.	Max.	Unit
VEN	Enable input logic low	VIN=1.5V to 5.5V, -40°C<TJ<125°C			0.4	V
	Enable input logic high		0.9			V
IEN	Enable pin input current	VEN= VIN		0.1	100	nA
tON	Turn-on time (4)			30		µs
TSHDN	Thermal shutdown			160		°C
	Hysteresis			20
		Capacitance (see typical
COUT	Output capacitor	performance characteristics for	1		22	µF
		stability)

1.All transient values are guaranteed by design, not production tested

2.Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply for output voltages below 1.5 V

3.PG pin floating

4.Turn-on time is time measured between the enable input just exceeding VEN high value and the output voltage just reaching 95% of its nominal value

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