ST LD39080 User Manual
Ultra low drop BICMOS voltage regulator
Feature summary
■ 0.8A Guaranteed output current
■ Ultra low dropout voltage (150mV typ. @ 0.8A
load, 20mV typ. @150mA load)
■ Very low quiescent current (1mA typ. @ 0.8A
load, 1µA max @ 25°C in off mode)
■ Logic-controlled electronic shutdown
■ Current and thermal internal limit
■ ±1.5% Output voltage tolerance @ 25°C
■ Fixed and ADJ output voltages: 1.22V, 1.8V,
2.5V, 3.3V, ADJ. (*see order code)
■ Temperature range: -40 to 125°C
■ Fast dynamic response to line and load
changes
■ Stable with ceramic capacitor (see paragraph
7.1, 7.2, 7.3)
■ Available in PPAK, DPAK and DFN8 (4x4mm)
Typical application
■ Microprocessor power supply
■ DSPs power supply
■ Post regulators for switching suppliers
■ High efficiency linear regulator
LD39080
PPAK
DFN8 (4x4 mm)
Description
The LD39080 is a fast ultra low drop linear
regulator which operates from 2.5V to 6V input
supply.
A wide range of output options are available. The
low drop voltage, low noise, and ultra low
quiescent current make it suitable for low voltage
microprocessor and memory applications. The
device is developed on a BiCMOS process which
allows low quiescent current operation
independently of output load current.
DPAK
Order codes
Part numbers
DPAK (T&R) PPAK (T&R) DFN
LD39080DT12-R LD39080PU12R 1.22V
LD39080DT18-R LD39080PT18-R LD39080PU18R 1.8V
LD39080DT25-R LD39080PT25-R LD39080PU25R 2.5V
LD39080DT33-R LD39080PT33-R LD39080PU33R 3.3V
LD39080PT-R LD39080PU-R ADJ From 1.22 to 5.0V
1. Available on request
January 2007 Rev. 1 1/20
(1)
Output voltage
www.st.com
20
LD39080
Contents
1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7 Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.1 External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.2 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.3 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.4 Thermal note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.5 Inhibit input operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/20
LD39080 Diagram
1 Diagram
Figure 1. Block diagram
(*) Not present on ADJ Versions
3/20
Pin configuration LD39080
2 Pin configuration
Figure 2. Pin connections (top view for DPAK and PPAK, bottom view for DFN8)
DFN8 (4x4 mm)
Table 1. Pin description
Pln N°
Symbol Note
DFN PPAK DPAK
V
85
SENSE
ADJ For adjustable version: Error Amplifier Input pin for V
3, 4 2 1 V
6, 7 4 3 V
21 V
O
INH
1 3 2 GND Common ground
5 N.C. Not Connected
For fixed versions: to be connected with LDO Output Voltage pins for DFN
/N.C.
package and Not Connected on PPAK
LDO Input Voltage; VI from 2.5V to 6V, CI=1µF must be located at a
I
distance of not more than 0.5’’ from input pin.
LDO Output Voltage pins, with minimum CO=2.2µF needed for stability
(also refer to C
Inhibit Input Voltage: ON MODE when V
0.3V (Do not leave floating, not internally pulled down/up)
PPAK
vs. ESR stability chart)
O
DPAK
from 1.22 to 5.0V
O
≥ 2V, OFF MODE when V
INH
INH
≤
4/20
LD39080 Typical application circuits
3 Typical application circuits
(CI and CO Capacitors must be placed as close as possible to the IC pins)
Figure 3. LD39080 fixed version with inhibit
1 Inhibit Pin is not internally pulled down/up then it must not be left floating. Disable the device
when connected to GND or to a positive voltage less than 0.3V
Figure 4. LD39080 adjustable version
VO = V
(1 + R1/R2)
REF
2 Set R2 as close as possible to 4.7K
Ω.
5/20
Typical application circuits LD39080
Figure 5. LD39080 DPAK
Figure 6. Timing diagram
6/20
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