Sony Z40HR Schematics

5
4
3
2
1
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Z50-HR(S204-SC) Schematics Document
D D
Intel PCH
2011-02-14
REV :-1
C C
Sandy Bridge
B B
A A
5
4
3
2
N12M GS2 HYN1GB
N12M GS2 HYN1GB
N12M GS2 HYN1GB
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Date: Sheet of
Date: Sheet of
Date: Sheet of
Cover Page
Cover Page
Cover Page
1 74
1 74
1 74
1
-1
-1
-1
5
Slot 0DDRIII
Slot 1
11
12
D D
1067/1333
DDRIII 1067/1333
SPEAKER
CR2032_220mA (Non Rechargeable)
INTERNAL MIC
C C
Headphone
External MIC
USB 2.0 x3
i/o Connector
59
USB Board
HDD 2.5'' SATA
B B
(SATA0)
Blu-ray BD Combo Super-Multi
(SATA4)
LED&Switch Board
59
Switch x 4 LEDx 4
A A
AUDIO CODEC
Conexant CX20671-21Z
25,28,46
USB2.0
45
45
59
i/o Connector
4
Z50-HR Block Diagram
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DDRIII 1067/1333 Channel A
Intel CPU
DDRIII 1067/1333 Channel B
Sandy Bridge DC FSB: 1066 MHz
FDI
4,5,6,7,8,9,10
DMI at 5G
3
PCI EXPRESS GRAPHIC
Nvidia N12M-GS
60,61,62,63,64
LVDS
2
DDR3 800MHz
VRAM x 4
15" LCD 1366x768
RTC
48
HDMI
HDMI
INTEL
RTC
PCH
RGB CRT
CRT
43
Cougar Point
HD Audio (Azalia)
SATA II
SPI Flash 4 MB
SPI
14 USB 2.0/1.1 ports ETHERNET High Definition Audio
Serial Peripheral I/F(dual output)
ACPI 1.1 LPC I/F 6 SATA
(10/100/1000Mb)
USB2.0
NC
PCIE
PCI Express
13,14,15,16,17,18,19,20,21
48
KBC
LPC Bus
MS&SD Connector
23
LED&RF SW
SPI
NPEC795P
USB 2.0 x1
CAMERA
BlueTooth
Mini-Card WLAN/WiMAX
Intel Kilmar Peak 2x2
Atheros LAN
AR8151 10/100/1000
WOL from S3
Memory Card Controller Chip
RTS5209
56
52
1
CPU DC/DC
ISL95831
INPUTS
DCBATOUT
SYSTEM DC/DC
TPS51218D
INPUTS
DCBATOUT
SYSTEM DC/DC
VRAM
1GB/512MB
42
44
65,66
RT8223
INPUTS
DCBATOUT 5V_S5
SYSTEM DC/DC
RT8207
INPUTS
DCBATOUT
SYSTEM DC/DC
ISL95831HRTZ
INPUTS
DCBATOUT
49
42
RT8208A
INPUTS
DCBATOUT
TI CHARGER
BQ24725
50
INPUTS
+DC_IN_S5
26
SYSTEM DC/DC
RT9025
INPUTS
51
3D3V_S0
SYSTEM DC/DC
RJ45
26
27
47
APL5916KAI-TRL-GP
INPUTS
26
3D3V_S0 0D85V_S0
Switches
INPUTS OUTPUTS
1D5V_S3 5V_S5
OUTPUTS
VCC_CORE
OUTPUTS
1D05V_VTT
OUTPUTS
5V_AUX_S5 3D3V_AUX_S5
3D3V_S5
OUTPUTS
1D5V_S3 0D75V_S0 DDR_VREF_S3
OUTPUTS
VCC_GFXCORE
VGA
OUTPUTS
VGA_CORE
OUTPUTS
OUTPUTS
OUTPUTS
35,36,37
DCBATOUT+PBATT
1D8V_S0
1D5V_S0 5V_S0 3D3V_S03D3V_S5
38
34
39
37
67
33
40
41
29
PCB LAYER
N12M GS2 HYN1GB
N12M GS2 HYN1GB
N12M GS2 HYN1GB
L1:Top L2:VCC L3:Signal
L4:Signal L5:GND L6:Bottom
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
2 74
2 74
2 74
1
-1
-1
-1
2453
3
Lid switch
Title
Title
Title
54
2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Date: Sheet of
Date: Sheet of
Date: Sheet of
Block Diagram
Block Diagram
Block Diagram
Touch Pad
5
4
Thermal Sensor P2800
A
PCH Strapping
Name Schematics Notes
SPKR
INIT3_3V# GNT3#/GPIO55
4 4
GNT2#/GPIO53 GNT1#/GPIO51
SPI_MOSI
NV_ALE
NC_CLE
HAD_DOCK_EN# /GPIO[33]
3 3
Reboot option at power-up
Internal weak Pull-down.
Default Mode:
Connect to Vcc3_3 with 8.2-k
No Reboot Mode with TCO Disabled:
- 10-k weak pull-up resistor. Weak internal pull-up. Leave as "No Connect".
GNT[3:0]# functionality is not available on Mobile. Mobile: Used as GPIO only Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3power rail.
Enable Danbury:
Disable Danbury:
Enable Danbury:
Disable Danbury:
DMI termination voltage. Weak internal pull-up. Do not pull low. Low (0) - Flash Descriptor Security will be overridden. Also,
when this signals is sampled on the rising edge of PWROK then it will also disable Intel ME and its features. High (1) - Security measure defined in the Flash Descriptor will be enabled. Platform design should provide appropriate pull-up or pull-down depending on the desired settings. If a jumper option is used to tie this signal to GND as required by the functional strap, the signal should be pulled low through a weak pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for strapping functions.
Huron River Schematic Checklist Rev.0_7
Connect to Vcc3_3 with 8.2-k? weak pull-up resistor.
Left floating, no pull-down required.
Connect to +NVRAM_VCCQ with 8.2-kohm weak pull-up resistor [CRB has it pulled up with 1-kohm no-stuff resistor]
Leave floating (internal pull-down)
B
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C
Processor Strapping
Pin Name Strap Description Configuration (Default value for each bit is
CFG[2]
CFG[4]
CFG[6:5]
CFG[7]
PCI-Express Static Lane Reversal
PCI-Express Port Bifurcation Straps
PEG DEFER TRAINING
1 unless specified otherwise)
1:
Normal Operation. Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
0:
Disabled - No Physical Display Port attached to
1:
Embedded DisplayPort. Enabled - An external Display Port device is
0:
connectd to the EMBEDDED display Port
11 : x16 - Device 1 functions 1 and 2 disabled 10 : x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01 : Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00 : x8, x4, x4 - Device 1 functions 1 and 2 enabled
1:
PEG Train immediately following xxRESETB de assertion PEG Wait for BIOS for training
0:
D
Huron River Schematic Checklist Rev.0_7
Default Value
1
0
11
1
E
HDA_SDO HDA_SYNC
GPIO15
GPIO8
2 2
GPIO27
Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no
confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality
Note : This is an un-muxed signal. This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. Sampled at rising edge of RSMRST#. CRB has a 1-kohm pull-up on this signal to +3.3VA rail.
GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is enabled.
Default = Do not connect (floating)
High(1) = Enables the internal VccVRM to have a clean supply for analog rails. No need to use on-board filter circuit. Low (0) = Disables the VccVRM. Need to use on-board filter circuits for analog rails.
USB Table
Pair
PCIE Routing
LANE1 LANE2 LANE3 LANE4
1 1
LANE5 LANE6 LANE7 LANE8
Mini Card1(WLAN) Card Reader N/A GIGA LAN N/A N/A N/A N/A
SATA Table
SATA
Pair
0 1 2 3 4 5
Device
HDD1
N/A N/A N/A
ODD
N/A
0 1 2 3 4 5 6 7 8 9 10 11 12 13
Device USB Ext. port 2 USB Ext. port 1 USB Ext. port 4
USB Ext. port 3 X X X X CAMERA X X Mini Card1 (WLAN) BLUETOOTH
OC#0 OC#1 OC#2
OC#3
OC#5
OC#7
N12M GS2 HYN1GB
N12M GS2 HYN1GB
N12M GS2 HYN1GB
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Date: Sheet of
Date: Sheet of
Date: Sheet of
Table of Content
Table of Content
Table of Content
3 74
3 74
3 74
-1
-1
-1
SSID = CPU
5
Note: Intel DMI supports both Lane
D D
Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.
Note: Intel FDI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap. Lane reversal does not apply to FDI sideband signals.
C C
If left as no connect, there is no functional impact, but power (~15 mW) may be wasted.
FDI_LSYNC0 FDI_FSYNC0 FDI_LSYNC1 FDI_FSYNC1 FDI_INT
12
R404
R404
1KR2J-1-GP
1KR2J-1-GP
DIS
DIS
EDP_COMPIO
B B
EDP_ICOMPO
Signal Routing Guideline: EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils.
Port
DG 0.9 P.54
Strap Enable Disable
CFG[4]
eDP
EDP_HDP
678
RN401
RN401 SRN1KJ-4-GP
SRN1KJ-4-GP
DIS
DIS
66.10236.08L
66.10236.08L
123
4 5
VCCIO
24.9R
4mil
12mil
Pull down to GND through a 1K ± 5% resistor Pull down to GND through a 1K ± 5% resistor
1D05V_VTT
No Connect
Pull high to CPU VCCIO through a 10K ± 5% resistor
DMI_TXN[3:0]15
DMI_TXP[3:0]15
DMI_RXN[3:0]15
DMI_RXP[3:0]15
FDI_TXN[7:0]15
FDI_TXP[7:0]15
FDI_FSYNC015 FDI_FSYNC115
FDI_INT15 FDI_LSYNC015
FDI_LSYNC115
R402 24D9R2F-L-GPR402 24D9R2F-L-GP
1 2
R403
R403
1 2
4
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CPU1A
CPU1A
SANDY
DMI_RX#0 DMI_RX#1 DMI_RX#2 DMI_RX#3
DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3
DMI_TX#0 DMI_TX#1 DMI_TX#2 DMI_TX#3
DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3
FDI0_TX#0 FDI0_TX#1 FDI0_TX#2 FDI0_TX#3 FDI1_TX#0 FDI1_TX#1 FDI1_TX#2 FDI1_TX#3
FDI0_TX0 FDI0_TX1 FDI0_TX2 FDI0_TX3 FDI1_TX0 FDI1_TX1 FDI1_TX2 FDI1_TX3
FDI0_FSYNC FDI1_FSYNC
FDI_INT FDI0_LSYNC
FDI1_LSYNC
EDP_COMPIO EDP_ICOMPO EDP_HPD
EDP_AUX EDP_AUX#
EDP_TX0 EDP_TX1 EDP_TX2 EDP_TX3
EDP_TX#0 EDP_TX#1 EDP_TX#2 EDP_TX#3
SANDY
DMI
DMI
Intel(R) FDI
Intel(R) FDI
eDP
eDP
10KR2J-3-GP
10KR2J-3-GP
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7
FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7
DP_COMP eDP_HPD
eDP Disable
B27 B25 A25 B24
B28 B26 A24 B23
G21 E22 F21 D21
G22 D22 F20 C21
A21 H19 E19 F18 B21 C20 D18 E17
A22 G19 E20 G18 B20 C19 D19 F17
H20
H17
A18 A17 B16
C15 D15
C17 F16 C16 G15
C18 E16 D16 F15
J18 J17
J19
ARRAN
ARRAN
3
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8
PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15
PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8
PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15
PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9
PEG_TX#10 PEG_TX#11
PCI EXPRESS* - GRAPHICS
PCI EXPRESS* - GRAPHICS
PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15
PEG_TX0
PEG_TX1
PEG_TX2
PEG_TX3
PEG_TX4
PEG_TX5
PEG_TX6
PEG_TX7
PEG_TX8
PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15
DG 0.9 P.32
PEG_RCOMPO PEG_ICOMPI PEG_ICOMPO
1 OF 9
1 OF 9
J22 J21 H22
K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32
J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32
M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25
M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25
VCCIO
4mil
12mil
PEG_IRCOMP_R
PEG_RXN15 PEG_RXN14 PEG_RXN13 PEG_RXN12 PEG_RXN11 PEG_RXN10 PEG_RXN9 PEG_RXN8 PEG_RXN7 PEG_RXN6 PEG_RXN5 PEG_RXN4 PEG_RXN3 PEG_RXN2 PEG_RXN1 PEG_RXN0
PEG_RXP15 PEG_RXP14 PEG_RXP13 PEG_RXP12 PEG_RXP11 PEG_RXP10 PEG_RXP9 PEG_RXP8 PEG_RXP7 PEG_RXP6 PEG_RXP5 PEG_RXP4 PEG_RXP3 PEG_RXP2 PEG_RXP1 PEG_RXP0
PEG_C_TXN15 PEG_C_TXN14 PEG_C_TXN13 PEG_C_TXN12 PEG_C_TXN11 PEG_C_TXN10 PEG_C_TXN9 PEG_C_TXN8 PEG_C_TXN7 PEG_C_TXN6 PEG_C_TXN5 PEG_C_TXN4 PEG_C_TXN3 PEG_C_TXN2 PEG_C_TXN1 PEG_C_TXN0
PEG_C_TXP15 PEG_C_TXP14 PEG_C_TXP13 PEG_C_TXP12 PEG_C_TXP11 PEG_C_TXP10 PEG_C_TXP9 PEG_C_TXP8 PEG_C_TXP7 PEG_C_TXP6 PEG_C_TXP5 PEG_C_TXP4 PEG_C_TXP3 PEG_C_TXP2 PEG_C_TXP1 PEG_C_TXP0
Signal Routing Guideline: PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
24.9R
PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
R401 24D9R2F-L-GPR401 24D9R2F-L-GP
1 2
PEG_RXN[0..15]
PEG_RXP[0..15]
2
1D05V_VTT
PEG_RXN[0..15] 60
NOTE. If PEG is not implemented, the RX&TX pairs can be left as No Connect
PEG Static Lane Reversal
close to the processor
C421 SCD22U10V2KX-1GP
C421 SCD22U10V2KX-1GP
1 2
DIS
DIS
C422 SCD22U10V2KX-1GP
C422 SCD22U10V2KX-1GP
1 2
DIS
DIS
C423 SCD22U10V2KX-1GP
C423 SCD22U10V2KX-1GP
1 2
DIS
DIS
C424 SCD22U10V2KX-1GP
C424 SCD22U10V2KX-1GP
1 2
DIS
DIS
C425 SCD22U10V2KX-1GP
C425 SCD22U10V2KX-1GP
1 2
DIS
DIS
C426 SCD22U10V2KX-1GP
C426 SCD22U10V2KX-1GP
1 2
DIS
DIS
C427 SCD22U10V2KX-1GP
C427 SCD22U10V2KX-1GP
1 2
DIS
DIS
C428 SCD22U10V2KX-1GP
C428 SCD22U10V2KX-1GP
1 2
DIS
DIS
C429 SCD22U10V2KX-1GP
C429 SCD22U10V2KX-1GP
1 2
DIS
DIS
C430 SCD22U10V2KX-1GP
C430 SCD22U10V2KX-1GP
1 2
DIS
DIS
C431 SCD22U10V2KX-1GP
C431 SCD22U10V2KX-1GP
1 2
DIS
DIS
C432 SCD22U10V2KX-1GP
C432 SCD22U10V2KX-1GP
1 2
DIS
DIS
C433 SCD22U10V2KX-1GP
C433 SCD22U10V2KX-1GP
1 2
DIS
DIS
C434 SCD22U10V2KX-1GP
C434 SCD22U10V2KX-1GP
1 2
DIS
DIS
C435 SCD22U10V2KX-1GP
C435 SCD22U10V2KX-1GP
1 2
DIS
DIS
C436 SCD22U10V2KX-1GP
C436 SCD22U10V2KX-1GP
1 2
DIS
DIS
C437 SCD22U10V2KX-1GP
C437 SCD22U10V2KX-1GP
1 2
DIS
DIS
C438 SCD22U10V2KX-1GP
C438 SCD22U10V2KX-1GP
1 2
DIS
DIS
C439 SCD22U10V2KX-1GP
C439 SCD22U10V2KX-1GP
1 2
DIS
DIS
C440 SCD22U10V2KX-1GP
C440 SCD22U10V2KX-1GP
1 2
DIS
DIS
C441 SCD22U10V2KX-1GP
C441 SCD22U10V2KX-1GP
1 2
DIS
DIS
C442 SCD22U10V2KX-1GP
C442 SCD22U10V2KX-1GP
1 2
DIS
DIS
C443 SCD22U10V2KX-1GP
C443 SCD22U10V2KX-1GP
1 2
DIS
DIS
C444 SCD22U10V2KX-1GP
C444 SCD22U10V2KX-1GP
1 2
DIS
DIS
C445 SCD22U10V2KX-1GP
C445 SCD22U10V2KX-1GP
1 2
DIS
DIS
C446 SCD22U10V2KX-1GP
C446 SCD22U10V2KX-1GP
1 2
DIS
DIS
C447 SCD22U10V2KX-1GP
C447 SCD22U10V2KX-1GP
1 2
DIS
DIS
C448 SCD22U10V2KX-1GP
C448 SCD22U10V2KX-1GP
1 2
DIS
DIS
C449 SCD22U10V2KX-1GP
C449 SCD22U10V2KX-1GP
1 2
DIS
DIS
C450 SCD22U10V2KX-1GP
C450 SCD22U10V2KX-1GP
1 2
DIS
DIS
C451 SCD22U10V2KX-1GP
C451 SCD22U10V2KX-1GP
1 2
DIS
DIS
C452 SCD22U10V2KX-1GP
C452 SCD22U10V2KX-1GP
1 2
DIS
DIS
PEG_TXN15 PEG_TXN14 PEG_TXN13 PEG_TXN12 PEG_TXN11 PEG_TXN10 PEG_TXN9 PEG_TXN8 PEG_TXN7 PEG_TXN6 PEG_TXN5 PEG_TXN4 PEG_TXN3 PEG_TXN2 PEG_TXN1 PEG_TXN0
PEG_TXP15 PEG_TXP14 PEG_TXP13 PEG_TXP12 PEG_TXP11 PEG_TXP10 PEG_TXP9 PEG_TXP8 PEG_TXP7 PEG_TXP6 PEG_TXP5 PEG_TXP4 PEG_TXP3 PEG_TXP2 PEG_TXP1 PEG_TXP0
PEG_RXP[0..15] 60
PEG_TXN[0..15]
PEG_TXP[0..15]
1
PEG_TXN[0..15] 60
PEG_TXP[0..15] 60
N12M GS2 HYN1GB
N12M GS2 HYN1GB
A A
N12M GS2 HYN1GB
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU (PCIE/DMI/FDI)
CPU (PCIE/DMI/FDI)
CPU (PCIE/DMI/FDI)
4 74
4 74
4 74
-1
-1
-1
SSID = CPU
DMI & FDI Termination Voltage
NV_CLE
Set to Vss when LOW Set to Vcc when HIGH
D D
H_PROCHOT#23,35
Connect EC to PROCHOT# through inverting OD buffer.
C C
B B
1D05V_VTT
H_PM_SYNC15
H_CPUPW RGD18,69
close to the processor
PM_DRAM_PWRGD15,30
VDDPWRGOOD30
1D05V_VTT
PLT_RST#14,22,23,26,27,51,55,60,69
Buffered reset to CPU
PLT_RST#14,22,23,26,27,51,55,60,69
+V_NVRAM_VCCQ
H_SNB_IVB#14
H_PECI18,23
R501
R501
1 2
62R2J-GP
62R2J-GP
NO_S3
NO_S3
R510
R510
1 2
1K5R2F-2-GP
1K5R2F-2-GP
U501
U501
NC#11VCC
2
A
3
GND
Do Not Stuff
Do Not Stuff
DY
DY
TP501Do Not Stuff TP501Do Not Stuff
TP502Do Not Stuff TP502Do Not Stuff
close to the processor
1 2
2K2R2J-2-GP
2K2R2J-2-GP
1
1
close to the processor
1 2
56R2J-4-GP
56R2J-4-GP
63.56034.1DL
63.56034.1DL
H_THERMTRIP#18,22
1D05V_VTT
1 2
Do Not Stuff
Do Not Stuff
R503
R503
1 2
10KR2J-3-GP
10KR2J-3-GP
1 2
NO_S3
NO_S3
Do Not Stuff
Do Not Stuff
R521
R521
1 2
Do Not Stuff
Do Not Stuff
1D05V_VTT
12
R514
R514 Do Not Stuff
Do Not Stuff
DY
DY
5 4
Y
R517
R517
R516
R516
R524
R524
R504
R504
12
R523
R523 56R2J-4-GP
56R2J-4-GP
R509
R509 750R2F-GP
750R2F-GP
3D3V_S0
Do Not Stuff
Do Not Stuff
5
4
CPU1B
CPU1B
SANDY
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C26
SKTOCC#_R
H_CATERR#
H_PROCHOT#_R
12
H_CPUPW RGD_R
VDDPWRGOOD
BUF_CPU_RST#
12
C501
C501
DY
DY
R515
R515
1 2
DY
DY
Do Not Stuff
Do Not Stuff
AN34
AL33
AN33
AL32
AN32
AM34
AP33
V8
AR33
ARRAN
ARRAN
62.10055.321
62.10055.321
BUF_CPU_RST#BUFO_CPU_RST#
12
R512
R512 Do Not Stuff
Do Not Stuff
DY
DY
SANDY
SNB_IVB#
SKTOCC#
CATERR#
PECI
PROCHOT#
THERMTRIP#
PM_SYNC
UNCOREPWRGOOD
SM_DRAMPWROK
RESET#
MISCTHERMALPWR MANAGEMENT
MISCTHERMALPWR MANAGEMENT
CLOCKS
CLOCKS
DDR3
DDR3
JTAG & BPM
JTAG & BPM
3
2 OF 9
2 OF 9
BCLK
BCLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
SM_DRAMRST#
SM_RCOMP0 SM_RCOMP1 SM_RCOMP2
MISC
MISC
PRDY# PREQ#
TRST#
DBR#
BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7
2
A28 A27
CLK_DP_P_R
A16
CLK_DP_N_R
A15
R502
R502
1 2
R8
SM_RCOMP_0
AK1
SM_RCOMP_1
A5
SM_RCOMP_2
A4
Signal Routing Guideline: SM_RCOMP[0,1] keep W/S=20/20 mils and routing length less than 500 mils. SM_RCOMP[2] keep W/S=15/20 mils and routing length less than 500 mils.
XDP_PRDY#
AP29
XDP_PREQ#
AP27
XDP_TCLK
AR26
TCK TMS
TDI
TDO
AR27 AP30
AR28 AP26
AL35
AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32
XDP_TMS XDP_TRST#
XDP_TDI XDP_TDO
XDP_DBRESET#
R506 140R2F-GPR506 140R2F-GP R507 25D5R2F-GPR507 25D5R2F-GP R508 200R2F-L-GPR508 200R2F-L-GP
XDP_BPM0 XDP_BPM1 XDP_BPM2 XDP_BPM3 XDP_BPM4 XDP_BPM5 XDP_BPM6 XDP_BPM7
SRN1KJ-7-GP
SRN1KJ-7-GP
DIS
DIS
2 3 1
RN503
RN503
4K99R2F-L-GP
4K99R2F-L-GP
1 2 1 2 1 2
3D3V_S0
CLK_EXP_P 16 CLK_EXP_N 16
4
12
R513
R513 1KR2J-1-GP
1KR2J-1-GP
EVT
1D05V_VTT
SM_DRAMRST# 30
EVT
Disabling Guidelines: If motherboard only supports external graphics: Connect DPLL_REF_SSCLK on Processor to GND through 1K +/- 5% resistor. Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K +/- 5% resistorpower (~15 mW) may be wasted.
XDP_TDI XDP_TMS
XDP_TCLK
XDP_TRST# XDP_TDO
RN501
RN501
1 2 3 4 5
Do Not Stuff
Do Not Stuff
RN502
RN502
1 2 3
SRN51J-GP
SRN51J-GP
1
CHKLST 0.9 P.53
1D05V_VTT
DY
DY
8 7 6
4
1D05V_VTT
XDP Test Point
XDP_PRDY# XDP_PREQ#
XDP_BPM0 XDP_BPM1 XDP_BPM2 XDP_BPM3 XDP_BPM4 XDP_BPM5 XDP_BPM6 XDP_BPM7
1 1 1 1 1 1 1 1 1 1
TP12 Do Not StuffTP12 Do Not Stuff TP13 Do Not StuffTP13 Do Not Stuff TP14 Do Not StuffTP14 Do Not Stuff TP15 Do Not StuffTP15 Do Not Stuff TP18 Do Not StuffTP18 Do Not Stuff TP16 Do Not StuffTP16 Do Not Stuff TP19 Do Not StuffTP19 Do Not Stuff TP20 Do Not StuffTP20 Do Not Stuff TP21 Do Not StuffTP21 Do Not Stuff TP22 Do Not StuffTP22 Do Not Stuff
N12M GS2 HYN1GB
N12M GS2 HYN1GB
A A
N12M GS2 HYN1GB
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU (THERMAL/CLOCK/PM )
CPU (THERMAL/CLOCK/PM )
CPU (THERMAL/CLOCK/PM )
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Wednesday, March 02, 2011
5 74
5 74
5 74
-1
-1
-1
5
4
3
2
1
SSID = CPU
CPU1C
CPU1C
SANDY
SANDY
D D
C C
B B
M_A_DQ011 M_A_DQ111 M_A_DQ211 M_A_DQ311 M_A_DQ411 M_A_DQ511 M_A_DQ611 M_A_DQ711 M_A_DQ811 M_A_DQ911 M_A_DQ1011 M_A_DQ1111 M_A_DQ1211 M_A_DQ1311 M_A_DQ1411 M_A_DQ1511 M_A_DQ1611 M_A_DQ1711 M_A_DQ1811 M_A_DQ1911 M_A_DQ2011 M_A_DQ2111 M_A_DQ2211 M_A_DQ2311 M_A_DQ2411 M_A_DQ2511 M_A_DQ2611 M_A_DQ2711 M_A_DQ2811 M_A_DQ2911 M_A_DQ3011 M_A_DQ3111 M_A_DQ3211 M_A_DQ3311 M_A_DQ3411 M_A_DQ3511 M_A_DQ3611 M_A_DQ3711 M_A_DQ3811 M_A_DQ3911 M_A_DQ4011 M_A_DQ4111 M_A_DQ4211 M_A_DQ4311 M_A_DQ4411 M_A_DQ4511 M_A_DQ4611 M_A_DQ4711 M_A_DQ4811 M_A_DQ4911 M_A_DQ5011 M_A_DQ5111 M_A_DQ5211 M_A_DQ5311 M_A_DQ5411 M_A_DQ5511 M_A_DQ5611 M_A_DQ5711 M_A_DQ5811 M_A_DQ5911 M_A_DQ6011 M_A_DQ6111 M_A_DQ6211 M_A_DQ6311
M_A_BS011 M_A_BS111 M_A_BS211
M_A_CAS#11 M_A_RAS#11 M_A_WE#11
M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
G10
N10
M10
AG6 AG5
AK6 AK5 AH5 AH6
AK8 AK9
AH8 AH9 AL9
AL8 AP11 AN11
AL12 AM12 AM11
AL11 AP12 AN12
AJ14 AH14
AL15 AK15
AL14 AK14
AJ15 AH15
AE10
AF10
AE8 AD9 AF9
C5
SA_DQ0
D5
SA_DQ1
D3
SA_DQ2
D2
SA_DQ3
D6
SA_DQ4
C6
SA_DQ5
C2
SA_DQ6
C3
SA_DQ7
F10
SA_DQ8
F8
SA_DQ9 SA_DQ10
G9
SA_DQ11
F9
SA_DQ12
F7
SA_DQ13
G8
SA_DQ14
G7
SA_DQ15
K4
SA_DQ16
K5
SA_DQ17
K1
SA_DQ18
J1
SA_DQ19
J5
SA_DQ20
J4
SA_DQ21
J2
SA_DQ22
K2
SA_DQ23
M8
SA_DQ24 SA_DQ25
N8
SA_DQ26
N7
SA_DQ27 SA_DQ28
M9
SA_DQ29
N9
SA_DQ30
M7
SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37
AJ5
SA_DQ38
AJ6
SA_DQ39
AJ8
SA_DQ40 SA_DQ41
AJ9
SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63
SA_BS0 SA_BS1
V6
SA_BS2
SA_CAS# SA_RAS# SA_WE#
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DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
3 OF 9
3 OF 9
SA_CLK0
SA_CLK#0
SA_CKE0
SA_CLK1
SA_CLK#1
SA_CKE1
SA_CLK2
SA_CLK#2
SA_CKE2
SA_CLK3
SA_CLK#3
SA_CKE3
SA_CS#0 SA_CS#1 SA_CS#2 SA_CS#3
SA_ODT0 SA_ODT1 SA_ODT2 SA_ODT3
SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7
SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7
SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8
SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15
AB6 AA6 V9
AA5 AB5 V10
AB4 AA4 W9
AB3 AA3 W10
AK3 AL3 AG1 AH1
AH3 AG3 AG2 AH2
C4 G6 J3 M6 AL6 AM8 AR12 AM15
D4 F6 K3 N6 AL5 AM9 AR11 AM14
AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7
M_A_DQS#0M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7
M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
M_A_DIM0_CLK_DDR0 11 M_A_DIM0_CLK_DDR#0 11 M_A_DIM0_CKE0 11
M_A_DIM0_CLK_DDR1 11 M_A_DIM0_CLK_DDR#1 11 M_A_DIM0_CKE1 11
M_A_DIM0_CS#0 11 M_A_DIM0_CS#1 11
M_A_DIM0_ODT0 11 M_A_DIM0_ODT1 11
M_A_DQS#0 11 M_A_DQS#1 11 M_A_DQS#2 11 M_A_DQS#3 11 M_A_DQS#4 11 M_A_DQS#5 11 M_A_DQS#6 11 M_A_DQS#7 11
M_A_DQS0 11 M_A_DQS1 11 M_A_DQS2 11 M_A_DQS3 11 M_A_DQS4 11 M_A_DQS5 11 M_A_DQS6 11 M_A_DQS7 11
M_A_A0 11 M_A_A1 11 M_A_A2 11 M_A_A3 11 M_A_A4 11 M_A_A5 11 M_A_A6 11 M_A_A7 11 M_A_A8 11 M_A_A9 11 M_A_A10 11 M_A_A11 11 M_A_A12 11 M_A_A13 11 M_A_A14 11 M_A_A15 11
4 OF 9
CPU1D
CPU1D
SANDY
M_B_DQ[63:0]12
M_B_DQ[63:0]
M_B_BS012 M_B_BS112 M_B_BS212
M_B_CAS#12 M_B_RAS#12 M_B_WE#12
M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
D10
K10
AM5 AM6 AR3
AP3 AN3 AN2 AN1
AP2
AP5 AN9
AT5
AT6
AP6 AN8 AR6 AR5 AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11 AN14 AR14
AT14
AT12 AN15 AR15
AT15
AA9 AA7
AA10
AB8 AB9
C9
SB_DQ0
A7
SB_DQ1 SB_DQ2
C8
SB_DQ3
A9
SB_DQ4
A8
SB_DQ5
D9
SB_DQ6
D8
SB_DQ7
G4
SB_DQ8
F4
SB_DQ9
F1
SB_DQ10
G1
SB_DQ11
G5
SB_DQ12
F5
SB_DQ13
F2
SB_DQ14
G2
SB_DQ15
J7
SB_DQ16
J8
SB_DQ17 SB_DQ18
K9
SB_DQ19
J9
SB_DQ20
J10
SB_DQ21
K8
SB_DQ22
K7
SB_DQ23
M5
SB_DQ24
N4
SB_DQ25
N2
SB_DQ26
N1
SB_DQ27
M4
SB_DQ28
N5
SB_DQ29
M2
SB_DQ30
M1
SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63
SB_BS0 SB_BS1
R6
SB_BS2
SB_CAS# SB_RAS# SB_WE#
SANDY
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
4 OF 9
SB_CLK0
SB_CLK#0
SB_CKE0
SB_CLK1
SB_CLK#1
SB_CKE1
SB_CLK2
SB_CLK#2
SB_CKE2
SB_CLK3
SB_CLK#3
SB_CKE3
SB_CS#0 SB_CS#1 SB_CS#2 SB_CS#3
SB_ODT0 SB_ODT1 SB_ODT2 SB_ODT3
SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7
SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7
SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8
SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15
AE2 AD2 R9
AE1 AD1 R10
AB2 AA2 T9
AA1 AB1 T10
AD3 AE3 AD6 AE6
AE4 AD4 AD5 AE5
D7 F3 K6 N3 AN5 AP9 AK12 AP15
C7 G3 J6 M3 AN6 AP8 AK11 AP14
AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4
M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7
M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15
M_B_DIM0_CLK_DDR0 12 M_B_DIM0_CLK_DDR#0 12 M_B_DIM0_CKE0 12
M_B_DIM0_CLK_DDR1 12 M_B_DIM0_CLK_DDR#1 12 M_B_DIM0_CKE1 12
M_B_DIM0_CS#0 12 M_B_DIM0_CS#1 12
M_B_DIM0_ODT0 12 M_B_DIM0_ODT1 12
M_B_DQS#[7:0] 12
M_B_DQS[7:0] 12
M_B_A[15:0] 12
ARRAN
ARRAN
A A
5
4
3
ARRAN
ARRAN
N12M GS2 HYN1GB
N12M GS2 HYN1GB
N12M GS2 HYN1GB
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
CPU (DDR)
CPU (DDR)
CPU (DDR)
6 74
6 74
6 74
1
-1
-1
-1
5
SSID = CPU
CFG0
AK28
1
TP713Do Not Stuff TP713Do Not Stuff
CFG1
AK29
1
TP701Do Not Stuff TP701Do Not Stuff
CFG2
AL26
CFG3
1
CFG4 CFG5 CFG6 CFG7 CFG8
1
CFG9
1
CFG10
1
CFG11
1
CFG12
1
CFG13
1
CFG14
1
CFG15
1
CFG16
1
CFG17
1
H_VCCP_SEL
AL27 AK26 AL29 AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29
AJ31 AH31 AJ33 AH33
AJ26
D1
F25 F24
F23 D24 G25 G24
E23 D23 C30
A31
B30
B29 D30
B31
A30 C29
J20
B18
A19
J15
TP702Do Not Stuff TP702Do Not Stuff
TP703Do Not Stuff TP703Do Not Stuff TP704Do Not Stuff TP704Do Not Stuff
D D
TP705Do Not Stuff TP705Do Not Stuff TP706Do Not Stuff TP706Do Not Stuff TP707Do Not Stuff TP707Do Not Stuff TP708Do Not Stuff TP708Do Not Stuff TP709Do Not Stuff TP709Do Not Stuff TP710Do Not Stuff TP710Do Not Stuff TP711Do Not Stuff TP711Do Not Stuff TP712Do Not Stuff TP712Do Not Stuff
M3 - Processor Generated SO-DIMM VREF_DQ
B4:VREF_DQ CHA D1:VREF_DQ CHB
M_VREF_DQ_D IMM0_C
4
1
RN701
RN701 SRN1KJ-7-G P
SRN1KJ-7-G P
2 3
M_VREF_DQ_D IMM1_C
R710
R710
1 2
DY
DY
Do Not Stuff
Do Not Stuff
EVT
C C
4
5 OF 9
CPU1E
CPU1E
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SANDY
SANDY
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17
RSVD#AJ31 RSVD#AH31 RSVD#AJ33 RSVD#AH33
RSVD#AJ26
B4
RSVD#B4 RSVD#D1
RSVD#F25 RSVD#F24 RSVD#F23 RSVD#D24 RSVD#G25 RSVD#G24 RSVD#E23 RSVD#D23 RSVD#C30 RSVD#A31 RSVD#B30 RSVD#B29 RSVD#D30 RSVD#B31 RSVD#A30 RSVD#C29
RSVD#J20 RSVD#B18 RSVD#A19
RSVD#J15
ARRAN
ARRAN
5 OF 9
L7
RSVD#L7
AG7
RSVD#AG7
AE7
RSVD#AE7
AK2
RSVD#AK2
W8
RSVD#W8
AT26
RSVD#AT26
AM33
RSVD#AM33
AJ27
RSVD#AJ27
T8
RSVD#T8
J16
RSVD#J16
H16
RSVD#H16
G16
RSVD#G16
AR35
RSVD#AR35
AT34
RSVD#AT34
AT33
RSVD#AT33
AP35
RSVD#AP35 RSVD#AR34
RSVD#B34 RSVD#A33 RSVD#A34 RSVD#B35 RSVD#C35
RESERVED
RESERVED
RSVD#AJ32
RSVD#AK32
RSVD#AH27
RSVD#AN35 RSVD#AM35
RSVD#AT2 RSVD#AT1
RSVD#AR1
AR34
B34 A33 A34 B35 C35
AJ32 AK32
AH27
AN35 AM35
AT2 AT1 AR1
CPU_CORN ER1
CPU_CORN ER2
CLK_XDP_ITP_P CLK_XDP_ITP_N
CPU_CORN ER3
1
1
1 1
1
TP716 Do Not StuffTP716 Do Not Stuff
TP717 Do Not StuffTP717 Do Not Stuff
TP715 Do Not StuffTP715 Do Not Stuff TP714 Do Not StuffTP714 Do Not Stuff
TP718 Do Not StuffTP718 Do Not Stuff
3
PEG Static Lane Reversal
CFG[0]
CFG2
CFG4
CFG5 CFG6
12
R703
R703 Do Not Stuff
Do Not Stuff
DY
DY
12
R701
R701 1KR2J-1-GP
1KR2J-1-GP
DIS
DIS
12
R702
R702 Do Not Stuff
Do Not Stuff
DY
DY
12
R704
R704 Do Not Stuff
Do Not Stuff
DY
DY
PEG Static Lane Reversal
CFG2
Display Port Presence Strap CFG4
PCIE Port Bifurcation Straps
CFG[6:5]
2
Connect a series 1K ohm resistor on the critical CFG[0] trace in a manner which does not introduce any stubs to CFG[0] trace. Route as needed from the opposite side of this series isolation resistor to the debug port. ITP will drive the net to GND.
1: Normal Operation; Lane # definition matches socket pin map definition
0:Lane Reversed
1: Disabled; No Physical Display Port attached to Embedded Display Port Can float on Processor if eDP interface is disabled
0: Enabled; An external Display Port device is connected to the Embedded Display Port
11: x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
1
CFG7
B B
A A
5
4
3
12
R705
R705 Do Not Stuff
Do Not Stuff
DY
DY
PEG DEFER TRAINING
1: PEG Train immediately following xxRESETB de assertion
CFG7
0: PEG Wait for BIOS for training
2
N12M GS2 HYN1GB
N12M GS2 HYN1GB
N12M GS2 HYN1GB
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.
Taipei Hsie n 221, Taiwan, R.O. C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A2
A2
A2
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Wednesd ay, March 02, 2011
Wednesd ay, March 02, 2011
Wednesd ay, March 02, 2011
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsie n 221, Taiwan, R.O. C.
CPU (RESERVED)
CPU (RESERVED)
CPU (RESERVED)
7 74
7 74
1
7 74
-1
-1
-1
5
SSID = CPU
PROCESSOR CORE POWER
D D
C C
B B
A A
VCC_CORE
12
12
12
C802
C802
C801
C801
DY
DY
12
C820
C820
DY
DY
12
12
DY
DY
DY
DY
DY
DY
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
12
C819
C819
DY
DY
DY
DY
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
12
C821
C821
C816
C816
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C836
C836
C837
C837
Do Not Stuff
Do Not Stuff
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
5
12
C803
C803
DY
DY
Do Not Stuff
Do Not Stuff
12
C818
C818
DY
DY
Do Not Stuff
Do Not Stuff
12
C822
C822
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C835
C835
Do Not Stuff
Do Not Stuff
DY
DY
12
C804
C804
C811
C811
DY
DY
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
12
12
C817
C817
C815
C815
DY
DY
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
12
12
C823
C823
C824
C824
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
C834
C834
C833
C833
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
DY
DY
12
C826
C826
C825
C825
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
DY
DY
12
C831
C831
C832
C832
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
4
POWER
CPU1F
AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26
AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27
AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
CPU1F
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
Y35
VCC
Y34
VCC
Y33
VCC
Y32
VCC
Y31
VCC
Y30
VCC
Y29
VCC
Y28
VCC
Y27
VCC
Y26
VCC
V35
VCC
V34
VCC
V33
VCC
V32
VCC
V31
VCC
V30
VCC
V29
VCC
V28
VCC
V27
VCC
V26
VCC
U35
VCC
U34
VCC
U33
VCC
U32
VCC
U31
VCC
U30
VCC
U29
VCC
U28
VCC
U27
VCC
U26
VCC
R35
VCC
R34
VCC
R33
VCC
R32
VCC
R31
VCC
R30
VCC
R29
VCC
R28
VCC
R27
VCC
R26
VCC
P35
VCC
P34
VCC
P33
VCC
P32
VCC
P31
VCC
P30
VCC
P29
VCC
P28
VCC
P27
VCC
P26
VCC
ARRAN
ARRAN
http://laptopblue.vn/
VCC_CORE
53A
12
C827
C827
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C828
C828
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
4
POWER
SANDY
SANDY
CORE SUPPLY
CORE SUPPLY
SENSE LINES SVID
SENSE LINES SVID
3
PEG AND DDR
PEG AND DDR
VCC_SENSE
VCCIO_SENSE VSSIO_SENSE
3
6 OF 9
6 OF 9
VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO
VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO
VCCIO
VIDALERT#
VIDSCLK
VIDSOUT
VSS_SENSE
2
AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12
E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11
J23
H_CPU_SVIDALRT#
AJ29
H_CPU_SVIDCLK
AJ30
H_CPU_SVIDDAT
AJ28
For CRB VIDSOUT need to pull high 130 ohm closr to CPU and IMVP7 For CRB VIDALERT# need to pull high 75 ohm close to CPU
1D05V_VTT
12
AJ35 AJ34
B10 A10
12
12
12
12
12
R804
R804 10R2F-L-GP
10R2F-L-GP
R805
R805 10R2F-L-GP
10R2F-L-GP
C806
C806
C805
C805
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
No-stuff sites outside the socket may be removed. No-stuff sites inside the socket cavity need to remain.
12
C812
C812
C813
C813
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
R803 43R2J-GPR803 43R2J-GP
1 2
VCCIO_SENSE 38 VSSIO_SENSE 38
C807
C807
12
C814
C814
DY
DY
10R2F-L-GP
10R2F-L-GP
10R2F-L-GP
10R2F-L-GP
12
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
Do Not Stuff
Do Not Stuff
VCC_CORE
R801
R801
R802
R802
C808
C808
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C829
C829
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
2
12
C810
C810
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
C842
C842
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
H_CPU_SVIDDAT
12
12
C838
C838
C839
C839
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
1D05V_VTT
12
12
C843
C843
C844
C844
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
R807 130R2F-1-GPR807 130R2F-1-GP
12
C809
C809
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C830
C830
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VR_SVID_ALERT# 35
H_CPU_SVIDCLK 35
H_CPU_SVIDDAT 35
R801,R802 close to CPU
VCCSENSE 35 VSSSENSE 35
12
12
ED801
ED801
ED802
ED802
N12M GS2 HYN1GB
N12M GS2 HYN1GB
N12M GS2 HYN1GB
VARISTOR-5V-1-GP
VARISTOR-5V-1-GP
VARISTOR-5V-1-GP
VARISTOR-5V-1-GP
Title
Title
PVT
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev Custom
Custom
Custom
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Date: Sheet of
Date: Sheet of
Date: Sheet of
1D05V_VTT
12
12
12
1 2
C841
C841
C840
C840
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
C845
C845
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
CPU (VCC_CORE)
CPU (VCC_CORE)
CPU (VCC_CORE)
1
1D05V_VTT
1
8 74
8 74
8 74
-1
-1
-1
5
4
3
2
1
SSID = CPU
http://laptopblue.vn/
VCC_GFXCORE
D D
C C
B B
VCC_GFXCORE
Disabling Guidelines for External Graphics Designs: Can connect to GND if motherboard only supports external graphics and if GFX VR is not stuffed. Can be left floating (Gfx VR keeps VAXG rail from floating) if the VR is stuffed
R903
R903 0R3J-0-U-GP
0R3J-0-U-GP
DIS
DIS
1 2
12
UMA
UMA
12
UMA
UMA
C901
C901
C907
C907
20110117
PROCESSOR VAXG: 24A
12
12
C903
Do Not Stuff
Do Not Stuff
12
Do Not Stuff
Do Not Stuff
UMA
UMA
C903
Do Not Stuff
Do Not Stuff
UMA
UMA
UMA
UMA
12
C918
C918
C908
C908
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
DY
DY
EVT 20100910 Del R904,R905,R901
1D8V_S0
12
TC902
TC902
Do Not Stuff
Do Not Stuff
DY
DY
12
C904
C904
C905
C905
Do Not Stuff
Do Not Stuff
UMA
UMA
12
12
C919
C919
Do Not Stuff
Do Not Stuff
DY
DY
UMA
UMA
PROCESSOR VCCPLL: 1.2A
12
12
C923
C923
Do Not Stuff
Do Not Stuff
DY
DY
DY
DY
CPU1G
CPU1G
AT24
VAXG
AT23
VAXG
12
C906
C906
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
UMA
UMA
C920
C920
Do Not Stuff
Do Not Stuff
12
C922
C922
C924
C924
Do Not Stuff
Do Not Stuff
SC1U10V2KX-1GP
SC1U10V2KX-1GP
AT21 AT20 AT18
AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17
AL24
AL23
AL21
AL20
AL18
AL17 AK24 AK23 AK21 AK20 AK18 AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17 AH24 AH23 AH21 AH20 AH18 AH17
VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG
B6
VCCPLL
A6
VCCPLL
A2
VCCPLL
ARRAN
ARRAN
POWER
POWER
SANDY
SANDY
GRAPHICS
GRAPHICS
1.8V RAIL
1.8V RAIL
SENSE
SENSE
VREFMISC
VREFMISC
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
SA RAIL
SA RAIL
7 OF 9
7 OF 9
VAXG_SENSE
VSSAXG_SENSE
LINES
LINES
SM_VREF
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA
VCCSA_SENSE
FC_C22
VCCSA_VID1
R906,R907 close to CPU
VCC_GFXCORE
12
Do Not Stuff
Do Not Stuff
UMA
AK35 AK34
AL1
AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1
+V_SM_VREF_CNT
UMA
12
Do Not Stuff
Do Not Stuff
UMA
UMA
Routing Guideline: Power from DDR_VREF_S3 and +V_SM_VREF_CNT should have 10 mils trace width.
PROCESSOR VCCSA: 6A
M27 M26 L26 J26 J25 J24 H26 H25
H23
C22 C24
VCCSA_SENSE
H_FC_C22 VCCSA_SEL
RN901
RN901
SRN10KJ-5-GP
SRN10KJ-5-GP
0D85V_S0
R906
R906
DVT
R907
R907
+V_SM_VREF_CNT 30
PROCESSOR VDDQ: 10A
12
12
C909
C909
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
12
C916
C916
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
R902
R902
R902 need be close to pin H23.
10R2J-2-GP
10R2J-2-GP
1
23
4
Refer to the latest Huron River Mainstream PDG (Doc# 436735) for more details on S3 power reduction implementation.
+V_SM_VREF_CNT should have 10 mil trace width
VCC_AXG_SENSE 35 VSS_AXG_SENSE 35
PVT
12
ED902
ED902
VARISTOR-5V-1-GP
C912
C912
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 1
VARISTOR-5V-1-GP
12
12
C913
C913
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
TP901 Do Not StuffTP901 Do Not Stuff TP902 Do Not StuffTP902 Do Not Stuff
1D5V_DDR_S0
12
C914
C914
DY
DY
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VARISTOR-5V-1-GP
VARISTOR-5V-1-GP
12
VCCSA Output Decoupling Recommendation: 1 x 330 uF 2 x 10 uF at Bottom Socket Cavity 1 x 10 uF at Bottom Socket Edge
12
C910
C910
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C915
C915
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VCCSA_SEL 41
12
ED901
ED901
C911
C911
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
0D85V_S0
C917
C917
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
H_FC_C22 VCCSA_SENSE
TC901
TC901
Do Not Stuff
Do Not Stuff
A A
5
4
3
2
N12M GS2 HYN1GB
N12M GS2 HYN1GB
N12M GS2 HYN1GB
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU (VCC_GFXCORE)
CPU (VCC_GFXCORE)
CPU (VCC_GFXCORE)
9 74
9 74
9 74
1
-1
-1
-1
5
4
3
2
1
SSID = CPU
CPU1H
CPU1H
AT35
VSS
AT32
VSS
AT29
VSS
AT27
VSS
AT25
VSS
AT22
VSS
D D
C C
B B
AT19 AT16 AT13 AT10
AT7 AT4
AT3 AR25 AR22 AR19 AR16 AR13 AR10
AR7
AR4
AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10
AP7
AP4
AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10
AN7
AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10
AM7 AM4 AM3 AM2
AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10
AL7 AL4
AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10
AK7
AK4
AJ25
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
http://laptopblue.vn/
SANDY
SANDY
VSS
VSS
8 OF 9
8 OF 9
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2
M34
G35 G32 G29 G26 G23 G20 G17 G11
N35 N34 N33 N32 N31 N30 N29 N28 N27 N26
K35 K32 K29 K26
H33 H30 H27 H24 H21 H18 H15 H13 H10
F34 F31 F29
9 OF 9
CPU1I
CPU1I
T35
VSS
T34
VSS
T33
VSS
T32
VSS
T31
VSS
T30
VSS
T29
VSS
T28
VSS
T27
VSS
T26
VSS
P9
VSS
P8
VSS
P6
VSS
P5
VSS
P3
VSS
P2
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
L33
VSS
L30
VSS
L27
VSS
L9
VSS
L8
VSS
L6
VSS
L5
VSS
L4
VSS
L3
VSS
L2
VSS
L1
VSS VSS VSS VSS VSS
J34
VSS
J31
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
H9
VSS
H8
VSS
H7
VSS
H6
VSS
H5
VSS
H4
VSS
H3
VSS
H2
VSS
H1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
SANDY
SANDY
VSS
VSS
9 OF 9
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3
CPU_CORNER4
R1001 Do Not Stuff
R1001 Do Not Stuff
1 2
DY
DY
1
TP719 Do Not StuffTP719 Do Not Stuff
ARRAN
ARRAN
A A
5
4
3
ARRAN
ARRAN
N12M GS2 HYN1GB
N12M GS2 HYN1GB
N12M GS2 HYN1GB
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
CPU (VSS)
CPU (VSS)
CPU (VSS)
10 74
10 74
10 74
1
-1
-1
-1
5
DDR_VREF_S3
D D
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C1425
C1425
DDR_VREF_S3
SCD1U10V2KX-5GP
Do Not Stuff
Do Not Stuff
12
12
C1423
C1423
DY
DY
C1424
C1424
EVT Del R1401
Do Not Stuff
Do Not Stuff
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C1411
C1411
C C
0D75V_S0
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
C1419
C1419
SA0_DIM0 SA1_DIM0
B B
A A
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
12
C1412
C1412
C1413
C1413
DY
DY
Do Not Stuff
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
Do Not Stuff
C1421
C1421
12
1
4
5
C1418
C1418
DY
DY
23
SRN10KJ-5-GP
SRN10KJ-5-GP RN1401
RN1401
3D3V_S0
12
1D5V_S3
M_A_DIM0_CLK_DDR06
M_A_DIM0_CLK_DDR#06
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
Do Not Stuff
Do Not Stuff
12
12
C1401
C1401
C1402
C1402
DY
DY
4
SA0_DIM0 SA1_DIM0
4
DDR_VREF_S3
M_A_DQ0 M_A_DQ1
M_A_DQ2 M_A_DQ3
M_A_DQ8 M_A_DQ9
M_A_DQS#1 M_A_DQS1
M_A_DQ10 M_A_DQ11
M_A_DQ16 M_A_DQ17
M_A_DQS#2 M_A_DQS2
M_A_DQ18 M_A_DQ19
M_A_DQ24 M_A_DQ25
M_A_DQ26 M_A_DQ27
M_A_BS2 M_A_A12
M_A_A9 M_A_A8
M_A_A5 M_A_A3
M_A_A1
M_A_A10 M_A_BS0
M_A_WE# M_A_CAS#
M_A_A13
M_A_DQ32 M_A_DQ33
M_A_DQS#4 M_A_DQS4
M_A_DQ34 M_A_DQ35
M_A_DQ40 M_A_DQ41
M_A_DQ42 M_A_DQ43
M_A_DQ48 M_A_DQ49
M_A_DQS#6 M_A_DQS6
M_A_DQ50 M_A_DQ51
M_A_DQ56 M_A_DQ57
M_A_DQ58 M_A_DQ59
0D75V_S0
http://laptopblue.vn/
M_A_DQ06 M_A_DQ16
M_A_DQ26 M_A_DQ36
M_A_DQ86 M_A_DQ96
M_A_DQS#16
M_A_DQS16 M_A_DQ106
M_A_DQ116 M_A_DQ166
M_A_DQ176
M_A_DQS#26
M_A_DQS26 M_A_DQ186
M_A_DQ196 M_A_DQ246
M_A_DQ256
M_A_DQ266 M_A_DQ276
M_A_DIM0_CKE06
M_A_BS26
M_A_A126 M_A_A96
M_A_A86 M_A_A56
M_A_A36 M_A_A16
M_A_A106
M_A_BS06
M_A_WE#6
M_A_CAS#6
M_A_A136
M_A_DIM0_CS#16
M_A_DQ326 M_A_DQ336
M_A_DQS#46 M_A_DQS46
M_A_DQ346 M_A_DQ356
M_A_DQ406 M_A_DQ416
M_A_DQ426 M_A_DQ436
M_A_DQ486 M_A_DQ496
M_A_DQS#66 M_A_DQS66
M_A_DQ506 M_A_DQ516
M_A_DQ566 M_A_DQ576
M_A_DQ586 M_A_DQ596
DM1
DM1
NP1
205
1 3
2
5
4
7
6
9
8
11
10
13
12
15
14
17
16
19
18
21
20
23
22
25
24
27
26
29
28
31
30
33
32
35
34
37
36
39
38
41
40
43
42
45
44
47
46
49
48
51
50
53
52
55
54
57
56
59
58
61
60
63
62
65
64
67
66
69
68
71
70 72
73 75
74
77
76
79
78
81
80
83
82
85
84
87
86
89
88
91
90
93
92
95
94
97
96
99
98
101
100
103
102
105
104
107
106
109
108
111
110
113
112
115
114
117
116
119
118
121
120
123
122
125
124
127
126
129
128
131
130
133
132
135
134
137
136
139
138
141
140
143
142
145
144
147
146
149
148
151
150
153
152
155
154
157
156
159
158
161
160
163
162
165
164
167
166
169
168
171
170
173
172
175
174
177
176
179
178
181
180
183
182
185
184
187
186
189
188
191
190
193
192
195
194
197
196
199
198
201
200
203
202 204
206
NP2
DDR3-204P-119-GP
DDR3-204P-119-GP
62.10017.Z81
62.10017.Z81
2nd = 62.10017.N41
2nd = 62.10017.N41
3rd = 62.10017.P41
3rd = 62.10017.P41
0D75V_S0
3
M_A_DQ4 M_A_DQ5
M_A_DQS#0 M_A_DQS0
M_A_DQ6 M_A_DQ7
M_A_DQ12 M_A_DQ13
M_A_DQ14 M_A_DQ15
M_A_DQ20 M_A_DQ21
M_A_DQ22 M_A_DQ23
M_A_DQ28 M_A_DQ29
M_A_DQS#3 M_A_DQS3
M_A_DQ30 M_A_DQ31
M_A_A15 M_A_A14
M_A_A11 M_A_A7
M_A_A6 M_A_A4
M_A_A2 M_A_A0
M_A_BS1 M_A_RAS#
DDR_VREF_S3 M_A_DQ36
M_A_DQ37
M_A_DQ38 M_A_DQ39
M_A_DQ44 M_A_DQ45
M_A_DQS#5 M_A_DQS5
M_A_DQ46 M_A_DQ47
M_A_DQ52 M_A_DQ53
M_A_DQ54 M_A_DQ55
M_A_DQ60 M_A_DQ61
M_A_DQS#7 M_A_DQS7
M_A_DQ62 M_A_DQ63
M_A_DQ4 6 M_A_DQ5 6
M_A_DQS#0 6 M_A_DQS0 6
M_A_DQ6 6 M_A_DQ7 6
M_A_DQ12 6 M_A_DQ13 6
DDR3_DRAMRST# 12,30
M_A_DQ14 6 M_A_DQ15 6
M_A_DQ20 6 M_A_DQ21 6
M_A_DQ22 6 M_A_DQ23 6
M_A_DQ28 6 M_A_DQ29 6
M_A_DQS#3 6 M_A_DQS3 6
M_A_DQ30 6 M_A_DQ31 6
M_A_DIM0_CKE1 6 M_A_A15 6
M_A_A14 6 M_A_A11 6
M_A_A7 6 M_A_A6 6
M_A_A4 6 M_A_A2 6
M_A_A0 6 M_A_DIM0_CLK_DDR1 6
M_A_DIM0_CLK_DDR#1 6
M_A_BS1 6 M_A_RAS# 6
M_A_DIM0_CS#0 6 M_A_DIM0_ODT0 6
M_A_DIM0_ODT1 6
M_A_DQ36 6 M_A_DQ37 6
M_A_DQ38 6 M_A_DQ39 6
M_A_DQ44 6 M_A_DQ45 6
M_A_DQS#5 6 M_A_DQS5 6
M_A_DQ46 6 M_A_DQ47 6
M_A_DQ52 6 M_A_DQ53 6
M_A_DQ54 6 M_A_DQ55 6
M_A_DQ60 6 M_A_DQ61 6
M_A_DQS#7 6 M_A_DQS7 6
M_A_DQ62 6 M_A_DQ63 6
PCH_SMBDATA 12,16,51 PCH_SMBCLK 12,16,51
1D5V_S3
DIMM main =62.10017.N41 2nd=62.10017.P41
3
2
1D5V_S3
12
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
2
C1414
C1414
Do Not Stuff
Do Not Stuff
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
TC1401
TC1401
DY
DY
12
C1415
C1415
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
TS#_DIMM0_1 12
1
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
Do Not Stuff
12
C1403
C1403
12
C1416
C1416
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
Do Not Stuff
12
12
C1404
C1404
C1405
C1405
DY
DY
Do Not Stuff
Do Not Stuff
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
12
C1408
C1408
C1417
C1417
DY
DY
N12M GS2 HYN1GB
N12M GS2 HYN1GB
N12M GS2 HYN1GB
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev Custom
Custom
Custom
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Date: Sheet of
Date: Sheet of
Date: Sheet of
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
Do Not Stuff
Do Not Stuff
C1407
C1407
C1406
C1406
12
C1409
C1409
DY
DY
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
DDR3-SODIMM1
DDR3-SODIMM1
DDR3-SODIMM1
1
Do Not Stuff
Do Not Stuff
12
C1410
C1410
DY
DY
11 74
11 74
11 74
-1
-1
-1
5
SSID = MEMORY
PART NUMBER
62.10017.Q31
62.10017.N11 9.2mm REVERSED
D D
DDR_VREF_S3
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
Do Not Stuff
Do Not Stuff
12
C1524
C C
B B
A A
C1524
DDR_VREF_S3
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C1519
C1519
0D75V_S0
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
Do Not Stuff
Do Not Stuff
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C1513
C1513
Height
9.2mm STANDARD
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
12
12
12
C1525
C1525
C1523
C1523
DY
DY
EVT Del R1501
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C1518
C1518
C1515
C1515
DY
DY
Place these caps close to VTT1 and VTT2.
Do Not Stuff
Do Not Stuff
12
C1521
C1521
C1520
C1520
DY
DY
5
TYPE
M_B_A[15:0]6
M_B_BS26 M_B_BS06
M_B_BS16
M_B_DQ[63:0]6
M_B_DQS#[7:0]6
M_B_DQS[7:0]6
M_B_DIM0_ODT06 M_B_DIM0_ODT16
DDR3_DRAMRST#11,30
0D75V_S0
DDR_VREF_S3 DDR_VREF_S3
4
DM2
M_B_A0 M_B_A1
http://laptopblue.vn/
M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15
M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7
M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7
98 97 96 95 92 91 90 86 89 85
107
84 83
119
80 78 79
109 108
5
7 15 17
4
6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70
129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194
10 27 45 62
135 152 169 186
12 29 47 64
137 154 171 188
116 120
126
1 30
203 204
2nd = 62.10017.N11
2nd = 62.10017.N11
3rd = 62.10017.N61
3rd = 62.10017.N61
4
DM2
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2
BA0 BA1
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7
ODT0 ODT1
VREF_CA VREF_DQ
RESET#
VTT1 VTT2
DDR3-204P-128-GP
DDR3-204P-128-GP
62.10024.D51
62.10024.D51
NP1 NP2
RAS#
WE#
CAS# CS0#
CS1# CKE0
CKE1
CK0
CK0#
CK1
CK1#
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7
SDA
SCL
EVENT#
VDDSPD
SA0 SA1
NC#1 NC#2
NC#/TEST
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8
VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
NP1 NP2
110 113 115
114 121
73 74
101 103
102 104
11 28 46 63 136 153 170 187
200 202
198 199 197
201 77
122 125
75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124
2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206
SA0_DIM1 SA1_DIM1
1D5V_S3
3
M_B_RAS# 6 M_B_WE# 6 M_B_CAS# 6
M_B_DIM0_CS#0 6 M_B_DIM0_CS#1 6
M_B_DIM0_CKE0 6 M_B_DIM0_CKE1 6
M_B_DIM0_CLK_DDR0 6 M_B_DIM0_CLK_DDR#0 6
M_B_DIM0_CLK_DDR1 6 M_B_DIM0_CLK_DDR#1 6
PCH_SMBDATA 11,16,51 PCH_SMBCLK 11,16,51
TS#_DIMM0_1 11
12
R1502
R1502 10KR2J-3-GP
10KR2J-3-GP
Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34
SO-DIMMB is placed farther from the Processor than SO-DIMMA
1D5V_S3
SODIMM B DECOUPLING
Do Not Stuff
Do Not Stuff
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
TC1501
TC1501
DY
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
12
C1512
C1512
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C1508
C1508
DIMM main =62.10017.N11 2nd=62.10017.N61
H = 9.2mm
3
2
3D3V_S0
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
Do Not Stuff
Do Not Stuff
12
12
C1501
C1501
DY
DY
Do Not Stuff
Do Not Stuff
12
12
C1511
C1511
C1517
C1517
DY
DY
12
12
C1509
C1509
C1510
C1510
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
3D3V_S0
SA1_DIM1 TS#_DIMM0_1
Do Not Stuff
Do Not Stuff
C1504
C1504
DY
DY
12
C1514
C1514
DY
DY
1
4
12
C1506
C1506
DY
DY
Do Not Stuff
Do Not Stuff
12
C1502
C1502
Layout Note: Place these Caps near SO-DIMMB.
Do Not Stuff
Do Not Stuff
12
Do Not Stuff
Do Not Stuff
23
SRN10KJ-5-GP
SRN10KJ-5-GP RN1501
RN1501
EVT 4P2R
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C1507
C1507
C1505
C1505
DY
DY
2
1
Do Not Stuff
Do Not Stuff
12
C1503
C1503
DY
DY
N12M GS2 HYN1GB
N12M GS2 HYN1GB
N12M GS2 HYN1GB
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev Custom
Custom
Custom
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Date: Sheet of
Date: Sheet of
Date: Sheet of
Taipei Hsien 221, Taiwan, R.O.C.
DDR3-SODIMM2
DDR3-SODIMM2
DDR3-SODIMM2
1
12 74
12 74
12 74
-1
-1
-1
5
4
3
2
1
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D D
L_BKLT_EN23
3D3V_S0
RN1701
RN1701
1 2 3
UMA
UMA
Do Not Stuff
Do Not Stuff
RN1702
RN1702
1 2 3
UMA
UMA
Do Not Stuff
Do Not Stuff
C C
4
4
L_CTRL_DATA L_CTRL_CLK
L_BKLT_EN LVDS_VDD_EN
L_DDC_DATA(PAGE17): This signal is on the LVDS interface. This signal needs to be left NC if eDP is used for the local flat panel display
12
R1701
R1701 Do Not Stuff
Do Not Stuff
UMA
Place near PCH
minimum spacing of 20 Mils
UMA
Impedance:90 ohm
B B
Close to PCH side
CRT_BLUE CRT_GREEN CRT_RED
678
RN1705
RN1705 Do Not Stuff
Do Not Stuff
UMA
UMA
123
4 5
LVDS_VDD_EN42
L_BKLT_CTRL42
LVDS_DDC_CLK_R42 LVDS_DDC_DATA_R42
RN1704
1 2 3
UMA
UMA
Do Not Stuff
Do Not Stuff
1KR2D-1-GP
1KR2D-1-GP
RN1704
TP1701Do Not Stuff TP1701Do Not Stuff
LVDSA_CLK#42 LVDSA_CLK42
LVDSA_DATA0#42 LVDSA_DATA1#42 LVDSA_DATA2#42
LVDSA_DATA042 LVDSA_DATA142 LVDSA_DATA242
CRT_BLUE43 CRT_GREEN43 CRT_RED43
CRT_DDC_CLK43 CRT_DDC_DATA43
CRT_HSYNC43 CRT_VSYNC43
R1702
R1702
LVDS_DDC_CLK_R LVDS_DDC_DATA_R
L_CTRL_CLK L_CTRL_DATA
LVDS_IBG LVDS_VBG
1
LVDS_VREFH
4
LVDS_VREFL
DAC_IREF_R
12
CHANGE TO 71.0HM65.00U
4 OF 10
PCH1D
PCH1D
J47
L_BKLTEN
M45
L_VDD_EN
P45
L_BKLTCTL
T40
L_DDC_CLK
K47
L_DDC_DATA
T45
L_CTRL_CLK
P39
L_CTRL_DATA
AF37
LVD_IBG
AF36
LVD_VBG
AE48
LVD_VREFH
AE47
LVD_VREFL
AK39
LVDSA_CLK#
AK40
LVDSA_CLK
AN48
LVDSA_DATA#0
AM47
LVDSA_DATA#1
AK47
LVDSA_DATA#2
AJ48
LVDSA_DATA#3
AN47
LVDSA_DATA0
AM49
LVDSA_DATA1
AK49
LVDSA_DATA2
AJ47
LVDSA_DATA3
AF40
LVDSB_CLK#
AF39
LVDSB_CLK
AH45
LVDSB_DATA#0
AH47
LVDSB_DATA#1
AF49
LVDSB_DATA#2
AF45
LVDSB_DATA#3
AH43
LVDSB_DATA0
AH49
LVDSB_DATA1
AF47
LVDSB_DATA2
AF43
LVDSB_DATA3
N48
CRT_BLUE
P49
CRT_GREEN
T49
CRT_RED
T39
CRT_DDC_CLK
M40
CRT_DDC_DATA
M47
CRT_HSYNC
M49
CRT_VSYNC
T43
DAC_IREF
T42
CRT_IRTN
COUGAR-GP-U2-NF
COUGAR-GP-U2-NF
Cougar
Cougar Point
Point
LVDS
LVDS
CRT
CRT
Digital Display Interface
Digital Display Interface
4 OF 10
SDVO_TVCLKINN SDVO_TVCLKINP
SDVO_STALLN SDVO_STALLP
SDVO_INTN
SDVO_INTP
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPB_AUXN DDPB_AUXP
DDPB_HPD
DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN DDPC_AUXP
DDPC_HPD
DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN DDPD_AUXP
DDPD_HPD
DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P
AP43 AP45
AM42 AM40
AP39 AP40
P38 M39
AT49 AT47 AT40
AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49
P46 P42
AP47 AP49 AT38
AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49
M43 M36
AT45 AT43 BH41
BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42
3D3V_S0
4
RN1706
RN1706 Do Not Stuff
Do Not Stuff
1
2 3
Impedance:90 ohm
UMA
UMA
EVT
DDI Port B Detect:(SDVO_CTRL_ DATA) Pulled-up through a 2.2 k ±5% to 3.3V: Enable Port B NO CONNECT: Disable the Port B
PCH_HDMI_CLK 44 PCH_HDMI_DATA 44
HDMI_DATA2_C# 44 HDMI_DATA2_C 44 HDMI_DATA1_C# 44 HDMI_DATA1_C 44 HDMI_DATA0_C# 44 HDMI_DATA0_C 44 HDMI_CLK_C# 44 HDMI_CLK_C 44
If using HDMI*, level shifter (3.3 V to 5 V) is required between PCH and HDMI connector
HDMI_PCH_DET 44
Impedance:100 ohm
A A
5
4
3
2
N12M GS2 HYN1GB
N12M GS2 HYN1GB
N12M GS2 HYN1GB
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Date: Sheet of
Date: Sheet of
Date: Sheet of
PCH (LVDS/CRT/DDI)
PCH (LVDS/CRT/DDI)
PCH (LVDS/CRT/DDI)
13 74
13 74
13 74
1
-1
-1
-1
5
SSID = PCH
RN1801
INT_PIRQH# INT_PIRQB#
D D
3D3V_S0
C C
B B
INT_PIRQF#
PLT_RST#5,22,23,26,27,51,55,60,69
A16 swap override Strap/Top-Block Swap Override jumper
PCI_GNT#3 Low = A16 swap
RN1801
1 2 3 4 5 6
SRN8K2J-2-GP-U
SRN8K2J-2-GP-U
3D3V_S0
RN1802
RN1802 SRN8K2J-4-GP
SRN8K2J-4-GP
1 2 3 4 5
override/Top-Block Swap Override enabled High = Default
PCI_REQ1#
8
PCI_REQ2#
7
PCI_REQ3#
6
12
R1816
R1816 Do Not Stuff
Do Not Stuff
DY
DY
10
INT_PIRQD#
9
INT_PIRQE#
8
INT_PIRQC#INT_PIRQA#
7
INT_PIRQG#
3D3V_S0
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
12
C1801
C1801
DY
DY
CLK_PCI_LPC55 CLK_PCI_FB16 CLK_PCI_KBC23
3D3V_S0
PCH_GPIO68 18
U1801
U1801
DY
DY
GND
R1807
R1807
1 2
Do Not Stuff
Do Not Stuff
1
A
2
B
3
Do Not Stuff
Do Not Stuff
5
VCC
4
Y
Do Not Stuff
Do Not Stuff
2ND = 73.7SZ08.EAH
2ND = 73.7SZ08.EAH
3RD = 73.01G08.L04
3RD = 73.01G08.L04
12
EC1803
EC1803
DY
DY
4
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PCI_PLTRST#
Do Not Stuff
Do Not Stuff
12
C1802
C1802
DY
DY
R1804 22R2J-2-GPR1804 22R2J-2-GP
1 2
R1805 22R2J-2-GPR1805 22R2J-2-GP
1 2
R1806 22R2J-2-GPR1806 22R2J-2-GP
EC1802
EC1802
DY
DY
Do Not Stuff
Do Not Stuff
1 2
12
EC1801
EC1801
DY
DY
Do Not Stuff
Do Not Stuff
12
BBS_BIT117
1
TP1803Do Not Stuff TP1803Do Not Stuff
R1801
R1801
Do Not Stuff
Do Not Stuff
TP1802Do Not Stuff TP1802Do Not Stuff
INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#
PCI_REQ1# PCI_REQ2# PCI_REQ3#
BBS_BIT1 PCI_GNT2# PCI_GNT3#
12
DY
DY
INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH#
PCI_PME#
1
PCI_PLTRST#
CLK_PCI_LPC_R CLK_PCI_FB_R CLK_PCI_KBC_R
BG26
BJ26
BH25
BJ16 BG16 AH38 AH37 AK43 AK45
C18 N30
AH12
AM4 AM5
AB46 AB45
M20 AY16 BG46
BE28 BC30 BE32
BJ32 BC28 BE30
BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28
AW30
PCH1E
PCH1E
TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11
H3
TP12 TP13 TP14 TP15
Y13
TP16
K24
TP17
L24
TP18 TP19 TP20
B21
TP21 TP22 TP23 TP24
TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40
K40
PIRQA#
K38
PIRQB#
H38
PIRQC#
G38
PIRQD#
C46
REQ1#/GPIO50
C44
REQ2#/GPIO52
E40
REQ3#/GPIO54
D47
GNT1#/GPIO51
E42
GNT2#/GPIO53
F46
GNT3#/GPIO55
G42
PIRQE#/GPIO2
G40
PIRQF#/GPIO3
C42
PIRQG#/GPIO4
D44
PIRQH#/GPIO5
K10
PME#
C6
PLTRST#
H49
CLKOUT_PCI0
H43
CLKOUT_PCI1
J48
CLKOUT_PCI2
K42
CLKOUT_PCI3
H40
CLKOUT_PCI4
COUGAR-GP-U2-NF
COUGAR-GP-U2-NF
3
Cougar
Cougar Point
Point
RSVD
RSVD
PCI
PCI
NVRAM
NVRAM
Device 29 Function 0
EHCI1
USB
USB
EHCI2
Device 26 Function 0
5 OF 10
5 OF 10
RSVD RSVD RSVD RSVD
RSVD RSVD
RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
RSVD
DF_TVS
RSVD RSVD RSVD
RSVD RSVD
RSVD
USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N
USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P
USBRBIAS#
USBRBIAS
OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43
OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14
AY7 AV7 AU3 BG4
AT10 BC8
AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6
AV5 AY1
AV10 AT8 AY5
BA2 AT12
BF3
C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32
C33
B33
A14 K20 B17 C16 L16 A16 D14 C14
Danbury Technology: Disabled when Low. Enable when High.
NV_ALE NV_CLE
NV_RCOMP
USB_RBIAS
1 2
R1808
R1808 22D6R2F-L1-GP
22D6R2F-L1-GP
CHKLST 0.9 P.53
USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7
2
R1809
R1809
1 2
1KR2J-1-GP
1KR2J-1-GP
1
USB_PN0 59 USB_PP0 59 USB_PN1 49 USB_PP1 49 USB_PN2 59 USB_PP2 59
USB_PN4 59 USB_PP4 59
USB_PN9 42 USB_PP9 42
USB_PN12 51 USB_PP12 51 USB_PN13 50 USB_PP13 50
Signal Routing Guideline: USBRBIAS/USBRBIAS# keep W/S=12/15 mils and routing length less than 500 mils.
KBC CLK EMI
+V_NVRAM_VCCQ
H_SNB_IVB# 5
TP17 Do Not StuffTP17 Do Not Stuff
USB_OC#0 59 USB_OC#1 49 USB_OC#2 59 USB_OC#3 59
3D3V_S5
12
R1810
R1810 Do Not Stuff
Do Not Stuff
DY
DY
Debug Port
USB_OC#0 USB_OC#1
Pair
0
MB
1 2 3 4 5 6 7 8 9 10 11 12 13
RN1803
RN1803
1 2 3 4 5 6
SRN8K2J-2-GP-U
SRN8K2J-2-GP-U
1
USB Table
Device USB Ext. port 4 USB Ext. port 1 USB Ext. port 2
USB Ext. port 3 X X X X CAMERA X X Mini Card1 (WMAX) BLUETOOTH
10
USB_OC#7
9
USB_OC#6USB_OC#2
8
USB_OC#5USB_OC#3
7
USB_OC#4
OC#0 OC#1 OC#2
OC#3
OC#5
OC#7
3D3V_S5
A A
5
4
3
2
N12M GS2 HYN1GB
N12M GS2 HYN1GB
N12M GS2 HYN1GB
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Date: Sheet of
Date: Sheet of
Date: Sheet of
PCH (PCI/USB/NVRAM)
PCH (PCI/USB/NVRAM)
PCH (PCI/USB/NVRAM)
14 74
14 74
14 74
1
-1
-1
-1
5
4
3
2
1
SSID = PCH
http://laptopblue.vn/
3 OF 10
PCH1C
DMI_RXN[3:0]4
Signal Routing Guideline:
D D
DMI_ZCOMP keep W=4 mils and routing length less than 500 mils. DMI_IRCOMP keep W=4 mils and routing length less than 500 mils.
1D05V_VTT
R1904 49D9R2F-GPR1904 49D9R2F-GP R1907 750R2F-GPR1907 750R2F-GP
C C
3D3V_S0
PVT
PWR_VCCSA_PWRGD29,35,41
SYS_PWROK29
S0_PWR_GOOD22,23,29,35,44
1 2
DY
DY
1 2 1 2
1 2
DY
DY
DMI_RXP[3:0]4
DMI_TXN[3:0]4
DMI_TXP[3:0]4
1 2 1 2
R1902
R1902
1 2
Do Not Stuff
Do Not Stuff
R1905
R1905
1 2
10KR2J-3-GP
10KR2J-3-GP
R1921 Do Not Stuff
R1921 Do Not Stuff R1911 1KR2J-1-GPR1911 1KR2J-1-GP
R1910
R1910
10KR2J-3-GP
10KR2J-3-GP
R1906 Do Not Stuff
R1906 Do Not Stuff
PM_DRAM_PWRGD5,30
S0_PWR_GOOD after PM_SLP_S3# delay 200 ms
SUS_PW R_ACK23
PM_PWRBTN#23,69
B B
R1908
R1908
12
100KR2J-1-GP
100KR2J-1-GP
3D3V_AUX_S5
12
R1916
R1916 10KR2J-3-GP
10KR2J-3-GP
A A
3V_5V_POK_#
2nd = 84.DM601.03F
2nd = 84.DM601.03F
PM_RSMRST#
R1909
R1909
12
100KR2J-1-GP
100KR2J-1-GP
Q1901
Q1901
5 6
2N7002KDW-GP
2N7002KDW-GP
84.2N702.A3F
84.2N702.A3F
5
34 2 1
AC_PRESENT23,63
BATLOW #16
PM_RSMRST#
R1912
R1912
1 2
1KR2J-1-GP
1KR2J-1-GP
3V_5V_POK 34
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
DMI_COMP_R RBIAS_CPY
R1923
R1923
1 2
DY
DY
Do Not Stuff
Do Not Stuff
R1903 Do Not StuffR1903 Do Not Stuff
1 2
MEPWROK
PM_RSMRST#
BATLOW #
PM_RI#
SUSACK#SUS_PW R_ACK
SYS_RESET#
PWROK
PCH1C
BC24
DMI0RXN
BE20
DMI1RXN
BG18
DMI2RXN
BG20
DMI3RXN
BE24
DMI0RXP
BC20
DMI1RXP
BJ18
DMI2RXP
BJ20
DMI3RXP
AW24
DMI0TXN
AW20
DMI1TXN
BB18
DMI2TXN
AV18
DMI3TXN
AY24
DMI0TXP
AY20
DMI1TXP
AY18
DMI2TXP
AU18
DMI3TXP
BJ24
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
DMI2RBIAS
C12
SUSACK#
K3
SYS_RESET#
P12
SYS_PWROK
L22
PWROK
L10
APWROK
B13
DRAMPWROK
OD Output
C21
RSMRST#
K16
SUSWARN#/SUSPWRDNACK/GPIO30
E20
PWRBTN#
internal pull-up
H20
ACPRESENT/GPIO31
E10
BATLOW#/GPIO72
A10
RI#
COUGAR-GP-U2-NF
COUGAR-GP-U2-NF
PWROK
RSMRST#_KBC 23
PVT
4
Cougar
Cougar Point
Point
VccASW Suspend 1D05_VTT
PM_RSMRST#
DMI
DMI
System Power Management
System Power Management
Do Not Stuff
Do Not Stuff
Q1904
Q1904
DY
DY
G
R1924 0R2J-2-GPR1924 0R2J-2-GP
1 2
83.BAS70.C11
83.BAS70.C11
3 OF 10
FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7
FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6
FDI
FDI
FDI_RXP7
FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1
DSWVRMEN
DPWROK
WAKE#
CLKRUN#/GPIO32
SUS_STAT#/GPIO61
SUSCLK/GPIO62
SLP_S5#/GPIO63
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
SLP_LAN#/GPIO29
S0_PWR_GOODPWROK
DS
G680_RST#
D1901
D1901
1
2
BAS70-05-7-F-GP
BAS70-05-7-F-GP
G680_RST#22
FDI_INT 4 FDI_FSYNC0 4 FDI_FSYNC1 4 FDI_LSYNC0 4 FDI_LSYNC1 4
PCIE_WAKE# 26,51
PM_CLKRUN# 23
1
R1913
R1913
1 2
Do Not Stuff
Do Not Stuff
1
R1914
R1914
1 2
Do Not Stuff
Do Not Stuff
1 2
Do Not Stuff
Do Not Stuff
1
1
1
C1901
C1901
12
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
5
VCC
4
RESET#/RESET
G680LT1UF-GP
G680LT1UF-GP
FDI_TXN[7:0] 4
FDI_TXP[7:0] 4
R1927
R1927
1 2
Do Not Stuff
Do Not Stuff
TP1901 Do Not StuffTP1901 Do Not Stuff
TP1902 Do Not StuffTP1902 Do Not Stuff
R1915
R1915
TP1903Do Not StuffTP1903Do Not Stuff
TP1904Do Not StuffTP1904Do Not Stuff
H_PM_SYNC 5
TP1905Do Not StuffTP1905Do Not Stuff
U1901
U1901
HTH
GND
LTH
74.00680.A7F
74.00680.A7F
1 2 3
FDI_TXN0
BJ14
FDI_TXN1
AY14
FDI_TXN2
BE14
FDI_TXN3
BH13
FDI_TXN4
BC12
FDI_TXN5
BJ12
FDI_TXN6
BG10
FDI_TXN7
BG9
FDI_TXP0
BG14
FDI_TXP1
BB14
FDI_TXP2
BF14
FDI_TXP3
BG13
FDI_TXP4
BE12
FDI_TXP5
BG12
FDI_TXP6
BJ10
FDI_TXP7
BH9
AW16 AV12 BC10 AV14 BB10
DSWODVREN
A18
PCH_DPW ROK PM_RSMRST#
E22
B9
N3
PM_SUS_STAT#
G8
SUS_CLK
N14
PM_SLP_S5#
D10
SLP_S4#_R
H4
SLP_S3#_R
F4
PM_SLP_A#
G10
PM_SLP_SUS#
G16
H_PM_SYNC
AP14
PM_SLP_LAN#
K14
5V_AUX_S5
G680_RST# LTH
3
3
For platforms not supporting Deep S4/S5
1.VccSUS3_3 and VccDSW3_3 will rise at the same time (connected on board)
2.DPWROK and RSMRST# will rise at the same time (connected on board)
3.SLP_SUS# and SUSACK# are left as ‘no connect’
4.SUSWARN# used as SUSPWRDNACK/GPIO30
DSWODVREN - On Die DSW VR Enable HIGH Enabled (DEFAULT) LOW Disabled
RTC_AUX_S5
R1917
R1917
1 2
330KR2J-L1-GP
330KR2J-L1-GP
PCH_SUSCLK_KBC 23
PM_SLP_S4# 23,29,39
PM_SLP_S3# 23,29,30,40,45,67
DCBATOUT
12
R1929
R1929 820KR2F-GP
820KR2F-GP
HTH
12
R1930
R1930 15KR2F-GP
15KR2F-GP
12
R1931
R1931 165KR2F-GP
165KR2F-GP
2
DSWODVREN
SUS_PW R_ACK
AC_PRESENT PCIE_WAKE# PM_RI#
PM_PWRBTN#
PM_SLP_LAN#
EVT
PM_CLKRUN#
N12M GS2 HYN1GB
N12M GS2 HYN1GB
N12M GS2 HYN1GB
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Date: Sheet of
Date: Sheet of
Date: Sheet of
R1918
R1918
1 2
DY
DY
Do Not Stuff
Do Not Stuff
PVT
R1925
R1925
1 2
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
R1919 8K2R2J-3-GPR1919 8K2R2J-3-GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
PCH (DM I/FDI/PM)
PCH (DM I/FDI/PM)
PCH (DM I/FDI/PM)
RN1901
RN1901
1 2 3 4 5
SRN10KJ-6-GP
SRN10KJ-6-GP
R1922
R1922
1 2
R1920
R1920
1 2
10KR2J-3-GP
10KR2J-3-GP
1 2
1
DY
DY
8 7 6
DY
DY
15 74
15 74
15 74
3D3V_S5
3D3V_S0
-1
-1
-1
5
SSID = PCH
PCIE_RXN151 PCIE_RXP151 PCIE_TXN151
D D
C C
PCIE_TXP151 PCIE_RXN227
PCIE_RXP227 PCIE_TXN227 PCIE_TXP227
PCIE_RXN426
PCIE_RXP426 PCIE_TXN426 PCIE_TXP426
100-MHZ PCIe 2.0 compliant differential Clocks to PCI Express Devices.
WLAN CLK
Card Reader
CLK_PCIE_LAN#26
RN2020
RN2020
1 2 3 4 5
SRN10KJ-6-GP
SRN10KJ-6-GP
RN2021
RN2021
1 2 3
SRN10KJ-5-GP
SRN10KJ-5-GP
R2015
R2015
1 2
10KR2J-3-GP
10KR2J-3-GP
R2017
R2017
1 2
10KR2J-3-GP
10KR2J-3-GP
RN2009
RN2009
1 2 3
SRN10KJ-5-GP
SRN10KJ-5-GP
CLK_PCIE_LAN26
B B
3D3V_S5
A A
3D3V_S0
PCIECLKRQ1# and PCIECLKRQ2#
C2001 SCD1U10V2KX-5GPC2001 SCD1U10V2KX-5GP
1 2
C2002 SCD1U10V2KX-5GPC2002 SCD1U10V2KX-5GP
1 2
C2009 SCD1U10V2KX-5GPC2009 SCD1U10V2KX-5GP
1 2
C2010 SCD1U10V2KX-5GPC2010 SCD1U10V2KX-5GP
1 2
C2005 SCD1U10V2KX-5GPC2005 SCD1U10V2KX-5GP
1 2
C2006 SCD1U10V2KX-5GPC2006 SCD1U10V2KX-5GP
1 2
CLK_PCIE_WLAN#51 CLK_PCIE_WLAN51
CLK_PCIE_WLAN_REQ#51
CLK_PCIE_CARD#27 CLK_PCIE_CARD27
CR_CLKREQ#18,27
PCIE_CLK_REQ2#18
PCIE_CLK_LAN_REQ#26
PCIE_CLK_REQ4#
8
PCIE_CLK_REQ5#
7
PCH_GPIO57
6
PEG_B_CLKRQ#
PCIE_CLK_REQ7#
4
PCIE_CLK_REQ6#
CLK_PCIE_WLAN_REQ# BATLOW #
PVT
4
PCH_GPIO57 18
BATLOW # 15
EC_SMI# 18 EC_SCI# 18,23
RN2014
RN2014
2 3 1
Do Not Stuff
Do Not Stuff
RN2015
RN2015
1 2 3
Do Not Stuff
Do Not Stuff
RN2012
RN2012
1 2 3
Do Not Stuff
Do Not Stuff
Support S0 power only
5
4
RN
RN
RN
RN
4
RN
RN
4
PCIE_TXN1_C PCIE_TXP1_C
PCIE_TXN2_C PCIE_TXP2_C
PCIE_TXN4_C PCIE_TXP4_C
CLK_PCH_SRC0_N CLK_PCH_SRC0_P
CLK_PCH_SRC1_N CLK_PCH_SRC1_P
PCIE_CLK_REQ2#
CLK_PCH_SRC3_N CLK_PCH_SRC3_P
PCIE_CLK_REQ4#
PCIE_CLK_REQ5#
PEG_B_CLKRQ#
PCIE_CLK_REQ6#
PCIE_CLK_REQ7#
4
3
2
http://laptopblue.vn/
2 OF 10
PCH1B
PCH1B
BG34
PERN1
BJ34
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0#/GPIO73
AB49
CLKOUT_PCIE1N
AB47
CLKOUT_PCIE1P
M1
PCIECLKRQ1#/GPIO18
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
V10
PCIECLKRQ2#/GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3#/GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4#/GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5#/GPIO44
AB42
CLKOUT_PEG_B_N
AB40
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ#/GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6#/GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7#/GPIO46
AK14
CLKOUT_ITPXDP_N
AK13
CLKOUT_ITPXDP_P
COUGAR-GP-U2-NF
COUGAR-GP-U2-NF
4
Cougar
Cougar Point
Point
WLAN
Card Reader
W-WAN
LAN
USB3.0
PCI-E*
PCI-E*
Intel GBE LAN
Dock
NEW CARD
100MHZ
100MHZ
SMBUSController
SMBUSController
SML1ALERT#/PCHHOT#/GPIO74
Link
Link
PEG_A_CLKRQ#/GPIO47
100MHZ
100MHZ
CLOCKS
CLOCKS
120MHZ
CLKIN_PCILOOPBACK
CLKOUTFLEX0/GPIO64 CLKOUTFLEX1/GPIO65 CLKOUTFLEX2/GPIO66 CLKOUTFLEX3/GPIO67
FLEX CLOCKS
FLEX CLOCKS
CLKOUTFLEX0–33 MHz/14.31818 MHz/27MHz (SSC/non-SSC)/48MHz/24MHz CLKOUTFLEX1,3–14.31818 MHz/27MHz (SSC/non-SSC)/48MHz/24MHz CLKOUTFLEX2–33 MHz/ 25MHz/14.31818 MHz/27MHz (SSC/non-SSC)/48MHz/24MHz
2 OF 10
SMBALERT#/GPIO11
SMBCLK
SMBDATA
SML0ALERT#/GPIO60
SML0CLK
SML0DATA
SML1CLK/GPIO58
SML1DATA/GPIO75
CL_CLK1
CL_DATA1
CL_RST1#
CLKOUT_PEG_A_N CLKOUT_PEG_A_P
CLKOUT_DMI_N CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKIN_DMI_N CLKIN_DMI_P
CLKIN_GND1_N CLKIN_GND1_P
CLKIN_DOT_96N CLKIN_DOT_96P
CLKIN_SATA_N CLKIN_SATA_P
REFCLK14IN
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
E12 H14 C9
A12 C8 G12
C13 E14 M16
M7
T11
P10
M10
AB37 AB38
AV22 AU22
AM12 AM13
BF18 BE18
BJ30 BG30
G24 E24
AK7 AK5
K45
H45
V47 V49
Y47
K43 F47 H47 K49
3
EC_SWI# SMB_CLK SMB_DATA
DRAMRST_CNTRL_PCH SML0_CLK SML0_DATA
PCH_GPIO74 PCH_SML1_CLK PCH_SML1_DATA
CL_CLK
1
TP2001 Do Not StuffTP2001 Do Not Stuff
CL_DATA
1
TP2002 Do Not StuffTP2002 Do Not Stuff
CL_RST#
1
TP2003 Do Not StuffTP2003 Do Not Stuff
PEG_CLKREQ#_R
CLKOUT_PEG_A_N CLKOUT_PEG_A_P
CLKOUT_DMI_N CLKOUT_DMI_P
CLK_BUF_EXP_N CLK_BUF_EXP_P
CLK_BUF_CPYCLK_N CLK_BUF_CPYCLK_P
CLK_BUF_DOT96_N CLK_BUF_DOT96_P
CLK_BUF_CKSSCD_N CLK_BUF_CKSSCD_P
CLK_BUF_REF14
CLK_PCI_FB
XTAL25_IN XTAL25_OUT
XCLK_RCOMP
JTAG_TCK CLK_48_USB30 LAN_25M DGPU_PRSNT#
90D9R2F-1-GP
90D9R2F-1-GP
1 2
1 1 1
EC_SWI# 23
DIMM&W-LAN
DRAMRST_CNTRL_PCH 30
XDP
PCH_SML1_CLK 23,63 PCH_SML1_DATA 23,63
R2003
R2003
RN
RN
1 2
Do Not Stuff
Do Not Stuff
RN2016
RN2016
1
4
2 3
Do Not Stuff
Do Not Stuff
RN2010
RN2010
2 3 1
4
Do Not Stuff
Do Not Stuff
RN
RN
RN2011
RN2011
1 2 3
RN2008
RN2008
2 3 1
RN2013
RN2013
1 2 3
RN2018
RN2018
2 3 1
R2016 10KR2J-3-GPR2016 10KR2J-3-GP
1 2
need very close to PCH
CLK_PCI_FB 14
SRN10KJ-5-GP
SRN10KJ-5-GP
4
SRN10KJ-5-GP
SRN10KJ-5-GP
4
SRN10KJ-5-GP
SRN10KJ-5-GP
4
SRN10KJ-5-GP
SRN10KJ-5-GP
4
KBC
EVT
R2007
R2007
TP2007
TP2007 TP2006
TP2006 TP2005
TP2005
Do Not Stuff
Do Not Stuff Do Not Stuff
Do Not Stuff Do Not Stuff
Do Not Stuff
1D05V_VTT
PEG_CLKREQ# 60
CLK_PCIE_VGA# 60 CLK_PCIE_VGA 60
CLK_EXP_N 5 CLK_EXP_P 5
BCLK
This input has to be terminated with a 10-kOhms pull-down termination resistor in Integrated Clock generation mode.
LAN_ 25M
2
1
SMB_CLK SMB_DATA
SML0_DATA SML0_CLK
PCIE_CLK_LAN_REQ#
PCH_GPIO74 DRAMRST_CNTRL_PCH EC_SWI# PEG_CLKREQ#_R
3D3V_S0
4
RN2007
RN2007 SRN2K2J-1-GP
SRN2K2J-1-GP
1
2 3
2nd = 84.DM601.03F
3D3V_S0
SMB_DATA
PCH_SMBCLK11,12,51
3D3V_S0 3D3V_S0
12
12
EVT
XTAL25_IN
XTAL25_OUT
N12M GS2 HYN1GB
N12M GS2 HYN1GB
N12M GS2 HYN1GB
Title
Title
Title
PCH (PCI-E/SMBUS/CLOCK/CL)
PCH (PCI-E/SMBUS/CLOCK/CL)
PCH (PCI-E/SMBUS/CLOCK/CL)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Date: Sheet of
Date: Sheet of
Date: Sheet of
2nd = 84.DM601.03F
84.2N702.A3F
84.2N702.A3F
2N7002KDW-GP
2N7002KDW-GP
6 5
Q2001
Q2001
R2012
R2012 Do Not Stuff
Do Not Stuff
UMA
UMA
R2010
R2010 10KR2J-3-GP
10KR2J-3-GP
DIS
DIS
12
12
R2008 and C2008 CO-LAY
R2006
R2006 1M1R2J-GP
1M1R2J-GP
1 2
4
4
1 2 3
R2018
R2018
1 2
10KR2J-3-GP
10KR2J-3-GP R2014
R2014
1 2
10KR2J-3-GP
10KR2J-3-GP
R2004
R2004
10KR2J-3-GP
10KR2J-3-GP
R2005
R2005
DY
DY
Do Not Stuff
Do Not Stuff
EVT
1 2
SMB_CLK
34
UMA_DISCRETE# UMA: 1 1 DIS :0 1
R2013
R2013 10KR2J-3-GP
10KR2J-3-GP
R2011
R2011 Do Not Stuff
Do Not Stuff
DY
DY
PX : 0 0
UMA_DIS# DGPU_PRSNT#
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
UMA_DIS# 18
X2001
X2001 XTAL-25MHZ-113-GP
XTAL-25MHZ-113-GP
1 2
82.30020.971
82.30020.971
2nd = 82.30020.851
2nd = 82.30020.851
1
3D3V_S5
RN2003
RN2003
1
SRN2K2J-1-GP
SRN2K2J-1-GP
23
RN2004
RN2004
1
SRN2K2J-1-GP
SRN2K2J-1-GP
23
RN2006
RN2006
4
SRN10KJ-5-GP
SRN10KJ-5-GP
12
12
PCH_SMBDATA 11,12,51
C2008
C2008
12
SC12P50V2JN-3GP
SC12P50V2JN-3GP
C2007
C2007
12
SC12P50V2JN-3GP
SC12P50V2JN-3GP
16 74
16 74
16 74
-1
-1
-1
5
4
3
2
1
SSID = PCH
Functional Strap Definitions
EDS 1.0 P.89
D D
12
C2101
C2101
SC5D6P50V2CN-1GP
SC5D6P50V2CN-1GP
GPIO33
Pull-down with 1K is recommended for manufacturing environment. There is an internal pull-up of 20 k for HDA_DOCK_EN# which is only enabled at boot/reset for strapping functions.
C C
1. HDA_SDO and HDA_BCLK must be length matched to within 500 mils
2.HDA_DOCK_EN#length matched of 500 mils with HDA_BCLK.
EDS 1.0 P.92
HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used tosample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this signal on the board. Signal may have leakage paths via powered off devices (Audio Codec) and hence contend with the external pull-up. A blocking FET is recommended in such a case to isolate HDA_SYNC from the Audio Codec device until after the Strap
B B
sampling is complete.
This signal has a weak internal pull down. On Die PLL VR is supplied by 1.5V when sampled high, 1.8 V when sampled low. Needs to be pulled High for Huron River platform. co-operate with R2310
On-Die PLL Voltage Regulator Voltage Select
HDA_SYNC
NO REBOOT STRAP
Note: the internal pull-down is disabled after PLTRST# deasserts. If the signal is sampled high, this indicates that the system is strapped to the "No Reboot" mode (Cougar Point will disable the TCO Timer system reboot feature)
3D3V_S0
R2106 Do Not Stuff
R2106 Do Not Stuff
1 2
DY
DY
A A
1 2
R2101 10MR2J-L-GPR2101 10MR2J-L-GP
X2101
X2101
1
4
2 3
X-32D768KHZ-34GPU
X-32D768KHZ-34GPU
82.30001.661
82.30001.661
2ND = 82.30001.B21
2ND = 82.30001.B21
CODEC_SYNC25
Low = 1.8V (Default) High = 1.5V
HDA_SPKR
RTC_X1 RTC_X2
12
C2102
C2102 SC5D6P50V2CN-1GP
SC5D6P50V2CN-1GP
No Reboot Strap
HDA_SPKR
EDS 1.0 P.89
Intruder Detect: This signal can be set to disable system if box
detected open. This signal’s status is readable, so it can be used like a GPI if the Intruder Detection is not needed.
RTC_AUX_S5
20KR2F-L-GP
20KR2F-L-GP 20KR2F-L-GP
20KR2F-L-GP
An RC delay circuit with a time delay in the range of 18 ms to 25 ms should be provided
CODEC_SDOUT25 HDA_CODEC_RST#25,28
HDA_CODEC_BITCLK25
+3VS_HDA_IO
R2124
EVT
R2124
1 2
33R2J-2-GP
33R2J-2-GP
Low = Default High = No Reboot
Flash Descriptor Security Override/ ME Debug Mode
HDA_SDOUT
+3VS_HDA_IO
R2102 Do Not Stuff
R2102 Do Not Stuff
1 2
DY
DY
Low = Default High = Enable
HDA_SDOUT
5
EDS 1.0 P.92
R2115
R2115
1 2
R2116
R2116
1 2
EDS 1.0 P.195
12
C2103
C2103 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
http://laptopblue.vn/
INTVRMEN- Integrated SUS
1.05V VRM Enable High - Enable internal 1.05 V regulators. Low - Enable external 1.05 V regulators.
LPC_AD1_PCHLPC_AD0_PCH LPC_AD2_PCH LPC_AD3_PCH LPC_FRAME#_PCH
12
C2105
C2105
SC22P50V2JN-4GP
SC22P50V2JN-4GP
12
C2107
C2107
SC22P50V2JN-4GP
SC22P50V2JN-4GP
EDS 1.0 P.90
12
NOTE: This signal should always be pulled high
1 OF 10
1 OF 10
FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3
LPC
LPC
FWH4/LFRAME#
LDRQ0#
LDRQ1#/GPIO23
SERIRQ
SATA0RXN SATA0RXP
SATA0TXN SATA0TXP
SATA1RXN SATA1RXP
SATA 6G
SATA 6G
SATA1TXN SATA1TXP
SATA2RXN SATA2RXP
SATA2TXN SATA2TXP
SATA3RXN SATA3RXP
SATA3TXN SATA3TXP
SATA4RXN SATA4RXP
SATA4TXN
SATA
SATA
SATA4TXP
SATA5RXN SATA5RXP
SATA5TXN SATA5TXP
SATAICOMPO
SATAICOMPI
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SATALED# SATA0GP/GPIO21 SATA1GP/GPIO19
LPC_AD0_PCH LPC_AD0
C38
LPC_AD1_PCH
A38
LPC_AD2_PCH
B37
LPC_AD3_PCH
C37
LPC_FRAME#_PCH
D36 E36
K36 V5
AM3 AM1 AP7 AP5
AM10 AM8 AP11 AP10
AD7 AD5 AH5 AH4
AB8 AB10 AF3 AF1
Y7 Y5 AD3 AD1
Y3 Y1 AB3 AB1
Y11 Y10
AB12 AB13
AH1
The SATALED# signal is open-collector and requires a weak external pull-up (8.2 k to10 k ) to Vcc3_3.
P3 V14 P1
C2104
C2104
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
R2125
R2125
1 2
33R2J-2-GP
33R2J-2-GP
2 3 1
RN2102
RN2102
SRN33J-5-GP-U
SRN33J-5-GP-U
R2103
R2103 1KR2J-1-GP
1KR2J-1-GP
1 2
HDA_SYNC
RTC_X1 RTC_X2
TP2105Do Not Stuff TP2105Do Not Stuff
RTC_RST# SRTC_RST# SM_INTRUDER#
12
PCH_INTVRMEN
HDA_BITCLK HDA_SYNC
HDA_RST#
HDA_SDOUT
12
4
21
G2101
G2101
DY
DY
Do Not Stuff
Do Not Stuff
HDA_SDOUT HDA_RST#
HDA_BITCLK
ME_UNLOCK23
RTC_AUX_S5
48 kHz fixed rate
HDA_SPKR25
HDA_SDIN025
Can be left NO CONNECT if not used (internal pull-down resistors that are always enabled).
R2104
R2104
1M1R2J-GP
1M1R2J-GP
R2105
R2105
1 2
330KR2F-L-GP
330KR2F-L-GP
R2107
R2107
1 2
1KR2J-1-GP
1KR2J-1-GP
This can be left unconnected when not in use.
R2108
R2108
R2109
R2109
R2110
R2110
PCH_JTAG_TCK_BUF
1
PCH_JTAG_TMS
1
PCH_JTAG_TDI
1
PCH_JTAG_TDO
1
PCH_SPI_CLK PCH_SPI_CS0#
PCH_SPI_SI
R2122
R2122
1 2
DY
DY
Do Not Stuff
Do Not Stuff R2123
R2123
1 2
DY
DY
Do Not Stuff
Do Not Stuff
SPI_CLK_R23,48 SPI_CS0#_R23,48
SPI_SI_R23,48
SPI_SO_R23,48
BBS_BIT1 BBS_BIT0
TP2101Do Not Stuff TP2101Do Not Stuff TP2102Do Not Stuff TP2102Do Not Stuff TP2103Do Not Stuff TP2103Do Not Stuff TP2104Do Not Stuff TP2104Do Not Stuff
1 2
33R2J-2-GP
33R2J-2-GP
1 2
33R2J-2-GP
33R2J-2-GP
1 2
33R2J-2-GP
33R2J-2-GP
BBS_BIT1 14
1-k to 2.2-k pulldown
BOOT BIOS Strap
PCH_GPIO33
1
PCH1A
PCH1A
A20
RTCX1
C20
RTCX2
D20
RTCRST#
G22
SRTCRST#
K22
INTRUDER#
C17
INTVRMEN
N34
HDA_BCLK
L34
HDA_SYNC
internal pull down
T10
SPKR
internal pull down
K34
HDA_RST#
E34
HDA_SDIN0
G34
HDA_SDIN1
internal pull down
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
internal pull down
C36
HDA_DOCK_EN#/GPIO33
internal pull UP
N32
HDA_DOCK_RST#/GPIO13
defaults GPIO13
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
Y14
SPI_CS0#
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
COUGAR-GP-U2-NF
COUGAR-GP-U2-NF
EVT
Cougar
Cougar Point
Point
24MHz
RTCIHDA
RTCIHDA
JTAG
JTAG
SPI
SPI
internal pull-up
GNT1#/GPIO51 BOOT BIOS LocationSATA1GP/GPIO19
0 0 LPC 0 1 Reserved
Reserved 01
11
4
SPI(Default)
3
PCH_JTAG_TCK_BUF
R2121 4K7R2J-2-GPR2121 4K7R2J-2-GP
1 2
2
12
C2109
C2108
C2108
C2109
PVT
SC22P50V2JN-4GP
SC22P50V2JN-4GP
SC22P50V2JN-4GP
SC22P50V2JN-4GP
PVT
R2127 47R2J-2-GPR2127 47R2J-2-GP
1 2
R2128 47R2J-2-GPR2128 47R2J-2-GP
1 2
R2129 47R2J-2-GPR2129 47R2J-2-GP
1 2
R2130 47R2J-2-GPR2130 47R2J-2-GP
1 2
R2126 0R2J-2-GPR2126 0R2J-2-GP
1 2
internal pull Up
INT_SERIRQ 23
Place the resistor within 500 mils of the PCH
SATA_COMP
SATA3_COMP
RBIAS_SATA3
SATA_DET#0 BBS_BIT0
R2112 37D4R2F-GPR2112 37D4R2F-GP
1 2
R2113 49D9R2F-GPR2113 49D9R2F-GP
1 2
R2114 750R2F-GPR2114 750R2F-GP
1 2
SATA_LED# 52
N12M GS2 HYN1GB
N12M GS2 HYN1GB
N12M GS2 HYN1GB
Title
Title
Title
PCH (SPI/RTC/LPC/SATA/IHDA)
PCH (SPI/RTC/LPC/SATA/IHDA)
PCH (SPI/RTC/LPC/SATA/IHDA)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Date: Sheet of
Date: Sheet of
Date: Sheet of
12
DY
DY
LPC_AD1 LPC_AD2 LPC_AD3
SATA_LED# SATA_DET#0
C2110
C2110
Do Not Stuff
Do Not Stuff
PCH_SPI_CS0#
Do Not Stuff
Do Not Stuff
12
LPC_AD[0..3]
LPC_FRAME# 23,55
SATA_RXN0 45 SATA_RXP0 45 SATA_TXN0 45 SATA_TXP0 45
INT_SERIRQ
1D05V_VTT
1D05V_VTT
2 3 1
SRN10KJ-5-GP
SRN10KJ-5-GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
1
R2111
R2111
1 2
10KR2J-3-GP
10KR2J-3-GP
SATA_RXN4 45 SATA_RXP4 45 SATA_TXN4 45 SATA_TXP4 45
pull-up to VCCIO
RN2103
RN2103
4
17 74
17 74
17 74
EC2104
EC2104
DY
DY
LPC_AD[0..3] 23,55
HDD1
3D3V_S0
ODD
3D3V_S0
-1
-1
-1
5
Integrated Clock Chip Enable
HIGH (R2211 DY)- DISABLED [DEFAULT]
ICC_EN# LOW (R2211)- ENABLED
GPIO8 has a weak[20K] internal pull up.
Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable.
D D
R2205
1 2
DY
DY
Do Not Stuff
Do Not Stuff
R2205
CKLIST P.66
Deep Sleep
GPIO27
GPIO27 has a weak[20K] internal pull up.
If not used then use 8.2-k to 10-k pull-down to GND.
The On-Die PLL voltage regulator
C C
ENABLED -- HIGH (R2212 UNSTUFFED) DEFAULT DISABLED -- LOW (R2212 STUFFED)
HIGH (R2019 DY)- ENABLED [DEFAULT] LOW (R2019) - DISABLED
PLL_ODVR_EN
R2212
R2212
1 2
DY
DY
Do Not Stuff
Do Not Stuff
NOTE:This signal has a weak internal pull-up 20K
If not used, 8.2-k to 10-k pull-up to +V3.3A power-rail.
RN2202
PCH_GPIO38
PCIE_CLK_REQ2#16
CR_CLKREQ#16,27
PCIE_CLK_REQ2# CR_CLKREQ# PCH_GPIO48
3D3V_S0
EVT
3D3V_S5
B B
3D3V_S0
Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable. This signal has a weak internal pull-down. NOTE: The internal pull-down is disabled after PLTRST# deasserts. NOTE: This signal should not be pulled high when strap is sampled.
A A
SRN10KJ-5-GP
SRN10KJ-5-GP
1KR2J-1-GP
1KR2J-1-GP
3D3V_S0
RN2204
RN2204
1 2 3
R2201
R2201
R2209
R2209
1 2
Do Not Stuff
Do Not Stuff
R2210
R2210
1 2
10KR2J-3-GP
10KR2J-3-GP
4
4
5
PCH_GPIO12
4
PCH_GPIO24
PCH_GPIO15
12
DY
DY
RN2201
RN2201
SRN10KJ-5-GP
SRN10KJ-5-GP
RN2206
RN2206
SRN10KJ-5-GP
SRN10KJ-5-GP
PCH_GPIO6
1
PCH_TEMP_ALERT#
23
PCH_GPIO22
1
PCH_GPIO0
23
1 2 3 4 5 6
DMI_OVRVLTG
PVT
RN2202
SRN10KJ-L3-GP
SRN10KJ-L3-GP
10 9 8 7
PSW_CLR# PCH_GPIO16 PCH_GPIO17 PCH_GPIO39
DMI TERMINATION VOLTAGE OVERRIDE GPIO36
(DMI_OVRVLTG)
4
3
2
SSID = PCH
http://laptopblue.vn/
If not used, 8.2 to 10-k pull-up to VccSuS3_3 (+V3.3A) OR pull-down to GND
3D3V_S0
LOW - Tx, Rx terminated to same voltage (DC Coupling Model DEFAULT)
Note: For PCH debug with XDP, need to NO STUFF R2218
Do Not Stuff
Do Not Stuff Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
PCH_TEMP_ALERT#23
4
EVT
EC_SCI#16,23
21
R2211
R2211
12
1KR2J-1-GP
1KR2J-1-GP
TP2202
TP2202
1
TP2203
TP2203
1
PSW_CLR#
If not used Can be NC
DY
DY
G2201
G2201
PCH_GPIO5716
TP726Do Not Stuff TP726Do Not Stuff TP727Do Not Stuff TP727Do Not Stuff
EC_SMI# PCH_GPIO6 EC_SCI# ICC_EN# PCH_GPIO12 PCH_GPIO15
PCH_GPIO16
PCH_GPIO17 PCH_GPIO22 PCH_GPIO24 PCH_GPIO27 PLL_ODVR_EN
DMI_OVRVLTG FDI_OVRVLTG PCH_GPIO38 PCH_GPIO39 PCH_GPIO48
PCH_GPIO57
PCH_CORNER7
1
PCH_CORNER8
1
PCH_GPIO0
PCH1F
PCH1F
T7
BMBUSY#/GPIO0
A42
TACH1/GPIO1
H36
TACH2/GPIO6
E38
TACH3/GPIO7
C10
GPIO8
C4
LAN_PHY_PWR_CTRL/GPIO12
G2
GPIO15
U2
SATA4GP/GPIO16
D40
TACH0/GPIO17
T5
SCLOCK/GPIO22
E8
GPIO24/MEM_LED
E16
GPIO27
P8
GPIO28
K1
STP_PCI#/GPIO34
K4
GPIO35
V8
SATA2GP/GPIO36
M5
SATA3GP/GPIO37
N2
SLOAD/GPIO38
M3
SDATAOUT0/GPIO39
V13
SDATAOUT1/GPIO48
V3
SATA5GP/GPIO49
D6
GPIO57
A4
NCTF_VSS#A4
A44
NCTF_VSS#A44
A45
NCTF_VSS#A45
A46
NCTF_VSS#A46
A5
NCTF_VSS#A5
A6
NCTF_VSS#A6
B3
NCTF_VSS#B3
B47
NCTF_VSS#B47
BD1
NCTF_VSS#BD1
BD49
NCTF_VSS#BD49
BE1
NCTF_VSS#BE1
BE49
NCTF_VSS#BE49
BF1
NCTF_VSS#BF1
BF49
NCTF_VSS#BF49
COUGAR-GP-U2-NF
COUGAR-GP-U2-NF
3
6 OF 10
6 OF 10
PCH_GPIO68
A20GATE
PECI
RCIN#
INIT3_3V#
TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4
NC_1
R2222
R2222
Do Not Stuff
Do Not Stuff
R2223
R2223
10KR2J-3-GP
10KR2J-3-GP
C40
UMA_DIS#
B41
VRAM_SIZE1
C41
VRAM_SIZE2
A40
P4
H_PECI_R
AU16 P5 AY11
PCH_THERMTRIP_R
AY10
INIT3_3V#
T14
TS_VSS
AH8 AK11 AH10 AK10 P37
PCH_CORNER1
BG2
PCH_CORNER2
BG48
PCH_CORNER3
BH3
PCH_CORNER4
BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6
PCH_CORNER5
C2
PCH_CORNER6
C48 D1 D49 E1 E49 F1 F49
1 2
Do Not Stuff
Do Not Stuff
FDI_OVRVLTG
Cougar
Cougar Point
Point
NCTF TEST PIN:
NCTF TEST PIN:
A4,A44,A45,A46,A5,A6,B3,B47,BD1,BD49,BE1,BE49,BF1,BF49
A4,A44,A45,A46,A5,A6,B3,B47,BD1,BD49,BE1,BE49,BF1,BF49
BG2,BG48,BH3,BH47,BJ4,BJ44,BJ45,BJ46,BJ5,BJ6,C2,C48
BG2,BG48,BH3,BH47,BJ4,BJ44,BJ45,BJ46,BJ5,BJ6,C2,C48
TACH4/GPIO68 TACH5/GPIO69 TACH6/GPIO70 TACH7/GPIO71
PROCPWRGD
NCTF
NCTF
D1,D49,E1,E49,F1,F49
D1,D49,E1,E49,F1,F49
3D3V_S0
CPU/MISC
CPU/MISC
THRMTRIP#
NCTF_VSS#BG2
NCTF_VSS#BG48
NCTF_VSS#BH3
NCTF_VSS#BH47
NCTF_VSS#BJ4 NCTF_VSS#BJ44 NCTF_VSS#BJ45 NCTF_VSS#BJ46
NCTF_VSS#BJ5
NCTF_VSS#BJ6
NCTF_VSS#C2
NCTF_VSS#C48
NCTF_VSS#D1
NCTF_VSS#D49
NCTF_VSS#E1
NCTF_VSS#E49
NCTF_VSS#F1
NCTF_VSS#F49
1 2
DY
DY
1 2
GPIO
GPIO
This signal has a weak internal pull-down. NOTE: The internal pull-down is disabled after PLTRST# deasserts. NOTE: This signal should not be pulled high when strap is sampled.
R2219
R2219
1
PCH_GPIO68 14
UMA_DIS# 16EC_SMI#16
R2203
R2203
1 2
DY
DY
Do Not Stuff
Do Not Stuff
TP2201
TP2201
This signal has a weak internal pull-up. Note: The internal pull-up is disabled after PLTRST# deasserts. NOTE: This signal should not be pulled low. Leave as "No Connect".
TS Signal Disable Guideline: TS_VSS1, TS_VSS2, TS_VSS3 and TS_VSS4 should not float on the motherboard. They should be tied to GND directly.
1 1 1 1
PCH_THERMTRIP_R
1 1
2
H_A20GATE 23
H_RCIN# 23
H_CPUPW RGD 5,69
DY
DY
R2204 Do Not Stuff
R2204 Do Not Stuff
1 2
Do Not Stuff
Do Not Stuff
TP720 Do Not StuffTP720 Do Not Stuff TP721 Do Not StuffTP721 Do Not Stuff TP722 Do Not StuffTP722 Do Not Stuff TP723 Do Not StuffTP723 Do Not Stuff
1 2
56R2J-4-GP
56R2J-4-GP
TP724 Do Not StuffTP724 Do Not Stuff TP725 Do Not StuffTP725 Do Not Stuff
H_PECI 5,23
DVT
R2202
R2202
20101029
1D05V_VTT
FDI TERMINATION VOLTAGE OVERRIDE
GPIO37 (FDI_OVRVLTG)
LOW - Tx, Rx terminated to same voltage (DC Coupling Model DEFAULT)
N12M GS2 HYN1GB
N12M GS2 HYN1GB
N12M GS2 HYN1GB
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
[VRAM_SIZE1:VRAM_SIZE2] LL=512M / HL=1G / LH=2G
3D3V_S0
12
R2214
R2214 Do Not Stuff
Do Not Stuff
VRAM 2G
VRAM 2G
VRAM_SIZE1 VRAM_SIZE2PCH_GPIO27
H_THERMTRIP# 5,22
PCH (GPIO/CPU)
PCH (GPIO/CPU)
PCH (GPIO/CPU)
12
R2215
R2215 10KR2J-3-GP
10KR2J-3-GP
VRAM 512M&1G
VRAM 512M&1G
Core power :3D3V_S0 Core power :3D3V_S0
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
1
12
12
18 74
18 74
18 74
R2216
R2216 Do Not Stuff
Do Not Stuff
VRAM 1G
VRAM 1G
R2217
R2217 10KR2J-3-GP
10KR2J-3-GP
VRAM 512M
VRAM 512M
-1
-1
-1
5
4
3
2
1
SSID = PCH
D D
(10uFx1_0603)
(1uF x4)
C C
B B
6A
1D05V_VTT
(1uFx3)
1D05V_VTT
2.925A(Total current of VCCIO)
12
C2305
C2305
0.266A (Totally VCC3_3 current)
0.159A(Totally current of VCCVRM)
1D5V_S0
0.042A (Totally current of VCCDMI)
1.3A
12
C2301
C2301
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C2306
C2306
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
(0.1uF x1)
68.00082.001
68.00082.001
C2302
C2302
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C2307
C2307
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
1D05V_VTT
1
12
3D3V_S0
C2303
C2303
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
VCCAPLLEXP
(10uF x1)
C2308
C2308
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
TP2301Do Not Stuff TP2301Do Not Stuff
12
DVT
L2304
L2304
1 2
BLM11A121S-GP
BLM11A121S-GP
CHIP BEAD BLM18AG121SN1D
CHIP BEAD BLM18AG121SN1D
TP2302Do Not Stuff TP2302Do Not Stuff
1D05V_VTT
1
VCCFDIPLL
+1.05VS_VCC_DMI
http://laptopblue.vn/
(0.1uF/0.01uF x1)
12
C2304
C2304
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
C2309
C2309
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C2310
C2310 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
VCCAFDI_VRM
PCH1G
PCH1G
AA23
VCCCORE
AC23
VCCCORE
AD21
VCCCORE
AD23
VCCCORE
AF21
VCCCORE
AF23
VCCCORE
AG21
VCCCORE
AG23
VCCCORE
AG24
VCCCORE
AG26
VCCCORE
AG27
VCCCORE
AG29
VCCCORE
AJ23
VCCCORE
AJ26
VCCCORE
AJ27
VCCCORE
AJ29
VCCCORE
AJ31
VCCCORE
AN19
VCCIO
BJ22
VCCAPLLEXP
AN16
VCCIO
AN17
VCCIO
AN21
VCCIO
AN26
VCCIO
AN27
VCCIO
AP21
VCCIO
AP23
VCCIO
AP24
VCCIO
AP26
VCCIO
AT24
VCCIO
AN33
VCCIO
AN34
VCCIO
BH29
VCC3_3
AP16
VCCVRM
BG6
VCCAFDIPLL
AP17
VCCIO
AU20
VCCDMI
COUGAR-GP-U2-NF
COUGAR-GP-U2-NF
POWER
POWER
Cougar
Cougar Point
Point
VCC CORE
VCC CORE
VCCIO
VCCIO
FDI
FDI
CRTLVDS
CRTLVDS
DMI
DMI
NAND / SPI HVCMOS
NAND / SPI HVCMOS
7 OF 10
7 OF 10
VCCADAC
VSSADAC
VCCALVDS
VSSALVDS
VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS
VCC3_3
VCC3_3
VCCVRM
VCCDMI
VCCCLKDMI
VccDFTERM
VccDFTERM
VccDFTERM
VccDFTERM
VCCSPI
U48
U47
+3VS_VCCA_LVDS
AK36 AK37
AM37 AM38 AP36 AP37
V33
V34
AT16
+1.05VS_VCC_DMI
AT20
SC4D7U6D3V2MX-GP
SC4D7U6D3V2MX-GP
AB36
+1.05VS_VCC_DMI_CCI
AG16
AG17
AJ16
AJ17
V1
(1uFx1)
(10uF x1_0603)
VCCADAC_3D3V
12
C2313
C2313
UMA
UMA
Do Not Stuff
Do Not Stuff
R2303
R2303
1 2
DIS
DIS
0R2J-2-GP
0R2J-2-GP
+1.8VS_VCCTX_LVDS
12
R2309
R2309 0R2J-2-GP
0R2J-2-GP
DIS
DIS
12
C2319
C2319
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C2320
C2320
12
C2321
C2321
SC4D7U6D3V2MX-GP
SC4D7U6D3V2MX-GP
12
C2322
C2322 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
0.02A
12
C2323
C2323 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
12
C2314
C2314
UMA
UMA
0.06A
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
12
C2316
C2316
UMA
UMA
(0.1uFx1)
VCCAFDI_VRM
BLM11A121S-GP
12
C2324
C2324
12
C2325
C2325 SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
BLM11A121S-GP
CHIP BEAD BLM18AG121SN1D
CHIP BEAD BLM18AG121SN1D
SC4D7U6D3V2MX-GP
SC4D7U6D3V2MX-GP
BLM11A121S-GP
BLM11A121S-GP
CHIP BEAD BLM18AG121SN1D
CHIP BEAD BLM18AG121SN1D
PVT
0.19A
12
C2315
C2315
UMA
UMA
0.001A
Do Not Stuff
Do Not Stuff
12
1 2
68.00082.001
68.00082.001
1 2
68.00082.001
68.00082.001
12
C2317
C2317
UMA
UMA
C2318
C2318
UMA
UMA
3D3V_S0
L2302
L2302
L2303
L2303
0.02A
+V_NVRAM_VCCQ 1D8V_S0
VCCSPI
The same BIOS SPI ROM power
1 2
UMA
UMA
Do Not Stuff
Do Not Stuff
1 2
UMA
UMA
Do Not Stuff
Do Not Stuff
1 2
UMA
UMA
1D05V_VTT
1D05V_VTT
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
L2301
L2301
R2305
R2305 Do Not Stuff
Do Not Stuff
R2308
R2308
(0.1uFx1) (0.1uFx1)
R2313
R2313 R2314
R2314
DY
DY
R2301
R2301
1 2
DIS
DIS
0R2J-2-GP
0R2J-2-GP
3D3V_DAC_S0
3D3V_S0
R2304
R2304
1D8V_S0
(0.01uF x2) (22uF x1)
12
12 12
Do Not Stuff
Do Not Stuff
3D3V_S0
R2312
R2312
1 2
DY
DY
Do Not Stuff
Do Not Stuff
3.3V CRT LDO
5V_S0 3D3V_DAC_S0
Do Not Stuff
Do Not Stuff
12
C2311
C2311
UMA
UMA
3D3V_S5 3D3V_S0
U2301
U2301
UMA
UMA
1
VIN
2
VOUT GND EN3NC#4
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
2nd = 74.09198.G7F
2nd = 74.09198.G7F
5 4
Do Not Stuff
Do Not Stuff
12
C2312
C2312
UMA
UMA
A A
5
4
3
2
N12M GS2 HYN1GB
N12M GS2 HYN1GB
N12M GS2 HYN1GB
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Date: Sheet of
Date: Sheet of
Date: Sheet of
PCH (POWER1)
PCH (POWER1)
PCH (POWER1)
19 74
19 74
19 74
1
-1
-1
-1
5
SSID = PCH
3D3V_S0
D D
R2401
R2401
1 2
DY
DY
Do Not Stuff
Do Not Stuff
L2401
L2401
1 2
IND-10UH-218-GP
IND-10UH-218-GP
Do Not Stuff
Do Not Stuff
(10uFx1) (1uFx1)
12
C2401
C2401
DY
DY
+V3.3S_VCC_CLKF33
SC1U10V2KX-1GP
SC1U10V2KX-1GP
12
C2402
C2402
EVT
1D05V_VTT
(22uFx2_0603) (1uFx3)
C C
1D05V_VTT
L2402
L2402
1 2
IND-10UH-218-GP
IND-10UH-218-GP
ST220U2VBM-3GP
ST220U2VBM-3GP
77.C2271.26L
77.C2271.26L
2nd = 77.22271.18L
2nd = 77.22271.18L
L2403
L2403
1 2
IND-10UH-218-GP
IND-10UH-218-GP
77.C2271.26L
77.C2271.26L
2nd = 77.22271.18L
2nd = 77.22271.18L
B B
1D05V_VTT
R2404
R2404
12
Do Not Stuff
Do Not Stuff
1D05V_VTT
R2405
R2405
12
Do Not Stuff
Do Not Stuff
A A
(1uFx1)
0.08A
(220uFx1)
+1.05VS_VCCA_A_DPL
12
TC2401
TC2401
0.08A
+1.05VS_VCCA_B_DPL
12
TC2402ST220U2VBM-3GP
TC2402ST220U2VBM-3GP
+VCCDIFFCLK
12
C2412
C2412
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
+V1.05S_SSCVCC
12
C2413
C2413
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
5
12
C2409
C2409 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
(1uFx1) (220uFx1)
12
C2410
C2410 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
3D3V_S5
(0.1uFx1)
1.01A (Total current of VCCASW)
12
DY
DY
C2403
C2403
Do Not Stuff
Do Not Stuff
C2411
C2411
12
C2404
C2404
12
(0.1uFx1)
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
+VCCRTCEXT
EVT
(0.1uFx1)
(1uFx1)
1D05V_VTT
0.001A
(0.1uFx2) (4.7uFx1_0603)
Do Not Stuff
Do Not Stuff
RTC_AUX_S5
6uA
4
TP2401Do Not Stuff TP2401Do Not Stuff
1
http://laptopblue.vn/
R2403
R2403
1 2
Do Not Stuff
Do Not Stuff
TP2405Do Not Stuff TP2405Do Not Stuff
TP2404Do Not Stuff TP2404Do Not Stuff
1
(10uFx1)
1D05V_VTT
TP2402Do Not Stuff TP2402Do Not Stuff
1
12
DY
DY
12
C2407
C2407
C2406
C2406
Do Not Stuff
Do Not Stuff
VCCACLK
0.002A
+VCCPDSW
DCPSUSBYP
1
+V3.3S_VCC_CLKF33
+VCCAPLL_CPY_PCH
+VCCSUS1
12
C2408
C2408
DY
DY
Do Not Stuff
Do Not Stuff
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
0.16A (Totally current of VCCVRM
1D5V_S0
+1.05VS_VCCA_A_DPL +1.05VS_VCCA_B_DPL
C2417
C2417
DY
DY
1D05V_VTT
12
C2414
C2414
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C2420
C2420
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
4
(1uFx1)
0.095A
C2415
C2415
12
TP2406Do Not Stuff TP2406Do Not Stuff
12
C2418
C2418
12
C2421
C2421 Do Not Stuff
Do Not Stuff
DY
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
+VCCDIFFCLK
0.055A
+V1.05S_SSCVCC
(1uFx1)
+VCCSST
DCPSUS
1
12
C2419
C2419
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
PCH1J
PCH1J
AD49
VCCACLK
T16
VCCDSW3_3
V12
DCPSUSBYP
T38
VCC3_3
BH23
VCCAPLLDMI2
AL29
VCCIO
AL24
DCPSUS
AA19
VCCASW
AA21
VCCASW
AA24
VCCASW
AA26
VCCASW
AA27
VCCASW
AA29
VCCASW
AA31
VCCASW
AC26
VCCASW
AC27
VCCASW
AC29
VCCASW
AC31
VCCASW
AD29
VCCASW
AD31
VCCASW
W21
VCCASW
W23
VCCASW
W24
VCCASW
W26
VCCASW
W29
VCCASW
W31
VCCASW
W33
VCCASW
N16
DCPRTC
Y49
VCCVRM
BD47
VCCADPLLA
BF47
VCCADPLLB
AF17
VCCIO
AF33
VCCDIFFCLKN
AF34
VCCDIFFCLKN
AG34
VCCDIFFCLKN
AG33
VCCSSC
V16
DCPSST
T17
DCPSUS
V19
DCPSUS
BJ8
V_PROC_IO
A22
VCCRTC
COUGAR-GP-U2-NF
COUGAR-GP-U2-NF
This rail needs to be connected to the +V3.3A power-rail or +V1.5A power-rail. Note: On CRB, +V3.3A power-rail is used as default (V3.3A_1.5A_HDA_IO). Also a 0.1-µF capacitor is required close the PCH ball.
3
POWER
POWER
Cougar
Cougar Point
Point
Clock and Miscellaneous
Clock and Miscellaneous
CPURTC
CPURTC
3
PCI/GPIO/LPCMISC
PCI/GPIO/LPCMISC
SATA USB
SATA USB
HDA
HDA
10 OF 10
10 OF 10
VCCIO VCCIO VCCIO VCCIO VCCIO
VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3
VCCIO
V5REF_SUS
DCPSUS
VCCSUS3_3
V5REF
VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3
VCC3_3 VCC3_3 VCC3_3
VCC3_3
VCCIO
VCCIO VCCIO
VCCIO
VCCAPLLSATA
VCCVRM
VCCIO VCCIO VCCIO
VCCASW
VCCASW
VCCASW
VCCSUSHDA
N26 P26 P28 T27 T29
0.097A (Totally current of VCCSUS3_3)
T23 T24 V23 V24 P24
T26
M26
AN23 AN24
P34
N20 N22 P20 P22
AA16 W16 T34
AJ2
AF13
AH13 AH14
AF14 AK1
AF11
AC16 AC17 AD17
T21
V21
T19
P32
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
(0.1uFx1)
1D05V_VTT
+5VA_PCH_VCC5REFSUS
+VCCA_USBSUS +V3.3A_VCCPSUS
+5VS_PCH_VCC5REF
+V3.3A_VCCPSUS
+V1.05S_VCCAPLL_SATA3
+V1.05S_VCC_SATA
1D05V_VTT
+3VS_HDA_IO
0.01A
12
C2433
C2433
12
C2430
C2430 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C2429
C2429 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C2432
C2432 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1D5V_S0
R2409
R2409
1 2
Do Not Stuff
Do Not Stuff
LOW POWER MODE
close the PCH
2
12
C2423
C2423
12
C2424
C2424 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C2425
C2425 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
12
C2437
C2437 Do Not Stuff
Do Not Stuff
12
C2428
C2428 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
C2434
C2434 Do Not Stuff
Do Not Stuff
12
C2435
C2435 SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
2
1D05V_VTT
(1uFx1)
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
3D3V_S5
(0.1uFx1)
3D3V_S5
(0.1uFx1)
0.001A
DVT
DY
DY
0.001A
R2410
R2410
1 2
Do Not Stuff
Do Not Stuff
12
C2431
C2431 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
(0.1uFx1)
(1uFx1)
R2411
R2411
1 2
DY
DY
Do Not Stuff
Do Not Stuff
DY
DY
R2412
R2412
1 2
Do Not Stuff
Do Not Stuff
3D3V_S5
1
3D3V_S5
(1uFx1)
3D3V_S0
3D3V_S5
83.R2004.B8F
83.R2004.B8F
2nd = 83.R0304.D8F
2nd = 83.R0304.D8F
RB751V-40-2-GP
RB751V-40-2-GP D2401
D2401
K A
12
C2426
C2426 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
3D3V_S0
83.R2004.B8F
83.R2004.B8F
2nd = 83.R0304.D8F
2nd = 83.R0304.D8F
RB751V-40-2-GP
RB751V-40-2-GP D2402
D2402
K A
12
C2427
C2427 SC1U10V2KX-1GP
SC1U10V2KX-1GP
R2408
R2408
1 2
10R2J-2-GP
10R2J-2-GP
1 2
10R2J-2-GP
10R2J-2-GP
R2407
R2407
5V_S5
(0.1uFx1)
5V_S0
(1uFx1)
(0.1uFx2)
3D3V_S0
1D05V_VTT
1D05V_VTT
(10uFx1)
1D05V_VTT
(1uFx1)
N12M GS2 HYN1GB
N12M GS2 HYN1GB
N12M GS2 HYN1GB
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Date: Sheet of
Date: Sheet of
Date: Sheet of
PCH (POWER2)
PCH (POWER2)
PCH (POWER2)
20 74
20 74
20 74
1
-1
-1
-1
5
4
3
2
1
SSID = PCH
http://laptopblue.vn/
D D
C C
B B
A A
5
PCH1H
PCH1H
H5
VSS
AA17
VSS
AA2
VSS
AA3
VSS
AA33
VSS
AA34
VSS
AB11
VSS
AB14
VSS
AB39
VSS
AB4
VSS
AB43
VSS
AB5
VSS
AB7
VSS
AC19
VSS
AC2
VSS
AC21
VSS
AC24
VSS
AC33
VSS
AC34
VSS
AC48
VSS
AD10
VSS
AD11
VSS
AD12
VSS
AD13
VSS
AD19
VSS
AD24
VSS
AD26
VSS
AD27
VSS
AD33
VSS
AD34
VSS
AD36
VSS
AD37
VSS
AD38
VSS
AD39
VSS
AD4
VSS
AD40
VSS
AD42
VSS
AD43
VSS
AD45
VSS
AD46
VSS
AD8
VSS
AE2
VSS
AE3
VSS
AF10
VSS
AF12
VSS
AD14
VSS
AD16
VSS
AF16
VSS
AF19
VSS
AF24
VSS
AF26
VSS
AF27
VSS
AF29
VSS
AF31
VSS
AF38
VSS
AF4
VSS
AF42
VSS
AF46
VSS
AF5
VSS
AF7
VSS
AF8
VSS
AG19
VSS
AG2
VSS
AG31
VSS
AG48
VSS
AH11
VSS
AH3
VSS
AH36
VSS
AH39
VSS
AH40
VSS
AH42
VSS
AH46
VSS
AH7
VSS
AJ19
VSS
AJ21
VSS
AJ24
VSS
AJ33
VSS
AJ34
VSS
AK12
VSS
AK3
VSS
COUGAR-GP-U2-NF
COUGAR-GP-U2-NF
Cougar
Cougar Point
Point
8 OF 10
8 OF 10
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28
4
PCH1I
PCH1I
AY4
VSS
AY42
VSS
AY46
VSS
AY8
VSS
B11
VSS
B15
VSS
B19
VSS
B23
VSS
B27
VSS
B31
VSS
B35
VSS
B39
VSS
B7
VSS
F45
VSS
BB12
VSS
BB16
VSS
BB20
VSS
BB22
VSS
BB24
VSS
BB28
VSS
BB30
VSS
BB38
VSS
BB4
VSS
BB46
VSS
BC14
VSS
BC18
VSS
BC2
VSS
BC22
VSS
BC26
VSS
BC32
VSS
BC34
VSS
BC36
VSS
BC40
VSS
BC42
VSS
BC48
VSS
BD46
VSS
BD5
VSS
BE22
VSS
BE26
VSS
BE40
VSS
BF10
VSS
BF12
VSS
BF16
VSS
BF20
VSS
BF22
VSS
BF24
VSS
BF26
VSS
BF28
VSS
BD3
VSS
BF30
VSS
BF38
VSS
BF40
VSS
BF8
VSS
BG17
VSS
BG21
VSS
BG33
VSS
BG44
VSS
BG8
VSS
BH11
VSS
BH15
VSS
BH17
VSS
BH19
VSS
H10
VSS
BH27
VSS
BH31
VSS
BH33
VSS
BH35
VSS
BH39
VSS
BH43
VSS
BH7
VSS
D3
VSS
D12
VSS
D16
VSS
D18
VSS
D22
VSS
D24
VSS
D26
VSS
D30
VSS
D32
VSS
D34
VSS
D38
VSS
D42
VSS
D8
VSS
E18
VSS
E26
VSS
G18
VSS
G20
VSS
G26
VSS
G28
VSS
G36
VSS
G48
VSS
H12
VSS
H18
VSS
H22
VSS
H24
VSS
H26
VSS
H30
VSS
H32
VSS
H34
VSS
F3
VSS
COUGAR-GP-U2-NF
COUGAR-GP-U2-NF
3
Cougar
Cougar Point
Point
9 OF 10
9 OF 10
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28
N12M GS2 HYN1GB
N12M GS2 HYN1GB
N12M GS2 HYN1GB
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
PCH (VSS)
PCH (VSS)
PCH (VSS)
21 74
21 74
21 74
1
-1
-1
-1
5
D D
R2613
IMVP_PWRGD29,35
THERM_SYS_SHDN#24
C C
G680_RST#15
B B
S0_PWR_GOOD15,23,29,35,44
R2613 Do Not Stuff
Do Not Stuff
DY
DY
2nd = 84.00610.C31
2nd = 84.00610.C31
3D3V_AUX_S5
3D3V_S0
DY
DY
Do Not Stuff
Do Not Stuff R2614
R2614
1 2
IMVP_PWRGD_RG
12
2ND = 84.2N702.J31
2ND = 84.2N702.J31
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
DY
DY
12
R2602
R2602 Do Not Stuff
Do Not Stuff
DY
DY
G
H_THERMTRIP#5,18
3D3V_AUX_S5
G
Q2603
Q2603
S D
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
R2617
R2617
1 2
0R2J-2-GP
0R2J-2-GP
2 1
CH551H-30PT-GP
CH551H-30PT-GP
83.R5003.C8F
83.R5003.C8F
2nd = 83.5R003.08F
2nd = 83.5R003.08F
Q2607
Q2607
SD
G
Q2610
Q2610 Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
2ND = 84.2N702.J31
2ND = 84.2N702.J31
DY
DY
S D
3
D2604
D2604 Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
2ND = 83.BAT54.D81
2ND = 83.BAT54.D81
3rd = 83.BAT54.S81
3rd = 83.BAT54.S81
DY
DY
PURE_HW_SHUTDOWN#
D2607
D2607
D2606
D2606
DY
DY
2 1
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
2nd = 83.5R003.08F
2nd = 83.5R003.08F
PVT
12
C2602
C2602 Do Not Stuff
Do Not Stuff
DY
DY
DY
DY
R2608
R2608
1KR2J-1-GP
1KR2J-1-GP
4
PVT
SSM3K15FV-GP
SSM3K15FV-GP
http://laptopblue.vn/
H_PWRGD_R
12
C2603
C2603
PURE_HW_SHUTDOWN#
G680_RST#15
2
D S
1
21
12
G
Q2602
Q2602
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
D2603
D2603 CH551H-30PT-GP
CH551H-30PT-GP
83.R5003.C8F
83.R5003.C8F
2ND = 83.5R003.08F
2ND = 83.5R003.08F
S5_ENABLE 23,69
3V_5V_EN 34,58
1 2
12
R2635
R2635 11KR2F-L-GP
11KR2F-L-GP
PVT
R2604
R2604
10KR2F-2-GP
10KR2F-2-GP
R2623
R2623
Do Not Stuff
Do Not Stuff
DY
DY
PVT
HW_SHUTDOWN#24
G
12
1 2
3D3V_AUX_S5
10KR2J-3-GP
10KR2J-3-GP
1 2
S D
U2602
U2602
GND RESET#
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
R2619
R2619
3
IMVP_PWRGD 29,35
PLT_RST# 5,14,23,26,27,51,55,60,69
3D3V_AUX_S5
DY
DY
3
VCC
C2613
C2613
R2607
R2607
Do Not Stuff
Do Not Stuff
DY
DY
Q2611
Q2611 2N7002A-7-GP
G
Q2612
Q2612 2N7002A-7-GP
2N7002A-7-GP
84.2N702.E31
84.2N702.E31
2ND = 84.2N702.J31
2ND = 84.2N702.J31
2N7002A-7-GP
84.2N702.E31
84.2N702.E31
2ND = 84.2N702.J31
2ND = 84.2N702.J31
S D
DY
DY
12
Do Not Stuff
Do Not Stuff
12
R2616
R2616
1 2
0R2J-2-GP
0R2J-2-GP
2
Prevent BIOS data loss solution
ECRST#23
PVT
R2610
R2606
R2606
Do Not Stuff
Do Not Stuff
R2610
1KR2J-1-GP
1KR2J-1-GP
DY
DY
HW_SHUTDOWN
12
R2615
R2615
Do Not Stuff
Do Not Stuff
DY
DY
12
12
PURE_HW_SHUTDOWN#
Do Not Stuff
Do Not Stuff
DY
DY
Do Not Stuff
Do Not Stuff
R2
R2
B
PURE_HW_SHUTDOWN#
E
R1
R1
C
Q2606
Q2606
3D3V_AUX_S5
D2605
D2605 CH551H-30PT-GP
CH551H-30PT-GP
83.R5003.C8F
83.R5003.C8F
2 1
2ND = 83.5R003.08F
2ND = 83.5R003.08F
G
Do Not Stuff
Do Not Stuff
12
C2612
C2612
DY
DY
ECRST#
12
C2615
C2615
Do Not Stuff
Do Not Stuff
DY
DY
Q2604
Q2604 Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
2ND = 84.2N702.J31
2ND = 84.2N702.J31
DY
DY
S D
3D3V_AUX_S5
R2612
R2612
12
100KR2J-1-GP
100KR2J-1-GP
Q2601
Q2601
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
EC
2nd = 84.03906.R11
2nd = 84.03906.R11
B
DY
DY
KBC_RST_G
1 2 3 4 5
RN2605
RN2605
Do Not Stuff
Do Not Stuff
DY
DY
1
8 7 6
KBC_RST_GPURE_HW_SHUTDOWN#
KBC_RST_G
3D3V_AUX_S5
N12M GS2 HYN1GB
N12M GS2 HYN1GB
N12M GS2 HYN1GB
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev Custom
Custom
Custom
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Wednesday, March 02, 2011
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
KBC_Reset
KBC_Reset
KBC_Reset
1
22 74
22 74
22 74
-1
-1
-1
SSID = KBC
5
3D3V_AUX_KBC
R2702
R2702
3D3V_AUX_KBC
12
R2705
R2705 Do Not Stuff
D D
C C
Do Not Stuff
12
C2701
C2701
35001_RESET#32
SUS_PW R_ACK15
ALL_SYS_PWROK29,64
35001_SCK32
SYS_THRM24
35001_SDA32
Do Not Stuff
Do Not Stuff
RSMRST#_KBC15 ME_UNLOCK17
WIFI_RF_EN51
BLUETOOTH_EN50,51
S0_PWR_GOOD
WLAN_TEST_LED52
USB_PW R_EN#49,59
AC_PRESENT15,63
PROCHOT_EC
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
AD_IA33
T8_THRM24
BT_PRS#50
VAIO_BTN#59
ASSIST_BTN#59
SCRDLL_LED52
S5_ENABLE22,69
NUM_LED52
BAT_IN#32
LID_CLOSE#54 PM_SLP_S4#15,29,39
CAP_LED52
AC_OK33
Do Not Stuff
Do Not Stuff
12
B B
S D
12
R2732
R2732 100KR2J-1-GP
100KR2J-1-GP
KBC_PW RBTN#59
A A
1 2
Do Not Stuff
Do Not Stuff
3D3V_KBC_AUX
12
C2704
C2704
C2705
C2705
DY
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
EC_AGND
TP2915
TP2915
TP2914
TP2914
2ND = 84.2N702.J31
2ND = 84.2N702.J31
G
84.2N702.E31
84.2N702.E31
2N7002A-7-GP
2N7002A-7-GP
Q2702
Q2702
KBC_PW RBTN#
12
C2706
C2706
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
KBC_GPIO24
1
R2734
R2734
1 2
Do Not Stuff
Do Not Stuff
1
PSL
H_PROCHOT#_EC
3D3V_AUX_S5
12
C2709
C2709
12
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C2717
C2717
1 2
DY
DY
PCB_VER_AD ADT_TYPE
KBC_GPIO6
AC_IN_KBC
KBC_GPIO71
KBC_RTC_PWR
DISCRETE#
12
12
R2704
R2704 330KR2J-L1-GP
330KR2J-L1-GP
1 2
470R2J-2-GP
470R2J-2-GP
G2702
G2702 Do Not Stuff
Do Not Stuff
2 1
12
C2710
C2710
EC_AGNDEC_AGND
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
12
C2707
C2707
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
KBC_VCORF
C2712
C2712 SC1U10V3ZY-6GP
SC1U10V3ZY-6GP
R2733
R2733
1 2
Do Not Stuff
Do Not Stuff
R2757
R2757
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C2708
C2708
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
KBC_GPIO6
104
97 98 99
100 101
105 106
79 95 96
108
93 94
114
6
109
14 15 80 17 20 21 23 26 73 74 75 82 83 84
91 110 112 107
44
H_PROCHOT# 5,35
VBAT
U2701A
U2701A
VREF GPIO90/AD0
GPIO91/AD1 GPIO92/AD2 GPIO93/AD3
GPIO94/DA0 GPIO95/DA1 GPIO96/DA2
GPIO2 GPIO3/AD6
1/2 IN
GPIO4/AD5
1/2 IN
GPIO5/AD4
1/2 IN
PSL_IN2#_GPIO6 GPIO7/AD7
1/2 IN
GPIO16
2/25
GPIO24 GPIO30
2/20
GPIO34/CIRRXL
4/4
GPIO36
2/25
GPIO41
2/4
GPIO42/TCK GPIO43/TMS GPIO44/TDI GPIO46/CIRRXM/TRST# GPIO51
2/20
PSL_IN1_GPIO70 PSL_OUT_GPIO71 VBKUP GPIO75
4/4
GPO76/SHBM GPIO77 GPIO81
2/20
GPO82/IOX_LDSH/TEST# GPIO84/IOX_SCLK/XORTR# GPIO97
4/4
VCORF
NPCE795PA0DX-GP-U
NPCE795PA0DX-GP-U
NOTE: Connect GND and AGND planes via either 0R resistor or one point layout connection.
12
4
PANEL_BLEN
http://laptopblue.vn/
115
102
4
VCC19VCC46VCC76VCC88VCC
1/2 IN 1/2 IN 1/2 IN 1/2 IN
1/2 1/2 4/4
2/4 2/4 2/4 2/4
2/4 2/4
GND18GND45GND78GND89GND
G2703
G2703
Do Not Stuff
Do Not Stuff
R2716
R2716 10KR2J-3-GP
10KR2J-3-GP
GND
5
116
21
VDD
AVCC
GPIO11/CLKRUN#
GPIO65/SMI#
ECSCI#/GPIO54
GPIO10/LPCPD#
GPIO67/PWUREQ#
GPIO85/GA20
KBRST#/GPIO86
GPIO52/PSDAT3/RDY#
GPIO50/PSCLK3/TDO
GPIO27/PSDAT2 GPIO26/PSCLK2 GPIO35/PSDAT1 GPIO37/PSCLK1
GPIO17/SCL1
GPIO22/SDA1
GPIO73/SCL2
GPIO74/SDA2
GPIO23/SCL3
GPIO31/SDA3
GPIO47/SCL4
GPIO53/SDA4
F_SDI/F_SDIO1
F_SDIO/F_SDIO0
103
EC_AGND
R2711
R2711
12
Do Not Stuff
Do Not Stuff
EC_AGND
FAN_PROTECT_DISABLE#
UMA
UMA
DIS
DIS
1 OF 2
1 OF 2
LRESET#
LCLK
LFRAME#
LAD3 LAD2 LAD1 LAD0
SERIRQ
F_CS0#
F_SCK
AGND
R2715
R2715
1 2
Do Not Stuff
Do Not Stuff
R2712
R2712
1 2
0R2J-2-GP
0R2J-2-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
7 2 3 1 128 127 126 125 8 9 29 124 123 121 122
27 25 11 10 71 72
70 69 67 68 119 120 24 28
90 92 86 87
0604 Modify: Add Pull down 100k ohm at F_SDI for Power consumption concern.
3D3V_AUX_S5 3D3V_AUX_KBC
12
C2702
C2702
PLT_RST#_EC
1 2
LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0
PANEL_BLEN ECSCI#_KBC_1
ECSWI#_KBC
MODEL_ID_1 MODEL_ID_0
PROCHOT_EC KBC_GPIO53
EC_SPI_CS#_C EC_SPI_CLK_C EC_SPI_DI_C EC_SPI_DO_C
12
R2773
R2773 100KR2J-1-GP
100KR2J-1-GP
EVT 20100921
MODEL_ID_1 MODEL_ID_0
L_BKLT_EN 13 GPU_BLEN 63
3D3V_S0
Do Not Stuff
Do Not Stuff
12
C2703
C2703
DY
DY
C2711
C2711
1 2
DY
DY
Do Not Stuff
Do Not Stuff
R2735
R2735
Do Not Stuff
Do Not Stuff
TPDATA 53 TPCLK 53
BAT_SCL 32,33 BAT_SDA 32,33 PCH_SML1_CLK 16,63 PCH_SML1_DATA 16,63
1
R2737 Do Not StuffR2737 Do Not Stuff R2722 33R2J-2-GPR2722 33R2J-2-GP
NOTE: Locate resistors R2719 and R2722 close to the NPCE795L.
3D3V_S5
Do Not Stuff
Do Not Stuff
12
10KR2J-3-GP
10KR2J-3-GP
12
Z50/Z70
Z50/Z70
R2772
R2772
1 2
Do Not Stuff
Do Not Stuff
EC_GPIO47 High Active
3
ECSWI#_KBC
ECSCI#_KBC_1
EVT
VAIO_BTN# LCD_DEC#
PLT_RST# 5,14,22,26,27,51,55,60,69 CLK_PCI_KBC 14
LPC_FRAME# 17,55
INT_SERIRQ 17 PM_CLKRUN# 15
PCH_TEMP_ALERT# 18
H_A20GATE 18 H_RCIN# 18
BLON_OUT 42
FAN_OFF# 24
<--- Touch Pad <--- BAT/ CHARGER
<---PCH/eDP
LCD_DEC# 42 WIRELESS_SW 52
TP2916
TP2916
Do Not Stuff
Do Not Stuff
33R2J-2-GPR2736 33R2J-2-GPR2736
12
33R2J-2-GPR2719 33R2J-2-GPR2719
12 12 12
Do Not Stuff
Do Not Stuff
12
R2717
R2718
R2718
Z40
Z40
R2709
R2709
R2717
Z70
Z70
12
10KR2J-3-GP
10KR2J-3-GP
R2740
R2740
Z40/Z50
Z40/Z50
KBC_RTC_PWR
CH551H-30PT-GP
CH551H-30PT-GP
RN2708
RN2708
1 2 3
SRN10KJ-5-GP
SRN10KJ-5-GP
LPC_AD[0..3] 17,55
SPI_CS0#_R 17,48 SPI_CLK_R 17,48
SPI_SO_R 17,48
SPI_SI_R 17,48
PCB_VER_AD
DY
DY
3D3V_S0
4
-1M
R2703
R2703
Do Not Stuff
Do Not Stuff
D2701
D2701
2 1
R2714
R2714
1 2
Do Not Stuff
Do Not Stuff
POP_MUTE
ASSIST_BTN#
WIRELESS_SW
STDBY_LED52
PCH_SUSCLK_KBC15
H_PECI5,18
1D05V_VTT
3D3V_AUX_KBC
EC_AGND
RTC_AUX_S5 3D3V_AUX_S5
R2706
R2706
1 2
Do Not Stuff
Do Not Stuff
R2713
R2713
1 2
Do Not Stuff
Do Not Stuff
DY
DY
12
EC_SCI#
FAN_TACH124
PM_PWRBTN#15,69
WEB_BTN#59
PM_SLP_S3#15,29,30,40,45,67 CHARGE_LED52 BRIGHTNESS42
PWRLED52
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
EC_SWI# 16
EC_SCI# 16,18
83.R5003.C8F
83.R5003.C8F
2nd = 83.5R003.08F
2nd = 83.5R003.08F
R2728
R2728
1 2
DY
DY
Do Not Stuff
Do Not Stuff
R2723
R2723
1 2
10KR2J-3-GP
10KR2J-3-GP
R2725
R2725
1 2
10KR2J-3-GP
10KR2J-3-GP
R2727
R2727
1 2
DY
DY
Do Not Stuff
Do Not Stuff
BT_PRS2#
1
1 2 1 2
Do Not Stuff
Do Not Stuff
KBC_GPIO32
TP2906Do Not Stuff TP2906Do Not Stuff
FAN1_PW M24
FAN_PROTECT_DISABLE#
ECRST#22
E51_RxD51
E51_TxD51
POP_MUTE28
R2721 43R2J-GPR2721 43R2J-GP R2720
R2720
Need very close to EC
12
C2716
C2716
PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE
R2724
R2724 64K9R2F-1-GP
64K9R2F-1-GP
1 2
12
R2726
R2726 100KR2F-L1-GP
100KR2F-L1-GP
3D3V_S0
3D3V_AUX_KBC
3D3V_S5
BT_PRS2#
ECRST#
PECI VTT _PECI
2
31
117
63 64
32
118
62 65 81 66 22 16
85
113 111
30 77
13 12
SM BUS Pull-Hi
BAT_SCL BAT_SDA
SRN4K7J-8-GP
SRN4K7J-8-GP
BAT_IN# 35001_RESET#
WEB_BTN# S5_ENABLE
H_A20GATE H_RCIN#
SRN10KJ-5-GP
SRN10KJ-5-GP
PCH_SML1_CLK
PCH_SML1_DATA
DVT
100KR2J-1-GP
100KR2J-1-GP
BT_PRS#
U2701B
U2701B
GPIO56/TA1 GPIO20/TA2 GPIO14/TB1 GPIO01/TB2
GPIO15/A_PWM GPIO21/B_PWM GPIO13/C_PWM GPIO32/D_PWM GPIO66/G_PWM GPIO33/H_PWM GPIO45/E_PWM GPIO40/F_PWM
VCC_POR#
GPIO87/CIRRXM/SIN_CR GPIO83/SOUT_CR/TRIST#
GPIO55/CLKOUT/IOX_DIN_DIO GPIO00/EXTCLK
PECI VTT
NPCE795PA0DX-GP-U
NPCE795PA0DX-GP-U
KBSOUT15/GPIO61/XOR_OUT
RN2701
RN2701
4
RN2703
RN2703
4
SRN100KJ-6-GP
SRN100KJ-6-GP
RN2707
RN2707
4
SRN10KJ-5-GP
SRN10KJ-5-GP
RN2705
RN2705
1 2 3
RN2706
RN2706
2 3 1
SRN2K2J-1-GP
SRN2K2J-1-GP
3D3V_S5
R2729
R2729
KBSOUT0/JENK#
KBSOUT4/JEN0#
KBSOUT9/SDP_VIS# KBSOUT10/P80_CLK KBSOUT11/P80_DAT
KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62
GPIO60/KBSOUT16 GPIO57/KBSOUT17
3D3V_AUX_KBC
23 1
1 23
23 1
3D3V_S0
4
4
12
KBSOUT1/TCK
KBSOUT2/TMS
KBSOUT3/TDI
KBSOUT5/TDO
KBSOUT6/RDY#
EC GPIO standard PH/PL
100.0KSA SB SC
-1
Reserved Reserved
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
N12M GS2 HYN1GB
N12M GS2 HYN1GB
N12M GS2 HYN1GB
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet of
Date: Sheet of
Date: Sheet of
KBC Nuvoton NPCE795
KBC Nuvoton NPCE795
KBC Nuvoton NPCE795
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Z50-HR { Huron River Platform}
Thursday, March 03, 2011
Thursday, March 03, 2011
Thursday, March 03, 2011
1
HW STRAP
3D3V_AUX_KBC
PVT
Do Not Stuff
Do Not Stuff
ADT_TYPE DISCRETE#
10KR2F-2-GP
3D3V_S5
65W_90W# High: 65W / Low 90W DISCRETE# High: UMA / Low: Discrete
E51_RxD
2 OF 2
2 OF 2
53 52 51 50 49 48 47 43
KBSOUT7
42
KBSOUT8
41 40 39 38 37 36 35 34 33
54
KBSIN0
55
KBSIN1
56
KBSIN2
57
KBSIN3
58
KBSIN4
59
KBSIN5
60
KBSIN6
61
KBSIN7
10.0K
20.0K
33.0K
47.0K
64.9K
76.8
100.0K
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
10KR2F-2-GP
EC_AGND
R2708
R2708
1 2
DY
DY
Do Not Stuff
Do Not Stuff
KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8
KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16 KCOL17
KROW0 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7
23 74
23 74
23 74
12
R2707
R2707
75W
75W
12
R2701
R2701
75W/90W
75W/90W
KROW0 53 KROW1 53 KROW2 53 KROW3 53 KROW4 53 KROW5 53 KROW6 53 KROW7 53
3.0V
2.75V
2.48V
2.24V
2.0V
1.87V
1.65VReserved
Do Not Stuff
Do Not Stuff
10KR2J-3-GP
10KR2J-3-GP
EC_AGND
3D3V_S0
KCOL0 53 KCOL1 53 KCOL2 53 KCOL3 53 KCOL4 53 KCOL5 53 KCOL6 53 KCOL7 53 KCOL8 53
KCOL9 53 KCOL10 53 KCOL11 53 KCOL12 53 KCOL13 53 KCOL14 53 KCOL15 53 KCOL16 53 KCOL17 53
12
12
R2710
R2710
UMA
UMA
R2739
R2739
DIS
DIS
-1
-1
-1
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