Sony MCX18LG0B, MCX18LG0A Datasheet

Description

The micro unit CCD is a CCD color camera unit
with a built-in CCD image sensor, drive system IC,
sample-and-hold IC, signal processor IC and lens
system.

Features

• Ultra-small size:

MCX18LG0A: 18.3mm × 18.3mm × 8.4mm
MCX18LG0B: 18.3mm × 18.3mm × 9.6mm

• Y, U/V 16-bit digital output

• 180,000-pixel color CCD image sensor

• Equipped with a fixed focus lens:

MCX18LG0A:

F2.8 f = 2.9

mm

MCX18LG0B:

F2.8 f = 4.0

mm

Applications

• TV conference cameras

• Image input cameras
Absolute Maximum Ratings

• Supply voltage VH +18 V

DVDD1, DVDD2 +7.0 V
AVDD1, AVDD2, AVDD3 +7.0 V
AVDD4 +7.0 V
VCC +14.0 V
VL –17.5 V

• Input voltage VI –0.5 to DVDD + 0.5 V

• Operating temperature Topr 0 to +40 °C

• Storage temperature Tstg –30 to +80 °C
Recommended Operating Conditions

• Supply voltage VH 14.25 to 15.75 V

DVDD1, DVDD2 3.0 to 3.6 V
AVDD1, AVDD2, AVDD3 4.75 to 5.25 V
AVDD4 4.7 to 5.5 V
VCC 4.5 to 5.25 V
VL –8.5 to –7.5 V

• Input voltage VDCIN 1.0 to 4.5 V

• Operating temperature Topr 0 to +40 °C
Block Diagram

Peripheral ICs

• EVR: MB88347 (Fujitsu Limited.)

• EEPROM: AK6420

(Asahi Kasei Microsystems Co., Ltd.)

– 1 –

MCX18LG0A/MCX18LG0B

E97541-PS

Micro Unit CCD

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

64 pin QFN (Ceramic)

Lens

Y, U/V

CCD
Image
Sensor

S/H, AGC

Digital
Signal
Process

Timing
Generator

– 2 –

MCX18LG0A/MCX18LG0B

Pin Configuration

40
39
38
37
36
35
34

31

32

33

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57
58
59
60

63
64

61

62

2
3
4

5
6
7
8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

1

SIFSEL

AGND

VH

AGND

AV

DD

4

V

CC

AGND

SUBIN

AGCCONT

OFFSET

AV

DD

1

AV

DD

2

AV

DD

3

DCIN

DCOUT

SUBOUT

DGND

DGND

CO7

CO6

CO5

CO4

CO3

CO2

CO1

CO0

NRB

HD

VD

TEST

XCLR

SCK

SI
SO
CASI
CSROM
RESETTG
DGND
OSCI
OSCO
CK
DV

DD1

XCS
CASCK
CASO
CSEVR
DGND
VL

DGND

DCK

YO7
YO6
YO5
YO4
YO3
YO2
YO1
YO0

DV

DD2

SHOUT

SHIN

AGND

CCDOUT

AGND

– 3 –

MCX18LG0A/MCX18LG0B

Pin Description

Pin
No.

Symbol I/O Description

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29

30

31
32
33
34
35

YO1
YO0
DVDD2
SHOUT
SHIN
AGND
CCDOUT
AGND
SIFSEL
AGND
VH
AGND
AVDD4
VCC
AGND
SUBIN
AGCCONT
OFFSET
AVDD1
AVDD2
AVDD3
DCIN
DCOUT
SUBOUT
VL
DGND
CSEVR
CASO
CASCK

XCS

DVDD1
CK
OSCO
OSCI
DGND

O
O

—

O

I

—

O

—

I
—
—
—
—
—
—

I

I

I
—
—
—

I

O

O
—
—

O

O

O

I

—

I

O

I

—

Luminance signal output.
Luminance signal output.
+3.3V power supply for signal processing system.
Sample-and-hold output. Connect directly to Pin 5.
Sample-and-hold input.
Analog GND
CCD image sensor buffer output.
Analog GND
Serial communication mode selection: Microcomputer (low) /RS232C (high).
Analog GND
+15V power supply for CCD image sensor drive.
Analog GND
+5V power supply for A/D converter.
+5V power supply for sample-and-hold.
Analog GND
CCD image sensor SUB voltage input.
AGC control.
OFFSET control.
+5V power supply for sample-and-hold pulse.
+5V power supply for RG pulse.
+5V power supply for H pulse.
DC amplifier input.
DC amplifier output.
SUB pulse output.
–8V power supply for CCD image sensor drive.
Digital GND
EVR chip select.
Serial communication data output for peripheral ICs (EVR, EEPROM).
Serial communication clock output for peripheral ICs (EVR, EEPROM).
Switched by the SIFSEL setting.

Chip select during microcomputer mode.
Baud rate setting (4800bps (low)/9600bps (high)) during RS232C mode.

+3.3V power supply for timing generator.
27MHz clock input.
27MHz oscillator output.
27MHz oscillator input.
Digital GND

– 4 –

MCX18LG0A/MCX18LG0B

Pin
No.

Symbol I/O Description

36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

RESETTG
CSROM
CASI
SO
SI
SCK
XCLR
TEST
VD
HD
NRB
CO0
CO1
CO2
CO3
CO4
CO5
CO6
CO7
DGND
DGND
DGND
DCK
YO7
YO6
YO5
YO4
YO3
YO2

I

O

I

O

I
I
I

I
O
O
O
O
O
O
O
O
O
O
O

—
—
—

O
O
O
O
O
O
O

Reset pin (active low) with pull-up resistor for timing generator.
EEPROM chip select.
Serial communication data input for peripheral ICs (EVR, EEPROM).
Serial communication data output.
Serial communication data input.
Serial communication clock input.
Initialization pin (active low). EEPROM re-read.
Test pin. Leave this pin open.
Vertical sync signal output.
Horizontal sync signal output.
Color identification signal output.
Chroma signal output.
Chroma signal output.
Chroma signal output.
Chroma signal output.
Chroma signal output.
Chroma signal output. System setting pin during power on. (Connect pull-down resistor.)
Chroma signal output. System setting pin during power on. (Connect pull-down resistor.)
Chroma signal output. System setting pin during power on. (Connect pull-down resistor.)
Digital GND
Digital GND
Digital GND
Clock output pin for digital output.
Luminance signal output.
Luminance signal output.
Luminance signal output.
Luminance signal output.
Luminance signal output.
Luminance signal output.

– 5 –

MCX18LG0A/MCX18LG0B

Item

Electrical Characteristics

DC Characteristics

Symbol

UnitMin.

Typ.

Max.

Pins

Conditions

Input voltage 1

Input voltage 2
Input voltage 3
Input voltage 4
Output voltage

1
Output voltage

2
Output voltage

3
Output voltage

4
Hysteresis 1
Hysteresis 2

DVDD1
DVDD2
AVDD1
AVDD2
AVDD3
AVDD4
VCC
VH
VL
IDD1
IDD2
IADD1
IADD2
IADD3
IADD4
ICC
IH
IL
VT+

VT–
VIH1

VIL1
VDCIN

VSUB
VOH1

VOL1
VOH2

VOL2
VOH3

VOL3
VOH4

VOL4

∗1, ∗6,
∗8

∗2, ∗7

DCIN

SUBIN

∗3

∗4

∗5

SUBOUT

∗1, ∗8

∗6

A/D input amplitude = 2Vp-p

DVDD1 = 3.3V
DVDD2 = 3.3V
AVDD1 = 5.0V
AVDD2 = 5.0V
AVDD3 = 5.0V
AVDD4 = 5.0V
VCC = 5.0V
VH = 15.0V
VL = –8.0V

IOH1 = –1.2mA
IOL1 = 2.4mA

IOH2 = –2.4mA
IOL2 = 4.8mA

IOH3 = –8mA
IOL3 = 8mA

IOH4 = –4mA
IOL4 = 5.4mA

V
V
V
V
V
V
V
V

V
mA
mA
mA
mA
mA
mA
mA
mA
mA

V

V

V

V

V

V

V

V

V

V

3.0

3.0

4.75

4.75

4.75

4.5

4.5

14.25
–8.5

DVDD2 × 0.8

DVDD1 × 0.7

1.0

Display
value – 0.1

DVDD2 – 0.8

DVDD2 – 0.8

DVDD1/2

VH – 0.25

3.3

3.3

5.00

5.00

5.00

5.0

5.0

15.00
–8.0

7.0

38.5

3.1

1.0

5.3

16.1

53.5

7.1

1.5

Display
value

0.5

0.6

3.6

3.6

5.25

5.25

5.25

5.5

5.25

15.75
–7.5

DVDD2 × 0.2

DVDD1 × 0.3

4.5

Display
value + 0.1

0.4

0.4

DVDD1/2

VL + 0.25

Operating
current

Supply voltage

– 6 –

MCX18LG0A/MCX18LG0B

∗7

OSC

CK

∗2

SIFSEL

∗6
∗1

Item

Symbol

UnitMin.

Typ.

Max.

Pins

Conditions
Threshold value
Feedback resistance
Input amplitude
Pull-up resistor
DC amplifier gain
Input leak current 1
Input leak current 2
Input leak current 3

VTH
RFE1

RPU
G
II1
II2
II3

OSCI = DVDD1 or GND
50MHz sine wave

VIN = DVDD2
VIN = GND or DVDD2
VIN = GND or DVDD2

V

Ω

Vp-p

Ω

µA
µA
µA

250k

0.5

25k

12
–10
–40

DVDD1/2

1M

50k

4.4
30

2.5M

75k

75
10
40

∗1

CO0 to 7

∗2

RESETTG

∗3

CSEVR, CSROM, SO, TEST, VD, HD, YO0 to 7, CO0 to 7, NRB

∗4

CASO, CASCK, DCK

∗5

OSCO

∗6

XCS, SI, SCK, XCLR, CASI

∗7

OSCI, CK

∗8

SIFSEL

Note) VSUB display value
The VSUB display value is displayed by a code on the rear surface of the MUC.

Code

—

Actual voltage (V)

5.00=5.2505.5015.7526.0036.2546.5066.7577.0087.2597.50A7.75C8.00D8.25

Code E

8.50f8.75G9.00h9.25J9.50K9.75L10.00m10.25N10.50P10.75R11.00S11.25U11.50V11.75

Code

W

12.00X12.25Y12.50Z12.75

Actual voltage (V)

Actual voltage (V)

– 7 –

MCX18LG0A/MCX18LG0B

TSUXCS

THXCS

TWLSCK TWHSCK

TZDSO

TPDSO TDZSO

DATA DATADATA

DATA DATA

THSI

DATA

TSUSI

SI

SO

SCK

XCS

TpdYO
TpdCO
TpdNRB

YO0 to 7
CO0 to 7
NRB

DCK

Minimum low interval
Minimum low interval
SCK input pulse width (high interval)
SCK input pulse width (low interval)
XCS input setup time, activated by the falling edge of SCK
XCS input hold time, activated by the rising edge of SCK
SI input setup time, activated by the rising edge of SCK
SI input hold time, activated by the rising edge of SCK
SO output transition time (Hi-Z → Data active),

activated by the falling edge of XCS
SO transition time (Data active → Hi-Z),

activated by the rising edge of XCS
SO output delay time, activated by the falling edge of SCK
YO0 to 7 output delay time, activated by the falling edge

of DCK
CO0 to 7 output delay time, activated by the falling edge

of DCK
NRB output delay time, activated by the falling edge of

DCK

TWCLR
TWRST
TWHSCK
TWLSCK
TSUXCS
THXCS
TSUSI
THSI

TZDSO

TDZSO
TPDSO
TPDYO

TPDCO

TPDNRB

500

35
430
430
430
640
140
140

70

70

70

—
—
—
—
—
—
—
—

—

—
—

7

7

7

—
—
—
—
—
—
—
—

200

200
240

ns
ns
ns
ns
ns
ns
ns
ns

ns

ns
ns
ns

ns

ns

Serial
communication

Digital output

XCLR
RESETTG

Classification

Item

Symbol Min. Typ. Max. Unit

(CL = 20pF, within recommended operating range)