2-3. Printed Wiring Board – MAIN Board – ....................... 2-5
2-4. Schematic Diagram – MAIN Board (1/2) – ................. 2-7
2-5. Schematic Diagram – MAIN Board (2/2) – ................. 2-9
2-6. Printed Wiring Board – SUB Board – ........................ 2-11
2-7. Schematic Diagram – SUB Board – ........................... 2-13
2-8. IC Pin Function Description ........................................ 2-19
3.ELECTRICAL PARTS LIST .............................. 3-1
Flexible Circuit Board Repairing
• Keep the temperature of the soldering iron around 270 ˚C during repairing.
• Do not touch the soldering iron on the same conductor of the
circuit board (within 3 times).
• Be careful not to apply force on the conductor when soldering
or unsoldering.
Notes on chip component replacement
• Never reuse a disconnected chip component.
• Notice that the minus side of a tantalum capacitor may be damaged by heat.
S
ony, VAIO, the VAIO logo, Music Clip,
OpenMG and the OpenMG logo are trademarks
of Sony Corporation.
IBM and PC/AT are registered trademarks of
International Business Machines Corporation.
Microsoft, Windows and the Windows 98 logo
are registered trademarks of Microsoft
Corporation.
MMX and Pentium are registered trademarks of
Intel Corporation.
Creative and SoundBlaster 16 are trademarks or
registered trademarks of Creative Labs. Inc.
CD-related data through the Internet from the
CDDB Music CD Database.
Copyright 1999 CDDB Inc. CDDB Client
Software. Copyright 1999 CDDB Inc.
CDDB-Enabled, CDDB, CDDB 2 and the
CDDB Logo are trademarks of CDDB, Inc.
All other trademarks are trademarks of their
respective owners.
– 2 –
SECTION 1
SERVICING NOTES
1-1.At the beginning
Service Tool List
Ref.No.Tool NamePart No.Usage
1Service Tool 9100 (CD-ROM)J-2500-377-1Board Test
In replacing the following parts, replace the board altogether.
Board NameRef. No.
Main BoardIC201, 202, 203, 601, 901
Sub BoardIC803
Precautions on repairing the main board:
1. IC202 and 203 store music data. These parts are special packages called TCP, and they are very sensitiv e to a shock. Therefor e, do not
touch these parts or leads directly, or do not give a shock.
2. IC601 and 901 are CSP packages. Do not give a shock to these parts.
3. The ground pattern around the board is in a height restriction “0” zone. Do not put a solder in this zone.
Precaution on repairing the sub board:
1. Special ID has been written to the IC803. When this part seems to be faulty, replace the sub board altogether.
Additional precaution:
1. This set can cooperate with PC using the ID written to the set. After repaired, confirm the connection and check in/check out using the
“OpenMg JukeBox”.
1-2.Board Replacement
This set consists of two boards, Main and Sub, and the contents of respective boards are as shown in Table 1.
Table 1
Board NameContents
Main boardMusic data, Battery adjustment value, Equalizer
initial value, CODEC program
Sub boardID/IK, Music information on Main board
If either board was replaced during repair, the music data in Main board do not match the music information in Sub board, and therefore
be sure to perform the following checking and work.
Replacing the board causes the conditions as listed in Table 2.
Table 2
Replaced Board Conditions
Main boardMusic data, if stored in set, are cleared. How ever, the data can be recovered
by connecting the set to the same PC as that used when check-out was executed.
(Supposed check-in)
Sub boardMusic data, if stored in set, are cleared, same as in the Main board replacement.
Also, the data are not recoverable because ID/IK are changed.
Preparation
Replacing the board causes the music data in Main board and the music information in Sub board to be unmatched, thus requiring the
music data in Main board and the music information in Sub board to be initialized. T o initialize these data, perf orm the following checking
and work.
In performing the work, set the boards in position. Also, do not load the battery (the power is supplied through the USB cable).
1-1
Procedure
1. From the PC, start “VMC_TEST” (J-2500-377-1) of the service tool.
2. Confirm that the following screen appears.
3. Connect the set with an exclusive cable. At this time, make sure that “Open” is displayed at the part 1 of the following screen.
The “Open” display means that the set is connected to PC normally (“Close” is displayed when the set is disconnected). Also, confirm
that the “PC” is displayed on the LCD of the set.
1
1
1-2
4. Click the “Press Button” at the part 2 of the following screen.
2
5. Check that, after several seconds, “Complete!” is displayed in the “Result” field at the part 3 of the following screen. Also, check that
“1 PC” is displayed on the LCD of the set.
3
Precautions
1. Never disconnect the cable during work.
2. If the PC is hung up during work, disconnect the cable and close the “VMC_TEST” once, and then retry from the beginning.
3. After the work, make sure that the check-in and check-out can be executed using the PC application “OpenMG Jukebox”. Also,
confirm that the checked out data can be played normally.
1-3.System Requirements
•IBM PC/AT and compatibles
CPU: MMX
above recommended)
Hard disk drive space: 20 MB and above (Free space is required,
depending on the version of Windows 98 and the size of the audio
data you are using.)
RAM: 64 MB and above
CD-ROM drive
Sound Board: Creative SoundBlaster 16 compatible
Default built-in USB port
• Operating system: The default installation of Windows
version (The product does not work on Windows 95/3.1 or Windows
NT. Not assured trouble-free if you use an upgrade version from
Windows 95/3.1 to Windows 98.)
• Display: SVGA (800 × 600 pixel) (supports High Color (16 bit) and
above)
• Internet access
Pentium 233 MHz and above (Pentium II 400 MHz and
98 English
1-3
1-4.Test Mode
This set has the T est mode in the microcomputer , and the use of e xclusive application softw are on the PC side can check various functions.
Preparation
1. From the PC, start the T est mode “Vmo_Check.e xe” (J-2500-377-1) of the sevice tool, and confirm that the following screen appears.
2. Connect the set with exclusive cable (the po wer for the set is supplied from USB), then check that the part 1 on the following screen
is “Open”, and also “1 PC” is displayed on the LCD of the set. (Part 1 becomes “Close” if disconnecting the cable again.) At this time,
a sine wave is generated from the headphone.
1
Supplement: If the part 1 does not become “Open”, the USB of the set will be faulty.
Also, audio signals are outputted from the reference signal in the DSP of the set.
1-4
Description of Service Mode Operation
1. Checking the Functions of Audio Section
Clicking the Up/Down at part 2 of the screen can change the output frequency. Also, clicking the Up/Down at part 3 can change the
volume. Clicking the L/Stereo/R/Mute at part 4 can change the output.
8
23
9
4
0
6
5
7
2. Battery Threshold Value Reading and Measurement
When the Test mode is selected, the threshold values for the remaining battery capacity written in the set are displayed at the part 5.
These values are adjusted values at the shipment, and inherent data.
The threshold values are provided separately for the PLAY and for the IDLE; values are at scale 3→4, scale 2→3, scale 1→2, and OFF
from the right to left.
Standard threshold value is given with “1024/1.8 × Battery T erminal Voltage”, and the battery terminal voltages to respective threshold
values are as follows.
qa
OFFScale 1→2Scale 2→3Scale 3→4
At idle1.05 V1.13 V1.20 V1.31 V
At play1.00 V1.10 V1.18 V1.30 V
Click the part 6, and the calculated value corresponding to the voltage will be displayed if the voltage is applied to the battery terminals.
For example, if 1.2 V is applied to the battery terminals, approximate 680 is displayed.
3. LCD Test
Clicking the FULL/COL 1/COL 2/OFF respectively at part 7 can cause the LCD on the set to turn on full LCD, column 1, column 2,
or turn off LCD.
4. Flash Memory Read/Write Check
Clicking the part 8 can check the read/write of the flash memory. If normal, “Success” is displayed.
5. CODEC Info Check
The CODEC program versions written in the set can be checked, and they are displayed when the Test mode is selected (part 9). At
the shipment, they are as follows (these values vary when the progr ams are updated).
NameVersion
CODEC1AT38
CODEC2MP37
CODEC3blank0
CODEC4blank0
1-5
Supplement: As the CODEC Info has been written in the EEPROM on the Sub board, it may be said that the EEPROM operation is OK,
if the information is displayed normally.
6. Firmware Info Check
The microcomputer program version and the flash memory capacity can be checked, and they are displayed when the Test mode is
selected (part 0).
At the shipment, they are as follows (these values var y when the program is updated).
Ver (microcomputer version)38
Flash Size63766528
7. Key Check
Click the part qa with any key on the set pressed, and “ON” will be displayed in the field corresponding to that key.
V2
FLASH MEMORY CONTROLLER (IC201),
FLASH MEMORY (IC202, 203),
LED DRIVER (IC501),
DIGITAL SIGNAL PROCESSOR (IC601),
D/A CONVERTER (IC605),
EEPROM (IC803),
USB CONTROLLER (IC901)
B+
V1
CPU (IC801)
B+
Q102
VBATT
+2.8V
REGULATOR
IC103
REGULATOR
IC104
CS
10
C/D
11
SI
9
CK
8
RESET SIGNAL
INTERFACE
COMMAND/
REGISTER
COMMAND
DECODER
B+ SWITCH
Q103
GENERATOR
IC107
SERIAL
DATA
ADDRESS
COUNTER
TIMING
GENERATOR
L103
DISPLAY
COMMON
COUNTER
LCD DIRVER
IC501
+3.2V
REGULATOR
IC102
D103
DATA
RAM
LCD
SEGMENT
DRIVER
LCD
COMMON
DRIVER
SWITCHING
REGULATOR
IC101, Q101
THP501
SEG0
ı
SEG14
COM0
COM1
L101
17
31
12
13
L102
2-12-2
2-2.NOTE FOR PRINTED WIRING BOARDS AND SCHEMATIC DIAGRAMS
Note on Printed Wiring Board:
• X : parts extracted from the component side.
• Y : parts extracted from the conductor side.
• b : Pattern from the side which enables seeing.
(The other layers' patterns are not indicated.)
Caution:
Pattern face side: Parts on the pattern face side seen from
(Conductor Side)the pattern face are indicated.
Parts face side:Parts on the parts face side seen from
(Component Side) the parts face are indicated.
• MAIN and SUB boards are multi-layer printed board.
However, the patterns of intermediate-layer hav e not been included in the diagram.
Note on Schematic Diagram:
• All capacitors are in µF unless otherwise noted. pF: µµF
50 WV or less are not indicated except for electrolytics
and tantalums.
• All resistors are in Ω and 1/
specified.
•%: indicates tolerance.
f
•
• C : panel designation.
• U : B+ Line.
• Power voltage is dc 1.5 V and fed with regulated dc power
• Voltages and wav ef orms are dc with respect to ground in
• Voltages are taken with a VOM (Input impedance 10 MΩ).
• Waveforms are taken with a oscilloscope.
• Circled numbers refer to waveforms.
• Signal path.
: internal component.
supply from battery terminal.
playback mode.
no mark : PLAYBACK
Voltage var iations may be noted due to normal produc-
tion tolerances.
Voltage var iations may be noted due to normal produc-
—Ground terminal
I/O
I/O
I/O
I/OTwo-way data bus with the CPU(IC801)
I/O
I/O
—Ground terminal
OSystem clock output terminal Not used (open)
—Ground terminal
—Power supply terminal (+3.1V)
OCommand data enable signal output terminal Not used (open)
OWrite enable signal output terminal Not used (open)
Description
Not used (fixed at “L”)
Address signal input terminal Not used (fixed at “L”)
Chip select signal input from the CPU(IC801)
IPower supply terminal (+3.1V)
ITest signal input terminal Not used (fixed at “H”)
IReset signal input from the CPU(IC801) “L”: reset
ITest signal input terminal Not used (open)
ISystem clock input from the CPU(IC801)
Test signal input terminal Not used (open)
Ground terminal
ITest signal input terminal Not used (open)
40, 41F SC B0, F SC B1
42 to 45F D B7 to F D B4
46VDD
47TEST14
48GND
49VDD
50F D B3
51GND
52 to 54F D B2 to F D B0I/O
55, 56
57F RSTB
58 F RDY
59F CEB 0
60F CEB1
61 to 64 F CEB 2 to F CEB 5
65GND
F OE B0B,
F OE B1B
OSerial data clock output terminal Not used (open)
I/OTwo-way data bus Not used (open)
—Power supply terminal (+3.1V)
—Ground terminal
—Power supply terminal (+3.1V)
I/OTwo-way data bus Not used (open)
—Ground terminal
OEnable signal output terminal Not used (open)
OReset signal output to the flash memory (IC202, 203) “L”: reset
OChip enable signal output to the flash memory (IC202) “L” active
OChip enable signal output to the flash memory (IC203) “L” active
OChip enable signal output terminal Not used (open)
—Ground terminal
ITest signal input terminal Not used (open)
Two-way data bus Not used (open)
IReady signal input from the flash memory (IC202, 203) “H”: ready
2-19
Pin No.Pin NameI/O
66, 67F CEB 6, F CEB7
68F CDE AB
69GND
70F WE A0B
71F WE A1B
72F SC A0
73F SC A1O
OChip enable signal output terminal Not used (open)
OCommand data enable signal output to the flash memory (IC202, 203) “L” active
—Ground terminal
OWrite enable signal output to the flash memory (IC202, 203) “L” active
OWrite enable signal output terminal Not used (open)
OSerial data clock output to the flash memory (IC202, 203)
I/OTwo-way data bus with the flash memory (IC202, 203)
—Power supply terminal (+3.1V)
I/OTwo-way data bus with the flash memory (IC202, 203)
—Ground terminal
I/OTwo-way data bus with the flash memory (IC202, 203)
OEnable signal output to the flash memory (IC202, 203) “L” active
OEnable signal output terminal Not used (open)
—Power supply terminal (+3.1V)
I/OTwo-way data bus with the CPU(IC801)
ONot used (open)
I/O
I/OTwo-way data bus with the CPU(IC801)
I/O
—Ground terminal
I/OTwo-way data bus with the CPU(IC801)
—Not used (open)
I/OTwo-way data bus with the CPU(IC801)
—Not used (open)
ONot used (open)
OReset signal output to the CPU (IC801) “L”: reset
—Power supply terminal (+3.1V)
—Ground terminal
OInterrupt request signal output to the CPU (IC801)
—Ground terminal
Description
Serial data clock output terminal Not used (open)
ITest signal input terminal Not used (open)
Address signal input from the CPU(IC801)
Not used (open)
I
Address signal input from the CPU(IC801)
INot used (open)
Address signal input from the CPU(IC801)
Address signal input terminal Not used (fixed at “L”)
IAddress signal input terminal Not used (fixed at “L”)
INot used (fixed at “L”)
ITest signal input terminal Not used (open)
Address signal input terminal Not used (fixed at “L”)
INot used (fixed at “H”)
Address signal input terminal Not used (fixed at “L”)
IWrite enable signal input from the CPU (IC801)
Address signal input terminal Not used (fixed at “L”)
IRead enable signal input from the CPU (IC801)
2-20
• MAIN BOARD IC601 TMX320VC5409GGU100 (DIGITAL SIGNAL PROCESSOR)
OProgram space select signal output terminal Not used (open)
OData space select signal output terminal Not used (open)
OI/O space select signal output terminal Not used (open)
ORead/write signal output terminal Not used (open)
OMemory strobe signal output terminal Not used (open)
OI/O strobe signal output terminal Not used (open)
—Ground terminal
—Ground terminal
—Ground terminal
OClock output to the D/A converter (IC605)
OClock output terminal (fixed at “H”)
—Ground terminal
OInterrupt signal output to the CPU (IC801)
Description
Ground terminal
Address signal input terminal Not used (open)
Ground terminal
Power supply terminal (+3.1V)
Address signal input terminal Not used (open)
IAddress signal input terminal Not used (open)
IAddress strobe signal input terminal (fixed at “H”)
Ground terminal
IChip select signal input from the CPU (IC801)
IAddress signal input from the CPU (IC801)
IData ready signal input terminal (fixed at “H”)
Microstate complete signal output terminal Not used (open)
External flag signal output terminal Not used (open)
Hold acknowledge signal output terminal Not used (open)
Instruction acquisition signal output terminal Not used (open)
Hold signal input terminal (fixed at “H”)
Branch control signal input terminal (fixed at “H”)
Mode select signal input terminal (fixed at “L”)
Power supply terminal (+3.1V)
ISerial data receive signal input terminal (fixed at “H”)
IFrame synchronization pulse signal input terminal (fixed at “H”)
IData receive clock input terminal (fixed at “H”)
IAddress signal input from the CPU (IC801)
IData receive clock input terminal (fixed at “H”)
IFrame synchronization pulse signal input terminal (fixed at “H”)
ISerial data receive signal input terminal (fixed at “H”)
IAddress signal input from the CPU (IC801)
ISerial data receive signal input terminal (fixed at “H”)
Power supply terminal (+1.8V)
LR frame signal output to the D/A converter (IC605)
Serial data receive signal output terminal Not used (fixed at “H”)
OReady signal output terminal Not used (open)
Power supply terminal (+3.1V)
—Ground terminal
OSerial data transmit signal output to the D/A converter (IC605)
OSerial data transmit signal output terminal Not used (open)
OInterrupt request signal output terminal
IAddress signal input from the CPU (IC801)
INonmaskable interrupt request signal input terminal (fixed at “H”)
IInterrupt request signal input from the CPU (IC801)
IInterrupt request signal input terminal (fixed at “H”)
Power supply terminal (+1.8V)
—Ground terminal
OClock out put terminal (fixed at “H”)
—Ground terminal
Serial data receive signal output terminal (fixed at “H”)
OSerial data transmit signal output terminal Not used (open)
—Power supply terminal (+3.1V)
—Ground terminal
IClock mode signal output terminal (fixed at “L”)
IClock mode signal output terminal (fixed at “H”)
IClock mode signal output terminal (fixed at “L”)
—Not used (open)
OTimer signal output terminal Not used (open)
IEmulator signal input terminal (fixed at “H”)
OEmulator signal output terminal (fixed at “H”)
OTest data signal output terminal
ITest data signal input terminal
ITest reset signal input terminal
ITest clock input terminal
ITest mode select signal input terminal
—Ground terminal
Power supply terminal (+1.8V)
IHPI module select signal input terminal (fixed at “H”)
I/OTwo-way data bus Not used (open)
I/OTwo-way data bus with the CPU (IC801)
I/OTwo-way data bus Not used (open)
I/OTwo-way data bus with the CPU (IC801)
Power supply terminal (+1.8V)
—Ground terminal
IData read signal input from the CPU (IC801)
—Ground terminal
IData write signal input from the CPU (IC801)
—Power supply terminal (+3.1V)
IAddress signal input terminal Not used (open)
I/OTwo-way data bus with the CPU (IC801)
IAddress signal input terminal Not used (open)
Power supply terminal (+1.8V)
IAddress signal input terminal Not used (open)
—Ground terminal
2-23
• MAIN BOARD IC801 HD6432328A05TE (CPU)
Pin No.Pin NameI/O
1VCC—
2A0O
3 to 5A1 to A3O
6VSS
7 to 10A4 to A7
11A8
12A9
13A10
14A11
15VSS—
16A12
17A13
18 to 20A14 to A16
21 to 23A17 to A19
24VSS
25IRQ4
26IRQ5I
27IRQ6
28IRQ7
29IRQ3
30IRQ2
31IRQ1I
32IRQ0
33VCC—
34 to 37D0 to D3
38VSS
39 to 42D4 to D7
43 to 46D8 to D11
47VSS
48 to 51D12 to D15
52VCC—
53TXD0
54TXD1
55RXD0
56RXD1
57SCK0
58 SCK1
59VSS
60CS4
61TEND0
62DREQ1
63TEND1
64TIOCB5
65TIOCA5
66TIOCB4
Power supply terminal (+3.1V)
Address signal output to the digital signal processor (IC601) and USB controller (IC901)
Address signal output to the USB controller (IC901)
—Ground terminal
OAddress signal output to the USB controller (IC901)
IHs key (S805) input terminal
IL key (S806) input terminal
Il key (S807) input terminal
IMODE key (S808) input terminal
OAddress signal output terminal Not used (open)
OAddress signal output to the digital signal processor (IC601)
—Ground terminal
ITest mode signal input terminal “L”: test mode
AVLS switch (S813) input terminal
IInterrupt signal input from the MODE key (S808)
IInterrupt signal input from the Hs, L, l, VOL +/- key (S805 to 807, 809, 810)
IInterrupt signal input from the flash memory controller (IC201)
IInterrupt signal input from the digital signal processor (IC601)
Interrupt signal input from the USB controller (IC901)
IUSB connection detect signal input terminal
Power supply terminal (+3.1V)
I/OTwo-way data bus with the flash memory controller (IC201)
—Ground terminal
I/OTwo-way data bus with the flash memory controller (IC201)
I/OTwo-way data bus with the flash memory controller (IC201) and USB controller (IC901)
—Ground terminal
I/OTwo-way data bus with the flash memory controller (IC201) and USB controller (IC901)
Power supply terminal (+3.1V)
OSerial data output to the LCD driver (IC501) and EEPROM (IC803)
OSerial data output terminal for the test mode
ISerial data input to the EEPROM (IC803)
ISerial data input terminal for the test mode
OSerial data clock output to the LCD driver (IC501) and EEPROM (IC803)
OCommand/data output to the LCD driver (IC501)
—Ground terminal
OEnable signal output to the digital signal processor (IC601) “L” active
O
Not used (open)
O
OUSB D+ pull up control signal output terminal “L”: ON
OPower supply (V2) control signal output terminal “L”: ON
OChip select signal output to the LCD driver (IC501)
OLCD back light (D401, 404, 405) ON/OFF control signal output terminal “H”: LED ON
O
ONot used (open)
OPower supply control signal output to the headphone amp (IC605) “H”: ON
OReset signal output to the flash memory controller (IC201) “L”: reset
O
OWatch dog timer mode over flow signal output terminal Not used (open)
—Power supply terminal (+3.1V)
OMain system clock output terminal (12MHz)
—Ground terminal
OSystem clock output to the flash memory controller (IC201)
—Power supply terminal (+3.1V)
OAddress strobe signal output terminal “L” active Not used (open)
O
O
OLower byte data write enable signal output terminal “L” active Not used (open)
OBus wait request signal output terminal Not used (open)
OInterrupt request signal output to the digital signal processor (IC601)
OReset signal output to the digital signal processor (IC601) “L”: reset
OMute control signal output to the D/A converter (IC605) “L”: mute
O
ONot used (open)
O
—Power supply terminal (+3.1V)
Description
Chip select signal output to the EEPROM (IC803)
Reset signal output to the flash memory controller (IC201) , digital signal processor (IC601)
and USB controller (IC901) “L”: reset
System reset signal input from the reset signal generator (IC107) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
INonmaskable interrupt request signal input terminal
Istandby mode input terminal “L”: standby
IMain system clock input terminal (12MHz)
Data read signal output to the flash memory controller (IC201) , digital signal processor
(IC601) and USB controller (IC901) “L” active
Upper byte data write enable signal output to the flash memory controller (IC201) , digital
signal processor (IC601) and USB controller (IC901) “L” active
IVoltage detect input terminal
INot used (pull up)
—Ground terminal
—Ground terminal
OReset signal output to the USB controller (IC901) “L”: reset
O
OAddress signal output to the flash memory controller (IC201)
O
ONot used (open)
O
ONot used (open)
O
2-25
Pin No.Pin NameI/O
113 to 115MD0 to MD2
116CAS
117, 118CS3, CS2
119CS1
120CS0
Description
IOperation mode control signal input terminal
OColumn address strobe signal output terminal Not used (open)
OChip select signal output to the flash memory controller (IC201)
OChip select signal output to the USB controller (IC901)
OChip select signal output terminal Not used (open)
2-26 E
2-26
SECTION 3
ELECTRICAL PARTS LIST
JACK SUB
NOTE:
• Due to standardization, replacements in the
parts list may be different from the parts specified in the diagrams or the components used
on the set.
• -XX and -X mean standardized parts, so they
may have some difference from the original
one.
• RESISTORS
All resistors are in ohms.
METAL: Metal-film resistor.
METAL OXIDE: Metal oxide-film resistor.
F: nonflammable
D4018-719-075-56 LED FA1113F-Y641-TR (LCD BACK LIGHT)
D4048-719-075-56 LED FA1113F-Y641-TR (LCD BACK LIGHT)
D4058-719-075-56 LED FA1113F-Y641-TR (LCD BACK LIGHT)
D6018-719-056-59 DIODE MAZS120008SO
D6028-719-056-59 DIODE MAZS120008SO
IC1018-759-656-52 IC MAX1674EUA-TG069
IC1028-759-676-78 IC MM1320FNLE
IC1048-759-656-53 IC MM1426CNLE
IC1078-759-659-13 IC PST3428UL
IC201(Not supplied) IC HN29W256H02TE-1
IC202(Not supplied) IC HN29W25611TBE-50
IC203(Not supplied) IC HN29W25611TBV-50
IC601(Not supplied) IC TMX320VC5409GGU100
IC8018-759-659-02 IC HD6432328A05TE
IC901(Not supplied) IC ML60851CLBZ060
R1011-208-955-11 METAL CHIP680K0.5%1/16W
R1021-208-947-11 METAL CHIP330K0.5%1/16W
R1031-208-921-81 METAL CHIP27K0.5%1/16W
R1041-208-893-81 METAL CHIP1.8K0.5%1/16W
R1051-208-918-81 METAL CHIP20K0.5%1/16W